Finfet with discontinuous channel region

Abstract

A fin transistor with discontinuous channel regions includes M gate terminal structures, N drain terminal structures, and a conductive structure. Each gate terminal structure includes a first channel structure including a source region and a first channel region, and a gate structure formed on surfaces of the first channel region. Each drain terminal structure includes a second channel structure including a second channel region and a drain region, where the second channel region and the first channel region are two discontinuous regions, and a reduced surface field structure formed on surfaces of the second channel region. The conductive structure is coupled to the first channel region of one of the M gate terminal structures and the second channel region of one of the N drain terminal structures. The fin transistor of the present invention can achieve high voltage withstand and low on-resistance simultaneously.

Description

Technical Field

[0001] This invention relates to fin transistors, and more particularly to fin transistors having discontinuous channel regions. Background Technology

[0002] FinFETs (Fin Field Transistors) are widely used in semiconductor manufacturing. Traditional FinFETs have only a single fin. While these FinFETs can function as high-voltage devices, their on-state resistance (R0) is high. ON ) and breakdown voltage (V) BD The optimization of the relationship between the transistor and its operating voltage is limited by its single-fin structure, making it difficult to simultaneously achieve low on-resistance and high breakdown voltage. Generally, the breakdown voltage of a transistor should be much higher than its operating voltage (V). OP (For example: V) BD ≥2V OP Because high-voltage components operate at high voltages, their breakdown voltages should also be high. Summary of the Invention

[0003] One of the objectives of this disclosure is to provide a fin transistor with discontinuous channel regions that can simultaneously achieve low on-resistance and high breakdown voltage.

[0004] One embodiment of the fin transistor disclosed herein includes M gate structures, N drain structures, and a conductive structure, wherein M and N are both positive integers. Each of the M gate structures includes a first channel structure and a gate structure. The first channel structure includes a source region and a first channel region; the gate structure is formed on multiple surfaces of the first channel region. Each of the N drain structures includes a second channel structure and a surface-reducing structure. The second channel structure includes a second channel region and a drain region; the surface-reducing structure is formed on multiple surfaces of the second channel region. The second channel region and the first channel region are two discontinuous regions; in other words, the channel between the source and drain of the fin transistor is not a continuous channel. The conductive structure couples the first channel region of one of the M gate structures to the second channel region of one of the N drain structures to couple the source and drain of the fin transistor.

[0005] Another embodiment of the finned transistor disclosed herein includes M gate structures, N drain structures, and a conductive structure. M and N are both positive integers, and at least one of M and N is greater than one; if M is greater than one, the M gate structures are coupled together; if N is greater than one, the N drain structures are coupled together. Each of the M gate structures includes a first channel structure and a gate structure. The first channel structure includes a source region and a first channel region; the gate structure is formed on multiple surfaces of the first channel region. Each of the N drain structures includes a second channel structure. The second channel structure includes a second channel region and a drain region, wherein the second channel region and the first channel region are two discontinuous regions. The conductive structure couples the first channel region of one of the M gate structures to the second channel region of one of the N drain structures.

[0006] The features, implementation, and technical effects of the present invention are described in detail below with reference to the accompanying drawings, and preferred embodiments are described in detail. Attached Figure Description

[0007] Figure 1 This invention illustrates an embodiment of a finned transistor.

[0008] Figure 2 show Figure 1 An embodiment of each gate terminal structure;

[0009] Figure 3 show Figure 1 An embodiment of each drain end structure;

[0010] Figure 4 show Figure 1 A cross-sectional view of an embodiment of the conductive structure;

[0011] Figure 5 show Figure 1 A top view of M gate terminal structures connected in parallel;

[0012] Figure 6 show Figure 1 The top view of the N drain extreme structures connected in parallel; and

[0013] Figure 7 show Figure 1 The top view of the N drain extreme structures connected in series.

[0014] Symbol Explanation

[0015] 100: Fin transistor

[0016] 110: Gate terminal structure

[0017] 120: Drain extreme structure

[0018] 130: Conductive structure

[0019] 112: First Channel Structure

[0020] 1122: Source Region

[0021] 1124: First Passage Area

[0022] 114: Gate Structure

[0023] 1142: Conductive part

[0024] 1144: Non-conductive part

[0025] 122: Second Channel Structure

[0026] 1222: Second Passage Area

[0027] 1224: Drain region

[0028] 124: Reduce surface electric field structure

[0029] 132: First contact window

[0030] 134: Second contact window

[0031] 410: Conductive layer

[0032] 510: Conductive structure

[0033] 610: Conductive structure

[0034] 710: First Drain Extreme Structure

[0035] 720: Conductive structure

[0036] 730: Second Drain Extreme Structure Detailed Implementation

[0037] This specification discloses a FinFET with discontinuous channel regions that can simultaneously achieve low on-resistance and high breakdown voltage.

[0038] Figure 1 This invention illustrates an embodiment of the finned transistor of the present disclosure. Figure 1 The finned transistor 100 includes M gate structures 110, N drain structures 120, and a conductive structure 130, where M and N are both positive integers. For example, at least one of M and N is greater than one; if M is greater than one, the M gate structures 110 are coupled together; if N is greater than one, the N drain structures 120 are coupled together.

[0039] Figure 2An embodiment of each gate terminal structure 110 is shown, which includes a first channel structure 112 and a gate structure 114. Figure 3 An embodiment of each drain end structure 120 is shown, which includes a second channel structure 122 and a reduced-surface-field (RESURF) structure 124. Figure 4 A cross-sectional view showing an embodiment of the conductive structure 130 is shown. The conductive structure 130 couples M gate terminal structures 110 to N drain terminal structures 120 via a conductive layer 410 (e.g., a metal layer). It is worth noting that the length of each of the M gate terminal structures 110 is a first length, and the length of each of the N drain terminal structures 120 is a second length. The first length may be equal to the second length to simplify the manufacturing process of the fin transistor 100; however, this is not a limitation of the present invention.

[0040] Please see Figure 1 , Figure 2 Each gate structure 110 includes a first channel structure 112 comprising a source region 1122 and a first channel region 1124. The size, shape, material, and doping concentration of the source region 1122 and the first channel region 1124 are determined according to implementation requirements and are not within the scope of this disclosure. M gate structures 110 may contain M source regions 1122 and M first channel regions 1124; if M is greater than one, the characteristics (e.g., doping concentration) of any two source regions 1122 may be the same or different, depending on implementation requirements; similarly, the characteristics (e.g., length or doping concentration) of any two first channel regions 1124 may be the same or different, depending on implementation requirements.

[0041] Please see Figure 1 , 2 Each gate structure 110 includes a conductive portion 1142 and a non-conductive portion 1144. The size, shape, material, etc., of the conductive portion 1142 and the non-conductive portion 1144 are determined according to implementation requirements and are not within the scope of this disclosure. The conductive portion 1142 is used to receive a gate voltage (e.g., a control signal, ground voltage, or voltage connected to the circuit (VCC)), which controls the on / off state of the fin transistor 100. The non-conductive portion 1144 (e.g., a dielectric layer) is located between the conductive portion 1142 and the first channel region 1124 to separate the conductive portion 1142 from the first channel region 1124. The gate structure 114 is formed on multiple surfaces of the first channel region 1124.

[0042] Please see Figure 1 , Figure 3Each drain end structure 120 includes a second channel structure 122 comprising a second channel region 1222 and a drain region 1224. The size, shape, material, and doping concentration of the second channel region 1222 and the source region 1124 are determined according to implementation requirements and are not within the scope of this disclosure. N drain end structures 120 include N second channel regions 1222 and N drain regions 1224; when N is greater than one, the characteristics (e.g., length or doping concentration) of any two second channel regions 1222 may be the same or different, depending on implementation requirements; similarly, the characteristics (e.g., doping concentration) of any two drain regions 1224 may be the same or different, depending on implementation requirements. It is worth noting that the second channel region 1222 of the drain end structure 120 and the first channel region 1124 of the aforementioned gate end structure 110 are two discontinuous regions; in other words, the channel between the source and drain of the fin transistor 100 is not a continuous channel.

[0043] Please see Figure 1 , Figure 3 Each drain terminal structure 120 has a reduced surface electric field structure 124 formed on multiple surfaces of the second channel region 1222 to optimize the trade-off between on-resistance and breakdown voltage. The size, shape, material, etc., of the reduced surface electric field structure 124 are determined according to implementation requirements and are not within the scope of this disclosure. In one implementation example, both the reduced surface electric field structure 124 and the gate structure 110 are used to receive the aforementioned gate voltage; therefore, the reduced surface electric field structure 124 may be the same as / similar to the gate structure 110, but this is not a limitation of the present invention. In another implementation example, the reduced surface electric field structure 124 is a dielectric film; therefore, the reduced surface electric field structure 124 does not receive the gate voltage and is different from the gate structure 110, but this is not a limitation of the present invention. It is worth noting that the reduced surface electric field structure 124 is not necessary; depending on implementation requirements, the reduced surface electric field structure 124 may be omitted.

[0044] Please see Figure 1 , Figure 4 The conductive structure 130 couples a first channel region 1124 of one of M gate terminal structures 110 to a second channel region 1222 of one of N drain terminal structures 120. For example... Figure 4 As shown, one embodiment of the conductive structure 130 includes a first contact window 132 and a second contact window 134. The first contact window 132 is used to couple a first channel region 1124 of one of the M gate terminal structures 110 to the conductive layer 410; the second contact window 134 is used to couple a second channel region 1222 of one of the N drain terminal structures 120 to the conductive layer 410; the M gate terminal structures 110 and the N drain terminal structures 120 are all located outside the conductive layer.

[0045] Please see Figures 1-5 Yu Ru Figure 5 In one implementation example shown, M is greater than one; the M first channel regions 1124 of the M gate terminal structures 110 are coupled together through (M-1) conductive structures 510, so that the M gate terminal structures 110 are connected in parallel, thereby reducing the on-resistance of the fin transistor 100 at the gate terminal. One embodiment of each conductive structure 510 is similar to Figure 4 The conductive structure 130 includes two contact windows; these two contact windows are used to pass through a conductive layer (e.g.: Figure 4 The conductive layer 410 is used to couple the first channel region 1124 of the two gate terminal structures 110. It is worth noting that, depending on the implementation requirements, a portion of the conductive portion 1142 of the M gate terminal structures 110 can be used to receive a control signal, a ground voltage, or a voltage (VCC) connected to a circuit, while another portion of the conductive portion 1142 of the M gate terminal structures 110 can be used to receive other signals / voltages.

[0046] Please see Figures 1-4 and Figure 6 Yu Ru Figure 6 In one implementation example shown, N is greater than one; the N second channel regions 1222 of the N drain terminal structures 120 are coupled together through (N-1) conductive structures 610, so that the N drain terminal structures 120 are connected in parallel, thereby reducing the on-resistance of the fin transistor 100 at the drain terminal. One embodiment of each conductive structure 610 is similar to Figure 4 The conductive structure 130 includes two contact windows; these two contact windows are used to pass through a conductive layer (e.g.: Figure 4 The conductive layer 410 is used to couple the second channel region 1222 of the two drain end structures 120. It is worth noting that... Figure 6 In practical examples, depending on implementation requirements, the fin transistor 100 may further include one or more drain terminal structures (e.g.: Figure 3 The structure of the N drain end structures 120 is coupled in series with one or more drain end structures.

[0047] Please see Figures 1-4 and Figure 7 Yu Ru Figure 7In one implementation example shown, N is greater than one; the drain region 1224 of a first drain structure 710 of N drain terminal structures 120 is coupled to the second channel region 1222 of a second drain structure 730 of N drain terminal structures 120 through a conductive structure 720, so that the first drain terminal structure 710 and the second drain terminal structure 730 are connected in series, thereby adjusting the on-resistance of the fin transistor 100 at the drain terminal (or adjusting the breakdown voltage affected by this on-resistance). One embodiment of the conductive structure 720 is similar to Figure 4 The conductive structure 130 includes two contact windows; these two contact windows are used to pass through a conductive layer (e.g.: Figure 4 The conductive layer 410 is used to couple the first drain end structure 710 and the second drain end structure 730.

[0048] Please see Figures 5-7 When developing the fin transistor 100, if the on-resistance of the fin transistor 100 is mainly determined by the on-resistance of the gate structure 110, multiple gate structures 110 can be connected in parallel (e.g., Figure 5 (As shown) to reduce the on-resistance of the fin transistor 100; in this case, the number of drain terminal structures 120 (i.e., N) can be one to save circuit area. Similarly, if the on-resistance of the fin transistor 100 is mainly determined by the on-resistance of the drain terminal structure 120, multiple drain terminal structures 120 can be connected in parallel (e.g., Figure 6 (As shown) to reduce the on-resistance of the fin transistor 100; at this time, the number of gate structures 110 (i.e., M) can be one to save circuit area.

[0049] Please note that, where feasible, those skilled in the art may selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement a combination of some or all of the technical features in the foregoing multiple embodiments, thereby increasing the flexibility in implementing the present invention.

[0050] In summary, the fin transistor disclosed herein has a discontinuous channel region, which enables it to simultaneously achieve characteristics such as low on-resistance and high breakdown voltage.

[0051] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on its explicit or implicit content. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

Claims

1. A finned transistor, comprising: M gate terminal structures, each of the M gate terminal structures comprising: A first-channel structure, comprising a source region and a first-channel region; and A gate structure is formed on multiple surfaces of the first channel region; There are N drain endpoint structures, each of which contains: A second channel structure includes a second channel region and a drain region, wherein the second channel region and the first channel region are two discontinuous regions. and A surface electric field reduction structure is formed on multiple surfaces in the second channel region; as well as A conductive structure is used to couple the first channel region of one of the M gate terminal structures to the second channel region of one of the N drain terminal structures. Where M is a positive integer and N is a positive integer.

2. The finned transistor of claim 1, wherein at least one of M and N is greater than one.

3. The finned transistor as claimed in claim 2, wherein M is greater than one, and the M first channel regions of the M gate terminal structures are coupled together through (M-1) first conductive structures to connect the M gate terminal structures in parallel.

4. The finned transistor of claim 2, wherein N is greater than one, and the N second channel regions of the N drain terminal structures are coupled together through (N-1) second conductive structures to connect the N drain terminal structures in parallel.

5. The fin transistor of claim 2, wherein N is greater than one, and the drain region of a first drain terminal structure of the N drain terminal structures is coupled to the second channel region of a second drain terminal structure of the N drain terminal structures through a second conductive structure, so that the first drain terminal structure and the second drain terminal structure are connected in series.

6. The fin transistor of claim 1, wherein both the reduced surface electric field structure and the gate structure are used to receive a gate voltage.

7. The fin transistor of claim 1, wherein the reduced surface electric field structure is a dielectric film.

8. The finned transistor of claim 1, wherein the conductive structure includes a first contact window and a second contact window, the first contact window being used to couple the first channel region of one of the M gate terminal structures to a conductive layer, and the second contact window being used to couple the second channel region of one of the N drain terminal structures to the conductive layer.

9. The finned transistor of claim 1, wherein the length of each of the M gate structures is a first length, and the length of each of the N drain structures is a second length, the first length being equal to the second length.

10. A finned transistor, comprising: M gate terminal structures, each of the M gate terminal structures comprising: A first-channel structure, comprising a source region and a first-channel region; and A gate structure is formed on multiple surfaces of the first channel region; There are N drain endpoint structures, each of which contains: A second channel structure comprising a second channel region and a drain region, wherein the second channel region and the first channel region are two discontinuous regions; and A conductive structure is used to couple the first channel region of one of the M gate terminal structures to the second channel region of one of the N drain terminal structures. Where M is a positive integer, N is a positive integer, and at least one of M and N is greater than one; if M is greater than one, the M gate terminal structures are coupled together; if N is greater than one, the N drain terminal structures are coupled together.

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