Tft backplane for improving the grayish appearance of electronic paper and preparation method thereof

Abstract

The application provides a TFT back plate for improving the ashing of electronic paper frame and a preparation method thereof. The TFT back plate comprises a display area provided with a plurality of normal pixels and a boundary area provided with a plurality of virtual pixels. The plurality of normal pixels and virtual pixels are arranged in a matrix. The gate layer of each row of normal pixels is electrically connected with a horizontal scanning line. The source layer of each column of normal pixels is electrically connected with a vertical scanning line. The virtual pixel comprises a virtual pixel TFT and a virtual common electrode layer. The virtual pixel TFT is arranged in an insulated and spaced manner with the horizontal scanning line and / or the vertical scanning line. An electronic film paper is arranged above the virtual pixel. The common electrode layer of the electronic film paper is electrically connected with the virtual common electrode layer. The pixel electrode layer of the electronic film paper is electrically connected with a driving IC through a boundary line. The virtual pixel TFT is arranged in an insulated and spaced manner with the horizontal scanning line and / or the vertical scanning line, so that the horizontal scanning line and / or the vertical scanning line is prevented from controlling the virtual pixel TFT to be turned on or off, thereby avoiding the ashing.

Description

Technical Field

[0001] This invention relates to the field of electronic paper display panel technology, and more specifically, to a TFT backplate for improving graying of the electronic paper bezel and its preparation method. Background Technology

[0002] Electronic paper e-ink displays feature ultra-low power consumption, low-frequency display, and energy saving, and are widely used in price tags, advertising signs, and bus stop signs. (See also...) Figure 1 and Figure 2 As shown, in existing electronic paper ink screens, in order to ensure that the four edges of the display area 1 can also be displayed normally, a boundary area 2 is usually set around the display area 1. Normal pixels 3 are set inside the display area 1, and virtual pixels 4 are set inside the boundary area 2.

[0003] In a traditional normal pixel 3, color display is achieved by controlling the voltage on both sides of the electronic film paper. Generally, the common electrode layer 71 on one side of the electronic film paper 7 is electrically connected to the common electrode layer 35 of the normal pixel 3, and the pixel electrode layer 72 on the other side of the electronic film paper 7 is electrically connected to the drain layer 33 in the pixel TFT of the normal pixel 3. However, the virtual pixel 4 within the boundary region 2 does not have charging and discharging functions. Therefore, the pixel electrode layer 72 of the electronic film paper 7 above it is directly electrically connected to the driver IC 6 through the boundary line 53, without the need for virtual pixel TFT control of the virtual pixel 4.

[0004] However, in the traditional design, the internal structure of the virtual pixel 4 is the same as that of the normal pixel 3, and the connection method is also the same. The gate of each row is electrically connected to the horizontal scan line 51, and the source of each column is electrically connected to the vertical scan line 52. Only the connection method of the electronic film paper above the virtual pixel is changed. Therefore, in actual use, the virtual pixel TFT of the virtual pixel 4 will still have the situation of being switched on and off. This will cause interference signals in the pixel electrode layer of the connected electronic film paper, resulting in graying of the boundary area display. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a TFT backplate that improves the graying of the electronic paper bezel, thereby solving the problem of graying of the electronic paper bezel in the prior art.

[0006] The technical solution adopted by this invention to solve the above problems is as follows: a TFT backplane for improving the graying of the electronic paper bezel, comprising a display area and a boundary area surrounding the display area. The display area contains multiple normal pixels, and the boundary area contains multiple virtual pixels. The normal pixels and virtual pixels are arranged in a matrix. The gate layer of each row of normal pixels is electrically connected to a horizontal scan line, and the source layer of each column of normal pixels is electrically connected to a vertical scan line. Both the horizontal and vertical scan lines are electrically connected to a driver IC.

[0007] Each virtual pixel includes a virtual pixel TFT and a virtual pixel capacitor. The virtual pixel TFT is disposed insulated and spaced from the horizontal scan lines and / or the vertical scan lines. The virtual pixel capacitor includes a virtual common electrode layer.

[0008] Each virtual pixel is provided with an electronic film paper above it. The common electrode layer on one side of each electronic film paper is electrically connected to the corresponding virtual common electrode layer, and the pixel electrode layer on the other side of each electronic film paper is electrically connected to the driver IC through a boundary line.

[0009] Compared with the prior art, the advantages of the present invention are: the virtual pixel TFT is set to be insulated from the horizontal scan lines and / or vertical scan lines, so as to prevent the horizontal scan lines and / or vertical scan lines from controlling the virtual pixel TFT to turn on and off, avoid the virtual pixel TFT from interfering with the pixel electrode layer, so that the virtual pixels in the boundary area can be displayed normally and avoid graying.

[0010] Preferably, the virtual pixel TFT includes a virtual gate layer, a virtual source layer, and a column connection layer; a first insulating layer is disposed above the virtual gate layer, a second insulating layer is disposed above the first insulating layer, the electronic film is disposed above the second insulating layer, the virtual source layer and the column connection layer are disposed in the same layer and are both disposed between the first insulating layer and the second insulating layer, the column connection layer is electrically connected to the column scan lines, and the virtual gate layer is electrically connected to the horizontal scan lines.

[0011] The technical effects achieved by adopting this technical solution are as follows: the virtual semiconductor layer and virtual drain layer of the virtual pixel TFT are removed, leaving only the virtual gate layer and virtual source layer, thus avoiding the transmission of signals from the virtual source layer to the pixel electrode layer, cutting off the connection of the virtual pixel TFT, and avoiding signal interference.

[0012] Preferably, the virtual source layer and the column connection layer are electrically connected.

[0013] The technical effect achieved by adopting this technical solution is that by electrically connecting the two layers, they can be combined into one layer during actual manufacturing, reducing the number of manufacturing steps.

[0014] Preferably, the virtual pixel TFT further includes a virtual drain layer, which is disposed between the first insulating layer and the second insulating layer, and the virtual drain layer is spaced apart from the virtual source layer.

[0015] The technical effects achieved by adopting this technical solution are as follows: only the virtual semiconductor layer of the virtual pixel TFT is removed, while the virtual gate layer, virtual source layer and virtual drain layer are retained. This can effectively avoid the connection between the virtual source layer and the virtual drain layer and avoid signal interference. Moreover, by only removing the virtual semiconductor layer, compared with the existing normal pixel, only one step is reduced in manufacturing process, requiring less modification to the manufacturing process and making the operation convenient.

[0016] Preferably, the virtual pixel TFT further includes a virtual semiconductor layer, which is disposed between a first insulating layer and a second insulating layer above the virtual gate layer. The virtual source layer and the virtual drain layer are both disposed at intervals above the virtual semiconductor layer, and the virtual source layer and the virtual drain layer are both electrically connected to the virtual semiconductor layer. The virtual source layer and the column connection layer are disposed at an insulating interval.

[0017] The technical effect achieved by adopting this technical solution is as follows: by setting an insulating gap between the virtual source layer and the vertical connection layer while retaining the complete structure of the entire virtual pixel TFT, the signal can be effectively prevented from entering the virtual source layer, thus playing a signal isolation role and avoiding signal interference.

[0018] Another technical solution adopted by the present invention to solve the above problems is: a method for preparing a TFT backplane to improve the graying of the electronic paper bezel, comprising the following steps:

[0019] S1. A glass substrate is provided, in which a plurality of normal pixels are disposed in a display area on the glass substrate, and a plurality of virtual pixels are disposed in a boundary area around the display area on the glass substrate, wherein the plurality of normal pixels and virtual pixels are arranged in a matrix; a gate layer and a common electrode layer are disposed at intervals in each normal pixel on the glass substrate, and a virtual gate layer and a virtual common electrode layer are disposed at intervals in each virtual pixel on the glass substrate.

[0020] S2. A first insulating layer is provided above each gate layer, common electrode layer, dummy gate layer and dummy common electrode layer;

[0021] S3. A semiconductor layer is disposed above the first insulating layer on each gate layer, a source layer and a drain layer are disposed at intervals on each semiconductor layer, and a virtual source layer and a column connection layer are disposed at intervals above the first insulating layer on each virtual gate layer.

[0022] S4. A second insulating layer is provided above each semiconductor layer, source layer, drain layer, virtual source layer and column interconnect layer;

[0023] S5. An electronic film is disposed on the second insulating layer above each normal pixel and virtual pixel, and a via is disposed in the second insulating layer for electrically connecting the drain layer and the pixel electrode layer of the corresponding electronic film.

[0024] Compared with the prior art, the advantages of the present invention are: no virtual semiconductor layer and virtual drain layer are set in the virtual pixel, thus avoiding the transmission of signals in the vertical connection layer to the pixel electrode layer, avoiding interference of the virtual pixel TFT to the pixel electrode layer, so that the boundary area can be displayed normally and avoiding graying.

[0025] Preferably, in step S3, the virtual source layer and the column connection layer are combined.

[0026] The technical effects achieved by adopting this technical solution are: merging the two layers ensures that the virtual source layer and the column connection layer can be electrically connected, and only one layer needs to be made after merging, reducing the number of manufacturing steps.

[0027] Preferably, in step S3, a virtual drain layer is further provided on the first insulating layer above each virtual gate layer, and the virtual drain layer is provided with an insulating gap from the virtual source layer.

[0028] The technical effects achieved by adopting this technical solution are as follows: only the virtual semiconductor layer of the virtual pixel TFT is removed, while the virtual gate layer, virtual source layer and virtual drain layer are retained. This can effectively avoid the connection between the virtual source layer and the virtual drain layer and avoid signal interference. Moreover, by only removing the virtual semiconductor layer, compared with the existing normal pixel, only one step is reduced in manufacturing process, requiring less modification to the manufacturing process and making the operation convenient.

[0029] Preferably, in step S3, a virtual semiconductor layer is provided on the first insulating layer above each virtual gate layer, a virtual drain layer is provided on one side of the virtual semiconductor layer, the virtual source layer is placed on the other side of the virtual semiconductor layer, and the virtual source layer is provided with an insulating gap from the column connection layer.

[0030] The technical effect achieved by adopting this technical solution is as follows: by setting an insulating gap between the virtual source layer and the vertical connection layer while retaining the complete structure of the entire virtual pixel TFT, the signal can be effectively prevented from entering the virtual source layer, thus playing a signal isolation role and avoiding signal interference. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the backplane structure of an electronic paper TFT in the prior art;

[0032] Figure 2 Cross-sectional views of normal pixels and virtual pixels of the backplane of electronic paper TFT in the prior art;

[0033] Figure 3This is a schematic diagram of the overall structure of a TFT backplate for improving graying of electronic paper bezels according to the present invention.

[0034] Figure 4 This is a schematic diagram of the structure of normal pixels and virtual pixels in a TFT backplane that improves graying of the electronic paper bezel according to the present invention;

[0035] Figure 5 For the present invention Figure 4 A cross-sectional view along line aa;

[0036] Figure 6 This is a schematic diagram of the structure of normal pixels and virtual pixels in a TFT backplane that improves graying of the electronic paper bezel according to the present invention;

[0037] Figure 7 For the present invention Figure 6 A sectional view along the middle edge of bb;

[0038] Figure 8 This is a schematic diagram of the structure of normal pixels and virtual pixels in a TFT backplane that improves graying of the electronic paper bezel according to the present invention;

[0039] Figure 9 For the present invention Figure 8 A sectional view along the middle edge cc.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Display area;

[0042] 2-Boundary area;

[0043] 3-Normal pixel; 31-Gate layer; 32-Source layer; 33-Drain layer; 34-Semiconductor layer; 35-Common electrode layer; 36-Via;

[0044] 4-Virtual pixel; 41-Virtual gate layer; 42-Virtual source layer; 43-Virtual drain layer; 44-Virtual semiconductor layer; 45-Virtual common electrode layer; 46-Vertical interconnect layer; 47-First insulating layer; 48-Second insulating layer;

[0045] 51 - Horizontal scan line; 52 - Vertical scan line; 53 - Boundary line;

[0046] 6-Driver IC;

[0047] 7-Electronic film paper; 71-Common electrode layer; 72-Pixel electrode layer;

[0048] 8-Glass substrate. Detailed Implementation

[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Example 1

[0051] like Figures 3-5 As shown, this embodiment relates to a TFT backplate for improving the graying of the electronic paper frame, including a display area 1 and a boundary area 2 surrounding the display area 1. The display area 1 is provided with a plurality of normal pixels 3, and the boundary area 2 is provided with a plurality of virtual pixels 4.

[0052] Multiple normal pixels 3 and virtual pixels 4 are arranged in a matrix. The virtual gate layer 41 of each row of normal pixels 3 is electrically connected to a horizontal scan line 51, and the virtual source layer 42 of each column of normal pixels 3 is electrically connected to a vertical scan line 52. The horizontal scan line 51 and the vertical scan line 52 are both electrically connected to the driver IC 6.

[0053] In this embodiment, each virtual pixel 4 includes a virtual pixel TFT and a virtual pixel capacitor. The virtual pixel TFT is insulated from the horizontal scan line 51 and / or the vertical scan line 52. The virtual pixel capacitor includes a virtual common electrode layer 45.

[0054] Each virtual pixel 4 is provided with an electronic film 7 above it. The common electrode layer 71 on one side of each electronic film 7 is electrically connected to the corresponding virtual common electrode layer 45. The pixel electrode layer 72 on the other side of each electronic film 7 is electrically connected to the driver IC 6 through a boundary line 53.

[0055] By insulating the virtual pixel TFT from the horizontal scan line 51 and / or the vertical scan line 52, the horizontal scan line 51 and / or the vertical scan line 52 are prevented from controlling the virtual pixel TFT to turn on and off, thus avoiding interference from the virtual pixel TFT to the pixel electrode layer 72. This allows the boundary area 2 to be displayed normally and prevents graying.

[0056] In practical use, the virtual gate layer 41 in the virtual pixel TFT can be isolated from the horizontal scan line 51, and the virtual source layer 42 in the virtual pixel TFT can be isolated from the vertical scan line 52.

[0057] Specifically, in this embodiment, the virtual pixel TFT includes a virtual gate layer 41, a virtual source layer 42, and a column connection layer 46;

[0058] A first insulating layer 47 is provided above the virtual gate layer 41, and a second insulating layer 48 is provided above the first insulating layer 47. The electronic film 7 is placed above the second insulating layer 48. The virtual source layer 42 and the column connection layer 46 are disposed on the same layer and are both placed between the first insulating layer 47 and the second insulating layer 48. The column connection layer 46 is electrically connected to the column scan line 52, and the virtual gate layer 41 is electrically connected to the horizontal scan line 51.

[0059] The virtual semiconductor layer 44 and virtual drain layer 43 of the virtual pixel TFT are removed, leaving only the virtual gate layer 41 and virtual source layer 42. This prevents the signal from the virtual source layer 42 from being transmitted to the pixel electrode layer 72, thus cutting off the connection of the virtual pixel TFT and avoiding signal interference.

[0060] The virtual source layer 42 and the vertical connection layer 46 are electrically connected. By electrically connecting the two layers, they can be combined into one layer during actual manufacturing, reducing the number of manufacturing steps.

[0061] Correspondingly, this embodiment provides a method for preparing a TFT backplane to improve the graying of the electronic paper bezel, comprising the following steps:

[0062] S1. A glass substrate 8 is provided. Multiple normal pixels 3 are disposed in a display area 1 on the glass substrate 8, and multiple virtual pixels 4 are disposed in a boundary area 2 around the display area 1 on the glass substrate 8. The multiple normal pixels 3 and virtual pixels 4 are arranged in a matrix. A gate layer 31 and a common electrode layer 35 are disposed at intervals in each normal pixel 3 on the glass substrate 8, and a virtual gate layer 41 and a virtual common electrode layer 45 are disposed at intervals in each virtual pixel 4 on the glass substrate 8.

[0063] S2. A first insulating layer 47 is provided above each gate layer 31, common electrode layer 35, dummy gate layer 41 and dummy common electrode layer 45.

[0064] S3. A semiconductor layer 34 is disposed on the first insulating layer 47 of each gate layer 31, and a source layer 32 and a drain layer 33 are disposed at intervals on each semiconductor layer 34. A virtual source layer 42 and a column connection layer 46 are disposed at intervals above the first insulating layer 47 of each virtual gate layer 41.

[0065] S4. A second insulating layer 48 is provided above each virtual source layer 32, virtual drain layer 33, semiconductor layer 34, virtual source layer 42 and column interconnect layer 46;

[0066] S5. An electronic film 7 is provided on the second insulating layer 48 above each normal pixel 3 and virtual pixel 4. A via 36 is provided in the second insulating layer 48 for electrically connecting the drain layer 33 and the pixel electrode layer 72 corresponding to the electronic film 7.

[0067] In step S3, the virtual source layer 42 and the column connection layer 46 are combined and configured.

[0068] By merging the two layers, the virtual source layer 42 and the column connection layer 46 can be electrically connected. After merging, only one layer needs to be manufactured, reducing the manufacturing steps. Of course, in actual use, they can also be set up with insulation staggered.

[0069] In this embodiment, compared to the normal pixel 3, the structure of the virtual pixel TFT in the virtual pixel 4 is completely destroyed, thereby achieving a disconnection setting and preventing the signal from entering the pixel electrode layer 72 of the electronic film paper 7 through the virtual pixel TFT.

[0070] Furthermore, in this embodiment, a virtual semiconductor layer 44 may also be disposed below the virtual source layer 42 and the column connection layer 46.

[0071] Example 2

[0072] See Figure 6 and Figure 7 As shown, this embodiment is basically the same as Embodiment 1, except that this embodiment also includes the following structure:

[0073] The virtual pixel TFT also includes a virtual drain layer 43, which is placed between the first insulating layer 47 and the second insulating layer 48, and the virtual drain layer 43 is spaced apart from the virtual source layer 42.

[0074] By removing only the virtual semiconductor layer 44 of the virtual pixel TFT, while retaining the virtual gate layer 41, virtual source layer 42, and virtual drain layer 43, the connection between the virtual source layer 42 and the virtual drain layer 43 can be effectively avoided, thus preventing signal interference. Moreover, by removing only the virtual semiconductor layer 44, compared to the existing normal pixel 3, only one step is missing in the manufacturing process, requiring less modification to the manufacturing process and making the operation more convenient.

[0075] Therefore, in the method for preparing a TFT backplane that improves the graying of the electronic paper frame in this embodiment, in step S3, a virtual drain layer 43 is also provided on the first insulating layer 47 above each virtual gate layer 41, and the virtual drain layer 43 and the virtual source layer 42 are provided with an insulating gap.

[0076] By removing only the virtual semiconductor layer 44 of the virtual pixel TFT, while retaining the virtual gate layer 41, virtual source layer 42, and virtual drain layer 43, the connection between the virtual source layer 42 and the virtual drain layer 43 can be effectively avoided, thus preventing signal interference. Moreover, by removing only the virtual semiconductor layer 44, compared to the existing normal pixel 3, only one step is missing in the manufacturing process, requiring less modification to the manufacturing process and making the operation more convenient.

[0077] Of course, in this embodiment, a virtual semiconductor layer 44 can also be fabricated below the virtual drain layer 43 and the virtual source layer 42, and the two virtual semiconductor layers 44 are arranged with an insulating gap. This can also play an isolation role, preventing signals from entering the pixel electrode layer 72 of the electronic film paper 7 through the virtual pixel TFT.

[0078] Example 3

[0079] See Figure 8 and Figure 9 As shown, this embodiment is basically the same as embodiment two, except that this embodiment also includes the following structure:

[0080] The virtual pixel TFT also includes a virtual semiconductor layer 44, which is placed between a first insulating layer 47 and a second insulating layer 48 above the virtual gate layer 41. The virtual source layer 42 and the virtual drain layer 43 are both disposed above the virtual semiconductor layer 44 at intervals, and the virtual source layer 42 and the virtual drain layer 43 are both electrically connected to the virtual semiconductor layer 44. The virtual source layer 42 and the column connection layer 46 are insulated and spaced apart.

[0081] In preserving the complete structure of the entire virtual pixel TFT, the virtual source layer 42 and the column connection layer 46 are set with an insulating gap, which can effectively prevent signals from entering the virtual source layer 42, play a signal isolation role, and avoid signal interference.

[0082] Therefore, in the method for preparing a TFT backplane that improves the graying of the electronic paper frame in this embodiment, in step S3, a virtual semiconductor layer 44 is provided on the first insulating layer 47 above each virtual gate layer 41, a virtual drain layer 43 is provided on one side of the virtual semiconductor layer 44, a virtual source layer 42 is placed on the other side of the virtual semiconductor layer 44, and the virtual source layer 42 is provided with an insulating gap from the column connection layer 46.

[0083] In preserving the complete structure of the entire virtual pixel TFT, the virtual source layer 42 and the column connection layer 46 are set with an insulating gap, which can effectively prevent signals from entering the virtual source layer 42, play a signal isolation role, and avoid signal interference.

[0084] The beneficial effects of the present invention are as follows: by setting the virtual pixel TFT to be insulated from the horizontal scan line 51 and / or the vertical scan line 52, the horizontal scan line 51 and / or the vertical scan line 52 are prevented from controlling the virtual pixel TFT to turn on and off, thus avoiding interference of the virtual pixel TFT to the pixel electrode layer 72, so that the boundary area 2 can be displayed normally and avoid graying.

[0085] The foregoing description illustrates and describes several preferred embodiments of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

[0086] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. A TFT backplane for improving graying of electronic paper bezels, comprising a display area (1) and a boundary area (2) surrounding the display area (1), wherein the display area (1) is provided with a plurality of normal pixels (3), and the boundary area (2) is provided with a plurality of virtual pixels (4), wherein the plurality of normal pixels (3) and virtual pixels (4) are arranged in a matrix, wherein the gate layer (31) of each row of normal pixels (3) is electrically connected to a horizontal scan line (51), and the source layer (32) of each column of normal pixels (3) is electrically connected to a vertical scan line (52), wherein the horizontal scan line (51) and the vertical scan line (52) are electrically connected to a driver IC (6), characterized in that: Each of the virtual pixels (4) includes a virtual pixel TFT and a virtual pixel capacitor, wherein the virtual pixel TFT is provided insulated from the horizontal scan line (51) and / or the vertical scan line (52), and the virtual pixel capacitor includes a virtual common electrode layer (45). An electronic film (7) is provided above each virtual pixel (4). The common electrode layer (71) on one side of each electronic film (7) is electrically connected to the corresponding virtual common electrode layer (45). The pixel electrode layer (72) on the other side of each electronic film (7) is electrically connected to the driver IC (6) through a boundary line (53). The virtual pixel TFT includes a virtual gate layer (41), a virtual source layer (42), and a column connection layer (46). A first insulating layer (47) is provided above the virtual gate layer (41), and a second insulating layer (48) is provided above the first insulating layer (47). The electronic film paper (7) is placed above the second insulating layer (48). The virtual source layer (42) and the column connection layer (46) are disposed on the same layer and are both placed between the first insulating layer (47) and the second insulating layer (48). The column connection layer (46) is electrically connected to the column scan line (52), and the virtual gate layer (41) is electrically connected to the horizontal scan line (51).

2. The TFT backplate for improving graying of electronic paper bezels according to claim 1, characterized in that: The virtual source layer (42) and the column connection layer (46) are electrically connected.

3. The TFT backplate for improving graying of electronic paper bezels according to claim 1, characterized in that: The virtual pixel TFT also includes a virtual drain layer (43), which is placed between the first insulating layer (47) and the second insulating layer (48), and the virtual drain layer (43) is spaced apart from the virtual source layer (42).

4. A TFT backplate for improving graying of electronic paper bezels according to claim 1, characterized in that: The virtual pixel TFT further includes a virtual semiconductor layer (44), which is placed between a first insulating layer (47) and a second insulating layer (48) above the virtual gate layer (41). The virtual source layer (42) and the virtual drain layer (43) are both spaced above the virtual semiconductor layer (44), and the virtual source layer (42) and the virtual drain layer (43) are both electrically connected to the virtual semiconductor layer (44). The virtual source layer (42) and the column connection layer (46) are insulated from each other.

5. A method for preparing a TFT backplate for improving graying of the electronic paper bezel, used to prepare the TFT backplate for improving graying of the electronic paper bezel as described in any one of claims 1-4, characterized in that: Includes the following steps: S1. A glass substrate (8) is provided, in which a plurality of normal pixels (3) are provided in a display area (1) on the glass substrate (8), and a plurality of virtual pixels (4) are provided in a boundary area (2) around the display area (1) on the glass substrate (8). The plurality of normal pixels (3) and virtual pixels (4) are arranged in a matrix. A gate layer (31) and a common electrode layer (35) are provided at intervals in each normal pixel (3) on the glass substrate (8), and a virtual gate layer (41) and a virtual common electrode layer (45) are provided at intervals in each virtual pixel (4) on the glass substrate (8). S2. A first insulating layer (47) is provided above each gate layer (31), common electrode layer (35), dummy gate layer (41) and dummy common electrode layer (45). S3. A semiconductor layer (34) is disposed above the first insulating layer (47) on each gate layer (31), and a source layer (32) and a drain layer (33) are disposed at intervals on each semiconductor layer (34), and a virtual source layer (42) and a column connection layer (46) are disposed at intervals above the first insulating layer (47) on each virtual gate layer (41). S4. A second insulating layer (48) is provided above each source layer (32), drain layer (33), semiconductor layer (34), virtual source layer (42) and column interconnect layer (46); S5. An electronic film paper (7) is provided on the second insulating layer (48) above each normal pixel (3) and virtual pixel (4). A via (36) for electrically connecting the drain layer (33) and the pixel electrode layer (72) of the corresponding electronic film paper (7) is provided in the second insulating layer (48).

6. The method for preparing a TFT backplane to improve graying of the electronic paper bezel according to claim 5, characterized in that: In step S3, the virtual source layer (42) and the column connection layer (46) are combined.

7. The method for preparing a TFT backplane to improve graying of the electronic paper bezel according to claim 6, characterized in that: In step S3, a virtual drain layer (43) is provided above the first insulating layer (47) on each virtual gate layer (41), and the virtual drain layer (43) is provided with an insulating gap from the virtual source layer (42).

8. The method for preparing a TFT backplane to improve graying of the electronic paper bezel according to claim 5, characterized in that: In step S3, a virtual semiconductor layer (44) is provided on the first insulating layer (47) above each virtual gate layer (41). A virtual drain layer (43) is provided on one side of the virtual semiconductor layer (44), and a virtual source layer (42) is placed on the other side of the virtual semiconductor layer (44). The virtual source layer (42) is insulated from the column connection layer (46).

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