Neuron cluster allocation method and apparatus for network simulation

Abstract

The present disclosure provides a neuron cluster allocation method and device for network simulation, the method comprising: obtaining a plurality of target neuron clusters corresponding to a neural network; pre-allocating the plurality of target neuron clusters to a plurality of processing cores, wherein each of at least some of the processing cores corresponds to pre-allocation of at least one target neuron cluster, and the size of the current cluster memory occupied by all target neuron clusters pre-allocated to the processing cores is less than or equal to the current available cluster memory size corresponding to the processing cores, the current available cluster memory size being equal to the difference between the available memory size and the current preset routing memory size; obtaining an estimated routing memory size currently required to be occupied by all target neuron clusters pre-allocated in the processing cores; when the estimated routing memory size corresponding to at least one of the processing cores is greater than the current preset routing memory size, adjusting the current preset routing memory size, and returning to the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the core system.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of network simulation, and in particular to a neuron cluster allocation method and device for network simulation, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] A neuron cluster is borrowed from the concept of a neuron cluster in the human brain, representing a collection of neurons. A core is the smallest computing unit in a brain-like chip (such as a many-core chip), which can also be referred to as a computing core or a processing core. A brain-like chip is composed of a plurality of cores. A logical neuron cluster refers to a logical neuron cluster represented in a brain-like computing network model (such as a spiking neural network model, a convolutional neural network model, etc.). In the related art, before network simulation is performed, each logical neuron cluster of a network model needs to be allocated and deployed to a corresponding core in a brain-like chip to implement the running of the brain-like computing network model. SUMMARY

[0003] The present disclosure provides a neuron cluster allocation method and device for network simulation, an electronic device, and a computer readable storage medium.

[0004] In a first aspect, the present disclosure provides a neuron cluster allocation method for network simulation, comprising:

[0005] obtaining a plurality of target neuron clusters to be allocated corresponding to a neural network to be simulated;

[0006] pre-allocating the plurality of target neuron clusters to a plurality of processing cores of a many-core system, wherein each processing core in at least part of the processing cores corresponds to pre-allocation of at least one target neuron cluster, and the current cluster memory size occupied by all target neuron clusters pre-allocated to the processing core is less than or equal to the current available cluster memory size corresponding to the processing core, which is equal to the difference between the available memory size of the processing core and the current preset routing memory size;

[0007] for each processing core in the at least part of the processing cores, obtaining an estimated routing memory size currently required to be occupied by all target neuron clusters pre-allocated in the processing core;

[0008] when there is at least one processing core in the at least part of the processing cores whose current corresponding estimated routing memory size is greater than the current preset routing memory size, adjusting the current preset routing memory size, and returning to perform the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system, until the current corresponding estimated routing memory size of each processing core in the at least part of the processing cores is less than or equal to the current preset routing memory size.

[0009] In a second aspect, the present disclosure provides a neuron cluster allocation apparatus for network simulation, the neuron cluster allocation apparatus comprising:

[0010] an obtaining unit configured to obtain a plurality of target neuron clusters to be allocated corresponding to a neural network to be simulated;

[0011] a pre-allocating unit configured to pre-allocate the plurality of target neuron clusters to a plurality of processing cores of a many-core system, wherein each of at least some of the processing cores is pre-allocated with at least one target neuron cluster, and a current cluster memory size occupied by all the target neuron clusters pre-allocated to the processing core is less than or equal to a current available cluster memory size corresponding to the processing core, the current available cluster memory size corresponding to the processing core being equal to a difference between an available memory size of the processing core and a current preset routing memory size;

[0012] a calculating unit configured to, for each of the at least some of the processing cores, obtain an estimated routing memory size currently required to be occupied by all the target neuron clusters pre-allocated in the processing core;

[0013] an iterating unit configured to, when there is at least one processing core in the at least some of the processing cores whose corresponding estimated routing memory size is greater than the current preset routing memory size, adjust the current preset routing memory size, and return to perform the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system until the estimated routing memory size corresponding to each of the at least some of the processing cores is less than or equal to the current preset routing memory size.

[0014] In a third aspect, the present disclosure provides an electronic device, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein

[0017] the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the neuron cluster allocation method of the first aspect.

[0018] In a fourth aspect, the present disclosure provides a computer-readable storage medium, the medium storing a computer program, the computer program being executed by a processor to implement the neuron cluster allocation method of the first aspect.

[0019] The technical scheme of the neuron cluster allocation method for network simulation according to the embodiment of the present disclosure sets the current preset routing memory size, and determines the current available cluster memory size corresponding to each processing core according to the difference between the available memory size of the processing core and the current preset routing memory size. In the pre-allocation, the plurality of target neuron clusters to be allocated are pre-allocated to at least part of the processing cores based on the current available cluster memory size corresponding to each processing core. After the pre-allocation, the estimated routing memory size corresponding to each processing core pre-allocated with at least one target neuron cluster is evaluated, and the estimated routing memory size is compared with the current preset routing memory size. If the estimated routing memory size corresponding to at least one processing core exceeds the current preset routing memory size, the current preset routing memory size is adjusted, and the current available cluster memory size corresponding to each processing core is also adaptively adjusted. The plurality of target neuron clusters to be allocated are re-pre-allocated based on the adjusted current preset routing memory size, until the current preset routing memory size is adjusted to a suitable value, so that the estimated routing memory size corresponding to each processing core is less than or equal to the current preset routing memory size. In this way, the memory size of the routing required for each processing core during simulation can be calculated, that is, the current preset routing memory size. At the same time, since the pre-allocation is based on the current available cluster memory size corresponding to each processing core, and the current available cluster memory size corresponding to each processing core is the difference between the available memory size of each processing core and the current preset routing memory size, the memory overflow situation can be improved when the neuron cluster is actually allocated to the processing core for running.

[0020] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure serve to explain the present disclosure, and do not constitute a limitation on the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of the specific example embodiments, with reference to the accompanying drawings, in which:

[0022] Figure 1 A flowchart of a neuron cluster allocation method for network simulation is provided for the embodiment of the present disclosure;

[0023] Figure 2 A structural diagram of a neuron cluster allocation device for network simulation is provided for the embodiment of the present disclosure;

[0024] Figure 3 A composition block diagram of an electronic device is provided for the embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the drawings, including various details of the embodiments of the present disclosure to help understanding, which should be considered only as exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0026] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0027] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] The terms used herein are only used to describe specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" and / or "consist of", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "connected" or "coupled" and / or similar terms are not limited to a physical or mechanical connection, but can include an electrical connection, whether direct or indirect.

[0029] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly idealized or overly formal sense unless expressly so defined herein.

[0030] In the embodiments of the present disclosure, a network simulation system can be used to run a brain-like computing network (such as a convolutional neural network, a spiking neural network, etc.), simulate the intelligent behavior function of the brain neural network of the brain by simulating the brain neural network structure and information processing mechanism of the human brain. The brain-like computing network can be used to perform image processing tasks, speech processing tasks, text processing tasks, etc., and the present disclosure does not limit the specific task type performed by the brain-like computing network. The network simulation system can include a plurality of computing nodes, and the brain-like computing network is deployed on the plurality of computing nodes (such as chips or servers) to implement parallel simulation.

[0031] In some embodiments, the network simulation system can run on a many-core system, where the many-core system can include one or more many-core chips, the many-core chips are composed of a plurality of processing cores and a NoC (Network-on-Chip) between the processing cores, the many-core chips are chips based on a many-core architecture of memory computing integration, each processing core is a smallest unit that can be independently scheduled and has complete computing capability on the many-core chip, and each processing core has an independent on-chip memory. In the many-core chip, the processing cores are responsible for completing the main computation, and the NoC is responsible for transmitting data between the processing cores.

[0032] In some embodiments, in the case that the network simulation system runs on a many-core system, the computing nodes in the network simulation system can include one or more processing cores in a many-core chip for running a certain number of neurons in a brain-like computing network.

[0033] In some embodiments, in the network simulation system, the brain-like computing network includes a plurality of neuron clusters, and each neuron cluster is a logical neuron cluster.

[0034] Before network simulation, the plurality of neuron clusters of the brain-like computing network need to be allocated and deployed to corresponding processing cores in the many-core system to run the brain-like computing network on the many-core system, so as to achieve corresponding computing task processing.

[0035] In the simulation of the spiking neural network, for each computing node, the neurons running on the computing node perform computation and update of their own membrane potential in response to receiving pulse information of other neurons (neurons of other computing nodes or other neurons of the computing node), and when the own membrane potential reaches a firing threshold, the pulse information is fired to the target neurons (neurons of other computing nodes or other neurons of the computing node) to drive the target neurons to perform computation.

[0036] In the related art, when the plurality of neuron clusters of the brain-like computing network are allocated and deployed to corresponding processing cores in the many-core system, the allocation and deployment of the neuron clusters are usually based on the memory size required to be occupied by the neuron clusters, that is, only the memory size required to be occupied by the neuron clusters is considered. However, in actual operation, data communication and interaction between different neuron clusters is also required, and the data communication and interaction between different neuron clusters also consumes a certain memory size (referred to as routing memory size). Since the routing memory size is not considered when the neuron clusters are allocated and deployed, when the upper layer compiles too many neuron clusters to be allocated to a single processing core at the bottom layer, a memory overflow situation may be caused due to too much routing memory size consumption, thereby affecting the running effect of the brain-like computing network.

[0037] To this end, the embodiments of the present disclosure provide a neuron cluster allocation method for network simulation, which aims to effectively solve the technical problems existing in the related art.

[0038] Figure 1 A flowchart of a method for allocating neuron clusters for network simulation is provided for the embodiments of the present disclosure. The embodiments of the present disclosure provide a method for allocating neuron clusters for network simulation. As shown in the figure, the method for allocating neuron clusters for network simulation comprises the following steps. Figure 1

[0039] In step S11, a plurality of target neuron clusters to be allocated corresponding to a neural network to be simulated are obtained.

[0040] The neural network to be simulated is a brain-like computing network as described above. For example, the neural network to be simulated can be a spiking neural network or a convolutional neural network, and can be used to perform image processing tasks, speech processing tasks, text processing tasks, etc. The embodiments of the present disclosure do not limit the specific task type performed by the neural network to be simulated.

[0041] In some embodiments, before deploying the neural network to a many-core system for network simulation, the network configuration of the neural network to be simulated is obtained, which includes a plurality of original neuron clusters included in the neural network and the number of original neuron clusters, the number of neurons included in each neuron cluster, the connection relationship between neuron clusters, the information of the destination neuron cluster corresponding to each neuron cluster, and the information of the source neuron cluster corresponding to each neuron cluster. The source neuron cluster corresponding to each neuron cluster refers to a neuron cluster having a connection relationship with the neurons in the neuron cluster and needing to transmit information to the neurons in the neuron cluster during simulation. The destination neuron cluster corresponding to each neuron cluster refers to a neuron cluster having a connection relationship with the neurons in the neuron cluster and needing to transmit information to the neurons in the destination neuron cluster during simulation. That is, the source neuron cluster is the neuron cluster sending information, and the destination neuron cluster is the neuron cluster receiving information. During simulation, when one neuron cluster needs to transmit information to another neuron cluster, the one neuron cluster is called the source neuron cluster corresponding to the other neuron cluster, and the other neuron cluster is called the destination neuron cluster corresponding to the one neuron cluster.

[0042] It should be noted that for any neuron cluster, different neurons in the neuron cluster can also have a connection relationship, and the neurons in the neuron cluster can also have a connection relationship with other neuron clusters. Therefore, the source neuron cluster corresponding to the neuron cluster can be the neuron cluster itself or other neuron clusters.

[0043] In step S11, a plurality of target neuron clusters to be allocated are obtained according to a plurality of original neuron clusters corresponding to the neural network to be simulated.​

[0044] Step S12: Pre-allocate multiple target neuron clusters to multiple processing cores of the many-core system, wherein at least some processing cores each processing core is pre-allocated with at least one target neuron cluster, and the current cluster memory size occupied by all target neuron clusters pre-allocated to the processing core is less than or equal to the current available cluster memory size corresponding to the processing core, and the current available cluster memory size corresponding to the processing core is equal to the difference between the available memory size of the processing core and the current preset route memory size.

[0045] In this embodiment of the disclosure, pre-allocation refers to the anticipated allocation but not yet actually allocated, where multiple target neuron clusters are pre-allocated to multiple processing cores of the many-core system, and at least some of the processing cores are determined to correspond to the pre-allocated target neuron clusters. These at least some processing cores may be located on the same many-core chip within the many-core system, or they may be located on different many-core chips within the many-core system.

[0046] In this embodiment of the disclosure, the current cluster memory size occupied by all target neuron clusters pre-allocated to the processing core refers to the total memory size required by all target neuron clusters pre-allocated to the processing core. For example, there are 3 target neuron clusters pre-allocated to processing core 1, namely target neuron cluster A, target neuron cluster B and target neuron cluster C. The memory size required by target neuron cluster A is a, the memory size required by target neuron cluster B is b, and the memory size required by target neuron cluster C is c. Then, the current cluster memory size occupied by all target neuron clusters pre-allocated to processing core 1 is d = a + b + c.

[0047] In this embodiment of the disclosure, the available memory size of the processing core refers to the maximum available memory size of the processing core; the route refers to the path for data communication and interaction between neuron clusters of different processing cores, used for communication between different neuron clusters; the current preset route memory size refers to the total memory size required for data communication and interaction of all routes currently set. Before the first pre-allocation of neuron clusters, the current preset route memory size is set to the initial value.

[0048] Since the estimated actual routing memory size cannot be determined before the first pre-allocation of neuron clusters, an initial value needs to be set as the current preset routing memory size. For example, the initial value of the current preset routing memory size can be set to 480B (bytes). 480B is an empirical value. After the first pre-allocation is completed, if the calculated estimated routing memory size exceeds the current preset routing memory size, the current preset routing memory size will be adjusted, and the pre-allocation of neuron clusters will be redistributed based on the adjusted current preset routing memory size.

[0049] Step S13, for each processing core in the at least partial processing cores, obtaining an estimated routing memory size currently required by all the target neuron clusters pre-allocated in the processing core.

[0050] After pre-allocating all the target neuron clusters to the at least partial processing cores, for each processing core in the at least partial processing cores, obtaining a routing memory size required by each target neuron cluster pre-allocated in the processing core, and determining an estimated routing memory size currently required by all the target neuron clusters pre-allocated in the processing core according to a sum of the routing memory sizes required by all the target neuron clusters pre-allocated in the processing core.

[0051] wherein the routing memory size required by each target neuron cluster is a product of a routing quantity corresponding to the target neuron cluster and a basic routing memory size, and the routing quantity corresponding to the target neuron cluster is a quantity of source neuron clusters corresponding to the target neuron cluster and in the same many-core chip as the target neuron cluster.

[0052] In some embodiments, after pre-allocating all the target neuron clusters to the at least partial processing cores and determining the many-core chip in which each processing core in the at least partial processing cores is located, each target neuron cluster is traversed to determine all the source neuron clusters corresponding to the target neuron cluster, thereby determining a routing quantity corresponding to each target neuron cluster, the routing quantity corresponding to each target neuron cluster being a quantity of source neuron clusters corresponding to the target neuron cluster and in the same many-core chip as the target neuron cluster, where the routing quantity is an on-chip routing quantity, and then a routing memory size required by each target neuron cluster is determined according to a product of the routing quantity corresponding to each target neuron cluster and a basic routing memory size; wherein the basic routing memory size, i.e., a unit routing memory size, is a memory size required by each routing, and is a pre-defined value, for example, the basic routing memory size is set to 48B.

[0053] Step S14, when there is at least one processing core in the at least partial processing cores whose corresponding estimated routing memory size is greater than the current preset routing memory size, adjusting the current preset routing memory size, and returning to perform the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system until the estimated routing memory size corresponding to each processing core in the at least partial processing cores is less than or equal to the current preset routing memory size.

[0054] After calculating the estimated routing memory size currently required by all target neuron clusters pre-allocated in each processing core of the at least part of processing cores, the estimated routing memory size corresponding to each processing core is compared with the current preset routing memory size. When the estimated routing memory size corresponding to at least one processing core is greater than the current preset routing memory size, the current preset routing memory size is adjusted, and the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system is returned to perform the pre-allocation of the neuron clusters again according to the adjusted current preset routing memory size, until the estimated routing memory size corresponding to each processing core of the at least part of processing cores is less than or equal to the current preset routing memory size.

[0055] According to the neuron cluster allocation method for network simulation provided by the embodiments of the present disclosure, the current preset routing memory size is set, and the current available cluster memory size corresponding to each processing core is determined according to the difference between the available memory size of the processing core and the current preset routing memory size. In the pre-allocation, the plurality of target neuron clusters to be allocated are pre-allocated to the at least part of processing cores based on the current available cluster memory size corresponding to each processing core. After the pre-allocation, the estimated routing memory size corresponding to each processing core pre-allocated with at least one target neuron cluster is evaluated, and the estimated routing memory size is compared with the current preset routing memory size. If the estimated routing memory size corresponding to at least one processing core exceeds the current preset routing memory size, the current preset routing memory size is adjusted, and the current available cluster memory size corresponding to each processing core is also adaptively adjusted. The plurality of target neuron clusters to be allocated are pre-allocated again based on the adjusted current preset routing memory size, until the current preset routing memory size is adjusted to a suitable value, so that the estimated routing memory size corresponding to each processing core is less than or equal to the current preset routing memory size. In this way, the memory size of the routing required for each processing core during simulation can be calculated, that is, the current preset routing memory size, and at the same time, since the pre-allocation is based on the current available cluster memory size corresponding to each processing core, and the current available cluster memory size corresponding to each processing core is the difference between the available memory size of each processing core and the current preset routing memory size, the memory overflow situation can be improved when the neuron clusters are actually allocated to the processing cores for running.

[0056] In some embodiments, obtaining the plurality of target neuron clusters corresponding to the neural network to be simulated includes: obtaining a plurality of original neuron clusters corresponding to the neural network to be simulated; for each original neuron cluster, determining whether the original neuron cluster satisfies a preset splitting condition; when the original neuron cluster satisfies the splitting condition, splitting the original neuron cluster into a plurality of sub-clusters; and determining the original neuron clusters and the sub-clusters that do not satisfy the splitting condition as target neuron clusters.

[0057] The splitting condition includes that a total memory size required to be occupied by the original neuron cluster is greater than an available memory size of a single processing core. The total memory size required to be occupied by the original neuron cluster is a sum of a cluster memory size required to be occupied by the original neuron cluster and a total routing memory size required to be occupied by the original neuron cluster. The total routing memory size required to be occupied by the original neuron cluster is a product of a number of source neuron clusters corresponding to the original neuron cluster and a basic routing memory size. The source neuron clusters corresponding to the original neuron cluster are source neuron clusters that have a connection relationship with neurons in the original neuron cluster and need to transmit information to the neurons in the original neuron cluster during simulation.

[0058] When the original neuron cluster meets the splitting condition, it indicates that the total memory size required to be occupied by a single original neuron cluster exceeds the available memory size of a single processing core. Therefore, the original neuron cluster needs to be split into multiple sub-clusters, and each sub-cluster is taken as a target neuron cluster. The total memory size required to be occupied by each sub-cluster is less than or equal to the available memory size of a single processing core. When the original neuron cluster does not meet the splitting condition, it indicates that the total memory size required to be occupied by a single original neuron cluster does not exceed the available memory size of a single processing core. Therefore, the original neuron cluster does not need to be split. The original neuron cluster that does not meet the splitting condition is determined as a target neuron cluster.

[0059] In some embodiments, splitting the original neuron cluster into multiple sub-clusters includes: constructing a current sub-cluster, the current sub-cluster being an empty list; adding neurons in the original neuron cluster remaining at present to the current sub-cluster one by one; calculating a total memory size required to be occupied by the current sub-cluster each time a neuron is added to the current sub-cluster; stopping adding neurons to the current sub-cluster and removing the neurons added at present from the current sub-cluster when the total memory size required to be occupied by the current sub-cluster is greater than the available memory size of a single processing core; constructing a new sub-cluster and taking the new sub-cluster as the current sub-cluster; and returning to execute the step of adding neurons in the original neuron cluster remaining at present to the current sub-cluster until the neurons in the original neuron cluster are all allocated to all sub-clusters.

[0060] In some embodiments, splitting the original neuron cluster into multiple sub-clusters comprises: sorting the neurons in the original neuron cluster in descending order of the number of other neurons connected to each neuron in the original neuron cluster; constructing a current sub-cluster; adding the neurons remaining in the original neuron cluster to the current sub-cluster one by one in the order of the sorting; calculating the total memory size required to be occupied by the current sub-cluster each time a neuron is added to the current sub-cluster; stopping adding neurons to the current sub-cluster and removing the currently added neuron from the current sub-cluster when the total memory size required to be occupied by the current sub-cluster is greater than the available memory size of a single processing core; constructing a new sub-cluster and taking the new sub-cluster as the current sub-cluster, and returning to execute the step of adding the neurons remaining in the original neuron cluster to the current sub-cluster one by one in the order of the sorting until all the neurons in the original neuron cluster are allocated to all the sub-clusters.

[0061] Each original neuron cluster contains one or more neurons, and the neurons in different original neuron clusters can have a connection relationship, and the neurons in an original neuron cluster can also have a connection relationship. Therefore, for each original neuron cluster, each neuron in the original neuron cluster can be connected to other neurons in the cluster, to other neurons in other original neuron clusters, and to itself. The number of other neurons connected to each neuron in the original neuron cluster refers to how many other neurons are connected to each neuron in the original neuron cluster.

[0062] In this way, when the original neuron cluster is split, neurons with a larger number of corresponding connections to other neurons can be allocated to the same sub-cluster as much as possible, thereby facilitating the reduction of the increase in routing between sub-clusters after splitting.

[0063] In some embodiments, splitting the original neuron cluster into multiple sub-clusters comprises: for each neuron in the original neuron cluster, marking the neuron as an important neuron when the number of other neurons connected to the neuron is greater than a preset number, and marking the neuron as a non-important neuron when the number of other neurons connected to the neuron is less than or equal to the preset number; constructing a corresponding number of first sub-clusters according to the number of important neurons in the original neuron cluster, and adding one important neuron to each first sub-cluster; traversing each first sub-cluster, and adding non-important neurons in the original neuron cluster to the first sub-cluster one by one when the total memory size required to be occupied by the first sub-cluster is less than the available memory size of a single processing core; calculating the total memory size required to be occupied by the first sub-cluster each time a non-important neuron is added to the first sub-cluster; and stopping adding non-important neurons to the first sub-cluster and removing the currently added non-important neuron from the first sub-cluster when the total memory size required to be occupied by the first sub-cluster is greater than the available memory size of a single processing core.

[0064] In this way, after splitting the original neuron clusters, each sub-cluster contains only one important neuron and at least one non-important neuron, which helps to improve the uniformity of the total memory size required by the split sub-clusters.

[0065] In some embodiments, when there are unallocated non-essential neurons in the original neuron cluster, the method further includes: constructing a second sub-cluster; adding the currently remaining non-essential neurons in the original neuron cluster to the second sub-cluster one by one; calculating the total memory size required by the second sub-cluster each time a non-essential neuron is added to the second sub-cluster; stopping the addition of non-essential neurons to the second sub-cluster and removing the currently added non-essential neurons from the second sub-cluster when the total memory size required by the second sub-cluster is greater than the available memory size of a single processing core; constructing a new second sub-cluster, and returning to the step of adding the currently remaining non-essential neurons in the original neuron cluster to the second sub-cluster one by one, until the neurons in the original neuron cluster are evenly allocated to all sub-clusters.

[0066] In some embodiments, pre-allocating multiple target neuron clusters to multiple processing cores of a many-core system includes: for the current processing core among the multiple processing cores of the many-core system, pre-allocating the remaining multiple target neuron clusters one by one to the current processing core; when allocating a target neuron cluster in the current processing core, determining whether the current cluster memory size occupied by all currently allocated target neuron clusters in the current processing core is greater than the current available cluster memory size corresponding to the current processing core; if the current cluster memory size occupied by all currently allocated target neuron clusters in the current processing core is greater than the current available cluster memory size corresponding to the current processing core, stopping the allocation of target neuron clusters to the current processing core, and removing the currently added target neuron cluster from the current processing core; taking the next processing core among the multiple processing cores of the many-core system as the current processing core, and returning to execute the step of pre-allocating the remaining multiple target neuron clusters one by one to the current processing core, until all target neuron clusters are pre-allocated to at least some processing cores.

[0067] In some embodiments, for each processing core in at least a portion of the processing cores, the estimated routing memory size currently required by all target neuron clusters pre-allocated in the processing core is the sum of the routing memory sizes required by each target neuron cluster pre-allocated in the processing core; the routing memory size required by a target neuron cluster is the product of the number of source neuron clusters corresponding to the target neuron cluster and pre-allocated on the same many-core chip as the target neuron cluster and the basic routing memory size, where the source neuron clusters corresponding to the target neuron cluster refer to the target neuron clusters that have a connection relationship with the neurons within the target neuron cluster and need to transmit information to the neurons within the target neuron cluster during simulation.

[0068] In some embodiments, the adjustment of the current preset routing memory size comprises: adjusting the current preset routing memory size to a sum of the current preset routing memory size and a predetermined value.

[0069] In some embodiments, if the difference between the estimated routing memory size corresponding to the processing core and the current preset routing memory size is less than 0, it indicates that the estimated routing memory size corresponding to the processing core is less than the current preset routing memory size, and no further adjustment of the current preset routing memory size is needed.

[0070] In some embodiments, if the difference between the estimated routing memory size corresponding to the processing core and the current preset routing memory size is greater than 0 and less than or equal to the initial preset routing memory size, it indicates that the estimated routing memory size corresponding to the processing core is greater than the current preset routing memory size, and the difference between them is less than the initial preset routing memory size, i.e., less than the initial value, and the predetermined value is the initial preset routing memory size, i.e., the aforementioned initial value.

[0071] In some embodiments, if the difference between the estimated routing memory size corresponding to the processing core and the current preset routing memory size is greater than the initial preset routing memory size, it indicates that the estimated routing memory size corresponding to the processing core is greater than the current preset routing memory size, and the difference between them is relatively large, and in order to reduce the number of iterative adjustments, the predetermined value is half of the difference between the estimated routing memory size and the current preset routing memory size.

[0072] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to the limited length, the present disclosure will not be described again. Those skilled in the art can understand that the specific execution order of each step in the above-mentioned method should be determined according to its function and possible internal logic.

[0073] In addition, the present disclosure also provides a neuron cluster allocation apparatus for network simulation, an electronic device, and a computer readable storage medium. The above-mentioned neuron cluster allocation apparatus for network simulation, electronic device, and computer readable storage medium can be used to implement the neuron cluster allocation method for network simulation provided by the present disclosure. The corresponding technical solutions and descriptions are described in the method part, and will not be described here.

[0074] Figure 2 A structural schematic diagram of a neuron cluster allocation apparatus for network simulation provided by an embodiment of the present disclosure.

[0075] As shown in Figure 2 The present disclosure also provides a neuron cluster allocation apparatus 200 for network simulation, which comprises:

[0076] The acquisition unit 201 is configured to acquire a plurality of target neuron clusters to be allocated corresponding to a neural network to be simulated.

[0077] The pre-allocation unit 202 is configured to pre-allocate the plurality of target neuron clusters to a plurality of processing cores of a many-core system, wherein each of at least part of the processing cores is pre-allocated with at least one target neuron cluster, and a current cluster memory size occupied by all the target neuron clusters pre-allocated to the processing core is less than or equal to a current available cluster memory size corresponding to the processing core, the current available cluster memory size corresponding to the processing core being equal to a difference between an available memory size of the processing core and a current preset routing memory size.

[0078] The calculation unit 203 is configured to, for each of at least part of the processing cores, acquire an estimated routing memory size currently required to be occupied by all the target neuron clusters pre-allocated in the processing core.

[0079] The iteration unit 204 is configured to, when there is at least one processing core in at least part of the processing cores whose current corresponding estimated routing memory size is greater than the current preset routing memory size, adjust the current preset routing memory size, and return to perform the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system until the current corresponding estimated routing memory size of each of at least part of the processing cores is less than or equal to the current preset routing memory size.

[0080] The neuron cluster allocation apparatus 200 provided by the embodiments of the present disclosure is used for implementing the neuron cluster allocation method for network simulation provided by any of the above embodiments, and specific related descriptions can be referred to the related descriptions in the data processing method based on brain simulation of the above embodiments, which will not be described here again.

[0081] Figure 3 The composition block diagram of the electronic device provided by the embodiments of the present disclosure is referred to Figure 3 The embodiments of the present disclosure provide an electronic device, which comprises at least one processor 31, at least one memory 32, and one or more I / O interfaces 33 connected between the processor 31 and the memory 32; wherein the memory 32 stores one or more computer programs executable by the at least one processor 31, and the one or more computer programs are executed by the at least one processor 31 to enable the at least one processor 31 to perform the neuron cluster allocation method for network simulation described above.

[0082] The embodiments of the present disclosure further provide a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the neuron cluster allocation method for network simulation described above. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0083] The embodiments of the present disclosure further provide a computer program product, comprising computer readable code, or a nonvolatile computer readable storage medium carrying the computer readable code, when the computer readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-mentioned method for assigning neuron clusters for network simulation.

[0084] Those of ordinary skill in the art can understand that all or some of the steps in the above disclosed method, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0085] As known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Furthermore, it is known to those of ordinary skill in the art that communication media typically includes computer readable program instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transport mechanisms, and can include any information delivery medium.

[0086] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0087] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device or server. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing / processing device, for example, through the Internet using an Internet Service Provider. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0088] The computer program product described herein can be embodied in a tangible computer readable storage medium, or embodied as a software product, such as a software development kit (SDK), and the like.

[0089] The computer program product described herein can be embodied in a tangible computer readable storage medium, or embodied as a software product, such as a software development kit (SDK), and the like.

[0090] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage cycles that change state. The instructions can be executed by one or more processors of a computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process such that the instructions which execute via the one or more processors of the computer or other programmable data processing devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0091] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0092] The flow and block diagrams in the drawings show architectural, functional, and operational aspects of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of instructions which comprise one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may

[0093] Example embodiments have been disclosed and, although a specific terminology is employed, it is merely for the convenience of the reader and is not intended to be limiting. In some instances, specific details have been included for the purpose of providing a thorough understanding of the embodiments presented, but it will be apparent to those skilled in the art that embodiments of the application can be practiced without these specific details. In some instances, features, characteristics and / or elements described in connection with a particular embodiment can be used in conjunction with, or switched to, features, characteristics and / or elements described in connection with other embodiments, unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A method for neuron cluster allocation for network simulation, characterized in that, The method comprises the following steps: obtaining a plurality of target neuron clusters corresponding to a neural network to be simulated; pre-allocating the plurality of target neuron clusters to a plurality of processing cores of a many-core system, wherein each of at least some of the processing cores is pre-allocated at least one target neuron cluster, and the size of the current cluster memory occupied by all the target neuron clusters pre-allocated to the processing core is less than or equal to the current available cluster memory size corresponding to the processing core, which is equal to the difference between the available memory size of the processing core and the current preset routing memory size; for each of the at least some of the processing cores, obtaining an estimated routing memory size currently required by all the target neuron clusters pre-allocated to the processing core; when the estimated routing memory size corresponding to at least one of the at least some of the processing cores is greater than the current preset routing memory size, adjusting the current preset routing memory size, and returning to the step of pre-allocating the plurality of target neuron clusters to the plurality of processing cores of the many-core system until the estimated routing memory size corresponding to each of the at least some of the processing cores is less than or equal to the current preset routing memory size.

2. The method of claim 1, wherein, The method comprises the following steps: obtaining a plurality of original neuron clusters corresponding to a neural network to be simulated; for each of the original neuron clusters, determining whether the original neuron cluster meets a preset splitting condition; when the original neuron cluster meets the splitting condition, splitting the original neuron cluster into a plurality of sub-clusters; determining the original neuron cluster that does not meet the splitting condition and the sub-clusters as the target neuron clusters.

3. The method of claim 2, wherein, The splitting condition comprises that the total memory size required by the original neuron cluster is greater than the available memory size of a single processing core. The total memory size required by the original neuron cluster is the sum of the cluster memory size required by the original neuron cluster and the total routing memory size required by the original neuron cluster, the total routing memory size required by the original neuron cluster is the product of the number of source neuron clusters corresponding to the original neuron cluster and the basic routing memory size, and the source neuron cluster corresponding to the original neuron cluster refers to the original neuron cluster that has a connection relationship with the neurons in the original neuron cluster and needs to transmit information to the neurons in the original neuron cluster during simulation.

4. The method of claim 2, wherein, The method comprises the following steps: constructing a current sub-cluster; adding the neurons in the original neuron cluster to the current sub-cluster one by one; calculating the total memory size required by the current sub-cluster when adding each neuron to the current sub-cluster; stopping adding neurons to the current sub-cluster and removing the added neurons from the current sub-cluster when the total memory size required by the current sub-cluster is greater than the available memory size of a single processing core; constructing a new sub-cluster and taking the new sub-cluster as a current sub-cluster, and returning to execute the step of adding the neurons remaining in the original neuron cluster one by one to the current sub-cluster in the order in the sorting until the neurons in the original neuron cluster are all allocated to all sub-clusters.

5. The method of claim 2, wherein, The step of splitting the original neuron cluster into multiple sub-clusters comprises: sorting the neurons in the original neuron cluster in an order from large to small according to the number of other neurons connected to the neurons; constructing a current sub-cluster; adding the neurons remaining in the original neuron cluster one by one to the current sub-cluster in the order in the sorting; calculating the total memory size required to be occupied by the current sub-cluster when adding one neuron to the current sub-cluster; stopping adding neurons to the current sub-cluster and removing the currently added neuron from the current sub-cluster when the total memory size required to be occupied by the current sub-cluster is greater than the available memory size of a single processing core; constructing a new sub-cluster and taking the new sub-cluster as a current sub-cluster, and returning to execute the step of adding the neurons remaining in the original neuron cluster one by one to the current sub-cluster in the order in the sorting until the neurons in the original neuron cluster are all allocated to all sub-clusters.

6. The method of claim 2, wherein, The step of splitting the original neuron cluster into multiple sub-clusters comprises: For each neuron in the original neuron cluster, marking the neuron as an important neuron when the number of other neurons connected to the neuron is greater than a preset number, and marking the neuron as a non-important neuron when the number of other neurons connected to the neuron is less than or equal to the preset number; constructing a corresponding number of first sub-clusters according to the number of important neurons in the original neuron cluster, and adding one important neuron to each first sub-cluster; traversing each first sub-cluster, and adding the non-important neurons in the original neuron cluster one by one to the first sub-cluster when the total memory size required to be occupied by the first sub-cluster is less than the available memory size of a single processing core; calculating the total memory size required to be occupied by the first sub-cluster when adding one non-important neuron to the first sub-cluster; stopping adding non-important neurons to the first sub-cluster and removing the currently added non-important neuron from the first sub-cluster when the total memory size required to be occupied by the first sub-cluster is greater than the available memory size of a single processing core.

7. The method of claim 6, wherein, When there are unallocated non-important neurons in the original neuron cluster, the method further comprises: constructing a second sub-cluster; adding the non-important neurons remaining in the original neuron cluster one by one to the second sub-cluster; calculating the total memory size required to be occupied by the second sub-cluster when adding one non-important neuron to the second sub-cluster; stopping adding non-important neurons to the second sub-cluster and removing the currently added non-important neuron from the second sub-cluster when the total memory size required to be occupied by the second sub-cluster is greater than the available memory size of a single processing core. constructing a new second sub-cluster and returning to perform the step of adding the currently remaining unimportant neurons in the original neuron cluster to the second sub-cluster one by one until the neurons in the original neuron cluster are all allocated to all sub-clusters.

8. The method of claim 1, wherein, The pre-allocating of the plurality of target neuron clusters to the plurality of processing cores of the many-core system comprises: pre-allocating the currently remaining plurality of target neuron clusters to a current processing core one by one for the current processing core among the plurality of processing cores of the many-core system; when each target neuron cluster is allocated in the current processing core, judging whether a current cluster memory size occupied by all the target neuron clusters currently allocated in the current processing core is greater than a current available cluster memory size corresponding to the current processing core; if the current cluster memory size occupied by all the target neuron clusters currently allocated in the current processing core is greater than the current available cluster memory size corresponding to the current processing core, stopping the allocation of target neuron clusters to the current processing core and removing the currently added target neuron cluster from the current processing core; taking a next processing core among the plurality of processing cores of the many-core system as the current processing core and returning to perform the step of pre-allocating the currently remaining plurality of target neuron clusters to the current processing core one by one until all the target neuron clusters are pre-allocated to at least part of the processing cores.

9. The method of claim 1, wherein, The estimated routing memory size currently required by all the target neuron clusters pre-allocated in the processing core is a sum of routing memory sizes required by each target neuron cluster pre-allocated in the processing core; The routing memory size required by the target neuron cluster is a product of a basic routing memory size and a number of source neuron clusters corresponding to the target neuron cluster and pre-allocated on the same many-core chip as the target neuron cluster, wherein the source neuron cluster corresponding to the target neuron cluster refers to a target neuron cluster having a connection relationship with a neuron in the target neuron cluster and needing to transmit information to the neuron in the target neuron cluster during simulation.

10. The method of claim 1, wherein, The adjusting of the current preset routing memory size comprises: adjusting the current preset routing memory size to a sum of the current preset routing memory size and a predetermined value.

11. The method of claim 10, wherein, If a difference between the estimated routing memory size corresponding to the processing core and the current preset routing memory size is greater than 0 and less than or equal to an initial preset routing memory size, the predetermined value is the initial preset routing memory size. If the difference between the estimated routing memory size corresponding to the processing core and the current preset routing memory size is greater than the initial preset routing memory size, the predetermined value is half of the difference between the estimated routing memory size and the current preset routing memory size.

12. A neuron cluster allocation apparatus for network simulation, characterized by comprising: comprises: an obtaining unit configured to obtain a plurality of target neuron clusters to be allocated corresponding to a neural network to be simulated; a pre-allocating unit configured to pre-allocate a plurality of the target neuron clusters to a plurality of processing cores of a many-core system, wherein each of at least part of the processing cores is pre-allocated with at least one target neuron cluster, and a current cluster memory size occupied by all the target neuron clusters pre-allocated to the processing core is less than or equal to a current available cluster memory size corresponding to the processing core, the current available cluster memory size corresponding to the processing core being equal to a difference between an available memory size of the processing core and a current preset routing memory size; a calculating unit configured to obtain, for each of the at least part of the processing cores, an estimated routing memory size currently required to be occupied by all the target neuron clusters pre-allocated in the processing core; an iterating unit configured to, when there is at least one processing core in the at least part of the processing cores whose corresponding estimated routing memory size is greater than the current preset routing memory size, adjust the current preset routing memory size, and return to perform the step of pre-allocating a plurality of the target neuron clusters to a plurality of processing cores of a many-core system until the estimated routing memory size corresponding to each of the at least part of the processing cores is less than or equal to the current preset routing memory size.

13. An electronic device, comprising: comprise: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the neuron cluster allocation method according to any one of claims 1-11. The computer program, when executed by a processor, implements the neuron cluster allocation method according to any one of claims 1-11.

14. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the neuron cluster allocation method according to any one of claims 1-11.

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