Inverse logic method and device for configuration interlocking logic, storage medium and electronic equipment

Abstract

The application provides a reverse logic method and device of configuration interlocking logic, a storage medium and an electronic device, and the method is: obtaining an interlocking logic diagram corresponding to a positive logic of an automatic control system; identifying a logic paragraph in the interlocking logic diagram; determining a target logic paragraph in the logic paragraph, the target logic paragraph being a logic paragraph containing an output bit number; establishing a logic node tree corresponding to the target logic paragraph; and performing reverse logic according to a level of the logic node tree to obtain an anti-logic interlocking configuration corresponding to the target logic paragraph. In the scheme, the logic paragraph is identified from the interlocking logic diagram, and the target logic paragraph in the logic paragraph is determined. The logic node tree corresponding to the target logic paragraph is established, the reverse logic is performed according to the level of the logic node tree, and the anti-logic interlocking configuration corresponding to the target logic paragraph is obtained. The anti-logic does not need to be manually drawn, and the configuration cost is reduced and the configuration efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of automatic control technology, and specifically to an inverse logic method, apparatus, storage medium, and electronic device for configuration interlocking logic. Background Technology

[0002] Automated control systems help improve industrial production efficiency and are also a necessary means to ensure safe production.

[0003] Currently, the configuration interlocking logic of automated control systems is mainly designed by the design engineers during the design phase, and then the design engineers debug and verify the configuration interlocking logic. However, design engineers need to spend a lot of time and energy designing the positive and negative logic, and it is easy to cause logical errors due to human error, which requires a lot of time to correct. This results in high configuration costs and low configuration efficiency. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, apparatus, storage medium, and electronic device for configuring interlocking logic in reverse logic, in order to solve the problems of high configuration cost and low configuration efficiency that currently exist when design engineers design both forward and reverse logic at the same time.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] The first aspect of this invention discloses an inverse logic method for configuration interlocking logic, the method comprising:

[0007] Obtain the interlocking logic diagram corresponding to the positive logic of the automated control system. The interlocking logic diagram includes at least tag numbers and function blocks.

[0008] Identify the logic segments in the interlocking logic diagram;

[0009] Identify the target logical segment within the logical segments, wherein the target logical segment is the logical segment containing the output bit number;

[0010] Establish a logical node tree corresponding to the target logical paragraph;

[0011] Perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment.

[0012] Preferably, identifying the logical segments in the interlocking logic diagram includes:

[0013] Add the input bit numbers, output bit numbers, and function blocks in the interlocking logic diagram as nodes to the node list;

[0014] Select nodes from the node list that do not belong to any logical paragraph as nodes to be processed;

[0015] The nodes to be processed are assigned to blank paragraphs;

[0016] Based on the input and output pins of the node to be processed, the input bit number, output bit number, and function block associated with the node to be processed are assigned to the blank segment to obtain the corresponding logical segment. Then, the process returns to the step of selecting a node in the node list that does not belong to any logical segment as the node to be processed, until no node that does not belong to any logical segment can be found.

[0017] Preferably, establishing a logical node tree corresponding to the target logical paragraph includes:

[0018] A node tree is established by taking the last part of the set of output bit numbers of the target logical paragraph as the virtual root node and taking the output bit numbers of the target logical paragraph as the subtrees of the virtual root node;

[0019] The nodes of the node tree are traversed in a top-to-bottom and left-to-right order.

[0020] For each node encountered during the traversal of the node tree, from the target logic segment, all the preceding nodes that are not yet tree nodes connected to the input pins of the encountered nodes are added to the subtree of the encountered nodes to obtain the logic node tree corresponding to the target logic segment.

[0021] Preferably, reverse logic is performed according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment, including:

[0022] According to the hierarchy of the logical node tree, reverse logic is performed on the logical node tree in the order from root to leaf and from left to right. Based on the preset adjustment rules and the types of nodes encountered in the reverse logic process, the functional blocks of the logical node tree are adjusted to obtain the anti-logic interlocking configuration corresponding to the target logical segment. The types of nodes encountered in the reverse logic process are tag numbers or functional blocks.

[0023] A second aspect of this invention discloses an inverse logic device for configuration interlocking logic, the device comprising:

[0024] The acquisition unit is used to acquire the interlocking logic diagram of the automatic control system that is positive logic, wherein the interlocking logic diagram includes at least tag numbers and function blocks;

[0025] The identification unit is used to identify the logic segments in the interlocking logic diagram;

[0026] A determining unit is used to determine a target logical segment in the logical segment, wherein the target logical segment is the logical segment containing the output bit number;

[0027] The construction unit is used to establish a logical node tree corresponding to the target logical paragraph;

[0028] The reverse unit is used to perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment.

[0029] Preferably, the identification unit includes:

[0030] The module is used to add the input bit numbers, output bit numbers, and function blocks in the interlocking logic diagram as nodes to the node list.

[0031] The selection module is used to select nodes in the node list that do not belong to any logical paragraph as nodes to be processed;

[0032] The attribution module is used to assign the node to be processed to a blank paragraph.

[0033] The processing module is used to assign the input bit number, output bit number, and function block associated with the node to be processed to the blank segment according to the input pin and output pin of the node to be processed, so as to obtain the corresponding logical segment, and return to execute the selection module until no node that does not belong to any logical segment can be found.

[0034] Preferably, the building unit includes:

[0035] The construction module is used to build a node tree with the last part of the set of output bits of the target logical paragraph as the virtual root node and the output bits of the target logical paragraph as the subtree of the virtual root node;

[0036] The traversal module is used to traverse the nodes of the node tree in a top-to-bottom and left-to-right order;

[0037] An addition module is used to add, from the target logic segment, all the preceding nodes that are not tree nodes connected to the input pins of the nodes encountered during traversal of the node tree to the subtree of the nodes encountered during traversal, so as to obtain the logic node tree corresponding to the target logic segment.

[0038] Preferably, the reverse unit is specifically used to: perform reverse logic on the logical node tree according to the hierarchy of the logical node tree, based on the order from root to leaf and from left to right, and adjust the functional blocks of the logical node tree according to the preset adjustment rules and the types of nodes encountered in the reverse logic process, so as to obtain the anti-logic interlocking configuration corresponding to the target logical segment, wherein the type of the node encountered in the reverse logic process is a tag number or a functional block.

[0039] A third aspect of the present invention discloses an electronic device, comprising: a processor and a memory, wherein the processor and the memory are connected via a communication bus; wherein the processor is used to call and execute a program stored in the memory; and the memory is used to store the program, wherein the program is used to implement the inverse logic method of the configuration interlocking logic disclosed in the first aspect of the present invention.

[0040] A fourth aspect of the present invention discloses a computer-readable storage medium storing computer-executable instructions for executing the inverse logic method of the configuration interlocking logic disclosed in the first aspect of the present invention.

[0041] Based on the above embodiments of the present invention, a method, apparatus, storage medium, and electronic device for reverse logic configuration of interlocking logic are provided. The method involves: acquiring an interlocking logic diagram corresponding to the forward logic of an automated control system; identifying logic segments in the interlocking logic diagram; determining a target logic segment within the logic segments, wherein the target logic segment is a logic segment containing output tag numbers; establishing a logic node tree corresponding to the target logic segment; and performing reverse logic according to the hierarchy of the logic node tree to obtain the inverse logic interlocking configuration corresponding to the target logic segment. In this solution, logic segments are identified from the interlocking logic diagram, and a target logic segment within the logic segments is determined. A logic node tree corresponding to the target logic segment is established, and reverse logic is performed according to the hierarchy of the logic node tree to obtain the inverse logic interlocking configuration corresponding to the target logic segment. This eliminates the need for manual drawing of the inverse logic, reducing configuration costs and improving configuration efficiency. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1 A flowchart illustrating the inverse logic method of configuration interlocking logic provided in an embodiment of the present invention;

[0044] Figure 2A flowchart for identifying logical segments provided in an embodiment of the present invention;

[0045] Figure 3 This is an example diagram of a positive logic interlocking configuration provided in an embodiment of the present invention;

[0046] Figure 4 Example diagram of a logical node tree provided in an embodiment of the present invention;

[0047] Figure 5 This is an example diagram of the anti-logic interlocking configuration provided in an embodiment of the present invention;

[0048] Figure 6 This is a structural block diagram of an inverse logic device for configuration interlocking logic provided in an embodiment of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0051] To facilitate understanding of this plan, the following explanations will first cover the terminology used in this plan.

[0052] Configuration: Configuration refers to the process of organically combining various control elements, sensors, actuators, and computers into a whole system suitable for a specific application during industrial automation.

[0053] Interlocking: Interlocking refers to the use of one or more logical means in industrial automation control systems to restrict the relationships between equipment or devices to prevent unsafe, unreasonable, or abnormal operations. Interlocking is usually implemented in hardware or software and ensures that equipment meets specific execution conditions and control requirements under normal operating conditions. For example, in some situations, when equipment A is running, equipment B must be stopped; otherwise, it may cause a safety accident or damage to the equipment. In this case, interlocking ensures that equipment B will not start when equipment A is running, thereby guaranteeing the safety and efficiency of the production process.

[0054] Interlocking logic diagram: An interlocking logic diagram is a graphical representation used to describe the logical relationships between various devices in an industrial automation control system. It typically uses symbols, lines, and text to represent different devices and signals, and different connection methods to represent different logical relationships.

[0055] Positive logic: Positive logic refers to logic where, for a given input signal, the output signal is the same as the input signal. For example, in the case of a switch controlling a light, when the switch is turned on, the light will also turn on; this is positive logic.

[0056] Inverse logic (negative logic): Inverse logic refers to logic where, for a given input signal, the output signal is the opposite of the input signal. For example, in a control system for a protective door, the equipment should stop operating when the door is opened. This requires inverse logic design, meaning that the equipment stops operating when the door is opened.

[0057] Reverse logic (inverted logic): Reverse logic is the process of converting the interlocking logic configuration from positive logic to negative logic.

[0058] Tag number: The data source or output source in the control system. The data of the instrument hardware in the control system is connected to the controller through hardware connections. The tag number represents the input data of the instrument or the data to be output to the instrument.

[0059] Function block: An abstract representation of computer code with a specific function on the user interface.

[0060] Pin: The element in a function block or tag that is responsible for connection, representing the channel through which data flows in or out.

[0061] Logical paragraph (logical segment): A piece of interlocking logic.

[0062] TIMER and TIMEREX: Timer function blocks that implement timed output after input.

[0063] RS, SR: Reset / Set Trigger, Set / Reset Trigger.

[0064] DV, RV: In this scheme, these refer to the two output pins of the SR and RS flip-flops, representing positive and negative outputs.

[0065] The above is a description of some of the terms used in this plan.

[0066] The inventors discovered through research that automated control systems help improve industrial production efficiency and are also a necessary means to ensure safe production. Distributed control system (DCS) interlocks are frequently used interlocks for opening and closing equipment or for starting and stopping equipment during production, and are considered normal operation. Safety interlocking systems (SIS) are mostly related to personnel and equipment safety, preventing equipment from being affected by external interference or load fluctuations during operation; therefore, safety interlocks often adopt a fail-safe design.

[0067] For instruments with the same interlocking logic input and output, if the input is 1, the normal interlocking logic is triggered under positive logic; under negative logic, the received signal is 0 (no trigger). If the input is 0, the interlocking logic is not triggered under positive logic; under negative logic, the received signal is 1 (triggering a safety interlock). Therefore, when the input instrument is normal, positive logic is used to trigger the normal production interlock; when the input instrument is abnormal, negative logic is used to trigger the safety interlock under abnormal conditions, thus ensuring production safety. Based on this, DCS interlocks typically use positive logic, while SIS interlocks typically use negative logic.

[0068] Currently, the configuration interlocking logic of automated control systems is mainly designed by design engineers simultaneously for both positive and negative logic during the design phase. This requires engineers to analyze logical relationships, determine the logical connections between various devices and their signal transmission paths, in order to determine the content and form of the negative logic. Then, debugging and verification are conducted to ensure the negative logic meets design requirements and actual operational needs. This consumes a significant amount of time and effort from design engineers and is prone to logical errors due to human error, requiring substantial time for correction. This results in high configuration costs and low configuration efficiency.

[0069] Therefore, this solution proposes a reverse logic method, device, storage medium, and electronic device for configuring interlocking logic. By analyzing the interlocking logic diagram of the positive logic interlocking and splitting the logic segments, the reverse logic interlocking configuration (reverse logic interlocking) is derived by recursively deriving from the output. That is, the reverse logic interlocking configuration is generated from the completed positive logic interlocking configuration, eliminating the need for manual drawing of the reverse logic, reducing configuration costs and improving configuration efficiency.

[0070] The following detailed description of the solution is provided through various embodiments.

[0071] See Figure 1This invention illustrates an inverse logic method for configuration interlocking logic provided by an embodiment of the present invention. The inverse logic method includes:

[0072] Step S101: Obtain the interlocking logic diagram with positive logic corresponding to the automatic control system.

[0073] In the specific implementation step S101, the interlocking logic diagram (positive logic interlocking) corresponding to the automatic control system, which is pre-drawn by computer software, is obtained. The interlocking logic diagram includes at least tag numbers and function blocks, and the tag numbers and function blocks are interconnected through input and output pins.

[0074] Step S102: Identify the logic segments in the interlocking logic diagram.

[0075] It should be noted that when drawing an interlocking logic diagram, each set of interlocks will be drawn on a separate diagram, and the interlocks do not affect each other. An interlock may contain several logic segments. Inverse logic is the inversion of a specific output result, where multiple input logics affect a single output result.

[0076] For example, a factory has two production lines, A and B, which share a single machine, C. To ensure production safety, it's necessary to prevent both production lines A and B from using machine C simultaneously. The correct logic is: when both production lines A and B need to operate, a conflict occurs with machine C. In this case, circuit breaker D of machine C should be opened to disconnect its power supply and prevent the conflict. Therefore, the reverse logic is determined by the states of the pre-input switches A (for production line A) and B (for production line B) of machine C. To distinguish which input data sources constitute the interlocking logic preceding a certain output result, it's necessary to identify the logical segments in the interlocking logic diagram.

[0077] In the specific implementation step S102, each interlocking logic diagram (positive logic interlocking) is used as a unit to identify all logic segments in the interlocking logic diagram.

[0078] It should be noted that the tag numbers and function blocks contained in the logical paragraph are abstracted into nodes. For details on how to identify logical paragraphs, please refer to the following embodiments of the present invention. Figure 2 Explanation of each step in the process.

[0079] Step S103: Identify the target logical paragraph within the logical paragraphs.

[0080] It should be noted that, according to the principle of reverse logic, if there is no output bit number in the logic segment, then the interlock has no practical meaning, and there is no operation of reverse logic.

[0081] Therefore, in the specific implementation step S103, after identifying all the logical segments in the interlocking logic diagram, the logical segments that lack output bit numbers are deleted, and the remaining logical segments that have not been deleted are determined as the target logical segments, that is, the target logical segments are the logical segments that contain output bit numbers.

[0082] Specifically, logical segments lacking output tag numbers are removed from the logical segment list, and the remaining logical segments that have not been deleted are identified as the target logical segments (positive logic interlocks).

[0083] Step S104: Establish the logical node tree corresponding to the target logical paragraph.

[0084] It should be noted that there are no other output nodes after the output bit number node. The output target of the output bit number node is its successor, and the input source of the output bit number node is its predecessor. There may be multiple output bit numbers in the target logic segment. The successors of these output bit number sets are uniformly grouped into a virtual root node (because there are no actual nodes, it is the root node of the virtual tree).

[0085] In the specific implementation step S104, for each target logic segment, a node tree is established by taking the last element of the output bit set of the target logic segment as the virtual root node and the output bit of the target logic segment as the subtree of the virtual root node. The nodes of the node tree are traversed in a top-down and left-to-right order. For each node encountered during the traversal, all the preceding nodes that are not yet tree nodes connected to the input pins of the encountered node are added to the subtree of the encountered node. The node tree is traversed in the aforementioned manner until each node in the target logic segment is created as a node in the node tree, thereby obtaining the logic node tree corresponding to the target logic segment.

[0086] Specifically, since the target logic segment may have one or multiple output bits, a virtual root node without actual nodes is created. The output bits are set as subtrees of the virtual root node to obtain a node tree. The tree level of the virtual root node is 0, and the tree level of the output bits is 1. The nodes of the node tree are traversed from top to bottom and from left to right. All the previous nodes that are not yet tree nodes connected to the input pins of the node are added to the subtree of that node. The node tree is traversed in the aforementioned manner until each node in the target logic segment is created as a node in the node tree, thereby constructing the logic node tree corresponding to the target logic segment.

[0087] It should be noted that, through the above method, nodes in the target logic segment are created as nodes in a logic node tree, where nodes are tag numbers and function blocks. If node A is the input source of node B, then node A is the predecessor node of node B; if node A is the output target of node B, then node A is the successor node of node B.

[0088] Using the above methods, a logical node tree corresponding to each target logical paragraph is created; that is, a corresponding logical node tree is created for each target logical paragraph using the above methods.

[0089] Step S105: Perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment.

[0090] In the specific implementation step S105, for each target logic segment, according to the hierarchy of the logic node tree corresponding to the target logic segment, the logic node tree is reversed in the order from root to leaf and from left to right. According to the preset adjustment rules and the types of nodes encountered in the reverse logic process, the function blocks of the logic node tree are adjusted to obtain the anti-logic interlocking configuration corresponding to the target logic segment. The types of nodes encountered in the reverse logic process are tag numbers or function blocks.

[0091] It should be noted that "adjusting the logical node tree function block" specifically refers to adjustment operations such as adding or modifying the logical node tree function block.

[0092] Using the above methods, reverse logic can be performed on each target logic segment to obtain the corresponding anti-logic interlocking configuration.

[0093] In some embodiments, the preset adjustment rules mentioned above include, but are not limited to, the following rules:

[0094] Let the node encountered during the reverse logic process be denoted as the current node.

[0095] Rule 1: If the type of the current node is bit and the type of the parent node of the logical node tree is also bit, then a "NOT" function block needs to be added between the output of the current node and the input of the parent node to negate the bit.

[0096] Rule 2: If the type of the current node is bit and the type of the parent node of the logical node tree is not bit, take the NOT on the input pin of the parent node of the logical node tree.

[0097] Rule 3: If the current node is a function block and its logic type is an AND function block or an OR function block, then the AND function block needs to be changed to an OR function block and the OR function block needs to be changed to an AND function block. If the node above the logic node tree is a flip-flop in a sequential logic circuit, then the input pin of the node above the logic node tree needs to be NOTed.

[0098] Rule 4: If the current node is a function block and its logic type is a comparison function block (such as "greater than", "less than", "greater than or equal to", etc.), it needs to be modified (or converted) to its opposite function block. For example: if the current node is a "greater than" function block, it needs to be converted to a "less than or equal to" function block; if the current node is a "less than or equal to" function block, it needs to be converted to a "greater than" function block; if the current node is an "equal to" function block, it needs to be converted to a "not equal to" function block. Furthermore, if the node at the previous level of the logic node tree is a flip-flop in a sequential circuit, the input pins of the previous level node also need to be NOTed. Since the lower level is already performing analog calculations and there is no digital logic, the inverse logic operation under this branch is stopped.

[0099] Rule 5: If the current node is a function block and its logic type is a flip-flop function block (such as "Timer", "RS", "SR", etc.); if the current node is an "RS" or "SR" function block, the input sources of the DV and RV pins of "RS" and "SR" need to be replaced. For example, if the DV pin was originally connected to the output of node A and the RV pin was connected to the output of node B, it needs to be changed to: the RV pin is connected to the output of node A and the DV pin is connected to the output of node B. Furthermore, if the node at the next higher level in the logic node tree is a flip-flop in a sequential circuit, the input pins of the node at the next higher level in the logic node tree also need to be NOTed.

[0100] Rule 6: If the current node is a function block, and it is neither a function block of basic logic units such as "AND" or "OR", nor a comparison type function block, nor a trigger function block, then the current node may be a new basic logic unit created and designed by the user. This type of logic unit is not a combinational logic circuit, but may be a sequential logic circuit. In this case, the internal logic of the function block needs to be inverted according to the above method based on the internal logic of the sequential logic circuit. If the internal logic cannot be decomposed, the output of the function block can only be negated. Since the internal logic cannot be decomposed, the previous logic cannot be reversed, so the inverse logic operation under this branch should be stopped here.

[0101] Rules 1 to 6 above are the preset adjustment rules of this solution; rules 1 to 6 are only some of the preset adjustment rules used for illustrative purposes.

[0102] By using the above preset adjustment rules, the hierarchy of the logical node tree is obtained by reversing the logic layer by layer.

[0103] In this embodiment of the invention, logical segments are identified from the interlocking logic diagram, and a target logical segment within that segment is determined. A logic node tree corresponding to the target logical segment is established, and reverse logic is performed according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logical segment. This eliminates the need for manual drawing of the anti-logic, reducing configuration costs and improving configuration efficiency.

[0104] The above embodiments of the present invention Figure 1 Step S102 involves the process of identifying logical segments in the interlocking logic diagram, see [link to relevant documentation]. Figure 2 The flowchart illustrating the identification of logical segments provided in an embodiment of the present invention includes the following steps:

[0105] Step S201: Add the input bit numbers, output bit numbers, and function blocks in the interlocking logic diagram as nodes to the node list.

[0106] In the specific implementation step S201, the input tag number, output tag number and function block in the interlocking logic diagram are abstracted into nodes, and each node is added to the node list.

[0107] Step S202: Select nodes in the node list that do not belong to any logical paragraph as nodes to be processed.

[0108] It should be noted that in the initial stage, none of the nodes in the node list belong to any logical paragraph. In the specific implementation step S202, a node in the node list that does not belong to any logical paragraph is selected as the node to be processed.

[0109] Step S203: Assign the node to be processed to the blank paragraph.

[0110] In the specific implementation step S203, after selecting the node to be processed, the node to be processed is first added to the blank paragraph (the new blank logical paragraph), and the node to be processed is the first node of the blank paragraph.

[0111] Step S204: Based on the input and output pins of the node to be processed, assign the input bit number, output bit number, and function block associated with the node to be processed to the blank segment to obtain the corresponding logical segment, and return to execute step S202 until no node that does not belong to any logical segment can be found.

[0112] In the specific implementation of step S204, based on the input pins and output pins of the node to be processed, the input bit number, output bit number, and function block associated with the node to be processed are added to the blank segment corresponding to the node to be processed (at this time, the node to be processed is the first node of the blank segment), thereby obtaining the corresponding logical segment; after obtaining the logical segment, return to step S202 to continue to identify new logical segments until no node that does not belong to any logical segment can be found.

[0113] Using the above method, m nodes can be assigned to n logical paragraphs. Each node belongs to only one logical paragraph, and a logical paragraph can contain multiple nodes, where n is less than m.

[0114] To better understand how to identify logical paragraphs, the following steps A1 to A5 will be used as examples.

[0115] A1. Add the input tag numbers, output tag numbers, and function blocks in the interlocking logic diagram as nodes to the node list.

[0116] A2. Select a node from the node list that does not belong to any logical paragraph as the node to be processed, and add the node to be processed to a blank paragraph X; if no node is found or if there is no node that does not belong to any logical paragraph, go to A5.

[0117] A3. Based on the input pins of the node to be processed, locate all input pin numbers and function blocks of the node to be processed, and add the located input pin numbers and function blocks to the blank segment X. If the node to be processed has no preceding inputs, execute A4; if the node to be processed has preceding inputs, execute A3.

[0118] A4. Based on the output pins of the node to be processed, find all the output bit numbers and function blocks of the node to be processed, and add the found output bit numbers and function blocks to the blank segment X to obtain the corresponding logic segment. If the node to be processed has no post-output, jump to A2 (after the jump, the blank segment X is a new blank segment); if the node to be processed has post-output, A4 can be executed.

[0119] A5. Organize all logical paragraphs.

[0120] The above is an explanation of how to identify logical paragraphs.

[0121] To better explain the above embodiments of the present invention Figure 1 and Figure 2 Content, combined Figures 3 to 5 The following example illustrates this point:

[0122] like Figure 3The positive logic interlock configuration shown includes: AI00020001, AI00020002, DI00020001, DI00020002, DI00020000, DO00020000, a "greater than" function block (represented as >), an "exclusive OR" function block (represented as = 1), an "OR" function block (represented as ≥ 1), and an RS trigger function block. AI00020001, AI00020002, DI00020001, DI00020002, DI00020000, and DO00020000 are tag numbers.

[0123] Specifically, AI00020001 being greater than AI00020002 is output to the OR function block; DI00020001 being XORed with DI00020002 is output to the OR function block; the OR function block and DI00020000 are output to the RS trigger function block; the RS trigger function block outputs to DO00020000; the above nodes form a logic segment, which is independent of other interlocks and does not affect each other; since this logic segment has a valid output bit number, this logic segment can be used as the target logic segment for inverse logic operation.

[0124] Establish a logical node tree corresponding to the target logical segment; specifically, using the output bit number DO00020000 as the virtual root node (called the virtual root), build a tree structure forward, resulting in the following: Figure 4 The logical node tree corresponding to the target logical paragraph is shown.

[0125] Figure 4 In this context, layer 0 is a virtual root, containing no actual node data.

[0126] The first level is the output tag node DO00020000, and the RS trigger function block is its subtree;

[0127] The second layer is the RS trigger function block, and the "OR" function block and DI00020001 are its subtree branches;

[0128] The third level consists of the "OR" function block, DI00020001, the "greater than" function block, and the "XOR" function block, which are subtree branches of the "OR" function block.

[0129] The fourth layer consists of the "greater than" function block and the "exclusive or" function block. AI00020001 and AI00020002 are subtree branches of the "greater than" function block, and DI00020001 and DI00020002 are subtree branches of the "exclusive or" function block.

[0130] The fifth layer consists of AI00020001, AI00020002, DI00020001, and DI00020002.

[0131] Based on traversing the logical node tree from root to leaf (i.e., from top to bottom) and from left to right, the following reverse logical operations (1)-(4) are performed according to the level of the logical node tree to obtain the following results. Figure 5 The anti-logic interlocking configuration shown is as follows:

[0132] (1) The first level is the tag number DO0002000, and the upper level is the virtual root, which is meaningless, so skip this level.

[0133] (2) The second layer consists of one node, of type RS function block; according to the above... Figure 1 In step S105, "Rule 5" refers to a node that is an RS function block (RS flip-flop) that swaps the connections of the output pins DV and RV.

[0134] (3) The third layer consists of two nodes, of type "OR" function block and tag number DI00020001 respectively; the logic of the "OR" function block is reversed first, from left to right. According to "Rule 3" in step S105, the "OR" function block should be replaced with an "AND" function block, and because the upper layer of the "OR" function block is a flip-flop, the NOT is taken on the input pin of the flip-flop (e.g., ...). Figure 5 The hollow circle on the line connecting the RS flip-flop and the "AND" function block is the "NOT" identifier. Then, reverse the logic of bit number DI00020001, and according to "Rule 2" in step S105, invert the value on the input pin of the flip-flop (e.g., ...). Figure 5 The hollow circle on the line connecting the RS flip-flop to the tag number represents "NOT".

[0135] (4) The fourth layer consists of two nodes, with types "greater than" and "XOR" functional blocks respectively. The logic of the "greater than" functional block is reversed first, from left to right. According to "Rule 4" in step S105, the "greater than" functional block is replaced with a "less than or equal to" functional block, and the logic is not reversed further. Next, the logic of the "XOR" functional block is reversed. According to "Rule 6" in step S105, the output of the "XOR" functional block is negated, and the logic is not reversed further.

[0136] By performing the reverse logic operations of (1)-(4), we can obtain the following: Figure 5 The anti-logic interlocking configuration corresponding to the target logic segment is shown.

[0137] Based on the above, this solution has the following beneficial effects: it automatically generates anti-logic interlock configurations, reducing logical errors caused by incomplete or erroneous considerations by design engineers; it only requires designing the positive logic, eliminating the need for design engineers to write the anti-logic, thus improving configuration efficiency and saving design time and costs; and it only requires design engineers to maintain the positive logic design diagram, reducing maintenance costs.

[0138] Corresponding to the inverse logic method of configuration interlocking logic provided in the above embodiments of the present invention, see also... Figure 6 The present invention also provides a structural block diagram of an inverse logic device for configuration interlocking logic, the inverse logic device including: an acquisition unit 601, an identification unit 602, a determination unit 603, a construction unit 604, and an inverse unit 605;

[0139] The acquisition unit 601 is used to acquire the interlocking logic diagram with positive logic corresponding to the automatic control system. The interlocking logic diagram includes at least tag numbers and function blocks.

[0140] The identification unit 602 is used to identify the logic segments in the interlocking logic diagram.

[0141] The determining unit 603 is used to determine the target logical paragraph in the logical paragraph, wherein the target logical paragraph is the logical paragraph containing the output bit number.

[0142] Construction unit 604 is used to build a logical node tree corresponding to the target logical paragraph.

[0143] The reverse unit 605 is used to perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment.

[0144] In a specific implementation, the reverse unit 605 is used to: perform reverse logic on the logical node tree according to the hierarchy of the logical node tree, based on the order from root to leaf and from left to right, and adjust the functional blocks of the logical node tree according to the preset adjustment rules and the types of nodes encountered in the reverse logic process, so as to obtain the anti-logic interlocking configuration corresponding to the target logical segment. The types of nodes encountered in the reverse logic process are tag numbers or functional blocks.

[0145] In this embodiment of the invention, logical segments are identified from the interlocking logic diagram, and a target logical segment within that segment is determined. A logic node tree corresponding to the target logical segment is established, and reverse logic is performed according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logical segment. This eliminates the need for manual drawing of the anti-logic, reducing configuration costs and improving configuration efficiency.

[0146] Preferred, combined Figure 6 The content shown indicates that the identification unit 602 includes an adding module, a selecting module, a belonging module, and a processing module; the execution principle of each module is as follows:

[0147] Add a module to add input tag numbers, output tag numbers, and function blocks from the interlocking logic diagram as nodes to the node list.

[0148] The selection module is used to select nodes in the node list that do not belong to any logical paragraph as nodes to be processed.

[0149] The attribution module is used to assign the node to be processed to a blank paragraph.

[0150] The processing module is used to assign the input bit number, output bit number, and function block associated with the node to be processed to the blank segment based on the input pin and output pin of the node to be processed, so as to obtain the corresponding logical segment, and return to the execution selection module until no node that does not belong to any logical segment can be found.

[0151] Preferred, combined Figure 6 The content shown indicates that construction unit 604 includes a construction module, a traversal module, and an addition module; the execution principle of each module is as follows:

[0152] The building module is used to construct a node tree with the last element of the target logical paragraph's output bit set as the virtual root node and the subtree with the output bit of the target logical paragraph as the virtual root node.

[0153] The traversal module is used to traverse the nodes of the node tree in a top-down, left-to-right order.

[0154] The module adds a logic node tree to the subtree of the node encountered during the traversal of the node tree. This is done by adding the previous nodes (which are not yet tree nodes) connected to all the input pins of the nodes encountered during the traversal of the target logic segment.

[0155] Preferably, the present invention also provides an electronic device, including: a processor and a memory, the processor and the memory being connected via a communication bus; wherein, the processor is used to call and execute a program stored in the memory; the memory is used to store the program, the program being used to implement the inverse logic method of the configuration interlocking logic provided in the above method embodiments.

[0156] Preferably, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions for executing the inverse logic method of the configuration interlocking logic provided in the above method embodiments.

[0157] In summary, embodiments of the present invention provide a method, apparatus, storage medium, and electronic device for reversing configuration interlocking logic. The method identifies logic segments from an interlocking logic diagram and determines a target logic segment within those segments. A logic node tree corresponding to the target logic segment is established, and reverse logic is performed according to the hierarchy of the logic node tree to obtain the inverse logic interlocking configuration corresponding to the target logic segment. This eliminates the need for manual drawing of the inverse logic, reducing configuration costs and improving configuration efficiency.

[0158] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0159] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0160] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for reversing configuration interlocking logic, characterized in that, The method includes: Obtain the interlocking logic diagram corresponding to the automatic control system with positive logic. The interlocking logic diagram includes at least tag numbers and function blocks. The tag numbers represent the input data of the instrument or the data to be output to the instrument. Identify the logic segments in the interlocking logic diagram; Identify the target logical segment within the logical segments, wherein the target logical segment is the logical segment containing the output bit number; Establish a logical node tree corresponding to the target logical paragraph; Reverse logic is performed according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment. The reverse logic is the process of converting the interlocking logic configuration from positive logic to anti-logic. Establishing a logical node tree corresponding to the target logical paragraph includes: A node tree is established by taking the last part of the set of output bit numbers of the target logical paragraph as the virtual root node and taking the output bit numbers of the target logical paragraph as the subtrees of the virtual root node; The nodes of the node tree are traversed in a top-to-bottom and left-to-right order. For each node encountered during the traversal of the node tree, from the target logic segment, all the preceding nodes that are not yet tree nodes connected to the input pins of the encountered nodes are added to the subtree of the encountered nodes to obtain the logic node tree corresponding to the target logic segment.

2. The method according to claim 1, characterized in that, Identifying the logical segments in the interlocking logic diagram includes: Add the input bit numbers, output bit numbers, and function blocks in the interlocking logic diagram as nodes to the node list; Select nodes from the node list that do not belong to any logical paragraph as nodes to be processed; The nodes to be processed are assigned to blank paragraphs; Based on the input and output pins of the node to be processed, the input bit number, output bit number, and function block associated with the node to be processed are assigned to the blank segment to obtain the corresponding logical segment. Then, the process returns to the step of selecting a node in the node list that does not belong to any logical segment as the node to be processed, until no node that does not belong to any logical segment can be found.

3. The method according to claim 1, characterized in that, Perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment, including: According to the hierarchy of the logical node tree, reverse logic is performed on the logical node tree in the order from root to leaf and from left to right. Based on the preset adjustment rules and the types of nodes encountered in the reverse logic process, the functional blocks of the logical node tree are adjusted to obtain the anti-logic interlocking configuration corresponding to the target logical segment. The types of nodes encountered in the reverse logic process are tag numbers or functional blocks.

4. A reverse logic device for configuration interlocking logic, characterized in that, The device includes: The acquisition unit is used to acquire the interlocking logic diagram of the automatic control system that is positive logic. The interlocking logic diagram includes at least tag numbers and function blocks. The tag numbers represent the input data of the instrument or the data to be output to the instrument. The identification unit is used to identify the logic segments in the interlocking logic diagram; A determining unit is used to determine a target logical segment in the logical segment, wherein the target logical segment is the logical segment containing the output bit number; The construction unit is used to establish a logical node tree corresponding to the target logical paragraph; The reverse unit is used to perform reverse logic according to the hierarchy of the logic node tree to obtain the anti-logic interlocking configuration corresponding to the target logic segment. The reverse logic is the process of converting the interlocking logic configuration from positive logic to anti-logic. The building unit includes: The construction module is used to build a node tree with the last part of the set of output bits of the target logical paragraph as the virtual root node and the output bits of the target logical paragraph as the subtree of the virtual root node; The traversal module is used to traverse the nodes of the node tree in a top-to-bottom and left-to-right order; An addition module is used to add, from the target logic segment, all the preceding nodes that are not tree nodes connected to the input pins of the nodes encountered during traversal of the node tree to the subtree of the nodes encountered during traversal, so as to obtain the logic node tree corresponding to the target logic segment.

5. The apparatus according to claim 4, characterized in that, The identification unit includes: The module is used to add the input bit numbers, output bit numbers, and function blocks in the interlocking logic diagram as nodes to the node list. The selection module is used to select nodes in the node list that do not belong to any logical paragraph as nodes to be processed; The attribution module is used to assign the node to be processed to a blank paragraph. The processing module is used to assign the input bit number, output bit number, and function block associated with the node to be processed to the blank segment according to the input pin and output pin of the node to be processed, so as to obtain the corresponding logical segment, and return to execute the selection module until no node that does not belong to any logical segment can be found.

6. The apparatus according to claim 4, characterized in that, The reverse unit is specifically used to: perform reverse logic on the logical node tree according to its hierarchy, based on the order from root to leaf and from left to right; adjust the functional blocks of the logical node tree according to preset adjustment rules and the types of nodes encountered during the reverse logic process, so as to obtain the anti-logic interlocking configuration corresponding to the target logical segment; the types of nodes encountered during the reverse logic process are tag numbers or functional blocks.

7. An electronic device, characterized in that, include: A processor and a memory are connected via a communication bus; wherein the processor is used to call and execute a program stored in the memory; The memory is used to store a program that implements the inverse logic method of the configuration interlocking logic as described in any one of claims 1-3.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for performing the inverse logic method of the configuration interlocking logic as described in any one of claims 1-3.

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