HDMI device and power saving method

Abstract

A power-saving method for a High-Definition Multimedia Interface (HDMI) device is provided. The method includes detecting color depth information of video data from an HDMI source connected to an HDMI port; deriving the horizontal length of each line of an image frame in segments based on the color depth information; generating multiple synchronization signals based on the horizontal length of each line in segments; powering on the HDMI port for a predetermined time period based on the synchronization signals to obtain encrypted information from the HDMI source; and powering off the HDMI port after the predetermined time period.

Description

Technical Field

[0001] This invention generally relates to audio and video transmission technologies, and more specifically, to power-saving aspects of High-Definition Multimedia Interface (HDMI) technology. Background Technology

[0002] High-Definition Multimedia Interface (HDMI) is a licensed audio / video connector interface used to transmit encrypted digital streams, whether uncompressed or compressed. Video and audio data from various DRM-enforced digital audio / video source devices (such as set-top boxes, HD DVD players, Blu-ray players, personal computers, video game control panels, or AV receivers) can be transmitted via the HDMI digital interface to compatible HDMI receiving devices (such as digital televisions, DTVs). The HDMI standard was initially introduced in 2006 for consumer HDTV camcorders and high-end digital cameras, representing a replacement for digital rights management (DRM) with consumer analog standards such as RF (coaxial cable), composite video, S-Video, SCART, component video, and VGA, as well as digital standards like DVI (DVI-D and DVI-I).

[0003] High-bandwidth Digital Content Protection (HDPP) is a standard used to protect digital content on certain interfaces. These interfaces can be, for example, between a set-top box (STB) (used to transmit audio and video via an HDMI interface) and a television (which receives HDMI signals). Protection is achieved by encrypting the data before it leaves the sender. The legitimate receiver then decrypts the data.

[0004] Current HDMI technology requires a fast switching function between HDMI ports.

[0005] However, due to HDCP encryption, when a user switches from one HDMI port to another, the HDMI device and source need to perform some synchronization operations first. Therefore, when a user switches from one HDMI port to another, they may need to wait a short while before seeing the video displayed on the electronic device connected to the new HDMI port. Furthermore, although all active HDMI ports can be pre-synchronized with all HDMI channel signals to reduce waiting time, high power consumption remains a problem. Additionally, how to instantly switch from one HDMI port to another is also a problem that needs to be solved in this field. Summary of the Invention

[0006] To overcome the above problems, a power-saving method and HDMI device are provided for instantly switching High Definition Multimedia Interface (HDMI) ports.

[0007] This invention provides a power-saving method. An HDMI device has one HDMI port that is disabled for display. The method includes: detecting color depth information of video data from an HDMI source connected to the HDMI port; deriving the horizontal length of each line of an image frame in segments based on the color depth information; generating multiple synchronization signals based on the horizontal length of each line in the segments; powering on the HDMI port for a predetermined time period based on the multiple synchronization signals to obtain encrypted information from the HDMI source; and powering off the HDMI port after the predetermined time period.

[0008] One embodiment of the present invention provides a High-Definition Multimedia Interface (HDMI) device. The HDMI device includes an HDMI interface, a second HDMI port, and an HDMI sync signal generator. The HDMI interface includes a plurality of HDMI ports. The HDMI ports include a first HDMI port and a second HDMI port. The first HDMI port is initially enabled for display. The second HDMI port is disabled for display. The HDMI sync signal generator is coupled to the HDMI interface. The HDMI sync signal generator provides a synchronization signal based on data from an HDMI source coupled to the second HDMI port.

[0009] Other aspects and features of the invention will become apparent to those skilled in the art upon reading the following description of specific embodiments of HDMI devices and power-saving methods for instantly switching HDMI ports.

[0010] The present invention provides a power-saving method for switching HDMI ports in an HDMI device and a mechanism for instantly switching ports. In power-saving mode, the HDMI synchronization signal generator calculates and transmits a virtual segmentation domain and generates enable data to the backend, causing the backend to appear to be operating in normal power-saving mode, thereby achieving rapid switching between power-saving mode and normal power mode. Therefore, power-saving mode can be implemented, and power consumption is reduced. Furthermore, when a user switches from one HDMI port to another, the user can immediately see the video data without waiting for re-authentication. Attached Figure Description

[0011] The present invention will be more fully understood by referring to the following detailed description of the accompanying drawings, in which:

[0012] Figure 1 A schematic diagram of a High Definition Multimedia Interface (HDMI) according to an embodiment of the present invention is shown.

[0013] Figure 2 A schematic diagram of an HDMI synchronization signal generator according to an embodiment of the present invention is shown.

[0014] Figure 3 A schematic diagram illustrating an embodiment of the present invention for generating an HDMI synchronization signal is shown.

[0015] Figure 4 A schematic diagram of an HDMI synchronization signal generator according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram of an HDMI device according to an embodiment of the present invention is shown.

[0017] Figure 6 A schematic diagram illustrating the processing of a 30-bit dark mode according to an embodiment of the present invention is shown.

[0018] Figure 7 A schematic diagram illustrating the processing of a 36-bit dark mode according to an embodiment of the present invention is shown.

[0019] Figure 8 A schematic diagram illustrating the processing of a 48-bit dark mode according to an embodiment of the present invention is shown.

[0020] Figure 9 This is a flowchart illustrating a power-saving method for enabling fast boot or fast HDMI port switching in dark mode. Detailed Implementation

[0021] The following description is the best intended mode for carrying out the invention. This description is intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by referring to the appended claims.

[0022] The invention will be described with reference to specific embodiments and particular drawings, but is not limited thereto and is limited only by the claims. It will be further understood that the terms “comprising,” “including,” “comprising,” and / or “containing,” as used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or combinations thereof.

[0023] The use of sequential terms such as “first,” “second,” and “third” in claims to modify claim elements does not imply any priority, precedence, or order of action of one claim element relative to another claim element, or the temporal order of the actions of the method of execution. Rather, it serves only as a label to distinguish one claim element with a specific name from another element with the same name (but using ordinal terms) to differentiate claim elements.

[0024] Figure 1 A schematic diagram of a High Definition Multimedia Interface (HDMI) device 100 according to an embodiment of the present invention is shown. In embodiments of the present invention, the HDMI device 100 can be considered as a receiving device supporting high bandwidth digital content protection (HDCP) technology, such as a television, repeater, or display device, but the present invention should not be limited thereto.

[0025] like Figure 1 As shown, the HDMI device 100 includes an HDMI interface 110, an HDMI sync signal generator 120, and a power mode controller 130. In one embodiment, the HDMI device 100 includes an HDMI interface 110, an HDMI sync signal generator 120, a power mode controller 130, an HDMI media access control (MAC) layer 140, and a multiplexer 150. In another embodiment, the HDMI device 100 includes an HDMI interface 110, an HDMI sync signal generator 120, a power mode controller 130, an HDMI MAC layer 140, a multiplexer 150, and a display device 160.

[0026] The HDMI interface 110 includes multiple HDMI ports (e.g., a first HDMI port, a second HDMI port, a third HDMI port, and a fourth HDMI port, but the invention is not limited thereto). For example, the first HDMI port is initially enabled for display; the second, third, and fourth HDMI ports are disabled for display. Each HDMI port can be switched to a normal power mode (enabled mode) or a power-saving mode via the power mode controller 130.

[0027] It should be noted that, in order to clarify the concept of this invention, Figure 1 This is a simplified schematic diagram, showing only the elements relevant to the present invention. However, the present invention should not be limited to... Figure 1 The content shown.

[0028] In one embodiment, an HDMI sync signal generator 120 is coupled to an HDMI interface 110. A power mode controller 130 is coupled to the HDMI interface 110, an HDMI MAC layer 140, a multiplexer 150, and the HDMI sync signal generator 120. The HDMI sync signal generator 120 is connected to a display device 160. The HDMI interface 110 is connected to both the HDMI sync signal generator 120 and the HDMI MAC layer 140. The HDMI sync signal generator 120 and the HDMI MAC layer 140 are coupled to the HDMI sync signal generator 120.

[0029] In normal color mode, the color depth is 24 bits per pixel. Each of the three channels of an HDMI port can process 8 bits in a TMDS clock. However, in dark mode, the color depth can be 30 bits, 36 bits, or 48 bits per pixel, thus requiring "dark pixel packing." All pixel data is grouped into a series of packed pixel groups, each carrying the same number of pixels, and each requiring the same number of TMDS clocks for transmission. In each TMDS clock, one segment of a pixel group is transmitted. The number of pixels and segments per group depends on the pixel size. For 30-bit dark mode, the pixel-to-segment-to-group ratio is 4 pixels per group and 5 segments per group. For 36-bit dark mode, the ratio is 2 pixels per group and 3 segments per group. For 48-bit dark mode, the ratio is 1 pixel per group and 2 segments per group. When dark mode is applied, signals such as horizontal synchronization signal (HSYNC), vertical synchronization signal (VSYNC), and data enable (DE) transitions will also be grouped into segments.

[0030] Figure 2 A block diagram of an HDMI synchronization signal generator 120 according to an embodiment of the present invention is shown.

[0031] In one embodiment, the HDMI sync signal generator 120 includes a horizontal sync valid and invalid detector 310, a total level calculation device 320, and a horizontal sync generator 330. These components can be implemented in hardware, such as circuits, chips, and / or devices.

[0032] In one embodiment, the horizontal synchronization valid and invalid detector 310 detects the HDMI synchronization valid timing and the corresponding HDMI synchronization invalid timing, and sends the HDMI synchronization valid timing and the corresponding HDMI synchronization invalid timing to the overall horizontal calculation device 320.

[0033] In one embodiment, the total horizontal calculation device 320 is coupled to the horizontal sync valid and invalid detector 310. The total horizontal calculation device 320 receives N HDMI sync valid timing sequences (e.g., four HDMI sync valid timing sequences used to calculate four horizontal lines) and corresponding N HDMI sync invalid timing sequences (e.g., four HDMI sync invalid timing sequences applied to four HDMI sync valid timing sequences for four horizontal lines). The total horizontal calculation device 320 obtains the number of pixels h of the horizontal lines in the image frame by calculating and summing the number of segments in each of the N lines, and dividing each value by the number of dark references. total for 1 line Depending on the color depth of the pixel, the variable "N" mentioned above and the dark reference number are different. For example, for 30-bit dark mode, the variable "N" is 4 and the dark reference number is 5; for 36-bit dark mode, the variable "N" is 2 and the dark reference number is 3; and for 48-bit dark mode, the variable "N" is 1 and the dark reference number is 2.

[0034] Figure 3 A schematic diagram illustrating an embodiment of the present invention generates an HDMI synchronization signal. Figure 3 In the image frame, the length between two adjacent effective horizontal synchronization timings represents the horizontal length L of the horizontal line. p L p This indicates the number of segments to be transmitted for each horizontal line. However, due to the application of dark pixel packing, the horizontal length Lp may vary line by line in the image frame.

[0035] In one embodiment, a horizontal sync generator 330 is coupled to a horizontal sync valid and invalid detector 310 and a total horizontal calculation device 320. The horizontal sync generator 330 receives an initial HDMI sync valid timing from the horizontal sync valid and invalid detector 310 and a horizontal length L from the total horizontal calculation device 320. pAnd based on the initial HDMI synchronization effective timing and horizontal length L p A virtual HSYNC is generated in the segmented domain of the second HDMI port.

[0036] In one embodiment, when the 30-bit dark mode is applied, 10 bits of data for each channel of the second HDMI port are processed for each pixel. The total horizontal calculation device 320 calculates the number of pixels h of the horizontal lines in the image frame using the following equation. total for 1 line :

[0037] h total for 1 line = N fragments for 4 lines / 5

[0038] Where, N fragments for 4 lines This indicates the number of segments to be transmitted in the four horizontal rows of the image frame.

[0039] Subsequently, the number of pixels h of the horizontal line in the image frame total for 1 line This can be represented as 4k+i. The symbol k is a positive integer, and the symbol i is a positive integer representing the remainder between 0 and 3. For example, if there are 1875 pixels on a horizontal line, h... total for 1 line =4k+i, where k=468 and i=3.

[0040] Using the values ​​of "k" and "i", the horizontal length L of each line is... p (like Figure 3 (As shown) can be calculated using the following equation:

[0041] ,

[0042] symbol L p The horizontal length can be represented in segments, i.e., L. p This represents the number of segments for each horizontal line in the image frame. It's important to note that the number of segments for each line in an image frame may vary. The symbol 'p' represents the row index. The horizontal length of each segment can be obtained from the values ​​of 'k' and 'i' derived from the number of pixels in the horizontal lines of the image frame, and from the floor function equation. For example, in a horizontal line with 1875 pixels, the value of 'k' is 468 and the value of 'i' is 3. The number of segments L1 in the first row is 5 * 468 + ... 5 / 4*3*1 - 5 / 4*3*(1-1) =5*468+3. The number of segments L2 in the second line is 5*468+3. 5 / 4*3*2 - 5 / 4*3*(2-1) = 5*468+4. The number of segments L in the nth row. n5*468+ 5 / 4*3*n - 5 / 4*3*(n-1) Accordingly, the number of segments in each row of the image frame can be obtained.

[0043] Based on the initial HDMI synchronization effective timing and horizontal length L p The subsequent effective timing of synchronization can be predicted, and virtual HSYNCs can be generated.

[0044] Figure 3 A schematic diagram illustrating an embodiment of the present invention generates an HDMI synchronization signal. Figure 3 In the diagram, hsync_active indicates an active HDMI synchronization timing sequence, and hsync_inactive indicates an inactive HDMI synchronization timing sequence. Based on the active and inactive HDMI synchronization timing sequences, the horizontal sync generator 330 generates a positive (polarity+) synchronization signal hsync and a negative (polarity-) synchronization signal hsync.

[0045] Figure 4 A block diagram of an HDMI sync signal generator 120 according to an embodiment of the present invention is shown. In one embodiment, the HDMI sync signal generator 120 includes a horizontal sync valid detector 510, a total vertical calculation device 520, a vertical sync valid and invalid detector 530, and a vertical sync signal generator 540. These components can be implemented in hardware, for example as circuits, chips, and / or devices.

[0046] In one embodiment, a horizontal sync valid detector 510 is configured to detect the HSYNC signal for each horizontal line in an image frame. A total vertical calculation device 520 is coupled to the horizontal sync valid detector 510. The total vertical calculation device 520 calculates the number of horizontal lines in the image frame by counting the HSYNC signal between two adjacent rising edges of the VSYNC signal. A vertical sync valid and invalid detector 530 is coupled to the total vertical calculation device 520. The vertical sync valid and invalid detector 530 detects multiple rising edges or multiple falling edges of the VSYNC signal, and the total vertical calculation device 520 calculates the number of rising edges of the HSYNC signal between two adjacent rising edges of the VSYNC signal. A vertical sync signal generator 540 is coupled to the total vertical calculation device 520 and the vertical sync valid and invalid detector 530. The vertical sync signal generator 540 generates a virtual VSYNC signal in the segmented domain of the second HDMI port based on the number of rising edges of the HSYNC of the frame and the horizontal lines.

[0047] In one embodiment, a line has only one rising edge. The rise time of the HDMI sync signal in a frame is calculated (counting stops when the VSYNC rising edge of the next frame is encountered). The number of vertical lines can then be calculated. By detecting the number of vertical lines in a frame, a virtual signal can be generated. This virtual signal has a fixed period.

[0048] Figure 5 A schematic diagram of an HDMI device according to an embodiment of the present invention is shown. In the segmented domain, virtual HSYNC and virtual VSYNC in the segmented domain are input to the dark processor 610.

[0049] In one embodiment, when the power mode signal to multiplexer 630 is a normal power mode signal, dark processor 610 receives the horizontal and vertical segmented domains of the first HDMI input. It then transmits the video data from the first HDMI input (initially enabled for display), the horizontal and vertical segmented domains of the first HDMI input, and the video data to multiplexer 630 to display the video data from the first HDMI input.

[0050] In one embodiment, when the power mode signal to multiplexer 630 is a power-saving mode signal, dark processor 610 receives virtual horizontal segmentation domains and virtual vertical segmentation domains from the second HDMI input, which are generated by vertical and horizontal sync generators. Dark processor 610 then converts the virtual horizontal segmentation domains and virtual vertical segmentation domains into virtual HSYNC signals and virtual VSYNC signals, and sends the virtual HSYNC and VSYNC signals from the second HDMI input to data enable scaling calculator 620. Enable scaling calculator 620 generates a DE signal and sends the DE signal along with the virtual HSYNC and VSYNC signals to multiplexer 630.

[0051] In one embodiment, the multiplexer 630 is configured to control the selection of a normal power mode or a power-saving mode.

[0052] In one embodiment, the horizontal segmentation domain is a sawtooth domain (the input to the data-enabled scaling calculator 620 is a sawtooth timing, and the output of the data-enabled scaling calculator 620 is also a virtual sawtooth domain).

[0053] In one embodiment, under normal power mode, the dark processor 610 directly transmits the horizontal segmented domain, vertical segmented domain, and video data to the multiplexer 630. If the multiplexer 630 detects instability in at least one of the domains, it enters a reset mode. In one embodiment, under power-saving mode, the length of the virtual signal changes because the data is invisible after power failure. The horizontal segmented domain, vertical segmented domain, and video data (which can be considered as virtual horizontal segmented domains, vertical segmented domains, and virtual video data) are calculated by the data-enabled scaling calculator 620. The backend assumes the signal is normal, and thus the power-saving mode operates normally.

[0054] In one embodiment, the virtual HSYNC and virtual VSYNC signals can be generated by a horizontal sync generator 330 and a vertical sync generator 540. In the simulated virtual signal method, the sync signal, i.e., the squared timing, is derived from the equation mentioned above and transmitted to the backend. Simultaneously, the virtual signals can be used to enable initially disabled HDMI ports within a predetermined time period, thereby obtaining encrypted information from the source device. In this embodiment, the encrypted information is HDCP information. In this embodiment, by acquiring updated HDCP information, virtual HSYNC, virtual VSYNC, and DE signals are generated. When the normal power mode signal is transmitted, the initially disabled HDMI port can be enabled to transmit video data, and this video data can be displayed very quickly.

[0055] Figure 6 This is a schematic diagram illustrating the processing of a 30-bit dark mode according to an embodiment of the present invention. Figure 6 In this configuration, when 30-bit dark mode is applied, 10 bits of data from each channel of the second HDMI port will be processed for each pixel. Each segment (i.e., 10P0-10P4, 10C0-10C4, 10PC2-10PC4) can process 8 bits. Each uppercase letter AD represents 2 bits. Each uppercase letter SV and (V) represents 8 bits.

[0056] Figure 7 A schematic diagram illustrating the processing of a 36-bit dark mode according to an embodiment of the present invention is shown. Figure 7 In this mode, when 36-bit dark mode is applied, 12 bits of data from each channel of the second HDMI port will be processed for each pixel. Each segment (i.e., 12P0-12P2, 12C0-12C2) can process 8 bits.

[0057] refer to Figure 2 In one embodiment, when the 36-bit dark mode is applied, 12 bits of data for each channel of the second HDMI port are processed for each pixel. The total horizontal calculation device 320 calculates the number of pixels h of the horizontal lines in the image frame using the following equation. total for 1 line :

[0058] h total for 1 line = N fragments for 2 lines / 3

[0059] N Fragments for 2 line This indicates the number of segments to be transmitted for the two horizontal lines in an image frame.

[0060] Subsequently, the number of pixels h of the horizontal line in the image frame total for 1 line It can be represented as 2k+i. The symbol k is a positive integer, and the symbol i is a positive integer with a remainder between 0 and 1. For example, if there are 1875 pixels on a horizontal line, h total for 1 line =2k+i, where k=937 and i=1.

[0061] Using the values ​​of "k" and "i", the horizontal length L of each line is... p (like Figure 3 (As shown) can be calculated using the following equation:

[0062] ,

[0063] symbol L p The horizontal length can be represented in segments, i.e., L. p This represents the number of segments for each horizontal line in an image frame. It's important to note that the number of segments for each line in an image frame may vary. The symbol 'p' represents the row index. The horizontal length of each segment can be obtained from the values ​​of 'k' and 'i' derived from the number of pixels in the horizontal lines of the image frame, and from the floor function equation. For example, for a horizontal line of 1875 pixels, the value of 'k' is 937, and the value of 'i' is 1. The number of segments L1 in the first row is 3 * 937 + 1. 3 / 2*1*1 - 3 / 2*1*(1-1) =3*937+1. The number of segments L2 in the second line is 3*937+1. 3 / 2*1*2 - 3 / 2*1*(2-1) =3*937+1= 3*937+2. The number of segments Lm in the m-th row is 3*937+1. 3 / 2*1*m - 3 / 2*1*(m-1) Accordingly, the number of segments for each line in the image frame can be obtained.

[0064] Based on the initial HDMI synchronization effective timing and horizontal length L p The subsequent effective timing of synchronization can be predicted, and a virtual HSYNC can be generated.

[0065] Figure 8 A schematic diagram illustrating the processing of a 48-bit dark mode according to an embodiment of the present invention is shown. Figure 8 As shown, when 48-bit dark mode is applied, 16 bits of data from each channel of the second HDMI port will be processed for each pixel. Each segment (i.e., 16P0-12P1, 16C0-12C1) can process 8 bits. Each uppercase letter "A" represents 4 bits. Each uppercase letter S and (S) represents 8 bits.

[0066] refer to Figure 2 In one embodiment, when the 48-bit dark mode is applied, 19 bits of data for each channel of the second HDMI port are processed for each pixel. The total horizontal calculation device 320 calculates the number of pixels h of the horizontal lines in the image frame using the following equation. total for 1 line :

[0067] h total for 1 line = N fragments for 1 line / 2

[0068] N Fragments for 1 line This indicates the number of segments to be transmitted in a horizontal line of an image frame.

[0069] Subsequently, the number of pixels h of the horizontal line in the image frame total for 1 line This can be represented as k. The symbol k is a positive integer. For example, if a horizontal line has 1875 pixels, h total for 1 line = k, where k = 1875.

[0070] Using the value of "k", the horizontal length L of each line p (like Figure 3 (As shown) can be calculated using the following equation:

[0071] ,

[0072] symbol L p The horizontal length can be represented in segments, i.e., L. p This represents the number of segments for each horizontal line in the image frame. The symbol p represents the row index. The horizontal length can be obtained from the value k, derived from the number of pixels in the horizontal lines of the image frame. For example, if a horizontal line has 1875 pixels, the value of k is 1875, and the value of i is 1. The number of segments L1 in the first row is 2 * 1875. The number of segments L2 in the second row is 2 * 1875. The number of segments Lq in the qth row is 2 * 1875. Accordingly, the number of segments for each line in the image frame can be obtained.

[0073] Based on the initial HDMI synchronization effective timing and horizontal length L p The subsequent effective timing of synchronization can be predicted, and a virtual HSYNC is generated.

[0074] In this embodiment, the HDMI receiving device includes multiple HDMI ports (e.g., a first HDMI port and a second HDMI port, but the invention is not limited thereto) coupled to multiple HDMI source devices (e.g., a first HDMI source device and a second HDMI source device, but the invention is not limited thereto). The first HDMI port operates in normal power mode, receiving data from the first source device, and simultaneously acquiring HDCP information, thus allowing video data from the first source to be displayed. The second HDMI port cannot display or operate in power-saving mode. Disabled HDMI ports are only powered on when acquiring HDCP information from the corresponding HDMI source device. Therefore, the VSYNC signal must be predicted and simulated in power-saving mode.

[0075] Figure 9 This is a flowchart illustrating a power-saving method 200 for enabling quick on or quick HDMI port switching when dark mode is applied.

[0076] In step 210, color depth information of video data from an HDMI source connected to an HDMI port that is disabled for display is detected.

[0077] Color depth information depends on the video data from the HDMI source. Dark depth is typically retrieved from the HDMI source's video data in a 30-bit, 36-bit, or 48-bit color mode.

[0078] In step 220, based on the color depth information, the horizontal length L of each segmented line is derived. p Taking 30-bit color mode as an example, the number of pixels h of the horizontal line in an image frame. total for 1 line Calculated by the following formula:

[0079] h total for 1 line = N fragments for 4 lines / 5

[0080] N Fragments for 4 line This indicates the number of segments to be transmitted for the four horizontal lines in the image frame.

[0081] Subsequently, the number of pixels h of the horizontal line in the image frame total for 1 line This can be represented as 4k+i. The symbol k is a positive integer, and the symbol i is a positive integer representing the remainder between 0 and 3. For example, if a horizontal line has 1875 pixels, h... total for 1 line = 4k+i, where k=468 and i=3.

[0082] Using the values ​​of "k" and "i", the horizontal length L of each line is... p (like Figure 3 (As shown) can be calculated using the following equation:

[0083] ,

[0084] symbol L p This indicates the horizontal length of the segment. That is, L. p This represents the number of segments for each horizontal line in an image frame. It's important to note that the number of segments for each line in an image frame may vary. The symbol p represents the row index. The horizontal length of each segment can be obtained from the values ​​of k and i derived from the number of pixels in the horizontal lines of the image frame, and from the floor function equation. For example, in a horizontal line with 1875 pixels, the value of k is 468, and the value of i is 3. The number of segments L1 in the first row is 5 * 468 + ... 5 / 4*3*1 - 5 / 4*3*(1-1) =5*468+3. The number of segments L2 in the second line is 5*468+3. 5 / 4*3*2 - 5 / 4*3*(2-1) = 5*468+4. The number of segments Ln in the nth row is 5*468+4. 5 / 4*3*n - 5 / 4*3*(n-1) Accordingly, the number of segments for each line in the image frame can be obtained.

[0085] The derivation details of the 36-bit and 48-bit color modes have been described in the previous text and will not be repeated here.

[0086] In step 230, based on the horizontal length L of each line p Generate a synchronization signal.

[0087] Horizontal length L p It is the segmentation quantity between two HSYNC signals of adjacent horizontal lines. It utilizes the initial HSYNC and the horizontal length L. p The timing of subsequent HSYNC signals can be predicted, and subsequent HSYNC signals can be generated accordingly.

[0088] Once the HSYNC signal can be predicted and generated, the VSYNC signal can be generated using information about the number of horizontal rows in the image frame and the count of the HSYNC signal.

[0089] In step 240, the HDMI port is powered on for a predetermined time period according to the synchronization signal to obtain encrypted information from the HDMI source, and then powered off the HDMI port after the predetermined time period. In one embodiment, the encrypted information is HDCP information.

[0090] Typically, HDCP information is located at a specific position associated with the HSYNC and VSYNC signals in an image frame. Once the HSYNC and VSYNC signals can be simulated, the HDMI port can be powered on for a predetermined period to acquire HDCP information from the HDMI source, and then powered off after acquiring the HDCP information. Based on this embodiment, HDCP information for each image frame of video data can be acquired by the HDMI receiving device. If a user wants to switch the display of video data connected to an initially disabled HDMI port, the video data can be displayed in a very short time without loss of HDCP information.

[0091] The present invention provides a power-saving method for enabling rapid on / off or rapid HDMI port switching when dark mode is applied, offering a mechanism for immediate port switching. In power-saving mode, an HDMI sync signal generator calculates and transmits a virtual segmentation domain and generates enable data for the backend, causing the backend to treat it as operating in normal power mode, thereby achieving rapid switching between power-saving mode and normal power mode. Thus, power-saving mode can be implemented, reducing power consumption. Furthermore, when a user switches from one HDMI port to another, the user can immediately see the video data without waiting for re-authentication.

[0092] The steps of the methods described in conjunction with the aspects disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module (e.g., including executable instructions and associated data) and other data can reside in data storage, such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable storage medium known in the art. The sample storage medium can be coupled to a machine, such as a computer / processor (which may be referred to herein as a "processor"), such that the processor can write information from and to the storage medium. The sample storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user device. Alternatively, the processor and storage medium can reside as discrete components in a user device. Furthermore, in some aspects, any suitable computer program product may include a computer-readable medium comprising code relating to one or more aspects of this disclosure. In some aspects, the computer software product may include packaging material.

[0093] It should be noted that, although not explicitly specified, one or more steps of the methods described herein may include steps for storing, displaying, and / or outputting data as needed for a particular application. In other words, any data, records, fields, and / or intermediate results discussed in the methods may be stored, displayed, and / or output to another device as needed for a particular application. Although the foregoing pertains to embodiments of the invention, other and further embodiments of the invention may be designed without departing from its basic scope. Various embodiments or portions thereof presented herein may be combined to produce further embodiments. The above description represents the best contemplated mode for carrying out the invention. This description is made to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims.

[0094] The preceding paragraphs describe many aspects. It is evident that the teachings of this invention can be implemented in various ways, and any particular configuration or function in the disclosed embodiments represents only representative conditions. Those skilled in the art will understand that all aspects disclosed in this invention can be applied independently or incorporated into it.

[0095] Although the invention has been described by way of example and preferred embodiments, it should be understood that the invention is not limited thereto. Various modifications and alterations can be made by those skilled in the art without departing from the scope and spirit of the invention. Therefore, the scope of the invention should be defined and protected by the appended claims and their equivalents.

Claims

1. A power-saving method for a high-definition multimedia interface device, the high-definition multimedia interface device including a high-definition multimedia interface port, wherein the high-definition multimedia interface port is disabled for display, the method comprising: Detect color depth information of video data from a high-definition multimedia interface source, wherein the high-definition multimedia interface source is connected to the high-definition multimedia interface port; Based on the color depth information, the horizontal length of each row of the image frame is derived in segments; Multiple synchronization signals are generated based on the horizontal length of each row in the segment; as well as Powering on the high-definition multimedia interface port according to the plurality of synchronization signals within a predetermined time period to obtain encrypted information from the high-definition multimedia interface source, and powering off the high-definition multimedia interface port after the predetermined time period.

2. The power-saving method for a high-definition multimedia interface device as described in claim 1, characterized in that, Deriving the horizontal length of each row by segmentation includes: converting the number of pixels in each row of the image frame into the number of segments in each row of the image frame based on the color depth information.

3. The power-saving method for a high-definition multimedia interface device as described in claim 2, characterized in that, When the color depth information is in 30-bit dark mode, the number of pixels in each row is represented by 4k+i, where k is a positive integer and i is an integer between 0 and 3; and According to the horizontal length L of each row in the segment. p This can be derived from the following equation: ， Wherein, p represents the row index.

4. The power-saving method for a high-definition multimedia interface device as described in claim 2, characterized in that, When the color depth information is in 36-bit dark mode, the number of pixels in each row is represented by 2k+i, where k is a positive integer; and According to the horizontal length L of each row in the segment. p This can be derived from the following equation: ， Where p represents the row index and i is an integer between 0 and 1.

5. The power-saving method for a high-definition multimedia interface device as described in claim 2, characterized in that, When the color depth information is in 48-bit dark mode, the number of pixels in each row is represented by 2k, where k is a positive integer; and According to the horizontal length L of each row in the segment. p This can be derived from the following equation: , Where p represents the row index.

6. The power-saving method for a high-definition multimedia interface device as described in claim 1, characterized in that, The virtual horizontal sync signal (HSYNC) of the high-definition multimedia interface port is generated based on the horizontal length of each line of the segmented image frame.

7. The power-saving method for a high-definition multimedia interface device as described in claim 6, characterized in that, The virtual horizontal sync signal (HSYNC) of the high-definition multimedia interface port is generated by calculating the number of horizontal sync signals of the image frames.

8. A high-definition multimedia interface device, comprising: A high-definition multimedia interface (HDMI) includes multiple HDMI ports, wherein the multiple HDMI ports include: The first high-definition multimedia interface port is initially enabled for display. The second high-definition multimedia interface port is disabled for display; A high-definition multimedia interface (HDMI) synchronization signal generator is coupled to the HDMI, wherein the HDMI synchronization signal generator provides a synchronization signal based on data from an HDMI source, wherein the HDMI source is coupled to a second HDMI port. A power mode controller is coupled to the high-definition multimedia interface, the multiplexer, and the high-definition multimedia interface synchronization signal generator, wherein the power mode controller is configured to send a power mode signal to the multiplexer. The display device is coupled to the power mode controller, and the display device displays video data according to the power mode signal received by the multiplexer.

9. The high-definition multimedia interface device as described in claim 8, characterized in that, When the multiplexer receives the power mode signal and the power mode signal is a normal power mode signal, video data from the High Definition Multimedia Interface Media Access Control layer is selected for display.

10. The high-definition multimedia interface device as described in claim 8, characterized in that, When the multiplexer receives the power mode signal and the power mode signal is in power-saving mode, the synchronization signal from the high-definition multimedia interface synchronization signal generator is transmitted.

11. The high-definition multimedia interface device as described in claim 8, characterized in that, The high-definition multimedia interface synchronization signal generator includes: Overall level calculation device; and A horizontal synchronization detector is used to detect the synchronization timing of multiple high-definition multimedia interfaces and to send the synchronization timing of the multiple high-definition multimedia interfaces to the overall horizontal computing device. The overall horizontal calculation device is coupled to the horizontal synchronization detector to receive the synchronization timing of the plurality of high-definition multimedia interfaces, and is configured to derive the horizontal length of each line of the image frame in segments.

12. The high-definition multimedia interface device as described in claim 11, characterized in that, The high-definition multimedia interface synchronization signal generator also includes: A horizontal sync signal generator, coupled to the horizontal sync detector and the overall horizontal calculation device, wherein the horizontal sync signal generator generates a horizontal sync signal (HSYNC) for the second high-definition multimedia interface port based on the horizontal length of each line.

13. The high-definition multimedia interface device as described in claim 12, characterized in that, The high-definition multimedia interface synchronization signal generator also includes: A horizontal synchronization effective detector is used to detect the horizontal synchronization signal for each line of the image frame; and A total vertical computing device is coupled to the horizontal synchronization effective detector to obtain the number of multiple horizontal lines in the image frame.

14. The high-definition multimedia interface device as described in claim 13, characterized in that, The high-definition multimedia interface synchronization signal generator also includes: A vertical synchronization detector, coupled to the overall vertical computing device, is used to detect the vertical synchronization signal (VSYNC); and A vertical synchronization signal generator, coupled to the total vertical calculation device and the vertical synchronization detector, is used to provide the vertical synchronization signal based on the number of multiple vertical lines in the image frame.

15. The high-definition multimedia interface device as described in claim 8, characterized in that, When the power mode signal input to the multiplexer is a normal power mode signal, the dark processor receives the horizontal and vertical segmented fields of the first high-definition multimedia interface port, as well as the video data transmitted from the first high-definition multimedia interface port that is initially enabled for display, the horizontal and vertical segmented fields of the first high-definition multimedia interface port, and the video data to the multiplexer to display the video data from the first high-definition multimedia interface port.

16. The high-definition multimedia interface device as described in claim 8, characterized in that, When the power mode signal input to the multiplexer is a power-saving mode signal, the dark processor receives the virtual horizontal segmentation domain and virtual vertical segmentation domain of the second high-definition multimedia interface port. The virtual horizontal segmentation domain and virtual vertical segmentation domain of the second high-definition multimedia interface port are generated by the horizontal synchronization signal generator and the vertical synchronization signal generator. The dark processor converts the virtual horizontal segmentation domain and the virtual vertical segmentation domain into virtual horizontal synchronization signals and virtual vertical synchronization signals, and transmits the virtual horizontal synchronization signal and multiple vertical synchronization signals of the second high-definition multimedia interface port to the data enable scaling calculator. The data enable scaling calculator generates a data enable signal and transmits the data enable signal together with the virtual horizontal synchronization signal and the multiple vertical synchronization signals to the multiplexer.

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