A fast comparator suitable for high voltage and large swing

Abstract

The present invention discloses a fast comparator suitable for high voltage and large swing, comprising a low-delay sampling circuit, a comparator core circuit, a driving capability enhancement circuit and a high-low level conversion circuit, wherein the input end of the low-delay sampling circuit inputs a sampled signal V_SH, the output end of the low-delay sampling circuit is connected to the first input end of the comparator core circuit, the second input end of the comparator core circuit inputs a reference voltage V_REF, the output end of the comparator core circuit is connected to the input end of the driving capability enhancement circuit, the output end of the driving capability enhancement circuit is connected to the input end of the high-low level conversion circuit, and the output end of the high-low level conversion circuit generates an output signal V‑OUT. The present invention can process input signals with large swings, perform accurate low-delay sampling of input signals with large swings, complete output signal flipping faster, reduce time delay, and convert high-voltage signals to low-voltage domains with low delay without increasing power consumption.

Description

Technical Field

[0001] The invention relates to a comparator, in particular to a fast comparator suitable for high voltage and large swing, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In the all-NMOS high-voltage H-bridge drive circuit, the connection point of the upper and lower NMOS of the same half bridge is defined as SH. There is a control mode to improve EMI control and NMOS on and off time, which requires collecting information about the voltage at the SH point, specifically the relationship between SH and the reference voltage. Since the reference voltage is high voltage, and the control mode requires a lower latency, and the digital logic circuit running the control mode is low voltage. Therefore, this technical problem requires a low-latency fast comparator whose input voltage can be a large swing, works in the high voltage domain, and whose output signal is a low-voltage domain of the digital circuit.

[0003] Prior art 1: Chinese patent publication number CN116404853A discloses a high-side driving method, device and circuit for an N-type dual H-bridge motor driver chip, including the steps of: obtaining the gate voltage of the NMOS driver tube; comparing the gate voltage of the NMOS driver tube with the preset voltage, and using negative feedback to keep the gate voltage near the preset voltage. This method divides the driving process of the NMOS driver tube at the high side into two charging stages, which greatly shortens the turn-on time of the NMOS driver tube at the high side. This technical solution can achieve pre-charging and shorten the turn-on time of the high-side NMOS. However, its comparator output signal is in the high-voltage domain, so its control cannot introduce digital logic and cannot achieve more precise regulation. At the same time, its comparator circuit does not focus on low latency, resulting in a large lag in its control.

[0004] Prior art 2: Chinese patent publication number CN115996044A discloses a fast comparator, including a differential input pair of tubes and tail current, a load circuit, a common source amplifier circuit, a digital logic circuit, a Class AB output control circuit and a clamping circuit. By adding a Class AB output control circuit and a clamping circuit, it is possible to prevent the relevant MOS tubes in the circuit from entering the deep linear region, ensure that there is no large voltage fluctuation at the key nodes, and achieve the characteristic of a small comparator transmission delay. This solution is limited by the lack of input sampling and limiting circuits. When the input signal swing is large, the gate of the input pair of tubes will be broken down, and it cannot be applied to high-voltage working environments.

[0005] Prior art 3: Chinese patent publication number CN116346095A discloses a high-speed comparator circuit with adjustable speed. Its structure adds a speed adjustment circuit on the basis of the traditional latch, so that the comparator speed is no longer limited by the power supply voltage, effectively improving the comparison speed of the comparator. It is suitable for high-speed analog-to-digital conversion applications in low power supply voltage scenarios. This solution adopts a pre-amplifier and a post-stage latch structure to reduce latency. However, an additional clock signal is required to work properly. In a high-voltage environment, it is difficult to have an external high-frequency clock signal. Therefore, it cannot be applied to high-voltage working environments.

[0006] It can be seen that the existing fast comparators basically work in the low voltage domain and cannot adapt to the high voltage working environment. At the same time, some inventions rely on external clock signals, which is not conducive to working in a high voltage environment. Finally, due to the lack of consideration of the high voltage working environment, the existing technology basically does not consider the problem of output signal voltage domain conversion, which results in that even if the existing technology is forcibly applied to a high voltage environment, its output signal cannot be transmitted to the digital logic module, and the circuit performance cannot be precisely controlled. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a fast comparator suitable for high voltage and large swing, so as to sample the large swing signal in a high voltage environment and convert the high voltage signal to a low voltage domain with low delay.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A fast comparator suitable for high voltage and large swing comprises a low-delay sampling circuit, a comparator core circuit, a driving capability enhancement circuit and a high-low level conversion circuit. The input end of the low-delay sampling circuit inputs a sampled signal V_SH, the output end of the low-delay sampling circuit is connected to a first input end of the comparator core circuit, the second input end of the comparator core circuit inputs a reference voltage V_REF, the output end of the comparator core circuit is connected to an input end of the driving capability enhancement circuit, the output end of the driving capability enhancement circuit is connected to an input end of the high-low level conversion circuit, and the output end of the high-low level conversion circuit generates an output signal V-OUT.

[0010] Furthermore, the low-latency sampling circuit includes a high-voltage resistant PMOS tube DEPM1, a resistor R1, a Zener diode D1 and a PMOS tube PM2, the source of the PMOS tube PM2 is connected to the power supply VS, the gate of the PMOS tube PM2 is connected to the bias voltage V_bias, the drain of the PMOS tube PM2 is connected to the cathode of the Zener diode D1 and the source of the high-voltage resistant PMOS tube DEPM1 and outputs a sampling signal V_SH1, the drain of the high-voltage resistant PMOS tube DEPM1 is connected to the sampled signal V_SH, the gate of the high-voltage resistant PMOS tube DEPM1 is connected to the anode of the Zener diode D1 and one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VS-5.

[0011] Further, the power supply VS-5 is a power rail 5V lower than the voltage of the power supply VS.

[0012] Furthermore, the comparator core circuit includes NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, NMOS tube NM7, NMOS tube NM8, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, current source I1, resistor R3 and resistor R4, one end of the current source I1 is connected to the PMOS tube PM3 The source of the PMOS tube PM4, one end of the resistor R3, one end of the resistor R4, the source of the PMOS tube PM5 and the source of the PMOS tube PM6 are connected, the other end of the current source I1 is connected to the source of the PMOS tube PM7 and the source of the PMOS tube PM8, the gate of the PMOS tube PM7 is connected to the sampling signal V_SH1, the gate of the PMOS tube PM8 is connected to the reference voltage V_REF, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 The gate of the PMOS tube PM4 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM4 and the gate of the NMOS tube NM5. The gate of the PMOS tube PM4 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM4 and the gate of the NMOS tube NM6. The source of the NMOS tube NM3 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM4 and the gate of the NMOS tube NM6. The electrode is connected to the source of the NMOS tube NM4 and one end of the current source I2, the other end of the resistor R3 is connected to the drain of the NMOS tube NM5 and the gate of the PMOS tube PM5, the other end of the resistor R4 is connected to the drain of the NMOS tube NM6 and the gate of the PMOS tube PM6, the source of the NMOS tube NM5 is connected to the source of the NMOS tube NM6 and one end of the current source I3, the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM7 and the gate of the NMOS tube NM8 and outputs a signal V_P, the drain of the PMOS tube PM6 is connected to the drain of the NMOS tube NM8 and the gate of the NMOS tube NM7 and outputs a signal V_N, the source of the NMOS tube NM1, the source of the NMOS tube NM2, the other end of the current source I2, the other end of the current source I3, the source of the NMOS tube NM7 and the source of the NMOS tube NM8 are connected to the power supply VS-5.

[0013] Further, the PMOS tube PM7, PMOS tube PM8, PMOS tube PM3, PMOS tube PM4, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, resistor R3 and resistor R4 form a three-stage operational amplifier, and the PMOS tube PM5, PMOS tube PM6, NMOS tube NM7 and NMOS tube NM8 form a latch.

[0014] Further, the driving capability enhancement circuit comprises a PMOS tube PM9, a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM9, an NMOS tube NM10, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13 and an NMOS tube NM14, a source of the PMOS tube PM9, a source of the PMOS tube PM10, a source of the PMOS tube PM11, a source of the PMOS tube PM12, a source of the PMOS tube PM13 and a source of the PMOS tube PM14 are connected to a power supply VS, a gate of the PMOS tube PM9 and a gate of the NMOS tube NM9 are connected to a signal V_P, a gate of the PMOS tube PM10 and a gate of the NMOS tube NM10 are connected to a signal V_N, The gate of the PMOS tube PM11 is connected to the gate of the NMOS tube NM11, the drain of the PMOS tube PM9 and the drain of the NMOS tube NM9, the gate of the PMOS tube PM12 is connected to the gate of the NMOS tube NM12, the drain of the PMOS tube PM10 and the drain of the NMOS tube NM10, the gate of the PMOS tube PM13 is connected to the gate of the NMOS tube NM13, the drain of the PMOS tube PM11 and the drain of the NMOS tube NM11, the gate of the PMOS tube PM14 is connected to the gate of the NMOS tube NM14, the drain of the PMOS tube PM12 and the drain of the NMOS tube NM12, the drain of the PMOS tube PM13 and the drain of the NMOS tube NM13 output the signal V_P1, and the drain of the PMOS tube PM14 and the drain of the NMOS tube NM14 output the signal V_N1.

[0015] Further, the PMOS tube PM9 and the NMOS tube NM9 constitute a first inverter, the PMOS tube PM10 and the NMOS tube NM10 constitute a second inverter, the PMOS tube PM11 and the NMOS tube NM11 constitute a third inverter, the PMOS tube PM12 and the NMOS tube NM12 constitute a fourth inverter, the PMOS tube PM13 and the NMOS tube NM13 constitute a fifth inverter, the PMOS tube PM14 and the NMOS tube NM14 constitute a sixth inverter, the first inverter and the second inverter have the same width-to-length ratio, the third inverter and the fourth inverter have the same width-to-length ratio, the fifth inverter and the sixth inverter have the same width-to-length ratio, the first inverter and the second inverter constitute a first inverter group, the third inverter and the fourth inverter constitute a second inverter group, the fifth inverter and the sixth inverter constitute a third inverter group, and the width-to-length ratios of the first inverter group, the second inverter group and the third inverter group increase in sequence.

[0016] Furthermore, the high-low level conversion circuit comprises a high-voltage PMOS tube DEPM3, a high-voltage PMOS tube DEPM4, a high-voltage NMOS tube DENM1, a high-voltage NMOS tube DENM2, an NMOS tube NM15, an NMOS tube NM16, an NMOS tube NM17, an NMOS tube NM18, an NMOS tube NM19, an NMOS tube NM20, a PMOS tube PM15, a PMOS tube PM16, a PMOS tube PM17, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2, a source electrode of the high-voltage PMOS tube DEPM3 and a source electrode of the high-voltage PMOS tube DEPM4 are connected to a power supply VS, and a high-voltage PMOS tube DEPM4 is connected to a power supply VS. The gate of the MOS tube DEPM3 is connected to the signal V_P1, the gate of the high-voltage PMOS tube DEPM4 is connected to the signal V_N1, the drain of the high-voltage PMOS tube DEPM3 is connected to the drain of the high-voltage NMOS tube DENM1, the drain of the high-voltage PMOS tube DEPM4 is connected to the drain of the high-voltage NMOS tube DENM2, the gate of the high-voltage NMOS tube DENM1 and the gate of the high-voltage NMOS tube DENM2 are connected to the power supply DVDD, the source of the high-voltage NMOS tube DENM1 and the drain of the NMOS tube NM15, the drain of the NMOS tube NM16 and the gate of the NMOS tube NM17 are connected to the node V1, and the high-voltage NMOS The source of transistor DENM2 is connected to the drain of PMOS transistor PM16, the drain of NMOS transistor NM18, the drain of NMOS transistor NM17 and the gate of NMOS transistor NM16 at node V2, the gate of NMOS transistor NM15 is connected to node B with one end of capacitor C2 and one end of resistor R5, the other end of capacitor C2 is connected to node V2, the gate of NMOS transistor NM18 is connected to node A with one end of capacitor C1 and one end of resistor R6, the other end of capacitor C1 is connected to node V1, the gate of PMOS transistor PM15 and the gate of NMOS transistor NM19, the source of PMOS transistor PM15, the source of PMOS transistor PM16 and the gate of PMOS transistor NM18 are connected to node B with one end of capacitor C2 and one end of resistor R5, the other end of capacitor C2 is connected to node V2, the gate of NMOS transistor NM18 is connected to node A with one end of capacitor C1 and one end of resistor R6, the other end of capacitor C1 is connected to node V1, the gate of PMOS transistor PM15 and the gate of NMOS transistor NM19, the source of PMOS transistor PM15, the source of PMOS transistor PM16 and the gate of PMOS transistor NM19 are connected to node V3, the gate of NMOS transistor NM18 is connected to node A with one end of capacitor C1 and one end of resistor R6, the other end of capacitor C1 is connected to node V3, the gate of PMOS transistor PM15 and the gate of NMOS transistor NM19, the source of PMOS transistor PM15, the source of PMOS transistor PM16 and the gate of PMOS transistor NM19 are connected to node V4, the gate of NMOS transistor NM18 is connected to node A with one end of capacitor C1 and one end of resistor R6, the gate of NMOS transistor NM18 is connected to node A with one end of capacitor C1 and one end of resistor R6, the gate of NMOS transistor NM18 is connected to node A with The source of PM17 is connected to the power supply DVDD, the drain of the PMOS tube PM15 and the drain of the NMOS tube NM19, the gate of the PMOS tube PM16, the gate of the PMOS tube PM17 and the gate of the NMOS tube NM20 are connected to the node C, the drain of the PMOS tube PM17 and the drain of the NMOS tube NM20 generate the output signal V_OUT, the other end of the resistor R5, the source of the NMOS tube NM15, the source of the NMOS tube NM16, the source of the NMOS tube NM17, the source of the NMOS tube NM18, the other end of the resistor R6, the source of the NMOS tube NM19 and the source of the NMOS tube NM20 are connected to the power supply DGND.

[0017] Compared with the prior art, the present invention has the following advantages and effects:

[0018] 1. The present invention can process input signals with large swing amplitudes and perform accurate low-delay sampling on input signals with large swing amplitudes. The swing amplitude of the input signal can be as low as -5V or as high as 5V higher than the power supply voltage.

[0019] 2. The new structure adopted by the present invention can complete the output signal flipping faster and reduce the time delay, which can be as low as 5 nanoseconds;

[0020] 3. The present invention can convert high-voltage signals to low-voltage domains with low latency without increasing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a fast comparator suitable for high voltage and large swing according to the present invention.

[0022] Figure 2 It is a circuit diagram of the low-delay sampling circuit of the present invention.

[0023] Figure 3 is a circuit diagram of the comparator core circuit of the present invention.

[0024] Figure 4 4 is a circuit diagram of a driving capability enhancement circuit of the present invention.

[0025] Figure 5 It is a circuit diagram of the high-low level conversion circuit of the present invention.

[0026] Figure 6 It is a time domain response diagram of the comparator core circuit of the present invention.

[0027] Figure 7 is the simulation result of the embodiment of the present invention Figure 1 .

[0028] Figure 8 is the simulation result of the embodiment of the present invention Figure 2 .

[0029] Fig. 9 is the simulation result of the embodiment of the present invention Figure 3 .

[0030] Fig.10 is the simulation result of the embodiment of the present invention Figure 4 .

[0031] Fig.11 is the simulation result of the embodiment of the present invention Figure 5 . DETAILED DESCRIPTION

[0032] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0033] like Figure 1 As shown, a fast comparator suitable for high voltage and large swing of the present invention comprises a low-latency sampling circuit, a comparator core circuit, a driving capability enhancement circuit and a high-low level conversion circuit, the input end of the low-latency sampling circuit inputs the sampled signal V_SH, the output end of the low-latency sampling circuit is connected to the first input end of the comparator core circuit, the second input end of the comparator core circuit inputs the reference voltage V_REF, the output end of the comparator core circuit is connected to the input end of the driving capability enhancement circuit, the output end of the driving capability enhancement circuit is connected to the input end of the high-low level conversion circuit, and the output end of the high-low level conversion circuit generates an output signal V-OUT.

[0034] Since the SH point voltage may fluctuate between -5V and the power supply voltage (e.g., 15V), the input of the comparator cannot directly receive such a large input range. The present invention uses a low-latency high-voltage sampling circuit to sample the SH voltage of concern to the user to the input of the comparator for comparison. The core circuit of the comparator adopts a static high-speed comparator structure with a pre-amplifier and a post-latcher. This structure utilizes the negative exponential time domain characteristics of the amplifier and the positive exponential time domain characteristics of the latch so that the output signal can be flipped with low latency without the need for an external clock signal to reset. The present invention designs a level shifter with an RC high-pass network that can convert high-voltage domain signals to low-voltage domains with low latency. Since the first three technical means all achieve low latency, the overall time delay is very low, only about 5 nanoseconds.

[0035] like Figure 2 As shown, the low-delay sampling circuit includes a high-voltage resistant PMOS tube DEPM1, a resistor R1, a Zener diode D1 and a PMOS tube PM2, the source of the PMOS tube PM2 is connected to the power supply VS, the gate of the PMOS tube PM2 is connected to the bias voltage V_bias, the drain of the PMOS tube PM2 is connected to the cathode of the Zener diode D1 and the source of the high-voltage resistant PMOS tube DEPM1 and outputs a sampling signal V_SH1, the drain of the high-voltage resistant PMOS tube DEPM1 is connected to the sampled signal V_SH, the gate of the high-voltage resistant PMOS tube DEPM1 is connected to the anode of the Zener diode D1 and one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VS-5.

[0036] Among them, the voltage of the power supply VS can be as high as 30V, and the power supply VS-5 is a power rail 5V lower than the voltage of the power supply VS.

[0037] The working principle of the low-latency sampling circuit is:

[0038] When the voltage of the sampled signal V_SH is lower than the power supply VS-5 plus the threshold voltage of the high-voltage PMOS tube DEPM1, the sampling signal V_SH1 will be pulled low. When the voltage of the sampling signal V_SH1 is lower than the power supply VS-5 plus the threshold voltage of the high-voltage PMOS tube DEPM1, the high-voltage PMOS tube DEPM1 is turned off, and the sampling signal V_SH1 cannot continue to decrease.

[0039] When the sampled signal V_SH is higher than the power supply VS, the sampling signal V_SH1 will follow the sampled signal V_SH. At this time, the sampling signal V_SH1 will discharge to the power supply VS through the parasitic diode of the PMOS tube PM2, ensuring that the highest bit of the sampling signal V_SH1 is VS+0.7V. At the same time, the Zener diode D1 is turned on, and the sampling signal V_SH1 discharges to the power supply VS-5 through the Zener diode D1, which will increase the gate voltage of the high-voltage PMOS tube DEPM1, ensuring that the gate-source voltage of the high-voltage PMOS tube DEPM1 is within a reasonable range to prevent breakdown.

[0040] When the sampled signal V_SH is between the power supply VS and the power supply VS-5, the high-voltage PMOS tube DEPM1 will be fully turned on and in the deep linear region. At this time, the high-voltage PMOS tube DEPM1 is only equivalent to a small resistor, and the bias voltage V_bias will be selected to a suitable value to ensure that the current on the PMOS tube PM2 is extremely small, so the voltage drop across the drain and source of the high-voltage PMOS tube DEPM1 is extremely small, which means that the sampling signal V_SH1 is almost completely equivalent to the sampled signal V_SH.

[0041] After the above analysis, it can be concluded that the upper and lower limits of the sampling signal V_SH1 are VS+0.7V, VS-5 plus the threshold voltage of the high-voltage PMOS tube DEPM1. Between the upper and lower limits, the sampling signal V_SH1 almost completely follows the sampled signal V_SH, and there is no risk of circuit damage.

[0042] like Figure 3As shown, the comparator core circuit includes NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, NMOS tube NM7, NMOS tube NM8, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, current source I1, resistor R3 and resistor R4, one end of the current source I1 is connected to the source of PMOS tube PM3, the source of PMOS tube PM4, one end of the resistor R3, one end of the resistor R4, and PMOS tube PM5. The source of the MOS tube PM5 is connected to the source of the PMOS tube PM6, the other end of the current source I1 is connected to the source of the PMOS tube PM7 and the source of the PMOS tube PM8, the gate of the PMOS tube PM7 is connected to the sampling signal V_SH1, the gate of the PMOS tube PM8 is connected to the reference voltage V_REF, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM3, the drain of the PMOS tube PM8 is connected to the drain of the NMOS tube NM2, the gate of the NMOS tube NM2 and the gate of the NMOS tube NM4 The gate of the PMOS tube PM3 is connected to the drain of the PMOS tube PM3, the drain of the NMOS tube NM3 and the gate of the NMOS tube NM5, the gate of the PMOS tube PM4 is connected to the drain of the PMOS tube PM4, the drain of the NMOS tube NM4 and the gate of the NMOS tube NM6, the source of the NMOS tube NM3 is connected to the source of the NMOS tube NM4 and one end of the current source I2, the other end of the resistor R3 is connected to the drain of the NMOS tube NM5 and the gate of the PMOS tube PM5, the other end of the resistor R4 is connected to the drain of the NMOS tube NM6 and the gate of the PMOS tube PM6 The source of the NMOS tube NM5 is connected to the source of the NMOS tube NM6 and one end of the current source I3, the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM7 and the gate of the NMOS tube NM8 and outputs a signal V_P, the drain of the PMOS tube PM6 is connected to the drain of the NMOS tube NM8 and the gate of the NMOS tube NM7 and outputs a signal V_N, the source of the NMOS tube NM1, the source of the NMOS tube NM2, the other end of the current source I2, the other end of the current source I3, the source of the NMOS tube NM7 and the source of the NMOS tube NM8 are connected to the power supply VS-5.

[0043] PMOS tube PM7, PMOS tube PM8, PMOS tube PM3, PMOS tube PM4, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, resistor R3 and resistor R4 form a three-stage operational amplifier, in which NMOS tube NM1, NMOS tube NM2, PMOS tube PM3 and PMOS tube PM4 are connected by diodes as loads, so that a sufficiently large bandwidth can be obtained to reduce time delay while ensuring gain. The reason why the first two stages of operational amplifiers use diode-connected MOS tubes as loads is that the DC voltage is more controllable. The last stage uses resistors as loads to ensure that the source of PMOS tube PM5 and PMOS tube PM6 can be completely turned off, otherwise it will cause leakage.

[0044] The PMOS transistor PM5, the PMOS transistor PM6, the NMOS transistor NM7 and the NMOS transistor NM8 form a latch, the PMOS transistor PM5 and the PMOS transistor PM6 serve as input pairs, and the NMOS transistor NM7 and the NMOS transistor NM8 form a negative impedance connection.

[0045] The principle of the comparator core circuit to achieve low time delay is:

[0046] For a single-stage operational amplifier, its time domain characteristics are:

[0047]

[0048] Where V O is the output of the operational amplifier, V I is the input of the operational amplifier, A V0 is the DC gain of the operational amplifier. The time constant τ1 is the product of the output resistance R and the output capacitance C. From the expression, it can be seen that when the input V I When it is a step signal, the output V O It will show negative exponential characteristics.

[0049] For a latch, its time domain characteristics are:

[0050]

[0051] Where, △V OUT is the output of the latch, △V IN is the input of the latch, and the time constant τ2 is 1 / gm of the latch load MOS tube multiplied by its C_gs. From the expression, it can be seen that the output expression of the latch is a positive exponential function, and its output voltage increases with the increase of the input voltage.

[0052] like Figure 6As shown, the above two expressions are put into the same figure to obtain the time domain response diagram of the operational amplifier and latch output. According to the circuit in the present invention, the output voltage of the front stage operational amplifier reaches V X It takes time t1, at which time the latch receives V X As input, it takes time t2 for the output to reach V OH Therefore, the entire comparator core circuit only takes time t1+t2 to complete the flipping action, saving flipping time, which is faster than a single operational amplifier or latch. In the present invention, although the front-stage operational amplifier has three stages, it does not affect its negative exponential characteristics, and the above inference still holds true.

[0053] like Figure 4 As shown, the driving capability enhancement circuit includes a PMOS tube PM9, a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM9, an NMOS tube NM10, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13 and an NMOS tube NM14, the source of the PMOS tube PM9, the source of the PMOS tube PM10, the source of the PMOS tube PM11, the source of the PMOS tube PM12, the source of the PMOS tube PM13 and the source of the PMOS tube PM14 are connected to a power supply VS, the gate of the PMOS tube PM9 and the gate of the NMOS tube NM9 are connected to a signal V_P, the gate of the PMOS tube PM10 and the gate of the NMOS tube NM10 are connected to a signal V_N, and the PMOS tube PM9 is connected to a signal V_P. The gate of the OS transistor PM11 is connected to the gate of the NMOS transistor NM11, the drain of the PMOS transistor PM9 and the drain of the NMOS transistor NM9, the gate of the PMOS transistor PM12 is connected to the gate of the NMOS transistor NM12, the drain of the PMOS transistor PM10 and the drain of the NMOS transistor NM10, the gate of the PMOS transistor PM13 is connected to the gate of the NMOS transistor NM13, the drain of the PMOS transistor PM11 and the drain of the NMOS transistor NM11, the gate of the PMOS transistor PM14 is connected to the gate of the NMOS transistor NM14, the drain of the PMOS transistor PM12 and the drain of the NMOS transistor NM12, the drain of the PMOS transistor PM13 and the drain of the NMOS transistor NM13 output the signal V_P1, and the drain of the PMOS transistor PM14 and the drain of the NMOS transistor NM14 output the signal V_N1.

[0054] The PMOS tube PM9 and the NMOS tube NM9 constitute a first inverter, the PMOS tube PM10 and the NMOS tube NM10 constitute a second inverter, the PMOS tube PM11 and the NMOS tube NM11 constitute a third inverter, the PMOS tube PM12 and the NMOS tube NM12 constitute a fourth inverter, the PMOS tube PM13 and the NMOS tube NM13 constitute a fifth inverter, the PMOS tube PM14 and the NMOS tube NM14 constitute a sixth inverter, the first inverter and the second inverter have the same width-to-length ratio, the third inverter and the fourth inverter have the same width-to-length ratio, the fifth inverter and the sixth inverter have the same width-to-length ratio, the first inverter and the second inverter constitute a first inverter group, the third inverter and the fourth inverter constitute a second inverter group, the fifth inverter and the sixth inverter constitute a third inverter group, and the width-to-length ratios of the first inverter group, the second inverter group and the third inverter group increase in sequence, that is, the further to the right the circuit goes, the stronger its driving capability is. The driving capability is enhanced here to drive the last stage of high-low level conversion circuit. Because the high voltage and low voltage are very different, a large driving capability is required to achieve the purpose of fast flipping.

[0055] like Figure 5As shown, the high-low level conversion circuit includes a high-voltage resistant PMOS tube DEPM3, a high-voltage resistant PMOS tube DEPM4, a high-voltage resistant NMOS tube DENM1, a high-voltage resistant NMOS tube DENM2, an NMOS tube NM15, an NMOS tube NM16, an NMOS tube NM17, an NMOS tube NM18, an NMOS tube NM19, an NMOS tube NM20, a PMOS tube PM15, a PMOS tube PM16, a PMOS tube PM17, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2, a source of the high-voltage resistant PMOS tube DEPM3 and a source of the high-voltage resistant PMOS tube DEPM4 are connected to a power supply VS, and the high-voltage resistant PMOS tube DEPM3 and the source of the high-voltage resistant PMOS tube DEPM4 are connected to a power supply VS, and the high-voltage resistant PMOS tube The gate of the high-voltage PMOS tube DEPM3 is connected to the signal V_P1, the gate of the high-voltage PMOS tube DEPM4 is connected to the signal V_N1, the drain of the high-voltage PMOS tube DEPM3 is connected to the drain of the high-voltage NMOS tube DENM1, the drain of the high-voltage PMOS tube DEPM4 is connected to the drain of the high-voltage NMOS tube DENM2, the gate of the high-voltage NMOS tube DENM1 and the gate of the high-voltage NMOS tube DENM2 are connected to the power supply DVDD, the source of the high-voltage NMOS tube DENM1 and the drain of the NMOS tube NM15, the drain of the NMOS tube NM16 and the gate of the NMOS tube NM17 are connected to the node V1, and the high-voltage NMOS tube D The source of ENM2 is connected to the drain of PMOS tube PM16, the drain of NMOS tube NM18, the drain of NMOS tube NM17 and the gate of NMOS tube NM16 at the node V2, the gate of NMOS tube NM15 is connected to the node B with one end of capacitor C2 and one end of resistor R5, the other end of capacitor C2 is connected to the node V2, the gate of NMOS tube NM18 is connected to the node A with one end of capacitor C1 and one end of resistor R6, the other end of capacitor C1 is connected to the node V1, the gate of PMOS tube PM15 and the gate of NMOS tube NM19, the source of PMOS tube PM15, the source of PMOS tube PM16 and the gate of PMOS tube P The source of M17 is connected to the power supply DVDD, the drain of the PMOS tube PM15 and the drain of the NMOS tube NM19, the gate of the PMOS tube PM16, the gate of the PMOS tube PM17 and the gate of the NMOS tube NM20 are connected to the node C, the drain of the PMOS tube PM17 and the drain of the NMOS tube NM20 generate an output signal V_OUT, the other end of the resistor R5, the source of the NMOS tube NM15, the source of the NMOS tube NM16, the source of the NMOS tube NM17, the source of the NMOS tube NM18, the other end of the resistor R6, the source of the NMOS tube NM19 and the source of the NMOS tube NM20 are connected to the power supply DGND.

[0056] As high-voltage PMOS tubes, DEPM3 and DEPM4 can withstand high voltage, and their drain voltage can be much lower than the gate voltage and source voltage, so they are used as input pairs. As high-voltage NMOS tubes, DENM1 and DENM2 can withstand high voltage, and their drain voltage can be much higher than the gate voltage and source voltage. They can resist high voltage in the circuit, ensure that the voltage of nodes V1 and V2 is lower than the power supply DVDD, and protect NMOS tubes NM16 and NMOS tubes NM17 from breakdown. NMOS tubes NM16 and NMOS tubes NM17 form a negative resistance structure, which can quickly flip and maintain between two states without consuming current.

[0057] Resistor R6 and capacitor C1 form a high-pass network, so that the voltage of node A can be coupled with the voltage of node V1. For example, if the voltage of node V1 rises rapidly, the voltage of node A will be coupled and rise, turning on NMOS tube NM18, and quickly pulling the voltage of node V2 to the power supply DGND. The same applies to resistor R5, capacitor C2 and NMOS tube NM15.

[0058] PMOS tube PM15, NMOS tube NM19, PMOS tube PM17 and NMOS tube NM20 form two inverters to provide sufficient driving capability for the output signal V_OUT. Since the highest voltage of node V2 is DVDD-V_TH, V_TH in the formula is the threshold voltage of the high-voltage NMOS tube DENM2. The voltage of node V2 is lower than DVDD, which will cause leakage in the inverter formed by PMOS tube PM15 and NMOS tube NM19, so PMOS tube PM16 is added. The inverter formed by PMOS tube PM15 and NMOS tube NM19 and PMOS tube PM16 form a positive feedback loop. When the voltage of node V2 is DVDD-V_TH, the voltage of node C is DGND, and PMOS tube PM16 is fully turned on, entering the deep linear region, and pulling up the voltage of node V2 to DVDD. When the voltage of node V2 is DGND, the voltage of node C is DVDD, which has no effect on the voltage of node V2.

[0059] During a flip process, each circuit will perform the following functions:

[0060] For example: the voltage of signal V_P1 rises, and the voltage of signal V_N1 drops (these two are differential outputs, one must rise and the other must drop). The drop of signal V_N1 turns on the high-voltage PMOS tube DEPM4, generating a large current to charge the voltage of node V2. The rise of signal V_P1 turns off the high-voltage PMOS tube DEPM3, and the rise of node V2 turns on the NMOS tube NM16, pulling down the voltage of node V1. However, due to the small width-to-length ratio of NMOS tubes NM16 and NMOS tubes NM17, the speed at which node V1 is pulled down is slow, and the signal flips not fast enough. At this time, the circuit of resistor R5, capacitor C2, and NMOS tube NM15 takes effect: resistor R5 and capacitor C2 form a high-pass network, the voltage of node B is pulled up by the rapid rise of node V1, NMOS tube NM15 is fully turned on, node V1 has a path to the ground, and the voltage can drop rapidly. The rapid drop of node V1 and the rapid rise of node V2 form a reinforced positive feedback to ensure the rapid flipping of the output signal. After the flipping is completed, since the voltages of nodes V1 and V2 no longer change, the voltages of nodes A and B are pulled down to DGND by R5 and R1, and NMOS tubes NM15 and NMOS tubes NM18 are turned off, and no additional current consumption is generated.

[0061] The present invention can process input signals with large swing amplitudes and perform accurate low-delay sampling on input signals with large swing amplitudes. The swing amplitude of the input signals can be as low as -5V or as high as 5V higher than the power supply voltage. The present invention adopts a new structure to complete output signal flipping faster and reduce time delay. The delay can be as low as 5 nanoseconds. The present invention can convert high-voltage signals to low-voltage domains with low delay without increasing power consumption.

[0062] like Figure 7 As shown, the power supply voltage of the simulation is set to 15V, the input signal V_SHx ranges from -5V to 20V, and the voltage range of the sampled signal net3 is from 11V to 16V, which is within the processable range of the power supply voltage.

[0063] like Figure 8 As shown, Figure 7 The two signals overlap, and it can be seen that the two signals overlap almost completely, proving the low time delay of the sampling circuit.

[0064] like Fig. 9 As shown, Fig. 9 The upper part is the input signal V_SHx and the reference voltage V_REF_HV. The two signals are amplified to clearly show the time delay. The time point when the two are equal is defined as point A. The lower part is the high-voltage output signal, and the middle voltage is taken as point B. The time difference from point A to point B is the time delay of the core circuit of the present invention, which is as low as 3.56 nanoseconds. At the same time, Fig. 9As can be seen in the figure, the voltage range of the high-voltage output signal SAMPLE1 is 10V to 15V, which is high voltage.

[0065] like Fig.10 As shown, in Fig. 9 Based on SAMPLE1, a column V_OUT_H is added. V_OUT_H is the final output of DVDD domain. It can be seen that V_OUT_H is delayed by only 0.78 nanoseconds based on SAMPLE1. It has completed the low-delay transmission of signals from high voltage to low voltage very well. Fig.10 The overall time delay is also shown, which is about 4.4 nanoseconds.

[0066] Since the waveform diagram is not convenient to intuitively show the time delay when V_SHx rises and falls at the same time, the present invention writes the time delay through such an expression: delay_H=t2-t1. t2 is the moment when the output voltage VOUT_H reaches DVDD / 2, and t1 is the moment when the input voltage V_SHx is equal to the reference voltage V_REF_HV.

[0067] like Fig.11 As shown, the time delay when V_SHx rises and falls is repeated many times to prove the reliability of the present invention. It can be seen that as V_SHx rises and falls, the time delay is slightly different, but generally less than 5 nanoseconds.

[0068] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fast comparator suitable for high voltage and large swing, characterized in that: It comprises a low-latency sampling circuit, a comparator core circuit, a driving capability enhancement circuit and a high-low level conversion circuit, wherein the input end of the low-latency sampling circuit inputs a sampled signal V_SH, the output end of the low-latency sampling circuit is connected to the first input end of the comparator core circuit, the second input end of the comparator core circuit inputs a reference voltage V_REF, the output end of the comparator core circuit is connected to the input end of the driving capability enhancement circuit, the output end of the driving capability enhancement circuit is connected to the input end of the high-low level conversion circuit, and the output end of the high-low level conversion circuit generates an output signal V-OUT; The low-delay sampling circuit includes a high-voltage resistant PMOS tube DEPM1, a resistor R1, a Zener diode D1 and a PMOS tube PM2, the source of the PMOS tube PM2 is connected to a power supply VS, the gate of the PMOS tube PM2 is connected to a bias voltage V_bias, the drain of the PMOS tube PM2 is connected to the cathode of the Zener diode D1 and the source of the high-voltage resistant PMOS tube DEPM1 and outputs a sampling signal V_SH1, the drain of the high-voltage resistant PMOS tube DEPM1 is connected to the sampled signal V_SH, the gate of the high-voltage resistant PMOS tube DEPM1 is connected to the anode of the Zener diode D1 and one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VS-5.

2. A fast comparator suitable for high voltage and large swing according to claim 1, characterized in that: The power supply VS-5 is a power rail that is 5V lower than the voltage of the power supply VS.

3. The fast comparator suitable for high voltage and large swing according to claim 1, characterized in that: The comparator core circuit comprises NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, NMOS tube NM7, NMOS tube NM8, PMOS tube PM3, PMOS tube PM4, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, PMOS tube PM8, current source I1, resistor R3 and resistor R4, one end of current source I1 is connected to the source of PMOS tube PM3, The source of the PMOS tube PM4, one end of the resistor R3, one end of the resistor R4, the source of the PMOS tube PM5 and the source of the PMOS tube PM6 are connected, the other end of the current source I1 is connected to the source of the PMOS tube PM7 and the source of the PMOS tube PM8, the gate of the PMOS tube PM7 is connected to the sampling signal V_SH1, the gate of the PMOS tube PM8 is connected to the reference voltage V_REF, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the NM The gate of the OS transistor NM3 is connected, the drain of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM2, the gate of the NMOS transistor NM2 and the gate of the NMOS transistor NM4, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM5, the gate of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM4, the drain of the NMOS transistor NM4 and the gate of the NMOS transistor NM6, the source of the NMOS transistor NM3 is connected to The source of the NMOS tube NM4 is connected to one end of the current source I2, the other end of the resistor R3 is connected to the drain of the NMOS tube NM5 and the gate of the PMOS tube PM5, the other end of the resistor R4 is connected to the drain of the NMOS tube NM6 and the gate of the PMOS tube PM6, the source of the NMOS tube NM5 is connected to the source of the NMOS tube NM6 and one end of the current source I3, the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM7 and the gate of the NMOS tube NM8 and outputs a signal V_P, the drain of the PMOS tube PM6 is connected to the drain of the NMOS tube NM8 and the gate of the NMOS tube NM7 and outputs a signal V_N, the source of the NMOS tube NM1, the source of the NMOS tube NM2, the other end of the current source I2, the other end of the current source I3, the source of the NMOS tube NM7 and the source of the NMOS tube NM8 are connected to the power supply VS-5.

4. A fast comparator suitable for high voltage and large swing according to claim 3, characterized in that: The PMOS tube PM7, PMOS tube PM8, PMOS tube PM3, PMOS tube PM4, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, resistor R3 and resistor R4 constitute a three-stage operational amplifier, and the PMOS tube PM5, PMOS tube PM6, NMOS tube NM7 and NMOS tube NM8 constitute a latch.

5. The fast comparator suitable for high voltage and large swing according to claim 1, characterized in that: The driving capability enhancement circuit comprises a PMOS tube PM9, a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, an NMOS tube NM9, an NMOS tube NM10, an NMOS tube NM11, an NMOS tube NM12, an NMOS tube NM13 and an NMOS tube NM14, the source of the PMOS tube PM9, the source of the PMOS tube PM10, the source of the PMOS tube PM11, the source of the PMOS tube PM12, the source of the PMOS tube PM13 and the source of the PMOS tube PM14 are connected to a power supply VS, the gate of the PMOS tube PM9 and the gate of the NMOS tube NM9 are connected to a signal V_P, the gate of the PMOS tube PM10 and the gate of the NMOS tube NM10 are connected to a signal V_N, and the PMOS tube PM9 is connected to a signal V_P. The gate of the OS transistor PM11 is connected to the gate of the NMOS transistor NM11, the drain of the PMOS transistor PM9 and the drain of the NMOS transistor NM9, the gate of the PMOS transistor PM12 is connected to the gate of the NMOS transistor NM12, the drain of the PMOS transistor PM10 and the drain of the NMOS transistor NM10, the gate of the PMOS transistor PM13 is connected to the gate of the NMOS transistor NM13, the drain of the PMOS transistor PM11 and the drain of the NMOS transistor NM11, the gate of the PMOS transistor PM14 is connected to the gate of the NMOS transistor NM14, the drain of the PMOS transistor PM12 and the drain of the NMOS transistor NM12, the drain of the PMOS transistor PM13 and the drain of the NMOS transistor NM13 output the signal V_P1, and the drain of the PMOS transistor PM14 and the drain of the NMOS transistor NM14 output the signal V_N1.

6. A fast comparator suitable for high voltage and large swing according to claim 5, characterized in that: The PMOS tube PM9 and the NMOS tube NM9 constitute a first inverter, the PMOS tube PM10 and the NMOS tube NM10 constitute a second inverter, the PMOS tube PM11 and the NMOS tube NM11 constitute a third inverter, the PMOS tube PM12 and the NMOS tube NM12 constitute a fourth inverter, the PMOS tube PM13 and the NMOS tube NM13 constitute a fifth inverter, the PMOS tube PM14 and the NMOS tube NM14 constitute a sixth inverter, the first inverter and the second inverter have the same width-to-length ratio, the third inverter and the fourth inverter have the same width-to-length ratio, the fifth inverter and the sixth inverter have the same width-to-length ratio, the first inverter and the second inverter constitute a first inverter group, the third inverter and the fourth inverter constitute a second inverter group, the fifth inverter and the sixth inverter constitute a third inverter group, and the width-to-length ratios of the first inverter group, the second inverter group and the third inverter group increase in sequence.

7. The fast comparator suitable for high voltage and large swing according to claim 1, characterized in that: The high-low level conversion circuit comprises a high-voltage resistant PMOS tube DEPM3, a high-voltage resistant PMOS tube DEPM4, a high-voltage resistant NMOS tube DENM1, a high-voltage resistant NMOS tube DENM2, an NMOS tube NM15, an NMOS tube NM16, an NMOS tube NM17, an NMOS tube NM18, an NMOS tube NM19, an NMOS tube NM20, a PMOS tube PM15, a PMOS tube PM16, a PMOS tube PM17, a resistor R5, a resistor R6, a capacitor C1 and a capacitor C2, a source electrode of the high-voltage resistant PMOS tube DEPM3 and a source electrode of the high-voltage resistant PMOS tube DEPM4 are connected to a power supply VS, and the high-voltage resistant PMOS tube DEPM4 is connected to a power supply VS. The gate of DEPM3 is connected to the signal V_P1, the gate of the high-voltage PMOS tube DEPM4 is connected to the signal V_N1, the drain of the high-voltage PMOS tube DEPM3 is connected to the drain of the high-voltage NMOS tube DENM1, the drain of the high-voltage PMOS tube DEPM4 is connected to the drain of the high-voltage NMOS tube DENM2, the gate of the high-voltage NMOS tube DENM1 and the gate of the high-voltage NMOS tube DENM2 are connected to the power supply DVDD, the source of the high-voltage NMOS tube DENM1 and the drain of the NMOS tube NM15, the drain of the NMOS tube NM16 and the gate of the NMOS tube NM17 are connected to the node V1, and the high-voltage NMOS tube D The source of ENM2 is connected to the drain of PMOS tube PM16, the drain of NMOS tube NM18, the drain of NMOS tube NM17 and the gate of NMOS tube NM16 at the node V2, the gate of NMOS tube NM15 is connected to the node B with one end of capacitor C2 and one end of resistor R5, the other end of capacitor C2 is connected to the node V2, the gate of NMOS tube NM18 is connected to the node A with one end of capacitor C1 and one end of resistor R6, the other end of capacitor C1 is connected to the node V1, the gate of PMOS tube PM15 and the gate of NMOS tube NM19, the source of PMOS tube PM15, the source of PMOS tube PM16 and the gate of PMOS tube P The source of M17 is connected to the power supply DVDD, the drain of the PMOS tube PM15 and the drain of the NMOS tube NM19, the gate of the PMOS tube PM16, the gate of the PMOS tube PM17 and the gate of the NMOS tube NM20 are connected to the node C, the drain of the PMOS tube PM17 and the drain of the NMOS tube NM20 generate an output signal V_OUT, the other end of the resistor R5, the source of the NMOS tube NM15, the source of the NMOS tube NM16, the source of the NMOS tube NM17, the source of the NMOS tube NM18, the other end of the resistor R6, the source of the NMOS tube NM19 and the source of the NMOS tube NM20 are connected to the power supply DGND.

Images