Alignment pattern, semiconductor device, electronic device and exposure compensation method

Abstract

The present application relates to an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method. The alignment pattern is located in a cutting path; the alignment pattern includes a first-layer alignment pattern and at least one measurement alignment pattern; the first-layer alignment pattern is located on the first-layer semiconductor film layer, including a central symmetric pattern with a common center point and axis of symmetry, and a rhombus located within the central symmetric pattern; at least one measurement alignment pattern is located on different semiconductor film layers stacked in sequence in a direction away from the first-layer semiconductor film layer; at least one measurement alignment pattern is a rhombus; the offset vector of at least one measurement alignment pattern compared to the first-layer alignment pattern is used to indicate the overlay offset of the semiconductor film layer. The present application can perform real-time measurement and timely compensation of the overlay offset in the chip manufacturing stage, thereby improving the overlay accuracy of the chip and thus improving the yield of the lithography product.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method. Background Art

[0002] In semiconductor technology, photolithography machines need to use alignment marks to align and expose each layer of the chip structure to ensure the accuracy of the photolithography patterns in each layer of the chip structure.

[0003] However, if the structure of the current layer and the structure of the previous layer in the alignment exposure process are formed based on different machines (that is, there is a machine error), or the offset of the lithography pattern does not exist in the relationship between the structure of the current layer and the structure of the previous layer, for example, the offset may exist between two non-adjacent layers or between different machines, then there is a problem of inaccurate measurement of the alignment error (Overlay, OVL for short), which makes it difficult to accurately compensate for the overlay offset of the lithography pattern, thereby reducing the overlay accuracy of the chip and causing adverse effects on the yield of the lithography product. Summary of the invention

[0004] Based on this, the embodiments of the present application provide an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method to perform real-time measurement and timely compensation of the overlay offset during the chip manufacturing stage, thereby improving the overlay accuracy of the chip and thus improving the yield of the lithography product.

[0005] In order to achieve the above-mentioned objectives, in the first aspect, some embodiments of the present application provide an alignment figure; the alignment figure is located in the cutting path; the alignment figure includes a first-layer alignment figure and at least one measurement alignment figure; the first-layer alignment figure is located on the first-layer semiconductor film layer, including a central symmetrical figure with a common center point and axis of symmetry, and a rhombus located within the central symmetrical figure; at least one measurement alignment figure is located on different semiconductor film layers stacked in sequence in a direction away from the first-layer semiconductor film layer; at least one measurement alignment figure is a rhombus; the offset vector of at least one measurement alignment figure compared to the first-layer alignment figure is used to indicate the overlay offset of the semiconductor film layer.

[0006] The alignment pattern in the above-mentioned embodiment is achieved by setting a first-layer alignment pattern on the first-layer semiconductor film layer, setting a measurement alignment pattern on different semiconductor film layers stacked in sequence in a direction away from the first-layer semiconductor film layer, and obtaining the overlay offset of each semiconductor film layer according to the central symmetric pattern in the first-layer alignment pattern and the offset vector between the rhombuses in each measurement alignment pattern; in this way, based on the alignment pattern in the embodiment of the present application, real-time measurement of the overlay offset between different semiconductor film layers and the first-layer semiconductor film layer can be achieved, so as to monitor the abnormality in real time and compensate for it in time during the manufacturing stage of each semiconductor film layer according to the overlay offset, thereby ensuring the exposure accuracy of the lithography product from the chip manufacturing stage, effectively eliminating the adverse effects of the machine error on the measurement of the alignment error (Overlay, referred to as OVL), and avoiding the chip scrapping incident caused by the slicing confirmation when the electrical abnormality occurs after the chip production is completed, while saving costs, realizing real-time measurement and timely compensation of the overlay offset, so as to improve the overlay accuracy of the chip, thereby effectively improving the yield of the lithography product.

[0007] In some embodiments, the central symmetrical figure is an ellipse, one symmetry axis of the rhombus is located on the short axis of the ellipse, and the other symmetry axis of the rhombus is located on the long axis of the ellipse.

[0008] In some embodiments, two opposing vertices of the diamond are located on the ellipse.

[0009] In some embodiments, the offset vector includes measuring the offset of the alignment figure along the extension direction of the short axis compared to the first-layer alignment figure, the offset along the extension direction of the long axis, and measuring the rotation angle of a symmetry axis of the alignment figure compared to the extension direction of the short axis of the first-layer alignment figure, or measuring the rotation angle of another symmetry axis of the alignment figure compared to the extension direction of the long axis of the first-layer alignment figure. By combining the offset in the two directions of the long axis and the short axis and the rotation angle to measure the overlay offset of the semiconductor film layer, it is beneficial to achieve accurate measurement and compensation of the overlay offset, thereby effectively improving the overlay accuracy of the chip.

[0010] In some embodiments, at least one measurement alignment pattern is disposed on each semiconductor film layer stacked in sequence in a direction away from the first semiconductor film layer.

[0011] In some embodiments, the cutting path includes a plurality of first-layer alignment patterns that are arranged at intervals and distributed around the chip area. By setting a plurality of first-layer alignment patterns evenly distributed in the cutting path and aligning the plurality of first-layer alignment patterns with corresponding measurement alignment patterns, accurate measurement and compensation of the overlay offsets of different semiconductor film layers can be achieved, thereby effectively improving the overlay accuracy of the chip.

[0012] In a second aspect, the present application also provides a semiconductor device according to some embodiments; the semiconductor device includes an alignment pattern as described in any one of the first aspect of the embodiments of the present application.

[0013] In a third aspect, the present application also provides an electronic device according to some embodiments; the electronic device includes an alignment pattern as described in any one of the first aspect of the embodiments of the present application; or, the electronic device includes a semiconductor device as described in any one of the second aspect of the embodiments of the present application.

[0014] In a fourth aspect, the present application also provides an exposure compensation method according to some embodiments, and the exposure compensation method is implemented based on the alignment figure as described in any one of the first aspects of the embodiments of the present application; the exposure compensation method includes: obtaining the offset vector of the measurement alignment figure of the current layer to be measured relative to the first layer alignment figure directly below it; adjusting the exposure center based on the offset vector and then exposing; by adjusting and compensating based on the offset vector between each layer of semiconductor film layer and the first layer of semiconductor film layer, real-time measurement and compensation correction of the overlay offset between different semiconductor film layers and the first layer of semiconductor film layer can be achieved, thereby improving the overlay accuracy of the chip.

[0015] In some embodiments, adjusting the exposure center based on the offset vector and then exposing includes: obtaining the initial coordinates of the current exposure center; using the coordinates after the initial coordinates are reversely adjusted by the offset vector as the coordinates of the adjusted exposure center; exposing again after the exposure center is adjusted to the coordinates of the adjusted exposure center; and determining the adjustment amount of the exposure center based on the coordinate value and the offset vector to achieve precise adjustment of the lithography exposure center, thereby effectively improving the overlay accuracy of the chip.

[0016] In summary, the present application provides an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method, which can realize real-time measurement of the overlay offset between different semiconductor film layers and the first semiconductor film layer, so as to monitor the abnormality in real time and compensate in time during the manufacturing stage of each semiconductor film layer according to the overlay offset, and ensure the exposure accuracy of the lithography product from the chip manufacturing stage. The unexpected effect is that the adverse effects of machine errors on the measurement of alignment errors (Overlay, referred to as OVL) are effectively eliminated, and the chip scrapping caused by slicing confirmation when electrical abnormalities occur after the chip production is completed is avoided. While saving costs, real-time measurement and timely compensation of the overlay offset are realized to improve the overlay accuracy of the chip, thereby effectively improving the yield of the lithography product.

[0017] The unexpected technical effects that can be produced by the embodiments of the present application include:

[0018] In the embodiment of the present application, by setting a first-layer alignment pattern on the first-layer semiconductor film layer, setting a measurement alignment pattern on different semiconductor film layers stacked in sequence in a direction away from the first-layer semiconductor film layer, and obtaining the overlay offset of each semiconductor film layer according to the offset vector between the central symmetric pattern in the first-layer alignment pattern and the rhombus in each measurement alignment pattern. In this way, based on the alignment pattern in the embodiment of the present application, the real-time measurement of the overlay offset between different semiconductor film layers and the first-layer semiconductor film layer can be realized, so as to monitor the abnormality in real time and compensate in time during the manufacturing stage of each semiconductor film layer according to the overlay offset, ensure the exposure accuracy of the lithography product from the chip manufacturing stage, effectively eliminate the adverse effects of the machine error on the measurement of the alignment error (Overlay, referred to as OVL), and avoid the chip scrapping caused by the slicing confirmation when the electrical abnormality occurs after the chip production is completed, while saving costs, realize the real-time measurement and timely compensation of the overlay offset, so as to improve the overlay accuracy of the chip, thereby effectively improving the yield of the lithography product.

[0019] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the structure of a first-layer alignment pattern and a measurement alignment pattern provided in some embodiments;

[0022] Figure 2 A schematic diagram of the structure of another first-layer alignment pattern provided in some embodiments;

[0023] Figure 3 A machine development pattern for a different semiconductor film layer provided in some embodiments;

[0024] Figure 4 Schematic diagrams of the structures of three semiconductor film layers provided in some embodiments;

[0025] Figure 5 A schematic flow chart of an exposure compensation method provided in some embodiments;

[0026] Figure 6A flowchart of step S200 provided in some embodiments.

[0027] Description of reference numerals:

[0028] A-first layer alignment pattern, B-measurement alignment pattern, 1-central symmetric pattern, 2-diamond, a1-first symmetry axis, a2-second symmetry axis. DETAILED DESCRIPTION

[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0032] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0034] In semiconductor technology, photolithography machines need to use alignment marks to align and expose each layer of the chip to ensure the accuracy of the photolithography patterns in each layer of the chip. However, if the current layer structure and the previous layer structure in the alignment exposure process are formed based on different machines (that is, there is a machine error), or the overlay offset of the photolithography pattern does not exist in the relationship between the current layer structure and the previous layer structure, for example, the offset may exist between two non-adjacent layers or between different machines, then there is a problem of inaccurate measurement of the alignment error (Overlay, referred to as OVL). In addition, the relevant technology cannot monitor and correct the overlay offset in real time during the chip manufacturing process. Often, when electrical abnormalities occur after the entire chip manufacturing is completed, the chip is sliced ​​to confirm the abnormal semiconductor film layer, which will cause the chip to be scrapped and increase costs.

[0035] Based on the above problems, the embodiments of the present application provide an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method to perform real-time measurement and timely compensation of the overlay offset during the chip manufacturing stage, thereby improving the overlay accuracy of the chip and thus improving the yield of the lithography product.

[0036] In a first aspect, some embodiments of the present application provide an alignment pattern. In some embodiments, the alignment pattern is located within the cutting path; see Figure 1 The alignment pattern includes a first-layer alignment pattern A and at least one measurement alignment pattern B; the first-layer alignment pattern A is located on the first-layer semiconductor film layer, including a central symmetric pattern 1 with a common center point and a symmetry axis, and a rhombus 2 located within the central symmetric pattern 1, such as Figure 1 As shown in (a) of FIG. 1 ; at least one measurement alignment pattern B is located on different semiconductor film layers stacked in sequence in a direction away from the first semiconductor film layer; at least one measurement alignment pattern B is a diamond 2, such as Figure 1 As shown in Figure (b); the offset vector of at least one measured alignment figure B compared to the first-layer alignment figure A is used to indicate the overlay offset of the semiconductor film layer.

[0037] For example, the alignment pattern in the embodiment of the present application can be defined based on a mask and formed by a photolithography process.

[0038] For example, please continue to see Figure 1 In Figure (a), the orthographic projection of the diamond 2 in the first-layer alignment figure A on the first-layer semiconductor film layer is located inside the central symmetric figure 1.

[0039] It needs to be explained that the at least one measurement alignment figure B is located on different semiconductor film layers stacked in sequence along a direction away from the first semiconductor film layer, wherein, except for the first semiconductor film layer, each other semiconductor film layer may have at least one measurement alignment figure B, or at least one measurement alignment figure B may be set on the target semiconductor film layer, and the present application does not impose any restrictions on this.

[0040] It can be understood that each measurement alignment figure B has a corresponding first-layer alignment figure A. Here, for example, each measurement alignment figure B can be located directly above its corresponding first-layer alignment figure A; and the center point of each measurement alignment figure B coincides with the center point of its corresponding first-layer alignment figure A in the direction perpendicular to the semiconductor film layer.

[0041] It should be noted that the diamond 2 in the first-layer alignment pattern A and the diamond 2 in the measurement alignment pattern B have the same or similar shapes.

[0042] It is worth mentioning that, in some embodiments, the method for obtaining the offset vector in the embodiments of the present application can adopt the following method 1: obtaining image information of each semiconductor film layer based on a scanning device, and feeding the image information back to the control system to determine the offset vector.

[0043] By way of example, the scanning device includes, but is not limited to, a critical dimension scanning electron microscope (Critical Dimension Scanning Electron Microscopy, CD-SEM for short) and the like.

[0044] By way of example, the control system includes but is not limited to an advanced process control (APC) system and the like.

[0045] In some embodiments, the method for obtaining the offset vector in the embodiments of the present application may also adopt the following method 2: obtaining the image information of each semiconductor film layer through a high-definition camera, and obtaining the offset vector by performing image processing through an image recognition system.

[0046] It should be supplemented that the offset vector in the embodiment of the present application can also be determined based on both method one and method two, and the present application does not impose any restrictions on this.

[0047] It should be noted that the above method 1 and / or method 2 can monitor the offset vector of each semiconductor film layer in real time during the formation process of each semiconductor film layer, which is beneficial to the real-time measurement and timely compensation of the overlay offset during the chip manufacturing stage.

[0048] In some embodiments, see Figure 1 , the central symmetrical figure 1 is an ellipse, one symmetry axis of the rhombus 2 is located on the short axis of the ellipse, and the other symmetry axis of the rhombus 2 is located on the long axis of the ellipse.

[0049] For example, the central symmetric figure 1 is an ellipse, the first symmetry axis a1 of the rhombus 2 is located on the short axis of the ellipse, and the second symmetry axis a2 of the rhombus 2 is located on the long axis of the ellipse.

[0050] It can be understood that the central symmetrical figure 1 can also be other central symmetrical figures 1 besides an ellipse, and the present application does not impose any limitation on this.

[0051] In some embodiments, two opposite vertices of the rhombus 2 are located on the ellipse.

[0052] For example, two opposite vertices (eg, point C and point D) of the rhombus 2 that are passed through by the first symmetry axis a1 along the minor axis extension direction (eg, the Y direction) are located on the ellipse.

[0053] In some embodiments, the offset vector includes measuring the offset of the alignment figure B compared to the first-layer alignment figure A along the extension direction of the short axis (for example, the Y direction), the offset along the extension direction of the long axis (for example, the X direction), and measuring a symmetry axis of the alignment figure B (for example, the first symmetry axis a1) compared to the extension direction of the short axis of the first-layer alignment figure A, or measuring the rotation angle of another symmetry axis of the alignment figure B (for example, the second symmetry axis a2) compared to the extension direction of the long axis of the first-layer alignment figure A.

[0054] Please refer to Figure 1 In the embodiment of the present application, the distance between the two relative vertices (for example, point C and point D) of the rhombus 2 in the first-layer alignment figure A passed by the first symmetry axis a1 and the ellipse in the direction extending along the minor axis (for example, the Y direction) is taken as the first reference value; the distance between the two relative vertices (for example, point E and point F) of the rhombus 2 in the first-layer alignment figure A passed by the second symmetry axis a2 and the ellipse in the direction extending along the major axis (for example, the X direction) is taken as the second reference value.

[0055] For example, the first reference value may be 0, for example.

[0056] It can be understood that each measurement alignment figure B is located directly above its corresponding first-layer alignment figure A.

[0057] Thus, it is necessary to explain that the offset along the minor axis extension direction (e.g., Y direction) refers to: measuring the offset of the distance between the orthographic projection of two opposite vertices (e.g., point C' and point D') of the rhombus 2 in the alignment figure B that are passed through by the first symmetry axis a1 on the first semiconductor film layer and the ellipse in the minor axis extension direction (e.g., Y direction) compared to the first reference value; the offset along the major axis extension direction (e.g., X direction) refers to: measuring the distance between the orthographic projection of the rhombus 2 in the alignment figure B that is passed through by the second symmetry axis a2 The offset of the distance between the orthographic projections of two opposite vertices (for example, point E' and point F') on the first semiconductor film layer and the ellipse in the direction along the major axis extension direction (for example, the X direction) compared to the second reference value; the rotation angle compared to the minor axis extension direction or the major axis extension direction refers to: measuring the rotation angle of the first symmetry axis a1 of the rhombus 2 in the alignment figure B compared to the first symmetry axis a1 in the first-layer alignment figure A, or measuring the rotation angle of the second symmetry axis a2 of the rhombus 2 in the alignment figure B compared to the second symmetry axis a2 in the first-layer alignment figure A.

[0058] It should be noted that the above embodiments and Figure 1 Although the central symmetrical figure 1 is elliptical in shape for example, it can be understood that the central symmetrical figure 1 in the embodiment of the present application can also be other central symmetrical figures 1 besides elliptical, and the present application does not impose any limitation on this.

[0059] For example, the central symmetrical figure 1 may also be a regular polygon with a side length greater than or equal to 4, such as a circle, a quadrilateral, a regular hexagon, a regular octagon, etc.

[0060] For some examples, see Figure 2 , taking the central symmetrical figure 1 as a regular hexagon as an example; accordingly, the regular hexagon and the rhombus 2 share a first symmetry axis a1 in a first direction (for example, the Y direction), and share a second symmetry axis a2 in a second direction (for example, the X direction); at least two opposite vertices of the rhombus 2 are located on the regular hexagon; the offset of the offset vector along the first symmetry axis a1, the offset along the second symmetry axis a2, and the rotation angle compared to the first symmetry axis a1 or the second symmetry axis a2.

[0061] In some embodiments, at least one measurement alignment pattern B is disposed on each semiconductor film layer stacked sequentially in a direction away from the first semiconductor film layer.

[0062] For example, the number of stacked semiconductor film layers may be 3, 4, 8, 10, 16, 32 or 64, etc.

[0063] In some examples, each measurement alignment figure B on each semiconductor film layer stacked in sequence in a direction away from the first semiconductor film layer may correspond to the same first alignment figure A, and each measurement alignment figure B is located directly above the first alignment figure A.

[0064] For example, see Figure 3 , taking the stacking number of semiconductor film layers as 8 as an example; the first-layer alignment pattern A can correspond to 7 measurement alignment patterns B located on 7 semiconductor film layers respectively (for example Figure 3 ①~⑦ in the figure); It should be noted that, in the embodiment of the present application, the machine expansion pattern (path) is obtained by a scanning device and / or an image recognition system as shown in FIG. Figure 3 As shown in (b) of FIG. 1 , the embodiment of the present application can obtain the difference between the machine development pattern and the preset lithography pattern by analyzing and comparing the offset vectors of different semiconductor film layers in the machine development pattern and comparing the machine development pattern with the preset lithography pattern, which is helpful to avoid machine errors and improve the chip overlay accuracy, thereby effectively improving the lithography product yield.

[0065] In some embodiments, the scribe line includes a plurality of first-layer alignment patterns A that are arranged at intervals and distributed around the chip area.

[0066] For example, a plurality of first-layer alignment patterns A may be arranged at equal intervals within the cutting lane.

[0067] It should be noted that each measurement alignment figure B has a corresponding first-layer alignment figure A; wherein, one first-layer alignment figure A can correspond to one measurement alignment figure B, or one first-layer alignment figure A can also correspond to multiple measurement alignment figures B located on different semiconductor film layers, and the present application does not impose any restrictions on this.

[0068] From the above, to verify the effect of the alignment pattern provided in the embodiment of the present application on improving the chip overlay accuracy, please refer to Figure 4 Taking the stacking number of semiconductor film layers as 3 as an example, for conventional semiconductor film layers (such as Figure 4 (b) in the figure) and the semiconductor film layer formed based on the alignment pattern provided in the embodiment of the present application (as shown in Figure 4 The alignment error (Overlay, abbreviated as OVL) is verified by (as shown in Figure (c)).

[0069] See also Figure 4 In Figure (a), in an ideal semiconductor film layer, the alignment error is OVL 0 =GH=0; see Figure 4 In the conventional semiconductor film layer, the alignment error OVL 1 = (G1-g1)-(H1-h1); see Figure 4 In Figure (c), in the semiconductor film layer formed based on the alignment pattern provided in the embodiment of the present application, the alignment error OVL 2 = (G2-g2)-(H2-h2); where OVL 2 <OVL 1 Therefore, the alignment pattern provided in the embodiment of the present application can effectively reduce the alignment error (Overlay, referred to as OVL) of the semiconductor film layer, so as to improve the overlay accuracy of the chip.

[0070] In the second aspect, the present application also provides a semiconductor device according to some embodiments; the semiconductor device includes an alignment pattern as described in any one of the first aspects of the embodiments of the present application. The semiconductor device also has the technical advantages of the aforementioned alignment pattern. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0071] In a third aspect, the present application also provides an electronic device according to some embodiments; the electronic device includes an alignment pattern as described in any one of the first aspect of the embodiments of the present application; or, the electronic device includes a semiconductor device as described in any one of the second aspect of the embodiments of the present application. The electronic device also has the technical advantages of the aforementioned alignment pattern. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0072] In a fourth aspect, the present application also provides an exposure compensation method according to some embodiments, and the exposure compensation method is implemented based on the alignment pattern as described in any one of the first aspects of the embodiments of the present application. The exposure compensation method also has the technical advantages of the aforementioned alignment pattern. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0073] In some embodiments, see Figure 5 The exposure compensation method includes the following steps S100~S200.

[0074] S100, obtaining an offset vector of a measurement alignment pattern of a current layer to be measured relative to an alignment pattern of a first layer directly below the measurement alignment pattern.

[0075] For example, the offset vector may be obtained through a scanning electron microscope (Critical Dimension Scanning Electron Microscopy, referred to as CD-SEM) and an advanced process control (APC) system; or the offset vector may also be obtained through a high-definition camera and an image recognition system.

[0076] S200, adjusting the exposure center based on the offset vector and then exposing.

[0077] Here, the offset vector includes an offset along the minor axis extension direction (eg, Y direction), an offset along the major axis extension direction (eg, X direction), and a rotation angle compared to the minor axis extension direction or the major axis extension direction.

[0078] It should be noted that the above steps S100~S200 can be performed when different semiconductor film layers are stacked in sequence in a direction away from the first semiconductor film layer, so as to realize real-time measurement of the overlay offset between different semiconductor film layers and the first semiconductor film layer, thereby facilitating real-time monitoring of abnormalities and timely compensation in the manufacturing stage of each semiconductor film layer according to the overlay offset, thereby ensuring the exposure accuracy of the lithography product from the chip manufacturing stage.

[0079] In addition, it should be added that the exposure compensation method provided in the relevant embodiments is generally performed by grouping different semiconductor film layers. Specifically, the semiconductor film layers are divided into a group with a target number of layers, and the offset vector of each semiconductor film layer in each group is determined according to the semiconductor film layer adjacent to it.

[0080] For example, take the case where the number of stacked semiconductor film layers is 8, and each semiconductor film layer is divided into a group of two; wherein the first offset vector of the second semiconductor film layer is determined according to the first-layer alignment pattern of the first layer directly below it; the second offset vector of the third and / or fourth semiconductor film layer is determined according to the first-layer alignment pattern of the second layer directly below it; the third offset vector of the fifth and / or sixth semiconductor film layer is determined according to the first-layer alignment pattern of the fourth layer directly below it; the fourth offset vector of the seventh and / or eighth semiconductor film layer is determined according to the first-layer alignment pattern of the sixth layer directly below it.

[0081] However, the exposure compensation method provided in the embodiments of the present application uses the first-layer alignment pattern on the first-layer semiconductor film layer as the 0-layer alignment pattern or the alignment reference pattern, measures the offset vector of the measured alignment pattern on other semiconductor film layers on the first-layer alignment pattern compared to the first-layer alignment pattern directly below it, and then compensates the overlay offset of the machine according to the offset vector. Compared with calculating the offset vector by using the first-layer alignment pattern on the non-first-layer semiconductor film layer as the alignment reference pattern, this embodiment can at least avoid the adverse effect of the offset vector of the alignment reference pattern itself on the offset vector obtained by the aforementioned calculation, and thus can effectively improve the accuracy of the compensation for the overlay offset of the machine, improve the accuracy of alignment, and thus improve the yield and performance of the manufactured semiconductor products.

[0082] In some embodiments, see Figure 6 , step S200 includes the following steps S210~S230.

[0083] S210, obtaining the initial coordinates of the current exposure center.

[0084] For example, the initial coordinates may be determined based on a longitudinal coordinate along a direction in which the minor axis extends (eg, the Y direction) and a transverse coordinate along a direction in which the major axis extends (eg, the X direction).

[0085] S220, taking the coordinates after reversely adjusting the offset vector of the initial coordinates as the coordinates of the adjusted exposure center.

[0086] S230, exposing again after the exposure center is adjusted to the coordinates of the adjusted exposure center.

[0087] It should be noted that determining the adjustment amount of the exposure center based on the coordinate value and the offset vector to obtain the coordinates of the adjusted exposure center is conducive to accurate adjustment of the lithography exposure center, thereby improving the overlay accuracy of the chip.

[0088] It should be understood that although Figure 5~Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5~Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0089] In summary, the present application provides an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method, which can produce unexpected technical effects including: being able to realize real-time measurement of the overlay offset between different semiconductor film layers and the first semiconductor film layer, so as to facilitate real-time monitoring of abnormalities and timely compensation in the manufacturing stage of each semiconductor film layer according to the overlay offset, ensuring the exposure accuracy of the lithography product from the chip manufacturing stage, effectively eliminating the adverse effects of machine errors on the measurement of alignment errors (Overlay, referred to as OVL), and avoiding chip scrapping caused by slicing confirmation when electrical abnormalities occur after chip production is completed, while saving costs, realizing real-time measurement and timely compensation of the overlay offset, so as to improve the overlay accuracy of the chip, thereby effectively improving the yield of the lithography product.

[0090] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. An alignment pattern, It is characterized in that Located in the cutting path, including a first-layer alignment pattern and at least one measurement alignment pattern; The first-layer alignment pattern is located on the first-layer semiconductor film layer, and includes a central symmetric pattern sharing a central point and a symmetry axis, and a rhombus located within the central symmetric pattern; The at least one measurement alignment pattern is located on different semiconductor film layers stacked in sequence in a direction away from the first semiconductor film layer; the at least one measurement alignment pattern is a rhombus; The offset vector of the at least one measured alignment pattern compared to the first layer alignment pattern is used to indicate the overlay offset of the semiconductor film layer; Wherein, the rhombus in the first-layer alignment pattern and the rhombus in the measurement alignment pattern have the same or similar shapes; At least one measurement alignment pattern is arranged on each semiconductor film layer stacked in sequence in a direction away from the first semiconductor film layer.

2. The alignment pattern according to claim 1, It is characterized in that The central symmetrical figure is an ellipse, one symmetry axis of the rhombus is located on the short axis of the ellipse, and the other symmetry axis of the rhombus is located on the long axis of the ellipse.

3. The alignment pattern according to claim 2, It is characterized in that Two opposite vertices of the rhombus are located on the ellipse.

4. The alignment pattern according to claim 3, It is characterized in that The offset vector includes the offset of the measured alignment figure compared to the first-layer alignment figure along the extension direction of the short axis, the offset along the extension direction of the long axis, and the rotation angle of a symmetry axis of the measured alignment figure compared to the extension direction of the short axis of the first-layer alignment figure, or the rotation angle of another symmetry axis of the measured alignment figure compared to the extension direction of the long axis of the first-layer alignment figure.

5. An alignment pattern according to any one of claims 1 to 4, It is characterized in that The cutting path includes a plurality of first-layer alignment patterns which are arranged at intervals and distributed around the chip area.

6. The alignment pattern according to claim 5, It is characterized in that A plurality of the first-layer alignment patterns are arranged at equal intervals in the cutting path.

7. A semiconductor device, It is characterized in that include: An alignment pattern as claimed in any one of claims 1 to 6.

8. An electronic device, It is characterized in that include: The alignment pattern according to any one of claims 1 to 6; or The semiconductor device according to claim 7.

9. An exposure compensation method, It is characterized in that Based on the alignment pattern according to any one of claims 1 to 6; The exposure compensation method comprises: Obtaining an offset vector of the measurement alignment pattern of the current layer to be measured relative to the alignment pattern of the first layer directly below it; The exposure center is adjusted based on the offset vector and then the exposure is performed.

10. The exposure compensation method according to claim 9, It is characterized in that Adjusting the exposure center based on the offset vector and then exposing includes: Get the initial coordinates of the current exposure center; The coordinates after the offset vector is reversely adjusted from the initial coordinates are used as the coordinates of the exposure center after adjustment; Exposure is performed after the exposure center is adjusted to the coordinates of the adjusted exposure center.

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