A switchable mode oscillator and DC-DC voltage converter system

Abstract

The present invention relates to the field of DC-DC voltage converters, and specifically to a switchable mode oscillator and DC-DC voltage converter system, comprising a gate circuit module, an oscillation module and a bias module, wherein the oscillation module is electrically connected to the gate circuit module; the oscillation module is electrically connected to an error detection module and a current detection module, and the current detection module outputs a switching voltage Vsw to a first input terminal of the oscillation module; the output terminal of the gate circuit module is electrically connected to a driving module and a triangular wave generation module, the switching voltage Vsw controls the oscillation module to select a PFM mode, and adjusts the on-time or off-time to obtain signals with different duty cycles; the switching voltage Vsw controls the oscillation module to select a PWM mode, changes the frequency of the oscillator, and uses a comparator U1 to obtain signals with different duty cycles. The switching between the PFM mode and the PWM mode is realized, the flexibility is high, the overall circuit structure is simple, and the application cost is effectively reduced.

Description

Technical Field

[0001] The invention relates to the field of DC-DC voltage converters, and in particular to an oscillator with switchable modes and a DC-DC voltage converter system. Background Art

[0002] The DC-DC converter uses microelectronic technology to assemble small surface-mount integrated circuits and microelectronic components into one to achieve DC voltage conversion. Its functions mainly include voltage conversion, isolation, protection, noise reduction and voltage regulation. Voltage conversion is its most basic function, which can convert the DC input voltage into a DC output voltage higher or lower than the input voltage. It uses the energy storage characteristics of inductors or capacitors to convert the DC voltage into another adjustable or fixed DC voltage circuit. The converter needs to detect the output signal circuit and modulate the output duty cycle according to the feedback information to achieve the stability of the output voltage. Common modulation methods include PWM modulation, PFM modulation and PWM / PFM hybrid modulation.

[0003] The frequency and duty cycle of the oscillator in the traditional DCDC switching power supply circuit are fixed, or only one of them can be changed; only a square wave signal with a fixed oscillation frequency and a fixed duty cycle is provided in the system. When adjusting the duty cycle, additional circuit modules need to be added to assist, the circuit is more complex, and the application cost is higher. Summary of the invention

[0004] The object of the present invention is to provide an oscillator and a DC-DC voltage converter system with switchable modes, aiming to improve the problem that the duty cycle of the oscillator in the traditional DCDC switching power supply circuit is fixed, and when adjusting the duty cycle, additional circuit modules need to be added to assist, the circuit is relatively complex, and the application cost is high.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] An oscillator with switchable modes includes a gate circuit module, an oscillation module and a bias module.

[0007] The oscillation module and the bias module are electrically connected to an external power supply VDD1, the oscillation module is electrically connected to a gate circuit module, and the bias module outputs a first bias voltage VB1 to the oscillation module;

[0008] The external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module to adjust the bias current of the bias module; the external logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module to adjust the capacitance value of the control capacitor group; the first input end of the oscillation module is electrically connected to the current detection module, the second input end of the oscillation module is electrically connected to the error detection module, and the current detection module outputs the switching voltage Vsw to the first input end of the oscillation module;

[0009] The output end of the gate circuit module is electrically connected to the driving module and the triangular wave generating module. The gate circuit module outputs the square wave voltage Vosc-PFM to the driving module or outputs the square wave voltage Vosc-PWM to the triangular wave generating module. The triangular wave generating module converts the square wave voltage Vosc-PWM into a triangular wave and outputs it to the second input end of the comparator U1. The error detection module outputs the duty cycle control voltage Vctrl to the second input end of the oscillation module and the first input end of the comparator U1. The output end of the comparator U1 is electrically connected to the driving module. The driving module outputs the control voltage Vdrv to the input end of the external control power tube and the current detection module.

[0010] Furthermore, the external logic control circuit outputs a reset voltage Vrst to the gate circuit module, and the external logic control circuit outputs a duty cycle mode switching voltage Vdms to the third input terminal of the oscillation module.

[0011] Further, the gate circuit module includes an inverter D1, an inverter D2, an inverter D3, an inverter D4, a NAND gate NA1, a NAND gate NA2, a NAND gate NA3 and a NAND gate NA4;

[0012] The oscillation module also includes an inverter D5, an inverter D6, an inverter D7, an inverter D8, a MOS tube P1, a MOS tube P2, a MOS tube P3, a MOS tube P4, a MOS tube P5, a MOS tube P16, a MOS tube N1, a MOS tube N2, a MOS tube N3, a MOS tube N4, a MOS tube N5, a MOS tube N6, a MOS tube N7, a MOS tube N8, a MOS tube N9, a MOS tube N10, a MOS tube N11, a MOS tube N12, a MOS tube N13, a MOS tube N28, a MOS tube N29, a MOS tube N30, a MOS tube N31, a MOS tube N32, a MOS tube N33, a MOS tube N34, a MOS tube N35 and a MOS tube N36; the control capacitor group includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6;

[0013] The sources of the MOS transistors P1, P2, P4 and P5 are all electrically connected to the external power supply VDD1;

[0014] The bias module outputs a first bias voltage VB1 to the gates of the MOS transistors P1, P2, P4 and P5; the drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P16; the gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor N1 and the output end of the NAND gate NA3; the drain of the MOS transistor P16 is electrically connected to the drain of the MOS transistor N1, the drain of the MOS transistor N2, the drain of the MOS transistor N28, the drain of the MOS transistor N29, the drain of the MOS transistor N30 and the gate of the MOS transistor N4; the gate of the MOS transistor N2 is electrically connected to the output end of the inverter D1;

[0015] The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P3, the gate of the MOS transistor P3 is electrically connected to the gate of the MOS transistor N3, the second input terminal of the NAND gate NA3 and the output terminal of the NAND gate NA4, and the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N2, the drain of the MOS transistor N5, the drain of the MOS transistor N7, the drain of the MOS transistor N8 and the gate of the MOS transistor N12;

[0016] The external logic control module outputs a voltage control signal EN1 to the gate of the MOS tube N28, the source of the MOS tube N28 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to the drain of the MOS tube N32; the external logic control module outputs a voltage control signal EN2 to the gate of the MOS tube N29, the source of the MOS tube N29 is electrically connected to one end of the capacitor C2; the external logic control module outputs a voltage control signal EN3 to the gate of the MOS tube N30, the source of the MOS tube N30 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C3 is electrically connected to the drain of the MOS tube N33. The external logic control module outputs a voltage control signal EN4 to the gate of the MOS tube N5, the source of the MOS tube N5 is electrically connected to one end of the capacitor C4, and the other end of the capacitor C4 is electrically connected to the drain of the MOS tube N6; the external logic control module outputs a voltage control signal EN5 to the gate of the MOS tube N7, the source of the MOS tube N7 is electrically connected to one end of the capacitor C5; the external logic control module outputs a voltage control signal EN6 to the gate of the MOS tube N8, the source of the MOS tube N8 is electrically connected to one end of the capacitor C6, and the other end of the capacitor C6 is electrically connected to the drain of the MOS tube N10;

[0017] The drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N4 and the first input terminal of the NAND gate NA2; the source of the MOS transistor N4 is electrically connected to the drain of the MOS transistor N9, the source of the MOS transistor N34, the drain of the MOS transistor N36 and the source of the MOS transistor N31; the drain of the MOS transistor P5 is electrically connected to the drain of the MOS transistor N12 and the second input terminal of the NAND gate NA1; the source of the MOS transistor N12 is electrically connected to the drain of the MOS transistor N13, the source of the MOS transistor N31 and the source of the MOS transistor N35;

[0018] The current detection module outputs the switching voltage Vsw to the gate of the MOS tube N36 and the input end of the inverter D5, and the output end of the inverter D5 is electrically connected to the input end of the inverter D6, the gate of the MOS tube N11, the gate of the MOS tube N32, the gate of the MOS tube N33, the gate of the MOS tube N6 and the gate of the MOS tube N10; the output end of the inverter D6 is electrically connected to the gate of the MOS tube N31; the error detection module outputs the duty cycle control voltage Vctrl to the drain of the MOS tube N11, and the source of the MOS tube N11 is electrically connected to the drain of the MOS tube N34 and the drain of the MOS tube N35;

[0019] The external logic control circuit outputs the duty cycle mode switching voltage Vdms to the gate of the MOS tube N34 and the input end of the inverter D7, the output end of the inverter D7 is electrically connected to the input end of the inverter D8 and the gate of the MOS tube N9, and the output end of the inverter D8 is electrically connected to the gate of the MOS tube N13;

[0020] The source of the MOS tube N1, the source of the MOS tube N2, the source of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N9, the source of the MOS tube N6, the source of the MOS tube N10, the source of the MOS tube N13 and the source of the MOS tube N36 are all grounded;

[0021] The external logic control circuit outputs a reset voltage Vrst to the input end of the inverter D1, the output end of the inverter D1 is electrically connected to the input end of the inverter D2, the output end of the inverter D2 is electrically connected to the first input end of the NAND gate NA1, the third input end of the NAND gate NA1 is electrically connected to the output end of the NAND gate NA2 and the first input end of the NAND gate NA4, the output end of the NAND gate NA1 is electrically connected to the second input end of the NAND gate NA2 and the first input end of the NAND gate NA3, the output end of the NAND gate NA3 is electrically connected to the second input end of the NAND gate NA4, the output end of the NAND gate NA4 is electrically connected to the input end of the inverter D3, the output end of the inverter D3 is electrically connected to the input end of the inverter D4, and the output end of the inverter D4 outputs a square wave voltage Vosc-PFM or outputs a square wave voltage Vosc-PWM.

[0022] Furthermore, the bias module includes a starting unit, a bias unit and a control unit.

[0023] The power input terminals of the startup unit and the bias unit are both electrically connected to an external power supply VDD1;

[0024] The output end of the startup unit is electrically connected to the input end of the bias unit, the external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the control unit, the output end of the control unit is electrically connected to the bias unit, and the output end of the bias unit outputs the first bias voltage VB1 to the oscillation module.

[0025] Further, the startup unit includes MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor N14, MOS transistor N15 and resistor R9;

[0026] The sources of the MOS transistors P6, P7, P8, P9 and P10 are all electrically connected to the external power supply VDD1;

[0027] The bias unit outputs a first bias voltage VB1 to the gates of the MOS transistors P6 and P8, and the bias unit outputs a second bias voltage VB2 to the gate of the MOS transistor P9;

[0028] The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor P7 and the gate and drain of the MOS transistor N14, and is electrically connected to the bias unit as a first output terminal; the gate of the MOS transistor P7 is electrically connected to the drain of the MOS transistor P8 and the drain of the MOS transistor N15, the gate of the MOS transistor N15 is electrically connected to the drain of the MOS transistor P10, and is electrically connected to the bias unit as a second output terminal; the drain of the MOS transistor P9 is electrically connected to the gate of the MOS transistor P10 and one end of the resistor R9;

[0029] The other end of the resistor R9, the source of the MOS transistor N14 and the source of the MOS transistor N15 are all grounded.

[0030] Further, the bias unit includes MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor P17, MOS transistor P18, MOS transistor N16, MOS transistor N17, MOS transistor N18, MOS transistor N19, MOS transistor N20, MOS transistor N21 and capacitor C9;

[0031] The control unit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R10, a MOS tube N22, a MOS tube N23, a MOS tube N24, a MOS tube N25, a MOS tube N26, a MOS tube N27 and an inverter D21, an inverter D22, an inverter D23, an inverter D12, an inverter D13, an inverter D14, an inverter D15, an inverter D16, an inverter D17, an inverter D18, an inverter D19, and an inverter D20;

[0032] The sources of the MOS transistors P11, P12, P13, P14 and P15 are all electrically connected to the external power supply VDD1;

[0033] The gate of the MOS transistor P11 is connected to the gate and drain of the MOS transistor P12, the drain of the MOS transistor N17, the gate of the MOS transistor P13 and the gate of the MOS transistor P14, and outputs the second bias voltage VB2 to the startup unit. The second output end of the startup unit is electrically connected to the drain of the MOS transistor P11, the drain and gate of the MOS transistor N16 and the gate of the MOS transistor N17. The source of the MOS transistor N17 is electrically connected to one end of the resistor R10.

[0034] The drain of the MOS transistor P13 is electrically connected to the source of the MOS transistor P17 and the source of the MOS transistor P18, the gate of the MOS transistor P17 is electrically connected to the source of the MOS transistor N21 and one end of the resistor R8, the drain of the MOS transistor P17 is electrically connected to the gate and drain of the MOS transistor N18 and the gate of the MOS transistor P19; the drain of the MOS transistor P18 is electrically connected to the drain of the MOS transistor N19, the gate of the MOS transistor N20 and one end of the capacitor C9, and the first output end of the startup unit is electrically connected to the gate of the MOS transistor P18;

[0035] The drain of the MOS transistor P14 is electrically connected to the other end of the capacitor C9, the drain of the MOS transistor N20 and the gate of the MOS transistor N21, the gate and drain of the MOS transistor P15 are electrically connected to the drain of the MOS transistor N21, and the first bias voltage VB1 is output to the start-up unit and the oscillation module;

[0036] The resistors R1, R2, R3, R4, R5, R6 and R7 are sequentially connected in series between the ground terminal and the other end of the resistor R8;

[0037] The external logic control module outputs a voltage control signal CC1 to the input end of the inverter D21, the output end of the inverter D21 is electrically connected to the input end of the inverter D22, the output end of the inverter D22 is electrically connected to the gate of the MOS tube N27, and the source and drain of the MOS tube N27 are electrically connected to the two ends of the resistor R2; the external logic control module outputs a voltage control signal CC2 to the input end of the inverter D23, the output end of the inverter D23 is electrically connected to the input end of the inverter D12. The output end of the inverter D12 is electrically connected to the gate of the MOS tube N26, and the source and drain of the MOS tube N26 are electrically connected to the two ends of the resistor R3; the external logic control module outputs a voltage control signal CC3 to the input end of the inverter D13, the output end of the inverter D13 is electrically connected to the input end of the inverter D14, the output end of the inverter D14 is electrically connected to the gate of the MOS tube N25, and the source and drain of the MOS tube N25 are electrically connected to the two ends of the resistor R4; The external logic control module outputs a voltage control signal CC4 to the input end of the inverter D20, the output end of the inverter D20 is electrically connected to the input end of the inverter D19, the output end of the inverter D19 is electrically connected to the gate of the MOS tube N24, and the source and drain of the MOS tube N24 are electrically connected to the two ends of the resistor R5; the external logic control module outputs a voltage control signal CC5 to the input end of the inverter D18, the output end of the inverter D18 is electrically connected to the input end of the inverter D17. The output end of the inverter D17 is electrically connected to the gate of the MOS tube N23, and the source and drain of the MOS tube N23 are electrically connected to the two ends of the resistor R6; the external logic control module outputs a voltage control signal CC6 to the input end of the inverter D16, the output end of the inverter D16 is electrically connected to the input end of the inverter D15, the output end of the inverter D15 is electrically connected to the gate of the MOS tube N22, and the source and drain of the MOS tube N22 are electrically connected to the two ends of the resistor R7.

[0038] Furthermore, the resistance value of the resistor R4 is R, the resistance value of the resistor R1 is 2R, the resistance value of the resistor R2 is 0.25R, the resistance value of the resistor R3 is 0.5R, the resistance value of the resistor R5 is 2R, the resistance value of the resistor R6 is 4R, the resistance value of the resistor R7 is 8R, and the resistance value of the resistor R8 is 3R.

[0039] Furthermore, the capacitance values ​​of the capacitor C3 and the capacitor C6 are C, the capacitance values ​​of the capacitor C2 and the capacitor C5 are 2C, and the capacitance values ​​of the capacitor C1 and the capacitor C4 are 4C.

[0040] To achieve the above object, the present invention adopts the following technical solutions:

[0041] A DC-DC voltage converter system includes a sampling module, a reference module, an error detection module, a logic control module, a current detection module, a triangular wave generation module, a comparator U1, a driving module, a control power tube P0 and an oscillator with switchable modes;

[0042] The sampling module outputs a sampling voltage Vsamp to the first input terminal of the error detection module; the reference module outputs a reference voltage Vref to the second input terminal of the error detection module; the error detection module outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module and the first input terminal of the comparator U1;

[0043] The logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module of the oscillator to adjust the bias current of the bias module; the logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module to adjust the capacitance value of the control capacitor group;

[0044] The oscillation module outputs a square wave voltage Vosc-PFM to the first input end of the driving module or outputs a square wave voltage Vosc-PWM to the input end of the triangular wave generating module. The triangular wave generating module converts the square wave voltage Vosc-PWM into a triangular wave and outputs it to the second input end of the comparator U1. The output end of the comparator U1 is electrically connected to the second input end of the driving module. The output end of the driving module outputs a control voltage Vdrv to the gate of the control power tube P0 and the input end of the current detection module. The output end of the current detection module outputs a switching voltage Vsw to the first input end of the oscillation module. The drain of the control power tube P0 is connected to the RLC circuit as the output end LX, and the source of the control power tube P0 is connected to the converter input voltage Vin.

[0045] Further, the error detection module includes an error amplifier U2 and a buffer U3;

[0046] The sampling module outputs a sampling voltage Vsamp to the non-inverting input terminal of the error amplifier U2, the reference module outputs a reference voltage Vref to the reverse input terminal of the error amplifier U2, the output terminal of the error amplifier U2 is electrically connected to the non-inverting input terminal of the buffer U3, the reverse input terminal of the buffer U3 is electrically connected to the output terminal, and the output terminal of the buffer U3 outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module and the first input terminal of the comparator U1.

[0047] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0048] The error detection module compares the reference voltage and the sampling voltage to generate a duty cycle control voltage Vctrl, and the current detection module detects the load current to generate a switching voltage Vsw.

[0049] When the load current is small, the switching voltage Vsw outputs a low level, and the oscillation module is controlled to select the PFM mode through the first input terminal; the output voltage Vctrl of the error detection module is made to correspond to the charging time of the capacitor group in the oscillator, and the on-time or off-time of the oscillator output is adjusted through the change of the Vctrl voltage to obtain signals with different duty cycles, and the capacitance value of the capacitor group can be controlled through the output voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 of the logic control module to adjust the initial duty cycle of the oscillator output to meet different needs; the oscillator output signal is converted into a control voltage Vdrv through the driving module to achieve the purpose of stabilizing the output load voltage Vout.

[0050] When the load current is large, the switching voltage Vsw outputs a high level, and the oscillation module is controlled to select the PWM mode through the first input terminal. The bias current is adjusted through the output voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 of the logic control module, thereby changing the frequency of the oscillator. The triangular wave signal output by the triangular wave generation module is compared with the duty cycle control voltage Vctrl by the comparator U1 to obtain a signal with a different duty cycle; the control voltage Vdrv is output by the driving module to achieve the purpose of stabilizing the output load voltage Vout. The switching between the PFM mode and the PWM mode is realized with high flexibility, simple overall circuit structure, and effective reduction of application cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A circuit diagram of an oscillator module and a gate circuit module of an oscillator with switchable modes according to the present invention;

[0052] Figure 2 A circuit diagram of a bias module of an oscillator with switchable modes according to the present invention;

[0053] Figure 3 It is an oscillator output waveform diagram under different capacitance values ​​when the PFM mode of the switchable mode oscillator of the present invention has a fixed conduction time;

[0054] Figure 4 It is an oscillator output waveform diagram under different capacitance values ​​when the PFM mode of the switchable mode oscillator of the present invention has a fixed off time;

[0055] Figure 5 An oscillator output waveform diagram of a fixed on-time in a PFM mode of the switchable mode oscillator of the present invention;

[0056] Figure 6 An oscillator output waveform diagram of a switchable oscillator with a fixed off time in a PFM mode of the present invention;

[0057] Figure 7 An oscillator output waveform diagram in the PWM mode of the oscillator with switchable modes described in the present invention;

[0058] Figure 8 The output waveform diagram of the oscillator under different bias currents in the PWM mode of the oscillator with switchable modes described in the present invention;

[0059] Fig. 9 is a system block diagram of the DC-DC voltage converter system of the present invention;

[0060] Fig.10 A circuit diagram of a driving module of the DC-DC voltage converter system of the present invention;

[0061] Fig.11 A circuit diagram of a current detection module of the DC-DC voltage converter system of the present invention;

[0062] Fig.12 FIG. 4 is a circuit diagram of the error amplifier U2 of the DC-DC voltage converter system of the present invention.

[0063] Description of reference numerals:

[0064] 1. Oscillation module; 2. Gate circuit module; 3. Bias module; 31. Start-up unit; 32. Bias unit; 33. Control unit. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0066] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0067] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0068] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0069] Please refer to Figure 1-12 As shown, this embodiment provides an oscillator with switchable modes, including a gate circuit module 2, an oscillation module 1 and a bias module 3; the oscillation module 1 and the bias module 3 are electrically connected to an external power supply VDD1, the oscillation module 1 is electrically connected to the gate circuit module 2, and the bias module 3 outputs a first bias voltage VB1 to the oscillation module 1. The external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module 3 to adjust the bias current of the bias module 3. The external logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module 1 to adjust the capacitance value of the control capacitor group. The first input end of the oscillation module 1 is electrically connected to a current detection module, and the second input end of the oscillation module 1 is electrically connected to an error detection module. The current detection module outputs a switching voltage Vsw to the first input end of the oscillation module 1. The output end of the gate circuit module 2 is electrically connected to the driving module and the triangular wave generating module. The gate circuit module 2 outputs a square wave voltage Vosc-PFM to the driving module or outputs a square wave voltage Vosc-PWM to the triangular wave generating module. The triangular wave generating module converts the square wave voltage Vosc-PWM into a triangular wave and outputs it to the second input end of the comparator U1. The error detecting module outputs the duty cycle regulating voltage Vctrl to the second input end of the oscillating module 1 and the first input end of the comparator U1. The output end of the comparator U1 is electrically connected to the driving module, and the driving module outputs the control voltage Vdrv to the input end of the external control power tube and the current detecting module. In this embodiment, the square wave voltage Vosc-PFM is the square wave voltage output by the oscillator in the PFM mode, and the square wave voltage Vosc-PWM is the square wave voltage output by the oscillator in the PWM mode.

[0070] The error detection module compares the reference voltage and the sampling voltage, and outputs the duty cycle switching voltage Vctrl. The current detection module detects the load current and outputs the switching voltage Vsw. When the load current is small, the output voltage Vctrl of the error detection module corresponds to the charging time of the capacitor group in the oscillator. Through the change of the Vctrl voltage, the on-time or off-time of the oscillator output is changed to obtain a signal with a different duty cycle. The logic control module can output voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to control the capacitance value of the capacitor group and adjust the initial duty cycle of the oscillator output to meet different needs. The oscillator output signal is converted into a control voltage Vdrv through the drive module to achieve the purpose of stabilizing the output load voltage Vout. When the load current is large, the switching voltage Vsw outputs a high level, and the oscillation module 1 is controlled to select the PWM mode through the first input terminal. The bias current is adjusted through the output voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 of the logic control module, thereby changing the frequency of the oscillator. The triangular wave signal output by the triangular wave generation module is compared with the duty cycle control voltage Vctrl by the comparator U1 to obtain a signal with a different duty cycle; the control voltage Vdrv is output by the driving module to achieve the purpose of stabilizing the output load voltage Vout. The switching between the PFM mode and the PWM mode is realized with high flexibility, simple overall circuit structure, and effective reduction of application cost.

[0071] In this example, the external logic control circuit outputs a reset voltage Vrst to the gate circuit module 2. The external logic control circuit outputs a duty cycle mode switching voltage Vdms to the third input terminal of the oscillation module 1, and controls the gate circuit module 2 to output a square wave signal with only a fixed on time or only a fixed off time through the duty cycle mode switching voltage Vdms.

[0072] Please refer to the attached Figure 1Specifically, the gate circuit module includes an inverter D1, an inverter D2, an inverter D3, an inverter D4, a NAND gate NA1, a NAND gate NA2, a NAND gate NA3 and a NAND gate NA4. The oscillation module 1 also includes an inverter D5, an inverter D6, an inverter D7, an inverter D8, a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor P4, a MOS transistor P5, a MOS transistor P16, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3, a MOS transistor N4, a MOS transistor N5, a MOS transistor N6, a MOS transistor N7, a MOS transistor N8, a MOS transistor N9, a MOS transistor N10, a MOS transistor N11, a MOS transistor N12, a MOS transistor N13, a MOS transistor N28, a MOS transistor N29, a MOS transistor N30, a MOS transistor N31, a MOS transistor N32, a MOS transistor N33, a MOS transistor N34, a MOS transistor N35 and a MOS transistor N36. The control capacitor group includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6.

[0073] Sources of the MOS transistors P1 , P2 , P4 and P5 are all electrically connected to the external power source VDD1 .

[0074] The bias module 3 outputs a first bias voltage VB1 to the gates of the MOS transistors P1, P2, P4 and P5. The drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P16, and the gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor N1 and the output end of the NAND gate NA3. The drain of the MOS transistor P16 is electrically connected to the drain of the MOS transistor N1, the drain of the MOS transistor N2, the drain of the MOS transistor N28, the drain of the MOS transistor N29, the drain of the MOS transistor N30 and the gate of the MOS transistor N4. The gate of the MOS transistor N2 is electrically connected to the output end of the inverter D1.

[0075] The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P3, and the gate of the MOS transistor P3 is electrically connected to the gate of the MOS transistor N3, the second input terminal of the NAND gate NA3, and the output terminal of the NAND gate NA4. The drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N2, the drain of the MOS transistor N5, the drain of the MOS transistor N7, the drain of the MOS transistor N8, and the gate of the MOS transistor N12.

[0076] The external logic control module outputs a voltage control signal EN1 to the gate of the MOS tube N28, the source of the MOS tube N28 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to the drain of the MOS tube N32. The external logic control module outputs a voltage control signal EN2 to the gate of the MOS tube N29, and the source of the MOS tube N29 is electrically connected to one end of the capacitor C2. The external logic control module outputs a voltage control signal EN3 to the gate of the MOS tube N30, the source of the MOS tube N30 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C3 is electrically connected to the drain of the MOS tube N33. The external logic control module outputs a voltage control signal EN4 to the gate of the MOS tube N5, the source of the MOS tube N5 is electrically connected to one end of the capacitor C4, and the other end of the capacitor C4 is electrically connected to the drain of the MOS tube N6. The external logic control module outputs a voltage control signal EN5 to the gate of the MOS tube N7, and the source of the MOS tube N7 is electrically connected to one end of the capacitor C5. The external logic control module outputs a voltage control signal EN6 to the gate of the MOS transistor N8 , the source of the MOS transistor N8 is electrically connected to one end of the capacitor C6 , and the other end of the capacitor C6 is electrically connected to the drain of the MOS transistor N10 .

[0077] The drain of MOS transistor P4 is electrically connected to the drain of MOS transistor N4 and the first input terminal of NAND gate NA2, and the source of MOS transistor N4 is electrically connected to the drain of MOS transistor N9, the source of MOS transistor N34, the drain of MOS transistor N36 and the source of MOS transistor N31. The drain of MOS transistor P5 is electrically connected to the drain of MOS transistor N12 and the second input terminal of NAND gate NA1; the source of MOS transistor N12 is electrically connected to the drain of MOS transistor N13, the source of MOS transistor N31 and the source of MOS transistor N35.

[0078] The current detection module outputs the switching voltage Vsw to the gate of the MOS tube N36 and the input end of the inverter D5. The output end of the inverter D5 is electrically connected to the input end of the inverter D6, the gate of the MOS tube N11, the gate of the MOS tube N32, the gate of the MOS tube N33, the gate of the MOS tube N6 and the gate of the MOS tube N10; the output end of the inverter D6 is electrically connected to the gate of the MOS tube N31. The error detection module outputs the duty cycle control voltage Vctrl to the drain of the MOS tube N11. The source of the MOS tube N11 is electrically connected to the drain of the MOS tube N34 and the drain of the MOS tube N35.

[0079] The external logic control circuit outputs the duty cycle mode switching voltage Vdms to the gate of the MOS tube N34 and the input end of the inverter D7. The output end of the inverter D7 is electrically connected to the input end of the inverter D8 and the gate of the MOS tube N9. The output end of the inverter D8 is electrically connected to the gate of the MOS tube N13.

[0080] The source of the MOS transistor N1, the source of the MOS transistor N2, the source of the MOS transistor N32, the source of the MOS transistor N33, the source of the MOS transistor N9, the source of the MOS transistor N6, the source of the MOS transistor N10, the source of the MOS transistor N13 and the source of the MOS transistor N36 are all grounded.

[0081] The external logic control circuit outputs a reset voltage Vrst to the input end of the inverter D1, the output end of the inverter D1 is electrically connected to the input end of the inverter D2, and the output end of the inverter D2 is electrically connected to the first input end of the NAND gate NA1. The third input end of the NAND gate NA1 is electrically connected to the output end of the NAND gate NA2 and the first input end of the NAND gate NA4, and the output end of the NAND gate NA1 is electrically connected to the second input end of the NAND gate NA2 and the first input end of the NAND gate NA3. The output end of the NAND gate NA3 is electrically connected to the second input end of the NAND gate NA4, and the output end of the NAND gate NA4 is electrically connected to the input end of the inverter D3. The output end of the inverter D3 is electrically connected to the input end of the inverter D4, and the output end of the inverter D4 outputs the square wave voltage Vosc-PFM or outputs the square wave voltage Vosc-PWM.

[0082] In this embodiment, the capacitance values ​​of capacitors C3 and C6 are C, the capacitance values ​​of capacitors C2 and C5 are 2C, and the capacitance values ​​of capacitors C1 and C4 are 4C.

[0083] In this embodiment, the capacitors C1 , C2 and C3 form a first capacitor group Ca, and the capacitors C4 , C5 and C6 form a second capacitor group Cb.

[0084] The voltage control signals EN1-EN3 control the size of Ca; specifically,

[0085] EN1 EN2 EN3=001 corresponds to Ca=C;

[0086] EN1 EN2 EN3=010 corresponds to Ca=2C;

[0087] EN1 EN2 EN3=011 corresponds to Ca=3C;

[0088] EN1 EN2 EN3 = 100 corresponds to Ca = 4C;

[0089] EN1 EN2 EN3 = 101 corresponds to Ca = 5C;

[0090] EN1 EN2 EN3 = 110 corresponds to Ca = 6C;

[0091] EN1 EN2 EN3 = 111 corresponds to Ca = 7C;

[0092] The voltage control signals EN4-EN6 control the size of Cb; specifically,

[0093] EN4 EN5 EN6=001 corresponds to Cb=C;

[0094] EN4 EN5 EN6=010 corresponds to Cb=2C;

[0095] EN4 EN5 EN6=011 corresponds to Cb=3C;

[0096] EN4 EN5 EN6 = 100 corresponds to Cb = 4C;

[0097] EN4 EN5 EN6=101 corresponds to Cb=5C;

[0098] EN4 EN5 EN6=110 corresponds to Cb=6C;

[0099] EN4 EN5 EN6=111 corresponds to Cb=7C;

[0100] The reset voltage Vrst is a reset signal. When the reset voltage Vrst is at a low level, the VCa voltage is set to a low level, and the output terminals of the NAND gate NA1 and the NAND gate NA4 are set to a high level, thereby setting VCb to a low level as well, thereby achieving reset. When the oscillator is working, the reset voltage Vrst is at a high level. VCa is the voltage on Ca, i.e., the gate voltage of the MOS tube N4, and VCb is the voltage on Cb, i.e., the gate voltage of the MOS tube N12.

[0101] Due to reset, the outputs of NAND gate NA1 and NAND gate NA4 are both at high level. After passing through inverter D3 and inverter D4, voltage Vosc is at high level, and the output of NAND gate NA3 is set to low level, so that MOS tube P16 is turned on, capacitor Ca is charged, and voltage VCa rises. When voltage VCa is higher than the turn-on voltage of MOS tube N4, the drain voltage of MOS tube N4 drops, and the output of NAND gate NA2 is set to high level, then the output of NAND gate NA1 is set to low level, and the outputs of NAND gate NA2 and NAND gate NA3 are set to high level, so that MOS tube N1 is turned on, capacitor Ca starts to discharge, and voltage VCa drops; at the same time, the output of NAND gate NA4 is set to low level, and voltage Vosc turns to low level. At this time, MOS tube P3 is turned on, capacitor Cb is charged, voltage VCb rises, and oscillation cycle is entered.

[0102] The charging time of voltage VCa and voltage VCb is the on-time and off-time of a single cycle in the oscillator output square wave. The charging cycle size corresponding to voltage VCa is:

[0103] ;

[0104] The charging cycle size corresponding to the voltage VCb is:

[0105] ；

[0106] The oscillation period of the oscillator is:

[0107] ;

[0108] Where Ta and Tb correspond to the on-time and off-time of a single cycle in the square wave voltage output by the oscillator. The length of the oscillation cycle is related to the size of the capacitor C, the voltage Vc on the capacitor, and the current I flowing into the capacitor.

[0109] Please refer to the attached Figure 2 Specifically, the bias module 3 includes a start-up unit 31, a bias unit 32 and a control unit 33. The power input terminals of the start-up unit 31 and the bias unit 32 are both electrically connected to the external power supply VDD1. The output terminal of the start-up unit 31 is electrically connected to the input terminal of the bias unit 32. The external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the control unit 33. The output terminal of the control unit 33 is electrically connected to the bias unit 32. The output terminal of the bias unit 32 outputs the first bias voltage VB1 to the oscillation module 1. The start-up unit 31 outputs a control signal to the input terminal of the bias unit 32 to control the bias power supply to output the first bias voltage VB1 to the oscillation module 1.

[0110] Specifically, the start-up unit 31 includes a MOS transistor P6, a MOS transistor P7, a MOS transistor P8, a MOS transistor P9, a MOS transistor P10, a MOS transistor N14, a MOS transistor N15 and a resistor R9.

[0111] Sources of the MOS transistors P6 , P7 , P8 , P9 and P10 are all electrically connected to the external power source VDD1 .

[0112] The bias unit 32 outputs a first bias voltage VB1 to the gates of the MOS transistors P6 and P8, and outputs a second bias voltage VB2 to the gate of the MOS transistor P9. The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor P7 and the gate and drain of the MOS transistor N14, and is electrically connected to the bias unit 32 as a first output terminal. The gate of the MOS transistor P7 is electrically connected to the drain of the MOS transistor P8 and the drain of the MOS transistor N15, and the gate of the MOS transistor N15 is electrically connected to the drain of the MOS transistor P10, and is electrically connected to the bias unit 32 as a second output terminal. The drain of the MOS transistor P9 is electrically connected to the gate of the MOS transistor P10 and one end of the resistor R9. The other end of the resistor R9, the source of the MOS transistor N14, and the source of the MOS transistor N15 are all grounded.

[0113] Specifically, the bias unit 32 includes MOS transistors P11, P12, P13, P14, P15, P17, P18, N16, N17, N18, N19, N20, N21 and capacitor C9.

[0114] The control unit 33 includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R10, a MOS tube N22, a MOS tube N23, a MOS tube N24, a MOS tube N25, a MOS tube N26, a MOS tube N27 and an inverter D21, an inverter D22, an inverter D23, an inverter D12, an inverter D13, an inverter D14, an inverter D15, an inverter D16, an inverter D17, an inverter D18, an inverter D19, and an inverter D20.

[0115] Sources of the MOS transistors P11 , P12 , P13 , P14 , and P15 are all electrically connected to the external power source VDD1 .

[0116] The gate of the MOS transistor P11 is connected to the gate and drain of the MOS transistor P12, the drain of the MOS transistor N17, the gate of the MOS transistor P13 and the gate of the MOS transistor P14, and outputs the second bias voltage VB2 to the start-up unit 31, that is, the gate of the MOS transistor P11 is also electrically connected to the gate of the MOS transistor P9. The second output end of the start-up unit 31 is electrically connected to the drain of the MOS transistor P11, the drain and gate of the MOS transistor N16 and the gate of the MOS transistor N17, that is, the gate of the MOS transistor N15 is electrically connected to the drain of the MOS transistor P11, the drain and gate of the MOS transistor N16 and the gate of the MOS transistor N17; the source of the MOS transistor N17 is electrically connected to one end of the resistor R10.

[0117] The drain of MOS transistor P13 is electrically connected to the source of MOS transistor P17 and the source of MOS transistor P18, the gate of MOS transistor P17 is electrically connected to the source of MOS transistor N21 and one end of resistor R8, the drain of MOS transistor P17 is electrically connected to the gate and drain of MOS transistor N18 and the gate of MOS transistor P19. The drain of MOS transistor P18 is electrically connected to the drain of MOS transistor N19, the gate of MOS transistor N20 and one end of capacitor C9; the first output end of the start unit 31 is electrically connected to the gate of MOS transistor P18, that is, the drain of MOS transistor P6 is electrically connected to the gate of MOS transistor P18.

[0118] The drain of the MOS transistor P14 is electrically connected to the other end of the capacitor C9, the drain of the MOS transistor N20, and the gate of the MOS transistor N21. The gate and drain of the MOS transistor P15 are electrically connected to the drain of the MOS transistor N21, and output the first bias voltage VB1 to the start-up unit 31 and the oscillation module 1, that is, the gate and drain of the MOS transistor P15 are also electrically connected to the gate of the MOS transistor P6, the gate of the MOS transistor P8, the gate of the MOS transistor P1, the gate of the MOS transistor P2, the gate of the MOS transistor P4, and the gate of the MOS transistor P5.

[0119] The resistor R1 , the resistor R2 , the resistor R3 , the resistor R4 , the resistor R5 , the resistor R6 and the resistor R7 are sequentially connected in series between the ground terminal and the other end of the resistor R8 .

[0120] The external logic control module outputs a voltage control signal CC1 to the input end of the inverter D21, the output end of the inverter D21 is electrically connected to the input end of the inverter D22, the output end of the inverter D22 is electrically connected to the gate of the MOS tube N27, and the source and drain of the MOS tube N27 are electrically connected to the two ends of the resistor R2. The external logic control module outputs a voltage control signal CC2 to the input end of the inverter D23, the output end of the inverter D23 is electrically connected to the input end of the inverter D12, the output end of the inverter D12 is electrically connected to the gate of the MOS tube N26, and the source and drain of the MOS tube N26 are electrically connected to the two ends of the resistor R3. The external logic control module outputs a voltage control signal CC3 to the input end of the inverter D13, the output end of the inverter D13 is electrically connected to the input end of the inverter D14, the output end of the inverter D14 is electrically connected to the gate of the MOS tube N25, and the source and drain of the MOS tube N25 are electrically connected to the two ends of the resistor R4. The external logic control module outputs a voltage control signal CC4 to the input end of the inverter D20, the output end of the inverter D20 is electrically connected to the input end of the inverter D19, the output end of the inverter D19 is electrically connected to the gate of the MOS tube N24, and the source and drain of the MOS tube N24 are electrically connected to the two ends of the resistor R5. The external logic control module outputs a voltage control signal CC5 to the input end of the inverter D18, the output end of the inverter D18 is electrically connected to the input end of the inverter D17, the output end of the inverter D17 is electrically connected to the gate of the MOS tube N23, and the source and drain of the MOS tube N23 are electrically connected to the two ends of the resistor R6. The external logic control module outputs a voltage control signal CC6 to the input end of the inverter D16, the output end of the inverter D16 is electrically connected to the input end of the inverter D15, the output end of the inverter D15 is electrically connected to the gate of the MOS tube N22, and the source and drain of the MOS tube N22 are electrically connected to the two ends of the resistor R7.

[0121] In this embodiment, the resistance value of resistor R4 is R, the resistance value of resistor R1 is 2R, the resistance value of resistor R2 is 0.25R, the resistance value of resistor R3 is 0.5R, the resistance value of resistor R5 is 2R, the resistance value of resistor R6 is 4R, the resistance value of resistor R7 is 8R, and the resistance value of resistor R8 is 3R.

[0122] When powered on, the gate voltage of MOS tube P10 is low level, MOS tube P10 is turned on, and current is poured into the drain of MOS tube N16. The gate voltage of MOS tube N15 is raised, MOS tube N15 is turned on, the gate voltage of MOS tube P7 is low level, MOS tube P7 is turned on, and current is poured into the drain of MOS tube N14. Thus, the degenerate state of all voltages in bias unit 32 is broken, and the circuit startup is completed. MOS tube P9 is turned on, the gate voltage of MOS tube P10 is increased, MOS tube P10 is turned off, and at the same time, MOS tube P8 is turned on, and MOS tube P7 is turned off, completing the disengagement of the startup circuit.

[0123] MOS tube P11, MOS tube P12, MOS tube N16 and MOS tube N17 form a self-bias circuit, providing a bias voltage VB2, providing a tail tube bias for the secondary operational amplifier composed of the subsequent MOS tube P13, MOS tube P14, MOS tube P17, MOS tube P18, MOS tube N18, MOS tube N19 and MOS tube N20, and capacitor C9 provides frequency compensation. The positive input terminal of the secondary operational amplifier is connected to the bias voltage Vgsn of the secondary tube connection method on the MOS tube N14, and the negative input terminal is connected to the source of the MOS tube N21, forming a gain improvement stage, realizing impedance multiplication, and stabilizing the bias current I B1 .

[0124] The output impedance Ro after multiplication is:

[0125] ;

[0126] Among them, Av is the gain of the second-stage operational amplifier, ɡ m，n21 is the transconductance of MOS tube N21, r o，n21 is the on-state internal resistance of MOS tube N21, R S is the sum of the resistors connected to the source of MOS tube N21. From the virtual short circuit, we can get the bias current I on MOS tube P15. B1 The size is:

[0127] ;

[0128] Please refer to the attached Figure 2 , by the attached Figure 2 It can be seen that R S The sum of the resistances of resistors R1 to R8 is controlled by CC1 to CC6 signals output by the logic control module to control the on / off of MOS tubes N22, N23, N24, N25, N26 and N27, and the R S The size of the bias current I B1 Carry out fine control.

[0129] When CC1 CC2 CC3 CC4 CC5 CC6 = 000000, R S Maximum, at this time R S =20.75R, then the minimum bias current is I B1 (min) = Vgsn / (20.75R).

[0130] When CC1 CC2 CC3 CC4 CC5 CC6 = 111111, R S Minimum, at this time R S =5R, then the maximum bias current is IB1 (max) = Vgsn / (5R).

[0131] In this embodiment, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14, MOS transistor N15, MOS transistor N16, MOS transistor N17, MOS transistor N18, MOS transistor N19, MOS transistor N20, MOS transistor N21, MOS transistor N22, MOS transistor N23, MOS transistor N24, MOS transistor N25, MOS transistor N26, MOS transistor N27, MOS transistor N28, MOS transistor N29, MOS transistor N30, MOS transistor N31, MOS transistor N32, MOS transistor N33, MOS transistor N34 and MOS transistor N35 are all NMOS transistors. MOS transistor P0 is a PMOS transistor.

[0132] When the oscillator is in PFM mode;

[0133] The current detection module detects that the load current is small, and the switching voltage Vsw outputs a low level. At this time, MOS tubes N36 and N31 are turned off, MOS tubes N32, N33, N6, N10 and N11 are turned on, and the oscillator enters the PFM mode. There are two duty cycle modes in the PFM mode: one is a fixed on-time, only the off-time is adjusted; the other is a fixed off-time, only the on-time is adjusted.

[0134] The conduction condition of NMOS tube is: V GS >V thn ;

[0135] That is: V G >V S +V thn ;

[0136] V GS is the gate-source voltage difference of the MOS tube; V G is the gate voltage of the MOS tube; V S is the source voltage of the MOS tube; V thn is the threshold voltage of the MOS tube.

[0137] Taking the MOS tube N4 as an example, changing the source potential of the MOS tube N4 can raise its on-voltage, so that VCa needs a longer charging time and the charging cycle is increased, that is, changing the on-time of a single cycle of the oscillator.

[0138] Similarly, by changing the source potential of the MOS tube N12, the off time of the oscillator can be changed.

[0139] Therefore, when the on-time needs to be fixed and only the off-time is adjusted, the potential of the source of the MOS tube N4 is fixed and the potential of the source of the MOS tube N12 is adjusted. When the off-time needs to be fixed and only the on-time is adjusted, the potential of the source of the MOS tube N12 is fixed and the potential of the source of the MOS tube N4 is adjusted. In this embodiment, the on-time and the off-time are respectively adjusted by connecting the duty cycle control voltage Vctrl to the source of the MOS tube N4 or the source of the MOS tube N12, so as to obtain oscillator outputs with different duty cycles.

[0140] Please refer to the attached Figure 3 and attached Figure 4 , including Figure 3 The oscillator output waveforms for different capacitance values ​​when the on-time is fixed in PFM mode are shown in the figure below. Figure 4 The following is the oscillator output waveform diagram for different capacitance values ​​when the off time is fixed in PFM mode. Figure 3 It can be seen that the charging time of the voltage VCa remains unchanged, while the charging time of the voltage VCb gradually increases with the increase of the duty cycle control voltage Vctrl, and finally the duty cycle of the oscillator output voltage Vosc changes accordingly. Figure 4 On the contrary, the charging time of the voltage VCa changes, thereby changing the duty ratio.

[0141] In addition, when Ca is equal to Cb, the duty cycle modulation cannot reach the full range, so six logic signals EN1 to EN6 are added to adjust the capacitance value to further change the duty cycle adjustment range.

[0142] When the duty cycle mode switching voltage Vdms=1, it is in the fixed on-time mode, and when the duty cycle mode switching voltage Vdms=0, it is in the fixed off-time mode. EN1 to EN3 change the Ca capacitor value, and EN4 to EN6 change the Cb capacitor value, thereby adjusting the duty cycle. Please refer to the attached Figure 3 and attached Figure 4 , attached Figure 3 and attached Figure 4 The simulation results of different duty cycles of the oscillator under five capacitance values ​​of "010001", "111001", "001001", "001010" and "001111" are shown. From the results, it can be seen that the oscillator duty cycle can be changed by adjusting the ratio of Ca and Cb capacitance values ​​in the fixed on-time mode or the fixed off-time mode. The length of the on-time and off-time are related to the Ca and Cb capacitance values ​​respectively. When the duty cycle control voltage Vctrl changes, the duty cycle changes accordingly. Adjusting the capacitance value can further expand the range of duty cycle variation. Among them, the "1" state represents a high level, and the "0" state represents a low level.

[0143] The mode switching of the duty cycle is controlled by the duty cycle mode switching voltage Vdms output by the logic control module. When the duty cycle mode switching voltage Vdms is at a high level, the MOS tube N34 and the MOS tube N13 are turned on, the MOS tube N35 and the MOS tube N9 are turned off, the source of the MOS tube N4 is the duty cycle control voltage Vctrl, the source of the MOS tube N12 is at a low level, and the oscillator enters a fixed on-time mode. When the duty cycle mode switching voltage Vdms is at a low level, the MOS tube N34 and the MOS tube N13 are turned off, the MOS tube N35 and the MOS tube N9 are turned on, the source of the MOS tube N4 is at a low level, the source of the MOS tube N12 is at the duty cycle control voltage Vctrl, and the oscillator enters a fixed off-time mode.

[0144] Please refer to the attached Figure 5 and attached Figure 6 , including Figure 5 The output waveform of the oscillator with fixed on-time in PFM mode is shown in the figure below. Figure 6 The following is the output waveform of the oscillator with fixed off time in PFM mode. Figure 5 and attached Figure 6 It can be seen that when the oscillator is in PFM mode, the on-time or off-time can be fixed for square wave control. In the fixed on-time mode, as the duty cycle control voltage Vctrl increases, the charging time of the voltage VCb gradually increases, the corresponding off-time gradually increases, and the charging time of the voltage VCa remains unchanged, and the corresponding on-time is constant. In the fixed off-time mode, as the duty cycle control voltage Vctrl increases, the charging time of the voltage VCa gradually increases, the corresponding on-time gradually increases, and the charging time of the voltage VCb remains unchanged, and the corresponding off-time is constant.

[0145] When the oscillator is in PWM mode;

[0146] The current detection module detects that the load current is large, the switching voltage Vsw is high, MOS tubes N36 and N31 are turned on, MOS tubes N11, N32, N33, N6 and N10 are turned off, and the oscillator switches to PWM mode. In PWM mode, the capacitance values ​​of Ca and Cb are fixed, Ca=C2=2C, Cb=C5=2C, and the on time and off time of the oscillator are equal. The sources of MOS tubes N12 and N4 are both low, and the gate-source voltage V GSEqual. According to the charging cycle formula corresponding to the voltage VCa, the charging cycle formula corresponding to the voltage VCb and the oscillation cycle formula of the oscillator, the period of the oscillator in PWM mode is only related to the bias current for charging the capacitor. After the triangle wave generation module converts the oscillator output voltage Vosc-PWM in PWM mode into a triangle wave, it compares it with the duty cycle control voltage Vctrl generated by the error detection module to obtain power tube control signals with different duty cycles.

[0147] Please refer to the attached Figure 7 , attached Figure 7 This is the oscillator output waveform in PWM mode. Figure 7 It can be seen that in PWM mode, the switching voltage Vsw is at a high level, and the oscillator outputs a square wave with equal on-time and off-time. It can be seen from the waveform that as the duty cycle control voltage Vctrl increases, the charging time of VCa and VCb remains constant, and the flip voltage remains unchanged.

[0148] Please refer to the attached Figure 8 , attached Figure 8 The output waveform of the oscillator under different bias currents in PWM mode is shown in the attached figure. Figure 8 It can be seen that when the values ​​of "000000", "000001", "000111" and "111111" are simulated, the oscillator output frequency and bias current I B1 The oscillator can output square wave signals of different frequencies in PWM mode.

[0149] Please refer to the attached Figure 9-12 In this embodiment, a DC-DC voltage converter system is also disclosed, including a sampling module, a reference module, an error detection module, a current detection module, a logic control module, a triangle wave generation module, a comparator U1, a driving module, a control power tube P0 and the above-mentioned switchable mode oscillator.

[0150] The sampling module outputs a sampling voltage Vsamp to the first input terminal of the error detection module; the reference module outputs a reference voltage Vref to the second input terminal of the error detection module; the error detection module outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module 1 and the first input terminal of the comparator U1.

[0151] The logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module 3 of the oscillator to adjust the bias current of the bias module 3; the logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module 1 to adjust the capacitance value of the control capacitor group.

[0152] The oscillation module 1 outputs a square wave voltage Vosc-PFM to the first input terminal of the driving module or outputs a square wave voltage Vosc-PWM to the input terminal of the triangle wave generating module. The triangle wave generating module converts the square wave voltage Vosc-PWM into a triangle wave and outputs it to the second input terminal of the comparator U1. The output terminal of the comparator U1 is electrically connected to the second input terminal of the driving module. The output terminal of the driving module outputs a control voltage Vdrv to the gate of the control power tube P0 and the input terminal of the current detection module. The output terminal of the current detection module outputs a switching voltage Vsw to the first input terminal of the oscillation module. The drain of the control power tube P0 is connected to the RLC circuit as the output terminal LX, and the source of the control power tube P0 is connected to the converter input voltage Vin. Please refer to the attached Fig. 9 In this embodiment, Vosc-PFM is the same as Vosc (PFM), and Vosc-PWM is the same as Vosc (PWM).

[0153] In this embodiment, the error detection module includes an error amplifier U2 and a buffer U3. The sampling module outputs a sampling voltage Vsamp to the same-direction input terminal of the error amplifier U2, and the reference module outputs a reference voltage Vref to the reverse input terminal of the error amplifier U2. The output terminal of the error amplifier U2 is electrically connected to the same-direction input terminal of the buffer U3, and the reverse input terminal of the buffer U3 is electrically connected to the output terminal. The output terminal of the buffer U3 outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module and the first input terminal of the comparator U1.

[0154] The sampling module samples the feedback voltage of the output voltage Vout above the converter load, and the reference module generates a reference voltage Vref; the error detection module compares the sampling voltage Vsamp with the reference voltage Vref and outputs the duty cycle control voltage Vctrl to the oscillation module 1, and the current detection module detects the load current and outputs the mode output switching voltage Vsw to the oscillation module 1 to control the oscillation module 1. The logic control module generates voltage control signals EN1-EN6 and CC1-CC6 to adjust the capacitance value of the capacitor group and the bias current I of the bias module 3 respectively. B1 The triangle wave generation module converts the square wave voltage Vosc-PWM into a triangle wave and outputs it to the second input terminal of the comparator U1. The error detection module outputs the duty cycle control voltage Vctrl to the first input terminal of the comparator U1. The comparator U1 compares the triangle wave signal with the duty cycle control voltage Vctrl, obtains a signal with a different duty cycle and outputs it to the driving module. The driving module increases the driving capability of the PWM or PFM control signal, forms the control voltage Vdrv of the power tube, controls the conduction of the power tube P0, and stabilizes the output load voltage Vout.

[0155] Please refer to Fig.10In this embodiment, in order to improve the driving capability of the oscillator output signal, a driving circuit in the form of an inverter chain is adopted. After the signal undergoes eight-level inversion, a control voltage Vdrv is output to control the on and off of the power tube.

[0156] Please refer to Fig.11 In this embodiment, the current detection module obtains the load current approximately by sampling the control power tube P0. Specifically, the sampling MOS tube P19 is used to sample the current of the control power tube P0. The gate of the MOS tube P19 and the control power tube P0 are electrically connected to the output Vdrv of the driving circuit. The positive and negative input terminals of the operational amplifier in the circuit are respectively connected to the drain of the MOS tube P19 and the control power tube P0. The output of the operational amplifier is connected to the gate of the MOS tube N37 to form a negative feedback, so that the drain voltage of the MOS tube P19 is equal to that of the control power tube P0. Therefore, the current ratio of the MOS tube P19 and the control power tube P0 is only related to their width-to-length ratio. The current is copied to the sampling resistor Rsen through the current mirror of the MOS tube N38, the MOS tube N39, the MOS tube P20 and the MOS tube P21 to form a sampling voltage Vsen. The control signal Vdrv controls the on-off of the transmission gate TG1 at the same time, and the capacitor Csen and the transmission gate TG1 form a sampling and holding circuit, which can obtain a relatively stable sampling voltage Vsen within the holding time. The voltage signal of the sampling voltage Vsen outputs the switching voltage Vsw after passing through the inverter D22 and the inverter D23. In this embodiment, the size of the MOS transistor P19 is smaller than that of the MOS transistor P0, which effectively reduces power consumption.

[0157] Specifically, the sampling voltage Vsen is calculated as follows:

[0158] Vsen=Rsen·k·I P0 ;

[0159] Where k is the ratio of the current mirror to the current, I P0 is the load current. When the load current I P0 When the load current I P0 When it is smaller, the sampling voltage Vsen outputs a low level. By controlling the ratio k and the size of the sampling resistor Rsen, the critical value for Vsw to flip can be adjusted.

[0160] Please refer to Fig.12In this embodiment, the error amplifier U2 needs to amplify the difference between the reference voltage Vref and the sampling voltage Vsamp, and needs to have a higher DC gain. Therefore, the error amplifier U2 in this embodiment is an approximate single-pole amplifier with a common source and common gate structure. The pole at the current mirror is a mirror pole, and the zero-pole cancellation can be ignored. The pole output resistance at the drain of the MOS tube N44 is very small, approximately 1 / gmn44. This pole is far away from the main pole at high frequency, so only the pole at the drain of the MOS tube N46 is left, which is approximately a single pole and has a larger bandwidth. The differential input stage and the gain stage are connected by a pair of current mirrors with a width-to-length ratio of 1:N, and it can be obtained:

[0161] I D，n40 :I D，n43 =1:N;

[0162] Among them, I D，n40 is the drain current of MOS tube N40; I D，n43 is the drain current of MOS tube N43.

[0163] Since it is available:

[0164] ;

[0165] Among them, m is the transconductance; u n is the carrier mobility; c ox is the gate oxide capacitance per unit area; w is the width of the MOS tube; l is the length of the MOS tube; I D is the drain current.

[0166] but

[0167] ɡ m，n40 :ɡ m，n43 =1:N;

[0168] Among them, m，n40 is the transconductance of MOS tube N40; m，n43 It is the transconductance of MOS tube N43.

[0169] Therefore, the gain of the error amplifier U2 is approximately:

[0170] ;

[0171] Among them, m，p27 is the transconductance of MOS tube P27; m，n46 is the transconductance of MOS tube N46; R out is the output impedance of the drain of MOS tube P26.

[0172] After simplification, we can get:

[0173] A V =N·ɡm，p27 ·R out ;

[0174] in,

[0175] R out = m，p26 ·r o，p26 ·r o，p25 / / ɡ m，n46 ·r o，n46 ·r o，n43 ;

[0176] Among them, m，p26 is the transconductance of MOS tube P26; r o，p26 is the on-state internal resistance of MOS tube P26; r o，p25 is the on-state internal resistance of MOS tube P25; r o，n46 is the on-state internal resistance of MOS tube N46; r o，n43 is the on-state internal resistance of MOS tube N43.

[0177] From the above, we can see that the error amplifier U2 can be approximately regarded as a gain stage output pole with only the drain of MOS tube P26 and MOS tube N27, so its gain-bandwidth product is

[0178] ;

[0179] Among them, m，p27 is the transconductance of MOS tube P27; Cc is the compensation capacitor, GBW is related to N, the larger the N value is, the larger the GBW is. However, since the increase in N value will affect the position of the mirror pole, the final N value is selected to be 4.

[0180] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A switchable mode oscillator, It is characterized in that Including gate circuit module, oscillation module and bias module, The oscillation module and the bias module are electrically connected to an external power supply VDD1, the oscillation module is electrically connected to a gate circuit module, and the bias module outputs a first bias voltage VB1 to the oscillation module; The external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module to adjust the bias current of the bias module; the external logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module to adjust the capacitance value of the control capacitor group; the first input end of the oscillation module is electrically connected to the current detection module, the second input end of the oscillation module is electrically connected to the error detection module, and the current detection module outputs the switching voltage Vsw to the first input end of the oscillation module; The output end of the gate circuit module is electrically connected to a driving module and a triangular wave generating module. The gate circuit module outputs a square wave voltage Vosc-PFM to the driving module or outputs a square wave voltage Vosc-PWM to the triangular wave generating module. The triangular wave generating module converts the square wave voltage Vosc-PWM into a triangular wave and outputs it to the second input end of the comparator U1. The error detection module outputs a duty cycle control voltage Vctrl to the second input end of the oscillation module and the first input end of the comparator U1. The output end of the comparator U1 is electrically connected to the driving module. The driving module outputs a control voltage Vdrv to the input end of the external control power tube and the current detection module. The external logic control circuit outputs a reset voltage Vrst to the gate circuit module, and the external logic control circuit outputs a duty cycle mode switching voltage Vdms to the third input terminal of the oscillation module; The gate circuit module includes an inverter D1, an inverter D2, an inverter D3, an inverter D4, a NAND gate NA1, a NAND gate NA2, a NAND gate NA3 and a NAND gate NA4; The oscillation module also includes an inverter D5, an inverter D6, an inverter D7, an inverter D8, a MOS tube P1, a MOS tube P2, a MOS tube P3, a MOS tube P4, a MOS tube P5, a MOS tube P16, a MOS tube N1, a MOS tube N2, a MOS tube N3, a MOS tube N4, a MOS tube N5, a MOS tube N6, a MOS tube N7, a MOS tube N8, a MOS tube N9, a MOS tube N10, a MOS tube N11, a MOS tube N12, a MOS tube N13, a MOS tube N28, a MOS tube N29, a MOS tube N30, a MOS tube N31, a MOS tube N32, a MOS tube N33, a MOS tube N34, a MOS tube N35 and a MOS tube N36; the control capacitor group includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a capacitor C6; The sources of the MOS transistors P1, P2, P4 and P5 are all electrically connected to the external power supply VDD1; The bias module outputs a first bias voltage VB1 to the gates of the MOS transistors P1, P2, P4 and P5; the drain of the MOS transistor P1 is electrically connected to the source of the MOS transistor P16; the gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor N1 and the output end of the NAND gate NA3; the drain of the MOS transistor P16 is electrically connected to the drain of the MOS transistor N1, the drain of the MOS transistor N2, the drain of the MOS transistor N28, the drain of the MOS transistor N29, the drain of the MOS transistor N30 and the gate of the MOS transistor N4; the gate of the MOS transistor N2 is electrically connected to the output end of the inverter D1; The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P3, the gate of the MOS transistor P3 is electrically connected to the gate of the MOS transistor N3, the second input terminal of the NAND gate NA3 and the output terminal of the NAND gate NA4, and the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N2, the drain of the MOS transistor N5, the drain of the MOS transistor N7, the drain of the MOS transistor N8 and the gate of the MOS transistor N12; The external logic control module outputs a voltage control signal EN1 to the gate of the MOS tube N28, the source of the MOS tube N28 is electrically connected to one end of the capacitor C1, and the other end of the capacitor C1 is electrically connected to the drain of the MOS tube N32; the external logic control module outputs a voltage control signal EN2 to the gate of the MOS tube N29, the source of the MOS tube N29 is electrically connected to one end of the capacitor C2; the external logic control module outputs a voltage control signal EN3 to the gate of the MOS tube N30, the source of the MOS tube N30 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C3 is electrically connected to the drain of the MOS tube N33. The external logic control module outputs a voltage control signal EN4 to the gate of the MOS tube N5, the source of the MOS tube N5 is electrically connected to one end of the capacitor C4, and the other end of the capacitor C4 is electrically connected to the drain of the MOS tube N6; the external logic control module outputs a voltage control signal EN5 to the gate of the MOS tube N7, the source of the MOS tube N7 is electrically connected to one end of the capacitor C5; the external logic control module outputs a voltage control signal EN6 to the gate of the MOS tube N8, the source of the MOS tube N8 is electrically connected to one end of the capacitor C6, and the other end of the capacitor C6 is electrically connected to the drain of the MOS tube N10; The drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N4 and the first input terminal of the NAND gate NA2; the source of the MOS transistor N4 is electrically connected to the drain of the MOS transistor N9, the source of the MOS transistor N34, the drain of the MOS transistor N36 and the source of the MOS transistor N31; the drain of the MOS transistor P5 is electrically connected to the drain of the MOS transistor N12 and the second input terminal of the NAND gate NA1; the source of the MOS transistor N12 is electrically connected to the drain of the MOS transistor N13, the source of the MOS transistor N31 and the source of the MOS transistor N35; The current detection module outputs the switching voltage Vsw to the gate of the MOS tube N36 and the input end of the inverter D5, and the output end of the inverter D5 is electrically connected to the input end of the inverter D6, the gate of the MOS tube N11, the gate of the MOS tube N32, the gate of the MOS tube N33, the gate of the MOS tube N6 and the gate of the MOS tube N10; the output end of the inverter D6 is electrically connected to the gate of the MOS tube N31; the error detection module outputs the duty cycle control voltage Vctrl to the drain of the MOS tube N11, and the source of the MOS tube N11 is electrically connected to the drain of the MOS tube N34 and the drain of the MOS tube N35; The external logic control circuit outputs the duty cycle mode switching voltage Vdms to the gate of the MOS tube N34 and the input end of the inverter D7, the output end of the inverter D7 is electrically connected to the input end of the inverter D8 and the gate of the MOS tube N9, and the output end of the inverter D8 is electrically connected to the gate of the MOS tube N13; The source of the MOS tube N1, the source of the MOS tube N2, the source of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N9, the source of the MOS tube N6, the source of the MOS tube N10, the source of the MOS tube N13 and the source of the MOS tube N36 are all grounded; The external logic control circuit outputs a reset voltage Vrst to the input end of the inverter D1, the output end of the inverter D1 is electrically connected to the input end of the inverter D2, the output end of the inverter D2 is electrically connected to the first input end of the NAND gate NA1, the third input end of the NAND gate NA1 is electrically connected to the output end of the NAND gate NA2 and the first input end of the NAND gate NA4, the output end of the NAND gate NA1 is electrically connected to the second input end of the NAND gate NA2 and the first input end of the NAND gate NA3, the output end of the NAND gate NA3 is electrically connected to the second input end of the NAND gate NA4, the output end of the NAND gate NA4 is electrically connected to the input end of the inverter D3, the output end of the inverter D3 is electrically connected to the input end of the inverter D4, and the output end of the inverter D4 outputs a square wave voltage Vosc-PFM or outputs a square wave voltage Vosc-PWM.

2. The switchable mode oscillator according to claim 1, Features: The bias module includes a starting unit, a bias unit and a control unit. The power input terminals of the startup unit and the bias unit are both electrically connected to an external power supply VDD1; The output end of the startup unit is electrically connected to the input end of the bias unit, the external logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the control unit, the output end of the control unit is electrically connected to the bias unit, and the output end of the bias unit outputs the first bias voltage VB1 to the oscillation module.

3. The switchable mode oscillator according to claim 2, Features: The startup unit includes MOS transistor P6, MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor N14, MOS transistor N15 and resistor R9; The sources of the MOS transistors P6, P7, P8, P9 and P10 are all electrically connected to the external power supply VDD1; The bias unit outputs a first bias voltage VB1 to the gates of the MOS transistors P6 and P8, and the bias unit outputs a second bias voltage VB2 to the gate of the MOS transistor P9; The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor P7 and the gate and drain of the MOS transistor N14, and is electrically connected to the bias unit as a first output terminal; the gate of the MOS transistor P7 is electrically connected to the drain of the MOS transistor P8 and the drain of the MOS transistor N15, the gate of the MOS transistor N15 is electrically connected to the drain of the MOS transistor P10, and is electrically connected to the bias unit as a second output terminal; the drain of the MOS transistor P9 is electrically connected to the gate of the MOS transistor P10 and one end of the resistor R9; The other end of the resistor R9, the source of the MOS transistor N14 and the source of the MOS transistor N15 are all grounded.

4. The switchable mode oscillator according to claim 2, Features: The bias unit includes MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor P17, MOS transistor P18, MOS transistor N16, MOS transistor N17, MOS transistor N18, MOS transistor N19, MOS transistor N20, MOS transistor N21 and capacitor C9; The control unit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R10, a MOS tube N22, a MOS tube N23, a MOS tube N24, a MOS tube N25, a MOS tube N26, a MOS tube N27 and an inverter D21, an inverter D22, an inverter D23, an inverter D12, an inverter D13, an inverter D14, an inverter D15, an inverter D16, an inverter D17, an inverter D18, an inverter D19, and an inverter D20; The sources of the MOS transistors P11, P12, P13, P14 and P15 are all electrically connected to the external power supply VDD1; The gate of the MOS transistor P11 is connected to the gate and drain of the MOS transistor P12, the drain of the MOS transistor N17, the gate of the MOS transistor P13 and the gate of the MOS transistor P14, and outputs the second bias voltage VB2 to the startup unit. The second output end of the startup unit is electrically connected to the drain of the MOS transistor P11, the drain and gate of the MOS transistor N16 and the gate of the MOS transistor N17. The source of the MOS transistor N17 is electrically connected to one end of the resistor R10. The drain of the MOS transistor P13 is electrically connected to the source of the MOS transistor P17 and the source of the MOS transistor P18, the gate of the MOS transistor P17 is electrically connected to the source of the MOS transistor N21 and one end of the resistor R8, the drain of the MOS transistor P17 is electrically connected to the gate and drain of the MOS transistor N18 and the gate of the MOS transistor P19; the drain of the MOS transistor P18 is electrically connected to the drain of the MOS transistor N19, the gate of the MOS transistor N20 and one end of the capacitor C9, and the first output end of the startup unit is electrically connected to the gate of the MOS transistor P18; The drain of the MOS transistor P14 is electrically connected to the other end of the capacitor C9, the drain of the MOS transistor N20 and the gate of the MOS transistor N21, the gate and drain of the MOS transistor P15 are electrically connected to the drain of the MOS transistor N21, and the first bias voltage VB1 is output to the start-up unit and the oscillation module; The resistors R1, R2, R3, R4, R5, R6 and R7 are sequentially connected in series between the ground terminal and the other end of the resistor R8; The external logic control module outputs a voltage control signal CC1 to the input end of the inverter D21, the output end of the inverter D21 is electrically connected to the input end of the inverter D22, the output end of the inverter D22 is electrically connected to the gate of the MOS tube N27, and the source and drain of the MOS tube N27 are electrically connected to the two ends of the resistor R2; the external logic control module outputs a voltage control signal CC2 to the input end of the inverter D23, the output end of the inverter D23 is electrically connected to the input end of the inverter D12. The output end of the inverter D12 is electrically connected to the gate of the MOS tube N26, and the source and drain of the MOS tube N26 are electrically connected to the two ends of the resistor R3; the external logic control module outputs a voltage control signal CC3 to the input end of the inverter D13, the output end of the inverter D13 is electrically connected to the input end of the inverter D14, the output end of the inverter D14 is electrically connected to the gate of the MOS tube N25, and the source and drain of the MOS tube N25 are electrically connected to the two ends of the resistor R4; The external logic control module outputs a voltage control signal CC4 to the input end of the inverter D20, the output end of the inverter D20 is electrically connected to the input end of the inverter D19, the output end of the inverter D19 is electrically connected to the gate of the MOS tube N24, and the source and drain of the MOS tube N24 are electrically connected to the two ends of the resistor R5; the external logic control module outputs a voltage control signal CC5 to the input end of the inverter D18, the output end of the inverter D18 is electrically connected to the input end of the inverter D17. The output end of the inverter D17 is electrically connected to the gate of the MOS tube N23, and the source and drain of the MOS tube N23 are electrically connected to the two ends of the resistor R6; the external logic control module outputs a voltage control signal CC6 to the input end of the inverter D16, the output end of the inverter D16 is electrically connected to the input end of the inverter D15, the output end of the inverter D15 is electrically connected to the gate of the MOS tube N22, and the source and drain of the MOS tube N22 are electrically connected to the two ends of the resistor R7.

5. The switchable mode oscillator according to claim 4, Features: The resistance value of the resistor R4 is R, the resistance value of the resistor R1 is 2R, the resistance value of the resistor R2 is 0.25R, the resistance value of the resistor R3 is 0.5R, the resistance value of the resistor R5 is 2R, the resistance value of the resistor R6 is 4R, the resistance value of the resistor R7 is 8R, and the resistance value of the resistor R8 is 3R.

6. The switchable mode oscillator according to claim 1, Features: The capacitance values ​​of the capacitors C3 and C6 are C, the capacitance values ​​of the capacitors C2 and C5 are 2C, and the capacitance values ​​of the capacitors C1 and C4 are 4C.

7. A DC-DC voltage converter system, It is characterized in that It includes a sampling module, a reference module, an error detection module, a current detection module, a logic control module, a triangle wave generation module, a comparator U1, a driving module, a control power tube P0 and an oscillator with switchable modes according to any one of claims 1 to 6; The sampling module outputs a sampling voltage Vsamp to the first input terminal of the error detection module; the reference module outputs a reference voltage Vref to the second input terminal of the error detection module; the error detection module outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module and the first input terminal of the comparator U1; The logic control module outputs voltage control signals CC1, CC2, CC3, CC4, CC5 and CC6 to the bias module of the oscillator to adjust the bias current of the bias module; the logic control module outputs voltage control signals EN1, EN2, EN3, EN4, EN5 and EN6 to the control capacitor group of the oscillation module to adjust the capacitance value of the control capacitor group; The oscillation module outputs a square wave voltage Vosc-PFM to the first input end of the driving module or outputs a square wave voltage Vosc-PWM to the input end of the triangular wave generating module. The triangular wave generating module converts the square wave voltage Vosc-PWM into a triangular wave and outputs it to the second input end of the comparator U1. The output end of the comparator U1 is electrically connected to the second input end of the driving module. The output end of the driving module outputs a control voltage Vdrv to the gate of the control power tube P0 and the input end of the current detection module. The output end of the current detection module outputs a switching voltage Vsw to the first input end of the oscillation module. The drain of the control power tube P0 is connected to the RLC circuit as the output end LX, and the source of the control power tube P0 is connected to the converter input voltage Vin.

8. The DC-DC voltage converter system according to claim 7, Features: The error detection module includes an error amplifier U2 and a buffer U3; The sampling module outputs a sampling voltage Vsamp to the non-inverting input terminal of the error amplifier U2, the reference module outputs a reference voltage Vref to the reverse input terminal of the error amplifier U2, the output terminal of the error amplifier U2 is electrically connected to the non-inverting input terminal of the buffer U3, the reverse input terminal of the buffer U3 is electrically connected to the output terminal, and the output terminal of the buffer U3 outputs a duty cycle control voltage Vctrl to the second input terminal of the oscillation module and the first input terminal of the comparator U1.

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