A load collaborative scheduling method and system for solid state drives

Abstract

The invention relates to the technical field of solid-state hard disks, and discloses a load collaborative scheduling method and system for solid-state hard disks, wherein the method comprises: collecting data from a solid-state hard disk main controller to obtain original feature data; inputting a Kolmogorov‑Arnold neural network to perform nonlinear feature transformation and linear combination operation to obtain a load prediction result; performing hierarchical processing to obtain a hierarchical scheduling model; constructing a multi-objective optimization function and setting constraints to obtain a constrained optimization equation group; performing convex difference function decomposition and augmented Lagrangian function construction on the constrained optimization equation group, solving the constrained optimization equation group by an alternating direction iteration method to obtain a scheduling decision plan; performing load balancing control on data write physical address allocation, data read cache scheduling and multi-channel parallel transmission according to the scheduling decision plan to obtain a real-time performance monitoring index, and the method realizes the load collaborative scheduling of solid-state hard disks.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state drives, and in particular to a load collaborative scheduling method and system for solid state drives. Background Art

[0002] The NAND flash memory cells of solid-state drives have a limited number of erase and write cycles and need to be erased before new data can be written. This characteristic creates a significant trade-off between data writing performance and storage cell life.

[0003] As data access patterns become increasingly complex, traditional SSD load scheduling methods have difficulty effectively balancing multiple performance objectives such as multi-channel parallel access, cache space allocation, and physical block erase and write balance. Especially in high-concurrency access scenarios, the lack of accurate prediction of load characteristics and multi-dimensional collaborative optimization mechanisms leads to large system performance fluctuations, low resource utilization, and inability to ensure balanced use of storage units. In addition, existing load scheduling methods mostly use empirical heuristic algorithms and lack in-depth modeling and theoretical analysis of the dynamic characteristics of the system. This method has difficulty finding the global optimal solution when dealing with highly dynamic, multi-constrained scheduling problems, and cannot adapt to complex and changeable workload characteristics, affecting the overall performance and reliability of the SSD. Summary of the invention

[0004] The present invention provides a load collaborative scheduling method and system for solid-state hard disks, which are used to implement load collaborative scheduling of solid-state hard disks.

[0005] In a first aspect, the present invention provides a load collaborative scheduling method for a solid-state hard disk, the load collaborative scheduling method for a solid-state hard disk comprising:

[0006] Collect data from the main controller of the solid-state hard disk to obtain original characteristic data;

[0007] The original feature data is input into a Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination operation to obtain a load prediction result;

[0008] Performing hierarchical processing based on the load prediction result to obtain a hierarchical scheduling model;

[0009] A multi-objective optimization function is constructed based on the hierarchical scheduling model, and constraints are set on a physical block life threshold, an upper limit of the number of parallel channels, and a cache capacity boundary to obtain a constrained optimization equation group;

[0010] The constrained optimization equations are decomposed by convex difference functions and constructed by augmented Lagrangian functions, and solved by alternating direction iteration method to obtain a scheduling decision plan;

[0011] According to the scheduling decision scheme, load balancing control is performed on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission to obtain real-time performance monitoring indicators.

[0012] In a second aspect, the present invention provides a load collaborative scheduling system for a solid-state hard disk, the load collaborative scheduling system for a solid-state hard disk comprising:

[0013] The acquisition module is used to collect data from the main controller of the solid-state hard disk to obtain original characteristic data;

[0014] A calculation module, used for inputting the original feature data into a Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination calculation to obtain a load prediction result;

[0015] A processing module, used for performing hierarchical processing based on the load prediction result to obtain a hierarchical scheduling model;

[0016] A construction module is used to construct a multi-objective optimization function based on the hierarchical scheduling model, and set constraints on the physical block life threshold, the upper limit of the number of parallel channels, and the cache capacity boundary to obtain a constrained optimization equation group;

[0017] A solution module, used for performing convex difference function decomposition and augmented Lagrangian function construction on the constrained optimization equation group, solving the equation group through alternating direction iteration method to obtain a scheduling decision plan;

[0018] The control module is used to perform load balancing control on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission according to the scheduling decision scheme to obtain real-time performance monitoring indicators.

[0019] In the technical solution provided by the present invention, by introducing the Kolmogorov-Arnold neural network to predict load characteristics, the spatiotemporal correlation of data access patterns can be accurately captured with high prediction accuracy, and a hierarchical scheduling architecture is adopted to realize the coordinated optimization of the flash translation layer, channel scheduling and cache management, which significantly improves the utilization efficiency of system resources and reduces scheduling conflicts; the multi-objective optimization problem is converted into a convex difference form and solved by the augmented Lagrangian method, which ensures the convergence of the solution process and the global optimality of the optimization result; a scheduling mechanism based on physical property constraints is designed, which effectively balances multiple objectives such as data reading and writing performance, channel bandwidth utilization and physical block life, and extends the service life of storage devices; a real-time performance monitoring system is established, and the system performance bottleneck is discovered in time through dynamic tracking and analysis of key performance indicators, providing a basis for dynamic adjustment of scheduling strategies.

[0020] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of an embodiment of a load collaborative scheduling method for a solid state drive in an embodiment of the present invention;

[0023] Figure 2 It is a schematic diagram of an embodiment of a load collaborative scheduling system for solid-state hard disks in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device end including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or device ends.

[0026] To facilitate understanding of this embodiment, a load coordination scheduling method for a solid state drive disclosed in an embodiment of the present invention is first described in detail. Figure 1 As shown, the method comprises the following steps:

[0027] 101. Collect data from the solid state hard disk main controller to obtain original feature data;

[0028] It is understandable that the execution subject of the present invention may be a load coordination scheduling system for solid state drives, or a terminal or a server, which is not specifically limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0029] Specifically, a counting matrix is ​​constructed for the execution status of the write operation of each NAND flash memory cell in the solid-state drive. The elements of each matrix are used to record the write count value, data block size and timestamp information of the corresponding physical block, and a physical block write state matrix describing the write state of the NAND flash memory cell is generated, reflecting the load state, frequency and time characteristics of each physical block during the write process. Based on the physical block write state matrix, the erase cycle count and the number of valid data copies of each NAND flash memory cell are statistically analyzed. Each erase operation involves information such as the threshold for triggering the erase, the execution time of the erase operation and the completion status of the erase process. The statistics of these data help to more accurately describe the wear and use status of each physical block, thereby constructing a physical block erase feature set. Indicators such as the erase frequency and the number of valid data copies of the physical block reflect the life and balance state of the block, which helps to improve the overall wear balance and extend the service life of the solid-state drive. According to the physical block erase feature set, the parallel transmission task count and bandwidth occupancy analysis are performed on each storage channel in the solid-state drive, and the data transmission rate, task queue length and channel blocking status of each channel are recorded to form a channel load feature set, which helps the system better understand the workload of each storage channel and clarify the resource utilization and load pressure of each channel at different time points. The cache mapping table is constructed and the access frequency statistics are performed on the data blocks in the channel load feature set, and the cache address, access count and life cycle of each data block are recorded to generate a cache dynamic feature set. The cache dynamic feature set describes the location of each data block in the cache and the frequency of its access. This information is helpful for optimizing cache management, especially in ensuring efficient data access and hit rate. The dynamic adjustment of the cache can effectively reduce the delay of I / O access. The data access records in the cache dynamic feature set are sorted, and the type identification, data size and access mode of each I / O request are analyzed to obtain the I / O behavior feature set, which describes the I / O request mode of the system, including the read-write ratio, request size distribution and access locality characteristics. Based on the I / O behavior feature set, the physical address space of the data block is scanned for heat distribution, and the hot and cold areas in the physical address space are identified, so as to facilitate the reasonable allocation of hot and cold data during the scheduling process. The address distribution feature set is generated by recording the data update frequency, access density, and fragmentation degree of each physical address area. Through heat analysis, the access mode and frequency characteristics of the data are effectively identified, so that different strategies can be adopted to optimize the physical location allocation and access efficiency of the data. The physical block write state matrix, physical block erase feature set, channel load feature set, cache dynamic feature set, I / O behavior feature set, and address distribution feature set are integrated to generate complete original feature data. These feature data are interrelated and comprehensively reflect the overall status of the solid-state drive, including the load conditions at each level, wear status, and data access mode.

[0030] 102. Input the original feature data into the Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination operation to obtain the load prediction result;

[0031] Specifically, the original feature data is subjected to component decomposition processing, and the original feature data is divided into an inner variable group and an outer variable group, which effectively captures the hierarchical structure between the data, so that the neural network can more flexibly extract features between different variables. The inner variable group is input into the first layer of the single variable function unit of the Kolmogorov-Arnold network, and the inner feature mapping value is obtained by calculating through the polynomial basis function, which reflects the feature expression of the inner variable group after being expanded in the high-order space and captures the complex characteristics inside the data. The outer variable group is input into the second layer of the single variable function unit of the Kolmogorov-Arnold network, and the outer feature mapping value is obtained by calculating through the trigonometric basis function. The trigonometric basis function has the characteristic of capturing periodic changes and can effectively characterize the potential periodic characteristics or correlation in the outer variable. The inner feature mapping value and the outer feature mapping value are input into the superposition unit, and the feature fusion is performed through the linear combination weight matrix to generate a combined feature vector. Based on the combined feature vector, a hyperplane mapping layer is constructed, and a high-dimensional feature representation is obtained through the Hilbert space inner product operation and kernel function transformation. By mapping the combined feature vector to a high-dimensional space, the nonlinear relationship that the original features cannot show in the low-dimensional space can be captured. The inner product operation and kernel function transformation of the Hilbert space enable the network to find better feature segmentation and mapping in the high-dimensional space, improving the model's ability to fit complex data relationships and prediction accuracy. High-dimensional feature representation can better describe the load characteristics of the SSD and capture the potential deep-level associations between the original feature data. The high-dimensional feature representation is input into the output layer of the Kolmogorov-Arnold network. Through itemized linear mapping, the values ​​of storage channel load, cache space allocation, and garbage collection time are calculated respectively to obtain the load prediction results. By performing a separate linear mapping on each target, accurate prediction of each specific indicator is guaranteed. For example, storage channel load prediction can help the system reasonably allocate IO requests to avoid overloading of certain channels, while cache space allocation prediction optimizes cache usage, improves data reading speed and reduces access latency. The prediction of garbage collection time can effectively plan GC (Garbage Collection) operations in advance, reduce interference with normal IO operations, and improve the overall work efficiency and user experience of the SSD.

[0032] 103. Perform hierarchical processing based on the load prediction results to obtain a hierarchical scheduling model;

[0033] Specifically, the hierarchical characteristic data of the system are obtained by hierarchically analyzing the predicted values ​​of the storage channel load, the predicted values ​​of the cache space allocation and the predicted values ​​of the garbage collection time in the load prediction results. These hierarchical characteristic data represent the resource usage of different system levels, including the load of each channel, the use of the cache and the arrangement of garbage collection. Based on the hierarchical characteristic data, the address mapping mechanism of the flash translation layer in the solid-state drive is dynamically reconstructed to achieve the optimal utilization of storage resources. In this process, by establishing a multi-level mapping table from logical address to physical address, each level of the mapping table contains an address conversion index, a data block status identifier and an update timestamp, an address mapping layer is constructed. The address mapping layer makes address conversion more flexible and increases the scalability and fine-grained control capability of address management through multi-level mapping. The dynamically reconstructed address mapping mechanism enables the solid-state drive to adjust the logical to physical address correspondence in real time according to the current load and resource status, thereby achieving wear leveling and performance optimization. Based on the address mapping layer, the data transmission of the storage channel is load balanced to improve the overall data throughput efficiency of the system. In this process, a channel scheduling layer is formed by dividing the priority level of the channel, setting the task waiting queue length and calculating the idle time window of the channel. The division of priority levels ensures that important tasks are executed first, while the design of task waiting queue length and idle time window effectively adjusts the load state of each channel to avoid excessive occupation or idleness of channel resources, thereby achieving load balancing between channels. The channel scheduling layer ensures that the system can maximize the use of bandwidth and reduce the generation of transmission bottlenecks when transmitting in parallel on multiple channels by reasonably allocating transmission tasks. Based on the channel scheduling layer, the cache space is dynamically partitioned and managed. By reasonably partitioning the cache, the space allocation ratio of the hot data cache area, the pre-read data cache area and the write buffer area is constructed to obtain the cache management layer. The hot data cache area is used to store frequently accessed data, thereby improving the cache hit rate and access speed; the pre-read data cache area is used to store data that the system predicts will be accessed in order to speed up data reading; the write buffer is used to temporarily store write data, reduce the impact of writing on the system and improve write efficiency. The cache management layer dynamically adjusts the size of each cache area so that the cache space can be flexibly allocated according to the load situation, thereby ensuring the overall performance of the system. The inter-layer communication interface is constructed based on the address mapping layer, channel scheduling layer and cache management layer. The inter-layer coordination mechanism enables each layer to exchange information and status in real time and ensure the coordination and consistency between layers by designing a data interaction protocol, defining a state synchronization mechanism, and establishing a resource sharing strategy. The data interaction protocol ensures the accurate transmission of information, the state synchronization mechanism ensures the consistency of the states of each layer, and the resource sharing strategy avoids resource contention by reasonably allocating system resources. The inter-layer coordination mechanism is input into the scheduling state machine, and the state transition rules and trigger conditions of the idle state, working state, and abnormal state are defined to obtain the state transition model.The state transition model ensures that the system can switch between different working modes according to the current operating conditions through the transition logic between different states. For example, when the system load is low, the system enters the idle state to save resources; when there are more requests, the system enters the working state to fully handle the load; and when a fault or abnormal situation occurs, the system enters the abnormal state to handle the fault. Based on the state transition model, each scheduling layer is hierarchically integrated and time-sequenced to build a multi-level scheduling framework. By designing the execution process of the scheduling, each layer can execute tasks in a predetermined order and time to ensure the overall scheduling coordination and consistency. Generate a hierarchical scheduling model so that the solid-state drive can adaptively adjust resource allocation when facing different loads and working conditions, thereby improving the performance of the overall system, extending the service life and effectively managing resource usage.

[0034] 104. Construct a multi-objective optimization function based on the hierarchical scheduling model, and set constraints on the physical block life threshold, the upper limit of the number of parallel channels, and the cache capacity boundary to obtain a constrained optimization equation group;

[0035] Specifically, the data read and write delay in the hierarchical scheduling model is quantitatively analyzed. By calculating the response time, queue waiting time and transmission completion time of data read and write requests, the delay optimization sub-function is obtained, which reflects the delay characteristics of the solid-state drive under different load conditions and provides a basis for subsequent optimization. The reduction of delay is directly related to the performance improvement of the system. Through fine quantitative analysis, the factors causing high delay can be identified and alleviated. The channel bandwidth utilization in the hierarchical scheduling model is statistically analyzed, and the bandwidth optimization sub-function is obtained by calculating the data throughput, transmission efficiency and idle time ratio of each channel. This sub-function can reflect the actual utilization of each channel, thereby providing a basis for load balancing scheduling. The effective use of the channel helps to improve the transmission efficiency and parallel performance of the entire solid-state drive. By improving the utilization of the channel, the overall data throughput is increased and the generation of bottlenecks is reduced. At the same time, the number of physical block erases in the hierarchical scheduling model is dynamically tracked, and the cumulative number of erases, the erase interval time and the remaining available times of each physical block are recorded to obtain the erase optimization sub-function. The erase optimization sub-function can reflect the wear of the physical block during use and provide reference data for wear leveling, ensuring that the system maintains a long life under high-frequency erase and write operations. The latency optimization sub-function, bandwidth optimization sub-function and erase optimization sub-function are linearly combined according to the preset weights, and the target trade-offs are made by constructing a penalty factor matrix to obtain a multi-objective optimization function. The purpose of constructing the penalty factor matrix is ​​to balance between different targets so that the synergy of multiple performance indicators can be considered in the optimization process. For example, in some cases, latency reduction is given priority, while in other cases, wear leveling and life extension are more emphasized. The weights of the optimization targets are flexibly adjusted through the penalty factor to ensure the comprehensiveness and effectiveness of the final scheduling strategy. Based on the constructed multi-objective optimization function, the life constraints of the physical blocks are set to ensure that the system will not cause premature failure of the memory due to excessive wear during long-term operation. The life constraints are implemented by limiting the maximum erase count threshold, the minimum remaining life ratio and the wear leveling coefficient of each physical block. These constraints ensure that the service life of each physical block is not over-consumed, thereby improving the stability of the overall solid-state drive. By setting reasonable life thresholds and balancing coefficients, the wear of different physical blocks can be balanced, reducing the problem of excessive wear caused by local hot spots. According to the life constraint conditions, the channel parallel constraints are constructed. By setting the maximum number of concurrent transmission tasks, the maximum bandwidth upper limit of a single channel, and the load balancing factor between channels, the parallel constraints are obtained to ensure good resource utilization when multiple channels are operated in parallel, while avoiding the problem of load imbalance between channels. By limiting the channel bandwidth and load balancing factor, the working status of each channel is dynamically adjusted, and the transmission tasks are reasonably allocated, thereby reducing the overload of some channels and the idleness of other channels.Based on the parallel constraint, the cache capacity constraint is set. By dividing the upper limit of the hot data cache capacity, the lower limit of the pre-read cache space, and the protection threshold of the write cache area, the capacity constraint is obtained. The cache capacity constraint helps the system to achieve refined management in the use of the cache. The upper limit of the hot data cache capacity ensures that the hot data can be effectively cached, reducing the delay during reading; the lower limit of the pre-read cache space ensures that the system can read the data predicted to be accessed in advance, reducing the waiting time for future data access; the protection threshold of the write cache area is used to avoid overfilling of the write cache to prevent the impact and blockage of the system during writing. By reasonably dividing the cache space, the effective utilization of the cache is maximized and the data access performance of the system is improved. The multi-objective optimization function is combined with the life constraint, parallel constraint and capacity constraint to establish a set of constraint optimization equations. Under the condition of considering multiple performance indicators and resource constraints, the global optimal scheduling strategy is found.

[0036] 105. Perform convex difference function decomposition and augmented Lagrangian function construction on the constrained optimization equations, solve them by alternating direction iteration method, and obtain the scheduling decision plan;

[0037] Specifically, the minimum data read and write delay, the maximum channel bandwidth utilization, and the minimum number of physical block erase times in the constraint optimization equation group are separated by convex functions and concave functions. The non-convex objective function is converted into The form of , where f(x) is the convex function part, representing the benefit function of resource utilization, h(x) is the concave function part, representing the system overhead function, and x is the decision variable vector, and the differential objective function is obtained. By decomposing, the complex non-convex problem is processed into a form that can be solved by difference, thereby simplifying the solution process. The differential objective function is combined with the physical block life constraint, channel parallel constraint and cache capacity constraint, and the augmented Lagrangian function is obtained by constructing an augmented term of the form λ∥Ax+By-c∥²+ρ / 2∥Ax+By-c∥², where A represents the address mapping matrix, B represents the channel allocation matrix, c is the resource capacity vector, λ is the Lagrangian multiplier vector, ρ is the penalty factor, and y represents the channel allocation decision variable. The construction of the augmented term allows the constraints in the optimization problem to be integrated into the objective function, and the satisfaction of the constraints is controlled by the penalty term. The augmented Lagrangian function not only considers the optimization of the target in the solution process, but also ensures the strict compliance of the constraints by adding the augmented term. Based on the augmented Lagrangian function, the x-minimization subproblem of the function is constructed. By fixing the variables y and λ, we can solve The physical address allocation scheme is obtained in the form of Represents the gradient vector of the convex function. The solution of the gradient helps to find the solution that minimizes the objective function. In this way, a preliminary physical address allocation scheme is obtained to ensure that the use of physical blocks optimizes the efficiency of data access as much as possible under the condition of overall wear leveling. Based on the physical address allocation scheme, the y-minimization subproblem is constructed, and the channel task sequence is obtained by solving the form of λ(Ax+By-c)+ρ / 2∥Ax+By-c∥²=0. Reasonable task allocation is performed on each channel of the solid-state drive so that the bandwidth of each channel can be maximized when multiple channels are transmitted in parallel, while ensuring the load balancing of each channel to avoid bottlenecks caused by some channels in a busy state. The physical address allocation scheme and channel task sequence are updated by λ. The multiplier is updated using the formula λk+1=λk+ρ(Amk+1+Bnk+1-c), where k is the number of iterations, mk+1 and nk+1 are the physical address allocation scheme and channel task sequence of the k+1th iteration, respectively, to obtain the multiplier update sequence. Through updating, the constraints are gradually approached and satisfied, and the objective function is optimized at the same time, so that the update of Lagrange multipliers becomes the key link in the alternating direction multiplier method, driving the entire optimization process to converge to the global optimal solution. According to the multiplier update sequence, the original residual and the dual residual are calculated, and the conditions of ∥Amk+1+Bnk+1-c∥≤ε and ρ∥A(mk+1-mk)∥≤ε are judged. ε is the preset convergence threshold used to control the accuracy of the solution. If the above conditions are met, it means that the current iterative solution is close enough to the optimal solution, and the iteration process ends; if not, it is necessary to continue iterating to obtain a higher accuracy solution. Through refined judgment, it is ensured that the solution process converges in time under the premise of meeting a certain accuracy, thereby improving the solution efficiency. After obtaining a solution that meets the convergence criteria, the continuous solution is discretized. By converting the continuous solutions m and n into discrete physical block number sequences, channel task number sequences and cache partition indexes, and performing physical constraint verification on these numbers, a preliminary scheduling decision plan is obtained. In actual systems, the allocation of physical resources is usually discretized. Discretization of continuous solutions ensures the operability and feasibility of solutions in physical systems. The feasibility of the preliminary decision plan is optimized. By calculating the erase balance, channel load balance and cache space utilization of each physical block, local adjustments are made to the decision variables that do not meet the constraints to generate the final scheduling decision plan. The service life of the entire solid-state drive is extended by balancing the wear of the physical blocks; the efficiency of data transmission is ensured by balancing the channel load; and the speed of data access is improved and the response time of the system is reduced by the rational use of cache space.

[0038] 106. According to the scheduling decision plan, load balancing control is performed on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission to obtain real-time performance monitoring indicators.

[0039] Specifically, address mapping is performed for each write request according to the physical block number sequence generated in the scheduling decision scheme. By calculating the number of P / E (Program / Erase) cycles, the number of valid pages, the size of the remaining space, and the data update frequency of each physical block, a 4×N-dimensional feature matrix is ​​constructed, where N represents the total number of physical blocks, and the address allocation matrix describing the status of all physical blocks is obtained. Write operations are distributed on the address allocation matrix. By calculating the wear degree M of each physical block, the formula is M=α×(number of P / E cycles)+β×(update frequency)+γ×(valid page ratio), where α, β, and γ are the weight coefficients of the corresponding indicators, and their sum is 1. Through this calculation, the wear degree M of each physical block is obtained, and a block allocation sequence is generated. The block allocation sequence can ensure that the write tasks are reasonably allocated to each physical block, thereby avoiding excessive use of some physical blocks and causing increased wear, thereby extending the life of the entire solid-state drive. Based on the above block allocation sequence, a task scheduling queue is established according to the channel task number sequence in the scheduling decision scheme. Calculate the current number of tasks Tc, data transmission rate Tr, and queue waiting time Tw of each channel, construct the channel state vector S=(Tc, Tr, Tw), and obtain the channel working state table. The channel working state table describes the current load and working status of each channel. According to the channel working state table, perform parallel transmission control by calculating the load balance degree B of the channel. The formula is B=max(Tc) / min(Tc)≤δ, where δ is the preset balance threshold, B is the channel load balance degree, max(Tc) represents the maximum value of the current number of tasks, and min(Tc) represents the minimum value of the current number of tasks. If the load difference between channels is too large, the load balance degree will exceed the threshold. At this time, it is necessary to dynamically adjust the allocation of data transmission tasks to ensure load balance between channels and obtain a parallel scheduling scheme, so as to effectively utilize the bandwidth resources of all channels and reduce the generation of transmission bottlenecks. At the same time, according to the cache partition index in the scheduling decision scheme, these indexes are mapped to the physical cache space. By constructing a cache mapping table T, where T(i,j) represents the storage location of the i-th data block in the j-th cache partition, a cache space allocation table is obtained to clarify the location of each data block in the cache, so that the system can perform cache management and maximize the use of cache space to speed up data access. After generating the cache space allocation table, read requests are processed for the contents in the table to calculate the access heat H of each data block. The access heat H is calculated using the formula H=g×(access frequency)+μ×(temporal locality), where g and μ are heat weights representing access frequency and temporal locality, respectively, and g+μ=1. Through calculation, the most frequently accessed data blocks and hot data blocks with time correlation are identified, and a cache scheduling sequence is generated. The cache scheduling sequence helps the system to reasonably allocate cache resources, ensuring that hot data can receive priority cache services, thereby improving the read and write performance of the entire system.Based on the block allocation sequence, parallel scheduling scheme and cache scheduling sequence, load balancing control is performed. In order to evaluate the scheduling effect and system performance, the data response time tr, channel bandwidth utilization ub and physical block erase balance ep need to be recorded in each control cycle Δt to obtain a performance parameter set. The data response time tr describes the time consumption of the system in read and write operations, the channel bandwidth utilization ub reflects the efficiency of the system's use of channel resources, and the physical block erase balance ep is used to evaluate the balance of wear between physical blocks. The performance parameter set is analyzed by sliding windows, and the window size is w control cycles. By calculating the mean variance of the data response time tr, the peak-to-valley ratio of the channel bandwidth utilization ub and the discrete coefficient of the physical block erase balance ep, real-time performance monitoring indicators are generated. The mean variance can describe the stability of the system response time, the peak-to-valley ratio is used to measure the fluctuation of bandwidth utilization, and the discrete coefficient reflects the uniformity of wear between physical blocks. Through real-time performance monitoring indicators, the scheduling strategy is dynamically adjusted to ensure that various resources are optimally utilized and improve the overall performance and reliability of the solid-state drive.

[0040] In the embodiment of the present invention, by introducing the Kolmogorov-Arnold neural network for load feature prediction, the spatiotemporal correlation of data access patterns can be accurately captured with high prediction accuracy. A hierarchical scheduling architecture is adopted to realize the coordinated optimization of the flash translation layer, channel scheduling and cache management, significantly improve the utilization efficiency of system resources, and reduce scheduling conflicts. The multi-objective optimization problem is converted into a convex difference form and solved by the augmented Lagrangian method, which ensures the convergence of the solution process and the global optimality of the optimization result. A scheduling mechanism based on physical property constraints is designed to effectively balance multiple objectives such as data read and write performance, channel bandwidth utilization and physical block life, thereby extending the service life of the storage device. A real-time performance monitoring system is established to timely discover system performance bottlenecks through dynamic tracking and analysis of key performance indicators, providing a basis for dynamic adjustment of scheduling strategies.

[0041] In a specific embodiment, the process of executing step 101 may specifically include the following steps:

[0042] A counting matrix is ​​constructed for the write operation execution status of each NAND flash memory cell in the solid-state drive, and each matrix element records the write count value, data block size and timestamp information of the corresponding physical block to obtain a physical block write status matrix;

[0043] Based on the physical block write state matrix, the erase cycle count and valid data copy times of each NAND flash memory cell are counted, and the trigger threshold, execution time and completion status of each erase operation are recorded to obtain the physical block erase feature set;

[0044] According to the physical block erase feature set, the parallel transmission task count and bandwidth occupancy rate analysis are performed on each storage channel, and the data transmission rate, task queue length and blocking state of each channel are recorded to obtain the channel load feature set;

[0045] Construct a cache mapping table and perform access frequency statistics on the data blocks in the channel load feature set, record the cache address, access count and life cycle of each data block, and obtain a cache dynamic feature set;

[0046] Sort the data access records in the cache dynamic feature set, and analyze the type, data size and access mode of each I / O request to obtain the I / O behavior feature set;

[0047] Based on the I / O behavior feature set, the physical address space of the data block is scanned for heat distribution, and the data update frequency, access density and fragmentation degree of each physical address area are recorded to obtain the address distribution feature set;

[0048] The physical block write state matrix, physical block erase feature set, channel load feature set, cache dynamic feature set, I / O behavior feature set and address distribution feature set are integrated to generate original feature data.

[0049] Specifically, data is collected and managed for the NAND flash memory cells inside the solid-state drive. For each physical block, the status of its write operation is recorded, including information such as the write count value, the size of the data block, and the timestamp of the operation. A physical block write status matrix is ​​set up ,matrix Each element of Indicates The physical block is in The status of the write operation. The write count value Record the cumulative number of writes to the physical block and the size of the data block Indicated in The amount of data written when writing, and the timestamp It indicates the time when the write occurs. Based on the physical block write status matrix, the erase cycle count and the number of valid data copies of each NAND flash memory cell are statistically analyzed. The NAND flash memory cells in the solid-state drive have a certain erase life limit, namely the P / E (Program / Erase) cycle. Define the erase count matrix ,matrix Each element of Indicates The cumulative number of erases of a physical block. At the same time, the erase operation records the threshold that triggers the erase. , Erase operation execution time , and the completion status of the erase For the statistics of effective data copies, define a matrix of effective data copy times ,matrix Each element of Indicates The number of valid data copies of a physical block. These copy operations usually occur during the garbage collection process. When a physical block needs to be erased, the valid data in it needs to be copied to a new physical block to ensure that the data is not lost. By counting the erase and valid data copies, the erase feature set of the physical block is obtained. , reflecting the usage and wear of each physical block. According to the erase and write feature set of the physical block, count the parallel transmission tasks and analyze the bandwidth occupancy of each storage channel. The solid-state drive adopts a multi-channel parallel transmission architecture to improve the efficiency of data reading and writing. Count the number of tasks for each channel and set a channel task counting matrix , where the elements Indicates The current number of tasks for each channel. At the same time, the data transmission rate for each channel Calculate to evaluate its bandwidth utilization and calculate the task queue length of each channel and blocking state Evaluate the working status of the channel. Obtain the channel load feature set through statistical analysis , describing the load of each channel during parallel transmission, which helps to better design load balancing during scheduling. After completing the analysis of channel load characteristics, a cache mapping table is constructed and the access frequency is statistically analyzed for the data blocks in the channel load characteristic set. For the efficient operation of solid-state drives, the use of cache is crucial, especially for improving the data reading speed. In order to achieve efficient cache management, a cache mapping table is established. , where the elements Indicates The data block is in The storage locations in the cache partition. At the same time, the access count for each data block And life cycle Record the access frequency and existence time of the data block in the cache. Through this information, we can get the cache dynamic feature set , which can help the system understand the usage of the cache, so as to reasonably allocate and adjust the cache resources during the scheduling process. Sort the data access records in the cache dynamic feature set, and analyze each I / O request, including type identification, data size and access mode analysis. The types of I / O requests are divided into read and write. Each type of operation has different resource requirements for the system, and each I / O request is identified. Data size Reflects the amount of data that needs to be processed for each request, while the access mode It describes the access characteristics of the request, such as sequential access or random access. Through analysis, we get the I / O behavior feature set , which can help the system understand the specific characteristics of I / O requests so that different strategies can be adopted for different request types during the scheduling process to improve system performance. Based on the I / O behavior feature set, the physical address space of the data block is scanned for heat distribution to understand the distribution of data in the physical address space. By recording the data update frequency of each physical address area , access density and the degree of fragmentation Perform analysis. Update frequency Indicates the number of times the data in a physical address area is updated, the access density It indicates how frequently the area is accessed, and the degree of fragmentation This reflects whether the data distribution in the area is continuous or has many fragments. By scanning the heat distribution, we can get the address distribution feature set. , which helps to process hot spot data and cold spot data differently during the scheduling process, improving the overall read and write performance. Write the physical block to the state matrix , Physical Block Erase Feature Set , channel load characteristic set , cache dynamic feature set , I / O behavior feature set And address distribution feature set Perform feature integration to generate original feature data .

[0050] In a specific embodiment, the process of executing step 102 may specifically include the following steps:

[0051] Decompose the original feature data into components and divide the original feature data into inner variable groups and outer variable groups;

[0052] The inner variable group is input into the first layer single variable function unit of the Kolmogorov-Arnold network, and the inner feature mapping value is obtained by calculating the polynomial basis function;

[0053] The outer variable group is input into the second layer single variable function unit of the Kolmogorov-Arnold network, and the outer feature mapping value is obtained by trigonometric basis function calculation;

[0054] The inner layer feature map value and the outer layer feature map value are input into the superposition unit, and the features are fused through the linear combination weight matrix to obtain the combined feature vector;

[0055] A hyperplane mapping layer is constructed based on the combined feature vector, and a high-dimensional feature representation is obtained through Hilbert space inner product operation and kernel function transformation;

[0056] The high-dimensional feature representation is input into the output layer of the Kolmogorov-Arnold network, and the values ​​of storage channel load, cache space allocation and garbage collection time are calculated respectively through itemized linear mapping to obtain the load prediction result.

[0057] Specifically, the original feature data is divided into an inner variable group and an outer variable group. The feature data contains a variety of information involved in the operation of the solid-state drive, such as the write status of the physical block, the number of erases, the load characteristics of the channel, the dynamic distribution of the cache, and the I / O behavior. For the inner variable group, data closely related to local characteristics are selected, such as the number of P / E cycles of the physical block, the ratio of valid pages, the access frequency of the cache, etc. These characteristics mainly reflect the internal state of the hardware. The outer variable group selects data that describes the overall characteristics of the system or involves the external environment of the system, such as I / O request mode, channel task queue length, cache space utilization, etc. These variables reflect the broader system dynamics. The inner variable group is input into the first layer of the single variable function unit of the Kolmogorov-Arnold neural network, and the inner feature mapping value is obtained by calculation through the polynomial basis function. Assume that the inner variable group is ,in Indicates The first layer of univariate function units uses polynomial basis functions:

[0058] ;

[0059] in is the order of the polynomial, The coefficients of the polynomial. By calculating the polynomial basis function for each inner variable, the inner feature mapping value matrix is ​​obtained. , each element of which Indicates The polynomial basis function can flexibly fit the nonlinear features in the data, which helps to accurately describe the local state of the SSD. For the outer variable group, let it be ,in Indicates The outer layer feature variables are input into the second layer single variable function unit of the Kolmogorov-Arnold neural network. The second layer single variable function unit uses the trigonometric function basis function:

[0060] ;

[0061] in is the frequency of the trigonometric function, The coefficients of the trigonometric functions are obtained by calculating the trigonometric basis functions of each outer variable to obtain the outer feature mapping value matrix: , each element of which Indicates The trigonometric basis functions are suitable for processing feature data with periodicity or volatility, such as the timing pattern of I / O requests, and can effectively capture the periodic behavior in the feature variables. and the outer feature map value The superposition unit input into the Kolmogorov-Arnold neural network performs feature fusion through the linear combination weight matrix to obtain the combined feature vector. Suppose the linear combination weight matrix is , then the combined eigenvector It is expressed as:

[0062] ;

[0063] in and are the weight matrices of the inner and outer feature maps respectively. The fusion process can combine feature information at different levels to improve the model's expressiveness and prediction accuracy. The combined feature vector after feature fusion is Contains multi-level information of the original data for high-dimensional mapping and prediction. Based on the combined feature vector , construct a hyperplane mapping layer, and obtain a high-dimensional feature representation through the inner product operation and kernel function transformation of the Hilbert space. Assume that the kernel function is ,in Indicates that The mapping function from the original feature space to the high-dimensional feature space, the use of the kernel function allows the system to perform inner product operations in the high-dimensional space without having to explicitly calculate the mapped feature vector. In this way, the representation of the combined feature vector in the high-dimensional space is obtained. . Represent high-dimensional features The input is sent to the output layer of the Kolmogorov-Arnold neural network, and a sub-item linear mapping is performed to calculate system performance indicators such as storage channel load, cache space allocation, and garbage collection time. Suppose the linear mapping of the output layer is:

[0064] ;

[0065] ;

[0066] ;

[0067] in , and They represent the load of the storage channel, the allocation of cache space, and the time of garbage collection. are the coefficients of the linear mapping, Represents the first combination of eigenvectors in high-dimensional space The itemized linear mapping method ensures the independent prediction of each performance indicator, thereby improving the accuracy and reliability of the prediction.

[0068] In a specific embodiment, the process of executing step 103 may specifically include the following steps:

[0069] Performing hierarchical analysis on the storage channel load prediction value, cache space allocation prediction value and garbage collection time prediction value in the load prediction result to obtain hierarchical feature data;

[0070] The address mapping mechanism of the flash translation layer is dynamically reconstructed according to the hierarchical feature data, and the address mapping layer is obtained by establishing a multi-level mapping table from logical address to physical address, each level of the mapping table contains an address conversion index, a data block status identifier and an update timestamp;

[0071] According to the address mapping layer, the data transmission of the storage channel is load balanced, and the channel scheduling layer is obtained by dividing the channel priority level, setting the task waiting queue length and calculating the channel idle time window;

[0072] Based on the channel scheduling layer, the cache space is dynamically partitioned and managed, and the cache management layer is obtained by constructing the space allocation ratio of the hot data cache area, the pre-read data cache area and the write buffer area;

[0073] The inter-layer communication interface is constructed based on the address mapping layer, channel scheduling layer and cache management layer. The inter-layer coordination mechanism is obtained by designing the data interaction protocol, defining the state synchronization mechanism and establishing the resource sharing strategy.

[0074] The inter-layer coordination mechanism is input into the scheduling state machine. By defining the transition rules and trigger conditions of the idle state, working state and abnormal state, the state transition model is obtained. Hierarchical integration and timing planning are performed based on the state transition model. By building a multi-level scheduling framework and designing the scheduling execution process, a hierarchical scheduling model is generated.

[0075] Specifically, each part of the load prediction result is analyzed in a hierarchical manner, and different prediction values ​​are used for the corresponding management levels. The load prediction result includes the storage channel load prediction value, the cache space allocation prediction value, and the garbage collection time prediction value. These prediction values ​​are analyzed in a hierarchical manner to obtain hierarchical feature data to describe the status and future load conditions of different components in the system. The prediction results are reasonably disassembled and allocated to specific management levels so that each level can obtain effective information for corresponding scheduling and optimization. The address mapping mechanism of the flash translation layer is dynamically reconstructed based on the hierarchical feature data. The flash translation layer is an important part of the solid-state drive and is responsible for managing the conversion of logical addresses to physical addresses. In order to improve system performance and extend service life, a multi-level mapping table from logical addresses to physical addresses is established, and each level of the mapping table contains an address conversion index. , data block status indicator and update timestamp Through these multi-level mapping tables, the correspondence between logical addresses and physical addresses is flexibly managed to adapt to different load requirements. For example, for frequently updated data blocks, address mapping can dynamically point them to physical blocks with less wear, reducing excessive wear on individual physical blocks. The multi-level mapping is expressed as:

[0076] ;

[0077] in Indicates Level mapping table, Indicates the number of logical addresses. Each time a write or update operation is performed, the mapping table is dynamically adjusted according to the data block status identifier and the update timestamp to ensure that the mapping of logical addresses to physical addresses remains optimal. Load balancing is performed on the data transmission of the storage channel based on the information of the address mapping layer. The purpose of channel scheduling is to achieve balanced task allocation in multi-channel parallel transmission, thereby improving the overall transmission efficiency. Divide the priority levels of the channels , Set the length of the task waiting queue And calculate the idle time window of the channel , this information is integrated into the channel scheduling layer. The priority level of the channel is used to ensure that important tasks can be processed first when system resources are limited; the length of the task waiting queue reflects the current load of the channel, and the calculation of the idle time window is used to decide when to assign tasks to a specific channel. Assume that there is a system channels, the channel scheduling is represented as a state vector:

[0078] ;

[0079] Through this step, load balancing scheduling is achieved for each channel to ensure balanced distribution of tasks between channels and reduce overload or idleness of some channels. Dynamic partition management of cache space is performed based on the channel scheduling layer to achieve efficient use of cache. In SSDs, cache is an important resource for improving read and write performance. Reasonable partition management of cache is performed based on current load conditions and data characteristics. The cache is divided into hot data cache area, pre-read data cache area and write buffer area, and the space allocation ratio of each area is set. , so that different data types can get appropriate cache resources according to their access frequency and pre-reading requirements. The hot data cache is used to store frequently accessed data to improve the reading speed; the pre-read data cache is used to store data predicted by the system to be accessed, reducing future reading delays; the write buffer is used to temporarily store write data, reducing the number of direct writes to the flash memory unit and extending the hardware life. The cache management layer is represented as:

[0080] ;

[0081] By adjusting The size of the cache space is dynamically optimized according to the system load. The address mapping layer, channel scheduling layer and cache management layer are combined to build an inter-layer communication interface to achieve coordination and information exchange between various layers to ensure the overall coordination of the system. Design a data interaction protocol , define the state synchronization mechanism and establish a resource sharing strategy The data interaction protocol is used to transfer information between different layers. For example, the cache management layer needs to obtain the current task load information from the channel scheduling layer in order to reasonably adjust the cache partition. The state synchronization mechanism ensures that each layer can maintain a consistent state during task execution. For example, the modification of the address mapping layer needs to be notified to the channel scheduling layer and the cache management layer in a timely manner. The resource sharing strategy is used to allocate and coordinate limited system resources between different layers, such as the allocation of cache space and channel bandwidth. The inter-layer coordination mechanism is expressed as:

[0082] ;

[0083] Through the establishment of the inter-layer coordination mechanism, the coordinated optimization and efficient operation of the entire system are achieved. The inter-layer coordination mechanism is input into the scheduling state machine, and the three states of the system are defined: idle state , working state and abnormality , and set the transition rules and trigger conditions for each state to obtain the state transition model. Assume that at time The state of the system at this moment is , the state transition is expressed by the following rules:

[0084] ;

[0085] in is the state transition function, When a trigger condition occurs, such as when the system load is too high or a channel is blocked, the system will switch from the working state to the Transition to abnormal state . The establishment of the state transition model enables the system to dynamically switch between different states according to the current working conditions, so as to make corresponding adjustments when the load changes or anomalies occur. Based on the state transition model, hierarchical integration and timing planning are carried out to build a multi-level scheduling framework. The multi-level scheduling framework includes various parts from the address mapping layer, channel scheduling layer, cache management layer to the inter-layer coordination mechanism. Each part performs corresponding task allocation and resource management according to the current system status and load conditions. In order to achieve this multi-level integration, a specific scheduling execution process is designed. For example, when a new write request arrives, the address mapping layer finds the appropriate physical block according to the mapping table, and then the channel scheduling layer selects the optimal transmission channel according to the current channel load status. Finally, the cache management layer decides how to allocate the location of the write data in the cache. This process is expressed as:

[0086] ;

[0087] in To schedule the execution function, the final scheduling decision is generated by combining the feature data and coordination mechanisms at each level.

[0088] In a specific embodiment, the process of executing step 104 may specifically include the following steps:

[0089] The data read and write delay in the hierarchical scheduling model is quantitatively analyzed, and the delay optimization sub-function is obtained by calculating the response time, queue waiting time and transmission completion time of data read and write requests;

[0090] The channel bandwidth utilization in the hierarchical scheduling model is statistically analyzed, and the bandwidth optimization sub-function is obtained by calculating the data throughput, transmission efficiency and idle time ratio of each channel.

[0091] Dynamically track the number of physical block erases in the hierarchical scheduling model, and obtain the erase optimization sub-function by recording the cumulative erase times, erase interval time and remaining available times of each physical block;

[0092] The delay optimization sub-function, bandwidth optimization sub-function and erasure optimization sub-function are linearly combined according to preset weights, and a penalty factor matrix is ​​constructed to weigh the objectives and obtain a multi-objective optimization function;

[0093] The physical block life constraint is set for the multi-objective optimization function, and the life constraint condition is obtained by limiting the maximum erasure times threshold, the minimum remaining life ratio and the wear leveling coefficient of each physical block;

[0094] Construct channel parallel constraints based on life constraints, and obtain parallel constraints by setting the maximum number of concurrent transmission tasks, the maximum bandwidth upper limit of a single channel, and the load balancing factor between channels;

[0095] The cache capacity constraint is set based on the parallel constraint condition, and the capacity constraint condition is obtained by dividing the upper limit of the hot data cache capacity, the lower limit of the pre-read cache space, and the write cache area protection threshold;

[0096] The multi-objective optimization function is combined with life constraints, parallel constraints and capacity constraints, and a constrained optimization equation group is established.

[0097] Specifically, quantitative analysis is performed on data reading and writing to better optimize the efficiency of data transmission. The latency of data reading and writing is divided into three parts: response time, queue waiting time, and transmission completion time. Refers to the time from sending a request to the system responding, the waiting time in the queue It is the time that data waits in the task queue to be processed and the time when the transmission is completed. is the time required for data to be transmitted to the destination in the channel. Based on these three times, the delay optimization sub-function is obtained , which is of the form:

[0098] ;

[0099] in , , The specific value of depends on factors such as the current load status of the system, the type of request, and the channel utilization. Through quantitative analysis, the factors that cause delays in the system can be identified, so that targeted optimization can be performed. When collecting statistics on channel bandwidth utilization, the data throughput, transmission efficiency, and idle time ratio of each channel are considered. Assume that the data throughput of each channel is , the transmission efficiency is , the idle time ratio is , channel bandwidth utilization optimization sub-function It is expressed by the following formula:

[0100] ;

[0101] in is the total number of channels, Indicates channel The data throughput (in bytes per second) Indicates the transmission efficiency of the channel, usually between [0,1], and It means channel The proportion of idle time in a given time period. By optimizing sub-functions, effectively evaluate the bandwidth usage of channels, identify which channels have resource waste, and optimize and load balance these channels accordingly. For the number of physical block erases, dynamically track the usage of each physical block to ensure wear leveling and extend the life of the SSD. Record the cumulative number of erases for each physical block , Erase interval time and the remaining available times , define the erase optimization subfunction for:

[0102] ;

[0103] in Indicates the total number of physical blocks, Indicates The cumulative number of erases of a physical block, Indicates the remaining available times of the physical block. Represents the time interval between two erasures. By optimizing the sub-function, the erasure frequency of the physical block is reasonably controlled to ensure uniform wear of each physical block and avoid excessive wear of local physical blocks. According to the preset weights, the delay optimization sub-function, bandwidth optimization sub-function and erasure optimization sub-function are linearly combined to construct a comprehensive multi-objective optimization function. The weights are set as , and satisfies , then the multi-objective optimization function It is expressed as:

[0104] ;

[0105] in Used to adjust the importance of each optimization goal. In order to more finely control the trade-offs between various goals, the penalty factor matrix is ​​introduced , by constructing penalty items to balance the contradictions between various objectives. Penalty factor matrix It is expressed as:

[0106] ;

[0107] in The penalty factor for each objective function is introduced into the multi-objective optimization function to control the priority and trade-off relationship between different objectives. Physical block life constraints are set for the multi-objective optimization function to ensure that the SSD can maintain a long service life under high-intensity read and write operations. By limiting the maximum erase count threshold for each physical block , minimum remaining life ratio , and the wear leveling coefficient , and the life constraint is obtained. The life constraint is expressed as:

[0108] ;

[0109] in Indicates the maximum number of erase times for each physical block. represents the minimum remaining life ratio, Indicates the allowed wear difference, effectively prevents some physical blocks from being overused through constraints, and ensures the life balance of each physical block in the system. According to the life constraint conditions, construct channel parallel constraints. In order to achieve the reasonable allocation of parallel transmission tasks, set the maximum number of concurrent transmission tasks for each channel , the maximum bandwidth limit of a single channel , and the load balancing factor between channels The channel parallel constraint is expressed as:

[0110] ;

[0111] in Indicates channel The current number of tasks, Indicates channel data throughput, and Respectively represent the maximum number of tasks and the maximum bandwidth limit, and It is used to measure the load balance between channels. By limiting the load difference between channels, it ensures that the parallel task allocation of the system is more reasonable and reduces the transmission bottleneck. Based on the parallel constraint conditions, set the cache capacity constraint conditions. By dividing the hot data cache capacity upper limit , Pre-read cache space lower limit and write cache area protection threshold , we get the capacity constraint. The capacity constraint is expressed as:

[0112] ;

[0113] in is the currently used cache capacity, Indicates the total cache capacity. and They represent the capacity limits of the hot data cache and the pre-read cache respectively. Represents the protection area of ​​the write cache. By limiting these capacities, we can ensure the effective use and reasonable allocation of cache resources. The multi-objective optimization function is combined with the life constraint, parallel constraint, and capacity constraint to establish a comprehensive constrained optimization equation set. The equation set is expressed as:

[0114] ;

[0115] The goal is to minimize the multi-objective optimization function , while satisfying the constraints of physical block life, channel parallelism, and cache capacity. By solving the constrained optimization equations, the optimal scheduling decision of each component of the system is obtained, thereby achieving efficient management of SSD resources and improving the overall performance and service life of the system.

[0116] In a specific embodiment, the process of executing step 105 may specifically include the following steps:

[0117] The minimum data read and write delay, the maximum channel bandwidth utilization, and the minimum number of physical block erase times in the constrained optimization equations are separated by convex functions and concave functions, and the non-convex objective function is expressed as In the form of, f(x) is the convex function part, which represents the benefit function of resource utilization, h(x) is the concave function part, which represents the system cost function, and x is the decision variable vector, and the differential objective function is obtained;

[0118] The differential objective function is combined with the physical block life constraint, channel parallel constraint and cache capacity constraint, and the augmented Lagrangian function is obtained by constructing an augmented term in the form of λ∥Ax+By-c∥²+ρ / 2∥Ax+By-c∥², where A is the address mapping matrix, B is the channel allocation matrix, c is the resource capacity vector, λ is the Lagrangian multiplier vector, ρ is the penalty factor, and y represents the channel allocation decision variable;

[0119] The x-minimization subproblem of the augmented Lagrangian function is constructed, with the variables y and λ fixed, by solving , Represent the gradient vector of the convex function and obtain the physical address allocation scheme;

[0120] Based on the physical address allocation scheme, the y-minimization subproblem is constructed, and the channel task sequence is obtained by solving λ(Ax+By-c)+ρ / 2∥Ax+By-c∥²=0;

[0121] Perform λ update on the physical address allocation scheme and channel task sequence, and obtain the multiplier update sequence by calculating λk+1=λk+ρ(Amk+1+Bnk+1-c), where k is the number of iterations, mk+1 and nk+1 are the physical address allocation scheme and channel task sequence of the k+1th iteration respectively;

[0122] The primal residual and the dual residual are calculated according to the multiplier update sequence, and the convergence criterion is obtained by judging whether ∥Amk+1+Bnk+1-c∥≤ε and ρ∥A(mk+1-mk)∥≤ε holds, where ε is the preset convergence threshold used to control the solution accuracy, and mk represents the physical address allocation scheme of the kth iteration;

[0123] The solutions that meet the convergence criteria are processed, and a preliminary decision plan is obtained by converting the continuous solutions m and n into discrete physical block number sequences, channel task number sequences and cache partition indexes, respectively, and performing physical constraint verification;

[0124] The feasibility of the preliminary decision plan is optimized. By calculating the erase balance, channel load balance and cache space utilization of each physical block, local adjustments are made to the decision variables that do not meet the constraints to generate a scheduling decision plan.

[0125] Specifically, the minimum data read and write delay, the maximum channel bandwidth utilization, and the minimum number of physical block erase times in the constraint optimization equation group are separated by convex functions and concave functions. The non-convex objective function is expressed as the convex function part and the concave function part The difference form is:

[0126] ;

[0127] in is a convex function, representing the benefits of resource utilization, is a concave function, representing the system overhead, is the decision variable vector. By separation, the differential objective function is obtained. The differential form makes the problem more suitable for solving using optimization algorithms, especially when multiple complex objectives are involved. The differential function can effectively help identify the benefit part and the cost part of the objective, thereby achieving overall optimization. The differential objective function is combined with the physical block life constraint, channel parallel constraint, and cache capacity constraint to construct the augmented Lagrangian function, and the constraints and the objective function are optimized and solved together to ensure that the final solution meets both the objective optimality and all constraints. The augmented Lagrangian function is constructed in the following form:

[0128] ;

[0129] in is the address mapping matrix, which represents the mapping from logical address to physical address. is the channel allocation matrix, which describes the distribution of tasks among channels. is the resource capacity vector, describing the total amount of each resource in the system, is the Lagrange multiplier vector, used to introduce penalties for constraints, is the penalty factor, which controls the intensity of the penalty term. is the decision variable for channel allocation. By introducing the penalty term, the augmented Lagrangian function can strictly constrain the resource allocation of the system while ensuring the target optimization. The x-minimization subproblem of the augmented Lagrangian function is constructed. Minimize, fix and , construct the x-minimization subproblem. By solving the following equation, we get the physical address allocation scheme:

[0130] ;

[0131] in, Represents the gradient vector of the convex function, which is used to describe the change of the profit function with the decision variable. Solving this equation can obtain a solution that can minimize the objective function and satisfy the constraints. The value is the optimal allocation scheme of the physical address. The physical address allocation scheme determines which physical blocks the logical data should be mapped to in order to maximize the efficiency and life of the storage system. Based on the physical address allocation scheme, the channel task allocation is optimized. Based on the physical address allocation scheme, the y-minimization subproblem is constructed. By solving the following equation, the allocation sequence of the channel tasks is obtained:

[0132] ;

[0133] Through this process, the task allocation between channels is optimized to ensure that the number of tasks for each channel is within the system's capacity, thereby achieving a balanced load distribution. Reasonable task allocation can minimize the overload of some channels and the idleness of other channels, thereby improving overall performance. The physical address allocation scheme and channel task sequence are updated. The Lagrange multiplier is updated to advance the optimization process. The multiplier is updated using the following formula:

[0134] ;

[0135] in is the number of iteration steps, and Respectively The physical address allocation scheme and channel task sequence are obtained by iteration. The update of Lagrange multipliers is a key step in the alternating direction multiplier method. By continuously adjusting the multipliers to approach the optimal solution, the resource allocation and target optimization of the system are balanced. In each iteration, it is determined whether the solution has converged, the original residual and the dual residual are calculated, and the convergence condition is determined by the following criteria:

[0136] ;

[0137] in is the preset convergence threshold, which is used to control the solution accuracy. If the above conditions are met, it means that the current solution is close enough to the optimal solution, and the iteration process ends; if not, it is necessary to continue iterating to obtain a more accurate solution. After obtaining a solution that meets the convergence criteria, the continuous solution is discretized. and They are converted into discrete physical block number sequences, channel task number sequences and cache partition indexes respectively. The discretization process is to apply the optimized theoretical solution to the actual system, because the physical blocks, channels and caches in the solid-state drive are managed in a discrete manner. After discretization, physical constraint verification is performed to ensure that the discretized solution meets the physical limitations of the system, such as the capacity of the physical block, the maximum bandwidth of the channel, etc., to obtain a preliminary decision plan. The feasibility of the preliminary decision plan is optimized to ensure that all constraints can be met and the performance of the system is improved. By calculating the erase balance of each physical block , Channel load balancing And cache space utilization , local adjustments are made to the decision variables that do not meet the constraints. For example, the erasure balance is calculated by the following formula:

[0138] ;

[0139] in Indicates the cumulative number of erases per physical block, by controlling The size of the physical blocks is adjusted to ensure wear balance of all physical blocks. Similarly, channel load balance and cache utilization are evaluated and adjusted through corresponding indicators to ensure that the system resources are fully utilized and the load of each part is as even as possible.

[0140] In a specific embodiment, the process of executing step 106 may specifically include the following steps:

[0141] The write request is mapped to the address according to the physical block number sequence in the scheduling decision scheme. The address allocation matrix is ​​obtained by calculating the number of P / E cycles, the number of valid pages, the size of the remaining space, and the data update frequency of the physical block, and constructing a 4×N dimensional feature matrix, where N is the total number of physical blocks.

[0142] Write operations are distributed on the address allocation matrix. The block allocation sequence is obtained by calculating the wear degree of each physical block M = α × (number of P / E cycles) + β × (update frequency) + γ × (valid page ratio), where α, β, and γ are weight coefficients and satisfy α + β + γ = 1, and M is the wear degree;

[0143] A task scheduling queue is established based on the channel task number sequence in the scheduling decision plan. By calculating the current task number Tc, data transmission rate Tr, and queue waiting time Tw of each channel, a channel state vector S=(Tc, Tr, Tw) is constructed to obtain a channel working state table.

[0144] According to the channel working status table, parallel transmission control is performed, and the channel load balance degree B=max(Tc) / min(Tc)≤δ is calculated, where δ is the preset balance threshold, B is the channel load balance degree, max(Tc) represents the maximum value of the current number of tasks, and min(Tc) represents the minimum value of the current number of tasks. The data transmission tasks are dynamically allocated to obtain a parallel scheduling scheme;

[0145] Map the cache partition index in the scheduling decision plan to the physical cache space, and obtain the cache space allocation table by constructing a cache mapping table T, where T(i,j) represents the storage location of the i-th data block in the j-th cache partition;

[0146] Process the read request of the cache space allocation table, and obtain the cache scheduling sequence by calculating the data block access heat H = g × (access frequency) + μ × (temporal locality), where g, μ are heat weights and g + μ = 1, and H represents the data block access heat;

[0147] Based on the block allocation sequence, parallel scheduling scheme and cache scheduling sequence, load balancing control is performed, and the data response time tr, channel bandwidth utilization ub and physical block erasure balance ep are recorded in each control cycle Δt to obtain a performance parameter set;

[0148] A sliding window analysis is performed on the performance parameter set with a window size of w control cycles. Real-time performance monitoring indicators are generated by calculating the mean variance of tr, the peak-to-valley ratio of ub, and the dispersion coefficient of ep.

[0149] Specifically, each physical block in the system is analyzed, and its characteristic data is constructed into a matrix. The total number of physical blocks. The characteristics that need to be recorded for each physical block include: P / E cycle number , Number of valid pages , remaining space size and data update frequency Build a The characteristic matrix , where each column represents the characteristic information of a physical block, specifically:

[0150] ;

[0151] in Indicates The cumulative number of erases of a physical block, Indicates the number of valid pages, Indicates the remaining space size, and Indicates the frequency of data update. Distributes write operations to the address allocation matrix. In order to select the most suitable physical block for writing, calculates the wear degree of each physical block. . Degree of wear It is an important indicator to measure the current wear state of the physical block and is calculated by the following formula:

[0152] ;

[0153] in is the weight coefficient and satisfies These coefficients are used to adjust the relative importance of various factors in the wear calculation. Calculate the current state of each physical block and generate a block allocation sequence The block allocation sequence is used to guide which physical blocks the write request is allocated to, so as to reduce the excessive wear of some physical blocks and improve the overall life and performance of the SSD. The task scheduling queue is established according to the channel task number sequence in the scheduling decision scheme. The task status of each channel includes the current task number , data transmission rate and queue waiting time By calculating this information, the state vector of each channel is constructed:

[0154] ;

[0155] in Indicates the total number of channels. By describing the task status of each channel, we can get the channel working status table. , this state table reflects the workload and task status of each channel at the current moment. According to the channel working state table, parallel transmission control is performed, and the load balance of each channel is calculated to ensure that the load is relatively balanced. Channel load balance Calculated by the following formula:

[0156] ;

[0157] in Indicates the maximum number of current tasks. Indicates the minimum number of current tasks and load balancing It is used to evaluate whether the load difference between channels is within a reasonable range. (in is the preset balance threshold), the load is considered balanced; otherwise, the tasks need to be redistributed until the balance condition is met and the final parallel scheduling solution is obtained. After completing the channel load balancing, the cache is managed and the cache partition index in the scheduling decision plan is mapped to the physical cache space. By building a cache mapping table , clearly define the storage location of each data block in the cache. Indicates The data block is in The storage location of each cache partition is obtained to obtain the cache space allocation table, which describes the layout of the data in the cache. For read requests in the cache, they are scheduled according to the cache space allocation table and the access heat of each data block is calculated. . Visit popularity It is an important indicator for evaluating the frequency of data blocks being accessed in the future. The calculation formula is:

[0158] ;

[0159] in Indicates The access frequency of each data block, Indicates the temporal locality of a data block, and is the weight coefficient of heat, and satisfies . By calculation, we get the cache scheduling sequence , which is used to decide which data blocks should be kept in the cache first to improve the overall cache hit rate and system response speed. Based on the block allocation sequence, parallel scheduling scheme and cache scheduling sequence, the overall load balancing control is performed. In each control cycle In the system, record the performance parameters of the system, including data response time , Channel bandwidth utilization , Physical block erase balance These parameters constitute the performance parameter set:

[0160] ;

[0161] Among them, data response time Indicates the total time from sending a request to receiving a response, channel bandwidth utilization Indicates the actual usage of bandwidth and physical block erase balance Used to evaluate whether the wear between physical blocks is balanced. By recording the performance parameter set, the system performance is monitored in real time so that necessary adjustments and optimizations can be made. Sliding window analysis is performed on the performance parameter set so that the dynamic changes of the system can be better tracked and responded to. Suppose the size of the sliding window is control cycle, then for each performance parameter in the sliding window, calculate the following indicators: data response time The mean variance of is used to evaluate the volatility of response time and channel bandwidth utilization Peak-to-valley ratio, used to measure the stability of bandwidth usage and physical block erase balance The coefficient of dispersion is used to evaluate whether the erasure is uniform. The mean variance is calculated by the following formula:

[0162] ;

[0163] in Indicates Data response time within a control cycle, express The peak-to-valley ratio is calculated by calculating the ratio of the maximum and minimum bandwidth utilization:

[0164] ;

[0165] The coefficient of dispersion is obtained by the ratio of the standard deviation of the number of physical block erases to the average value, which is used to measure the uniformity of erase:

[0166] ;

[0167] in Indicates the standard deviation of the number of physical block erases, Represents its average value. By calculating these indicators, the real-time performance monitoring indicators of the system are generated.

[0168] The load collaborative scheduling method for solid state drives in an embodiment of the present invention is described above. The load collaborative scheduling system for solid state drives in an embodiment of the present invention is described below. Figure 2 , an embodiment of a load collaborative scheduling system for a solid state drive in an embodiment of the present invention includes:

[0169] The acquisition module 201 is used to collect data from the solid state hard disk main controller to obtain original feature data;

[0170] The operation module 202 is used to input the original feature data into the Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination operation to obtain the load prediction result;

[0171] The processing module 203 is used to perform hierarchical processing based on the load prediction result to obtain a hierarchical scheduling model;

[0172] A construction module 204 is used to construct a multi-objective optimization function based on the hierarchical scheduling model, and set constraints on the physical block life threshold, the upper limit of the number of parallel channels, and the cache capacity boundary to obtain a constrained optimization equation group;

[0173] A solution module 205 is used to perform convex difference function decomposition and augmented Lagrangian function construction on the constrained optimization equations, and solve them by alternating direction iteration method to obtain a scheduling decision plan;

[0174] The control module 206 is used to perform load balancing control on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission according to the scheduling decision plan to obtain real-time performance monitoring indicators.

[0175] Through the collaborative cooperation of the above components, the Kolmogorov-Arnold neural network is introduced for load feature prediction, which can accurately capture the spatiotemporal correlation of data access patterns with high prediction accuracy. The hierarchical scheduling architecture is adopted to realize the collaborative optimization of flash translation layer, channel scheduling and cache management, which significantly improves the utilization efficiency of system resources and reduces scheduling conflicts. The multi-objective optimization problem is transformed into a convex difference form and solved by the augmented Lagrangian method, which ensures the convergence of the solution process and the global optimality of the optimization results. A scheduling mechanism based on physical characteristic constraints is designed to effectively balance multiple objectives such as data read and write performance, channel bandwidth utilization and physical block life, thereby extending the service life of storage devices. A real-time performance monitoring system is established to timely discover system performance bottlenecks through dynamic tracking and analysis of key performance indicators, providing a basis for dynamic adjustment of scheduling strategies.

[0176] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0177] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0178] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A load collaborative scheduling method for solid state drives, characterized in that: The method comprises: Collect data from the main controller of the solid-state hard disk to obtain original characteristic data; The original feature data is input into the Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination operation to obtain a load prediction result; specifically comprising: performing component decomposition on the original feature data, dividing the original feature data into an inner variable group and an outer variable group; inputting the inner variable group into the first layer single variable function unit of the Kolmogorov-Arnold network, and obtaining an inner feature mapping value through polynomial basis function calculation; inputting the outer variable group into the second layer single variable function unit of the Kolmogorov-Arnold network, and obtaining an outer feature mapping value through trigonometric basis function calculation; inputting the inner feature mapping value and the outer feature mapping value into the superposition unit, and performing feature fusion through a linear combination weight matrix to obtain a combined feature vector; constructing a hyperplane mapping layer based on the combined feature vector, and obtaining a high-dimensional feature representation through Hilbert space inner product operation and kernel function transformation; inputting the high-dimensional feature representation into the output layer of the Kolmogorov-Arnold network, and calculating the values ​​of storage channel load, cache space allocation and garbage collection time respectively through itemized linear mapping to obtain a load prediction result; Performing hierarchical processing based on the load prediction result to obtain a hierarchical scheduling model; A multi-objective optimization function is constructed based on the hierarchical scheduling model, and constraints are set on a physical block life threshold, an upper limit of the number of parallel channels, and a cache capacity boundary to obtain a constrained optimization equation group; The constrained optimization equation group is decomposed into convex differential functions and constructed with augmented Lagrangian functions, and solved by alternating direction iteration method to obtain a scheduling decision plan; specifically, the following steps are performed: the minimum data read and write delay, the maximum channel bandwidth utilization and the minimum number of physical block erase times in the constrained optimization equation group are separated by convex functions and concave functions, respectively, and the non-convex objective function is expressed in the form of ▽f(x)-h(x), wherein f(x) is the convex function part, which represents the benefit function of resource utilization, h(x) is the concave function part, which represents the system overhead function, and x is the decision variable vector, to obtain the differential objective function; the differential objective function is combined with the physical block life constraint, the channel parallel constraint and the cache capacity constraint, and an augmented term in the form of λ∥Ax+By-c∥²+ρ / 2∥Ax+By-c∥² is constructed, wherein A is The address mapping matrix, B is the channel allocation matrix, c is the resource capacity vector, λ is the Lagrangian multiplier vector, ρ is the penalty factor, and y represents the channel allocation decision variable, and an augmented Lagrangian function is obtained; the augmented Lagrangian function is constructed by performing an x-minimization subproblem, fixing the variables y and λ, and obtaining a physical address allocation scheme by solving ▽f(x)-h(x)+λ(Ax+By-c)+ρ / 2∥Ax+By-c∥²=0, ▽f(x) represents the gradient vector of the convex function; based on the physical address allocation scheme, a y-minimization subproblem is constructed, and a channel task sequence is obtained by solving λ(Ax+By-c)+ρ / 2∥Ax+By-c∥²=0; the physical address allocation scheme and the channel task sequence are updated by λ, and the channel task sequence is updated by calculating λk+1=λk+ρ(Am k+1 +Bn k+1 -c), where k is the number of iterations, m is the number of iterations k+1 and n k+1 are the physical address allocation scheme and channel task sequence of the k+1th iteration, and obtain the multiplier update sequence; calculate the original residual and the dual residual according to the multiplier update sequence, and judge ∥Am k+1 +Bn k+1 -c∥≤ε and ρ∥A(m k+1 -m k )∥≤ε is true, where ε is the preset convergence threshold used to control the solution accuracy, m k The physical address allocation scheme of the kth iteration is expressed to obtain the convergence criterion; the solution satisfying the convergence criterion is processed, and a preliminary decision scheme is obtained by converting the continuous solutions m and n into discrete physical block number sequences, channel task number sequences and cache partition indexes respectively, and performing physical constraint verification; the feasibility of the preliminary decision scheme is optimized, and the decision variables that do not meet the constraints are locally adjusted by calculating the erase balance, channel load balance and cache space utilization of each physical block, so as to generate a scheduling decision scheme; According to the scheduling decision scheme, load balancing control is performed on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission to obtain real-time performance monitoring indicators.

2. The load collaborative scheduling method for solid state drives according to claim 1, characterized in that: The data collection on the solid state hard disk main controller to obtain the original characteristic data includes: A counting matrix is ​​constructed for the write operation execution status of each NAND flash memory cell in the solid-state drive, and each matrix element records the write count value, data block size and timestamp information of the corresponding physical block to obtain a physical block write status matrix; Based on the physical block write state matrix, the erase cycle count and valid data copy times of each NAND flash memory unit are counted, and the trigger threshold, execution time and completion status of each erase operation are recorded to obtain a physical block erase feature set; According to the physical block erasure feature set, parallel transmission task counting and bandwidth occupancy rate analysis are performed on each storage channel, and the data transmission rate, task queue length and blocking state of each channel are recorded to obtain a channel load feature set; Constructing a cache mapping table and performing access frequency statistics on the data blocks in the channel load feature set, recording the cache address, access count and life cycle of each data block, and obtaining a cache dynamic feature set; Sorting the data access records in the cache dynamic feature set, and performing type identification, data size and access mode analysis on each I / O request to obtain an I / O behavior feature set; Based on the I / O behavior feature set, a heat distribution scan is performed on the physical address space of the data block, and the data update frequency, access density and fragmentation degree of each physical address area are recorded to obtain an address distribution feature set; The physical block write state matrix, the physical block erase feature set, the channel load feature set, the cache dynamic feature set, the I / O behavior feature set and the address distribution feature set are integrated to generate original feature data.

3. The load collaborative scheduling method for solid state drives according to claim 1, characterized in that: The hierarchical processing is performed based on the load prediction result to obtain a hierarchical scheduling model, including: Performing hierarchical analysis on the storage channel load prediction value, cache space allocation prediction value and garbage collection time prediction value in the load prediction result to obtain hierarchical feature data; Dynamically reconstructing the address mapping mechanism of the flash translation layer according to the hierarchical feature data, by establishing a multi-level mapping table from logical address to physical address, each level of the mapping table containing an address conversion index, a data block status identifier and an update timestamp, to obtain an address mapping layer; Perform load balancing design on the data transmission of the storage channel according to the address mapping layer, and obtain the channel scheduling layer by dividing the channel priority levels, setting the task waiting queue length and calculating the channel idle time window; Dynamically partition the cache space based on the channel scheduling layer, and obtain a cache management layer by constructing the space allocation ratio of the hot data cache area, the pre-read data cache area, and the write buffer area; An inter-layer communication interface is constructed according to the address mapping layer, the channel scheduling layer and the cache management layer, and an inter-layer coordination mechanism is obtained by designing a data interaction protocol, defining a state synchronization mechanism and establishing a resource sharing strategy; The inter-layer coordination mechanism is input into the scheduling state machine, and the state transition model is obtained by defining the transition rules and trigger conditions of the idle state, working state and abnormal state. Hierarchical integration and timing planning are performed based on the state transition model, and a hierarchical scheduling model is generated by building a multi-level scheduling framework and designing a scheduling execution process.

4. The load collaborative scheduling method for solid state drives according to claim 3, characterized in that: The multi-objective optimization function is constructed based on the hierarchical scheduling model, and constraints are set on the physical block life threshold, the upper limit of the number of parallel channels, and the cache capacity boundary to obtain a constrained optimization equation group, including: Quantitatively analyzing the data read and write delay in the hierarchical scheduling model, and obtaining a delay optimization sub-function by calculating the response time, queuing waiting time and transmission completion time of data read and write requests; Performing data statistics on the channel bandwidth utilization in the hierarchical scheduling model, and obtaining a bandwidth optimization sub-function by calculating the data throughput, transmission efficiency and idle time ratio of each channel; Dynamically tracking the number of physical block erases in the hierarchical scheduling model, and obtaining an erase optimization sub-function by recording the cumulative number of erases, the erase interval time, and the remaining available number of each physical block; The delay optimization sub-function, the bandwidth optimization sub-function and the erasure optimization sub-function are linearly combined according to preset weights, and a penalty factor matrix is ​​constructed to weigh the objectives to obtain a multi-objective optimization function; Setting a physical block life constraint for the multi-objective optimization function, and obtaining a life constraint condition by limiting a maximum erasure count threshold, a minimum remaining life ratio, and a wear leveling coefficient for each physical block; Constructing channel parallel constraints according to the lifetime constraints, and obtaining parallel constraints by setting the maximum number of concurrent transmission tasks, the maximum bandwidth upper limit of a single channel, and the load balancing factor between channels; Setting a cache capacity constraint based on the parallel constraint condition, and obtaining a capacity constraint condition by dividing the hot data cache capacity upper limit, the pre-read cache space lower limit, and the write cache area protection threshold; The multi-objective optimization function is combined with the life constraint, the parallel constraint and the capacity constraint, and a constrained optimization equation group is established.

5. The load collaborative scheduling method for solid state drives according to claim 1, characterized in that: The data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission are load balanced controlled according to the scheduling decision scheme to obtain real-time performance monitoring indicators, including: Performing address mapping on write requests according to the physical block number sequence in the scheduling decision scheme, calculating the number of P / E cycles, the number of valid pages, the size of the remaining space, and the data update frequency of the physical blocks, and constructing a 4×N dimensional feature matrix, where N is the total number of physical blocks, to obtain an address allocation matrix; Write operations are distributed on the address allocation matrix, and a block allocation sequence is obtained by calculating the wear degree of each physical block M=α×(P / E cycle number)+β×(update frequency)+γ×(valid page ratio), where α, β, and γ are weight coefficients and satisfy α+β+γ=1, and M is the wear degree; A task scheduling queue is established based on the channel task number sequence in the scheduling decision scheme, and a channel state vector S=(Tc, Tr, Tw) is constructed by calculating the current task number Tc, data transmission rate Tr, and queue waiting time Tw of each channel to obtain a channel working state table; Parallel transmission control is performed according to the channel working status table, and the channel load balance degree B=max(Tc) / min(Tc)≤δ is calculated, where δ is a preset balance threshold, B is the channel load balance degree, max(Tc) represents the maximum value of the current number of tasks, and min(Tc) represents the minimum value of the current number of tasks, and data transmission tasks are dynamically allocated to obtain a parallel scheduling scheme; Mapping the cache partition index in the scheduling decision scheme to the physical cache space, and obtaining a cache space allocation table by constructing a cache mapping table T, where T(i,j) represents the storage location of the i-th data block in the j-th cache partition; Processing a read request for the cache space allocation table, and obtaining a cache scheduling sequence by calculating a data block access heat H=g×(access frequency)+μ×(temporal locality), where g, μ are heat weights and g+μ=1, and H represents the data block access heat; Based on the block allocation sequence, the parallel scheduling scheme and the cache scheduling sequence, load balancing control is performed, and data response time tr, channel bandwidth utilization ub and physical block erasure balance ep are recorded in each control cycle Δt to obtain a performance parameter set; A sliding window analysis is performed on the performance parameter set, with a window size of w control cycles, and real-time performance monitoring indicators are generated by calculating the mean variance of tr, the peak-to-valley ratio of ub, and the dispersion coefficient of ep.

6. A load coordination scheduling system for solid state drives, characterized in that: The system is used to execute the load collaborative scheduling method for a solid state drive according to any one of claims 1 to 5, comprising: The acquisition module is used to collect data from the main controller of the solid-state hard disk to obtain original characteristic data; A calculation module, used for inputting the original feature data into a Kolmogorov-Arnold neural network for nonlinear feature transformation and linear combination calculation to obtain a load prediction result; A processing module, used for performing hierarchical processing based on the load prediction result to obtain a hierarchical scheduling model; A construction module is used to construct a multi-objective optimization function based on the hierarchical scheduling model, and set constraints on the physical block life threshold, the upper limit of the number of parallel channels, and the cache capacity boundary to obtain a constrained optimization equation group; A solution module, used for performing convex difference function decomposition and augmented Lagrangian function construction on the constrained optimization equation group, solving the equation group through alternating direction iteration method to obtain a scheduling decision plan; The control module is used to perform load balancing control on data writing physical address allocation, data reading cache scheduling and multi-channel parallel transmission according to the scheduling decision scheme to obtain real-time performance monitoring indicators.

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