Method for manufacturing field effect transistor and field effect transistor

Abstract

The present application provides a method for manufacturing a field-effect transistor and a field-effect transistor. The manufacturing method forms a second conductive type semiconductor body region with different doping concentrations by ion implantation, without significantly increasing the manufacturing process and cost of the field-effect transistor. Due to the difference in doping concentration of the second conductive type semiconductor body region, the turn-on time between cells is different, which avoids the concentration of current and heat, enhances the thermal stability of the field-effect transistor, and increases the safe operating area. Compared with devices with virtual cells, its on-resistance is significantly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a manufacturing method of a field effect transistor and the field effect transistor. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems because of its advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and fast frequency response. In various high-electrical stress systems, on the one hand, power field-effect transistors are required to have lower conduction losses, and on the other hand, the devices are required to be able to operate for a longer time under high voltage and high current, that is, the devices must have high reliability and a large safe operating area (SOA). Based on the thermal instability of MOSFET, the greater the channel density, the easier it is for the parasitic transistors in the body to turn on, resulting in current concentration, causing the internal temperature of the device to rise, and causing the safe operating area (SOA) to shrink. In related technologies, a virtual cell structure is used to reduce the channel density, but this structure greatly increases the on-resistance, resulting in a waste of chip area.

[0003] Therefore, how to provide a manufacturing method that neither increases the on-resistance nor significantly increases the cost while expanding the safe operating area of ​​the field effect transistor is an urgent problem that needs to be solved. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a field effect transistor and a field effect transistor to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.

[0006] In a first aspect, the present application provides a method for manufacturing a field effect transistor, comprising:

[0007] Providing a substrate, the substrate comprising a front surface and a back surface disposed opposite to each other, and generating a first conductive type semiconductor drift region on the front surface of the substrate;

[0008] forming first trenches on both sides of the first conductive type semiconductor drift region, and forming a first oxide layer in the first trenches;

[0009] Depositing polysilicon on the first oxide layer to form a shielding gate polysilicon electrode;

[0010] Performing thermal oxidation growth or deposition on the shield gate polysilicon electrode to form a second oxide layer, wherein the first oxide layer and the second oxide layer partially wrap the shield gate polysilicon electrode;

[0011] Thermally oxidizing and growing the first conductive type semiconductor drift region located on the second oxide layer and then etching to form a curved surface structure, thermally oxidizing and growing the curved surface structure to form a third oxide layer, and depositing polysilicon on the second oxide layer to form a gate polysilicon electrode;

[0012] Performing ion implantation and push-in junction on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope;

[0013] Performing thermal oxidation growth on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region to form a first conductive type semiconductor source region;

[0014] Performing passivation on the gate polysilicon electrode, the first conductive type semiconductor source region, and the third oxide layer to form a gate-source dielectric layer;

[0015] Performing photolithography on a side of the gate-source dielectric layer away from the first conductive type semiconductor source region to form a second trench, and performing ion implantation on the second trench to form a second conductive type semiconductor ohmic contact region in the second conductive type semiconductor body region;

[0016] Depositing metal on the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region to form a source metal layer;

[0017] depositing metal on the back side of the substrate to form a drain metal layer;

[0018] The first oxide layer, the second oxide layer and the third oxide layer constitute an insulating dielectric layer.

[0019] In one embodiment of the present invention, a first trench is formed in the first conductive type semiconductor drift region, and a first oxide layer is formed in the first trench, including: setting a mask on the first conductive type semiconductor drift region, and exposing, developing and etching the first conductive type semiconductor drift region to obtain the first trench; and performing thermal oxidation growth on the first trench to form the first oxide layer.

[0020] In one embodiment of the present invention, ion implantation and push-in are performed on the side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope, including: performing oblique ion implantation on the first conductive type semiconductor drift region based on a preset angle to form an initial second conductive type semiconductor body region; and pushing-in is performed on the initial second conductive type semiconductor body region to form a second conductive type semiconductor body region with a slope.

[0021] In one embodiment of the present invention, ion implantation and push-up are performed on the side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope, including: opening a window on the first conductive type semiconductor drift region based on a mask to obtain an ion implantation window; implanting ions into the first conductive type semiconductor drift region based on the ion implantation window to form an initial second conductive type semiconductor body region; and pushing-up is performed on the initial second conductive type semiconductor body region to form a second conductive type semiconductor body region with a slope.

[0022] In one embodiment of the present invention, the ion implantation window includes a single window or multiple windows, and ions are implanted into the first conductive type semiconductor drift region based on the ion implantation window to form an initial second conductive type semiconductor body region, including: when the ion implantation window is a single window, ions are implanted into the first conductive type semiconductor drift region through the single window to obtain the initial second conductive type semiconductor body region; when the ion implantation window is multiple windows, ions are implanted into the first conductive type semiconductor drift region through the multiple windows to obtain the initial second conductive type semiconductor body region.

[0023] In a second aspect, the present application further provides a field effect transistor, which is manufactured according to the method for manufacturing a field effect transistor described in the first aspect, comprising:

[0024] A drain metal layer, and a substrate and a first conductive type semiconductor drift region sequentially stacked on the drain metal layer;

[0025] The first oxide layer is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the first oxide layers;

[0026] The shielding gate polysilicon electrode is arranged on a side of the first oxide layer facing away from the substrate;

[0027] The second oxide layer is disposed on a side of the shielding gate polysilicon electrode facing away from the substrate, wherein the second oxide layer covers the first oxide layer and the shielding gate polysilicon electrode, and a portion of the first conductive type semiconductor drift region is located between the second oxide layers;

[0028] The third oxide layer is disposed on a side of the second oxide layer facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the third oxide layers;

[0029] The gate polysilicon electrode is arranged on a side of the second oxide layer facing away from the substrate;

[0030] The second conductive type semiconductor body region is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate;

[0031] The second conductive type semiconductor ohmic contact region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region, wherein the second conductive type semiconductor ohmic contact region is located within the second conductive type semiconductor body region;

[0032] The first conductive type semiconductor source region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region;

[0033] The gate-source dielectric layer is provided on a side of the first conductive type semiconductor source region away from the first conductive type semiconductor source region, and the gate-source dielectric layer covers the gate polysilicon electrode, the third oxide layer, and the first conductive type semiconductor source region;

[0034] The source metal layer is arranged on a side of the second conductive type semiconductor ohmic contact region away from the second conductive type semiconductor body region, and the source metal layer covers the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region.

[0035] In one embodiment of the present invention, the shielding gate polysilicon electrode is isolated from the first conductive type semiconductor drift region by the first oxide layer in the horizontal direction; the gate polysilicon electrode is isolated from part of the first conductive type semiconductor drift region, part of the second conductive type semiconductor body region and the first conductive type semiconductor source region by the third oxide layer, wherein the horizontal direction is a direction parallel to the drain metal layer.

[0036] In one embodiment of the present invention, a contact surface between the second conductive type semiconductor body region and the first conductive type semiconductor drift region has a slope, and a doping concentration of the second conductive type semiconductor body region decreases as its volume decreases.

[0037] In a third aspect, the present application further provides a method for manufacturing a field effect transistor, comprising:

[0038] Providing a substrate, the substrate comprising a front surface and a back surface disposed opposite to each other, and generating a first conductive type semiconductor drift region on the front surface of the substrate;

[0039] forming a third trench having a curved surface structure in the first conductive type semiconductor drift region, and forming an insulating dielectric layer in the third trench;

[0040] Depositing polysilicon on the insulating dielectric layer to form a gate polysilicon electrode;

[0041] Performing ion implantation and push-in junction on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope;

[0042] Performing thermal oxidation growth on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region to form a first conductive type semiconductor source region;

[0043] Performing passivation on the gate polysilicon electrode, the first conductive type semiconductor source region and a portion of the insulating dielectric layer to form a gate-source dielectric layer;

[0044] Performing photolithography on a side of the gate-source dielectric layer away from the first conductive type semiconductor source region to form a second trench, and performing ion implantation on the second trench to form a second conductive type semiconductor ohmic contact region in the second conductive type semiconductor body region;

[0045] Depositing metal on the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region to form a source metal layer;

[0046] Metal is deposited on the back side of the substrate to form a drain metal layer.

[0047] In a fourth aspect, the present application further provides a field effect transistor, which is manufactured according to the method for manufacturing the field effect transistor described in the third aspect, comprising:

[0048] A drain metal layer, and a substrate and a first conductive type semiconductor drift region sequentially stacked on the drain metal layer;

[0049] The insulating dielectric layer is provided on a side of the first conductive type semiconductor drift region facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the insulating dielectric layers;

[0050] The gate polysilicon electrode is provided on a side of the insulating dielectric layer facing away from the substrate;

[0051] The second conductive type semiconductor body region is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate;

[0052] The second conductive type semiconductor ohmic contact region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region, wherein the second conductive type semiconductor ohmic contact region is located within the second conductive type semiconductor body region;

[0053] The first conductive type semiconductor source region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region;

[0054] The gate-source dielectric layer is provided on a side of the first conductive type semiconductor source region away from the first conductive type semiconductor source region, and the gate-source dielectric layer covers the gate polysilicon electrode, the insulating dielectric layer, and the first conductive type semiconductor source region;

[0055] The source metal layer is arranged on a side of the second conductive type semiconductor ohmic contact region away from the second conductive type semiconductor body region, and the source metal layer covers the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region.

[0056] The present application provides a method for manufacturing a field-effect transistor and a field-effect transistor. The manufacturing method forms a second conductive type semiconductor body region with different doping concentrations by ion implantation, without significantly increasing the manufacturing process and cost of the field-effect transistor. Due to the difference in doping concentration of the second conductive type semiconductor body region, the turn-on time between cells is different, which avoids the concentration of current and heat, enhances the thermal stability of the field-effect transistor, and increases the safe operating area. Compared with devices with virtual cells, its on-resistance is significantly reduced.

[0057] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that a person skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0059] Figure 1 A flow chart of a method for manufacturing a field effect transistor according to an exemplary embodiment of the present invention is shown;

[0060] Figures 2 to 15 A schematic cross-sectional view illustrating a method for manufacturing a field effect transistor according to an exemplary embodiment of the present invention;

[0061] Figure 16 A flow chart of a method for manufacturing a field effect transistor according to another exemplary embodiment of the present invention;

[0062] Figure 17 A schematic cross-sectional view of a field effect transistor is shown according to another exemplary embodiment of the present invention.

[0063] Explanation of the figure marks: 1-drain metal layer; 2-substrate; 3-first conductive type semiconductor drift region; 4-second conductive type semiconductor body region; 4a-first second conductive type semiconductor body region; 4b-second second conductive type semiconductor body region; 4z-initial second conductive type semiconductor body region; 5-second conductive type semiconductor ohmic contact region; 6-first conductive type semiconductor source region; 7-gate polysilicon electrode; 8-shielding gate polysilicon electrode; 9-insulating dielectric layer; 9a-first oxide layer; 9b-second oxide layer; 9c-third oxide layer; 10-gate-source dielectric layer; 11-source metal layer. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0065] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0066] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0067] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is widely used in various power systems due to its advantages such as fast switching speed, low power consumption, easy gate drive, low drive power, high input impedance and fast frequency response. In various high-stress systems, on the one hand, power MOSFETs are required to have lower conduction losses, and on the other hand, the devices are required to be able to operate for a longer time under high voltage and high current, that is, the devices must have high reliability and a large safe operating area (SOA). According to the thermal instability of MOSFET, the greater the channel density, the easier it is for the parasitic transistors in the body to turn on, resulting in current concentration, causing the internal temperature of the device to rise, and causing the safe operating area (SOA) to shrink. In related technologies, a virtual cell structure is used to reduce the channel density, but this structure greatly increases the on-resistance, resulting in a waste of chip area.

[0068] First, as Figure 1 As shown, the present application provides a method for manufacturing a field effect transistor, which at least includes steps S110 to S211.

[0069] S110 , providing a substrate 2 , the substrate 2 including a front surface and a back surface opposite to each other, and forming a first conductive type semiconductor drift region 3 on the front surface of the substrate 2 ;

[0070] S120, forming first trenches on both sides of the first conductivity type semiconductor drift region 3, and forming first oxide layers 9a in the first trenches;

[0071] S130, depositing polysilicon on the first oxide layer 9a to form a shield gate polysilicon electrode 8;

[0072] S140, performing thermal oxidation growth or deposition on the shield gate polysilicon electrode 8 to form a second oxide layer 9b, wherein the first oxide layer 9a and the second oxide layer 9b partially wrap the shield gate polysilicon electrode 8;

[0073] S150, thermally oxidizing and growing the first conductive type semiconductor drift region 3 located on the second oxide layer 9b and then etching to form a curved surface structure, thermally oxidizing and growing the third oxide layer 9c on the curved surface structure, and depositing polysilicon on the second oxide layer 9b to form a gate polysilicon electrode 7;

[0074] S160 , performing ion implantation and push-in junction on a side of the first conductive type semiconductor drift region 3 facing away from the substrate 2 to form a second conductive type semiconductor body region 4 having a slope;

[0075] S170 , performing partitioned ion implantation and push-in junction on a side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3 to form a first conductive type semiconductor source region 6 ;

[0076] S180, performing passivation on the gate polysilicon electrode 7, the first conductive type semiconductor source region 6 and the third oxide layer 9c to form a gate-source dielectric layer 10;

[0077] S190 , performing photolithography on a side of the gate-source dielectric layer 10 away from the first conductive type semiconductor source region 6 to form a second trench, and performing ion implantation on the second trench to form a second conductive type semiconductor ohmic contact region 5 in the second conductive type semiconductor body region 4 ;

[0078] S210 , depositing metal on the gate-source dielectric layer 10 and the second conductive type semiconductor ohmic contact region 5 to form a source metal layer 11 ;

[0079] S211, depositing metal on the back side of the substrate 2 to form a drain metal layer 1;

[0080] The first oxide layer 9 a , the second oxide layer 9 b and the third oxide layer 9 c constitute the insulating dielectric layer 9 .

[0081] It should be noted that the substrate 2 is a heavily doped first conductivity type semiconductor, and the second conductivity type semiconductor ohmic contact region 5 is also heavily doped.

[0082] Specifically, if Figure 2 As shown, in step S110 , a substrate 2 is provided, and a single crystal material is grown on the front surface of the substrate 2 to form a first conductive type semiconductor drift region 3 .

[0083] Specifically, in step S120, first trenches are formed on both sides of the first conductive type semiconductor drift region 3, and a first oxide layer 9a is formed in the first trenches, including: setting a mask on the first conductive type semiconductor drift region 3, exposing, developing and etching the first conductive type semiconductor drift region 3 to obtain the first trenches, and performing thermal oxidation growth or deposition on the first trenches to form the first oxide layer 9a. Specifically, as Figure 3 As shown, a mask is set on the first conductive type semiconductor drift region 3, the first conductive type semiconductor drift region 3 provided with the mask layer is exposed and developed, the position of the first trench is determined, and the first conductive type semiconductor drift region 3 is etched to form the first trench. Because the semiconductor device is manufactured, the operation is performed on the entire substrate. Therefore, a substrate includes multiple field effect transistors, and the first trenches of two adjacent field effect transistors are adjacent. The first trench is located in the first conductive type semiconductor drift region 3, and then the first trench is thermally oxidized to form a first oxide layer 9a on the sidewall and bottom of the first trench.

[0084] Specifically, if Figure 4 As shown, in step S130, polysilicon is deposited on the first oxide layer 9a. If there is excess polysilicon deposition, the excess polysilicon material inside and outside the first trench is etched to form a shield gate polysilicon electrode 8 on the first oxide layer 9a.

[0085] Specifically, if Figure 5 As shown, in step S140, the first oxide layer 9a located on the shield gate polysilicon electrode 8 in the first trench is etched, and a second oxide layer 9b is formed on the shield gate polysilicon electrode 8 by thermal oxidation growth or deposition. The first oxide layer 9a and the second oxide layer 9b are used to wrap a portion of the shield gate polysilicon electrode 8. Because two adjacent field effect transistors are in contact with each other, the first oxide layer 9a and the second oxide layer 9b can completely wrap the shield gate polysilicon electrode 8.

[0086] Specifically, if Figure 6 As shown, in step S150, the first conductive type semiconductor drift region 3 located on the second oxide layer 9b is first thermally oxidized to form a sacrificial oxide layer, and then the sacrificial oxide layer is etched to form an arc surface structure, so that the side wall of the first trench located on the second oxide layer 9b is etched toward the first conductive type semiconductor drift region 3, so that the side wall of the first trench located on the second oxide layer 9b has an arc surface structure, thermal oxidation growth is performed on the arc surface structure to form a third oxide layer 9c, polysilicon is deposited on the second oxide layer 9b, and excess polysilicon is etched back to form a gate polysilicon electrode 7, and the second oxide layer 9b and the third oxide layer 9c wrap part of the gate polysilicon electrode 7.

[0087] Specifically, if Figure 7-12 As shown, in step S160, ion implantation and push-in junction are performed on the first conductive type semiconductor drift region 3 located between the third oxide layer 9c on the side of the first conductive type semiconductor drift region 3 facing away from the substrate 2, and a second conductive type semiconductor body region 4 with a slope is formed on the first conductive type semiconductor drift region 3.

[0088] Specifically, ion implantation and push-up are performed on the side of the first conductive type semiconductor drift region 3 facing away from the substrate 2 to form a second conductive type semiconductor body region 4 with a slope, including: performing oblique ion implantation on the first conductive type semiconductor drift region 3 based on a preset angle to form an initial second conductive type semiconductor body region 4z; and push-up is performed on the initial second conductive type semiconductor body region 4z to form a second conductive type semiconductor body region 4 with a slope. Specifically, as Figure 7As shown, ion implantation is performed on the side of the first conductive type semiconductor drift region 3 facing away from the substrate 2. The angle of the ion implantation is a preset angle with the first conductive type semiconductor drift region 3. An initial second conductive type semiconductor body region 4z is formed in the first conductive type semiconductor drift region 3. Then, push-joining is performed to obtain a second conductive type semiconductor region 4 with a slope.

[0089] Specifically, ion implantation and push-up are performed on a side of the first-conductivity-type semiconductor drift region 3 facing away from the substrate 2 to form a second-conductivity-type semiconductor body region 4 having a slope. The process includes: creating a window in the first-conductivity-type semiconductor drift region 3 using a mask to obtain an ion implantation window; implanting ions into the first-conductivity-type semiconductor drift region 3 based on the ion implantation window to form an initial second-conductivity-type semiconductor body region 4z; and push-up is performed on the initial second-conductivity-type semiconductor body region 4z to form a second-conductivity-type semiconductor body region 4 having a slope. The region formed by ion implantation using the mask is the initial second-conductivity-type semiconductor body region 4z.

[0090] In more detail, the ion implantation window includes a single window or multiple windows, and ions are implanted into the first conductive type semiconductor drift region 3 based on the ion implantation window to form an initial second conductive type semiconductor body region 4z, including: when the ion implantation window is a single window, ions are implanted into the first conductive type semiconductor drift region 3 through a single window to obtain an initial second conductive type semiconductor body region 4z; when the ion implantation window is multiple windows, ions are implanted into the first conductive type semiconductor drift region 3 through multiple windows to obtain an initial second conductive type semiconductor body region 4z.

[0091] The single window ion implantation method is as follows: ① Ions are implanted into the first conductive type semiconductor drift region 3 through a single ion implantation window to form an initial second conductive type semiconductor body region 4z in the first conductive type semiconductor drift region 3. ② First, low-doping concentration second conductive type impurities are implanted into the first conductive type semiconductor drift region 3, and then high-doping concentration second conductive type impurities are implanted into one side of the first conductive type semiconductor drift region 3 through a single window to form an initial second conductive type semiconductor body region 4z. ③ As Figure 8-9 As shown, the first conductive type semiconductor drift region 3 is respectively injected with second conductive type impurities of different doping concentrations through a single window mask with two opening positions coordinated with each other to obtain an initial second conductive type semiconductor body region 4z, wherein the two opening positions are coordinated with each other as follows: the openings of the two masks do not overlap and are relatively positioned. For example, the window position of the first mask is a partial area above the left side of the first conductive type semiconductor drift region 3, and the window position of the second mask is a partial area above the right side of the first conductive type semiconductor drift region 3.

[0092] Specifically, if Figure 10 As shown, three windows of different sizes are set on the mask, and the first conductive type semiconductor drift region 3 is opened to form three ion implantation windows. Ions are implanted into the first conductive type semiconductor drift region 3 through the three ion implantation windows, as shown in FIG. Figure 11 As shown, three initial second conductive type semiconductor body regions 4z of different sizes are formed in the first conductive type semiconductor drift region 3, and the three initial second conductive type semiconductor body regions 4z of different sizes are subjected to push-junction, as shown in FIG. Figure 12 As shown, a second conductive type semiconductor body region 4 (4a and 4b) with a slope is formed in the first conductive type semiconductor drift region 3. The number, size and position of the ion implantation windows can be set according to actual conditions and are not limited thereto.

[0093] It should be noted that if Figure 12 As shown, in order to accurately express the doping concentration of the second conductive type semiconductor body region 4, the second conductive type semiconductor body region 4 is divided into two parts. The doping concentration of the first second conductive type semiconductor body region 4a formed in the area with a large ion implantation window is greater than that of the second second conductive type semiconductor body region 4b formed in the area with a small ion implantation window. Figure 10 As shown, when the ion injection window decreases from left to right, as shown in Figure 12 As shown, the first second conductivity type semiconductor body region 4a located on the left side is heavily doped, and the second second conductivity type semiconductor body region 4b located on the right side is lightly doped.

[0094] In detail, in step S170, Figure 13 As shown, partitioned ion implantation and push-in junction are performed on the side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3 to form a first conductive type semiconductor source region 6 on the second conductive type semiconductor body region 4 .

[0095] Specifically, if Figure 14 As shown, in step S180, the surfaces of the gate polysilicon electrode 7, the first conductive type semiconductor source region 6 and the third oxide layer 9c are passivated to form a gate-source dielectric layer 10; in step S190, photolithography is performed on the side of the gate-source dielectric layer 10 away from the first conductive type semiconductor source region 6 to form a second trench between the first conductive type semiconductor source regions 6, and ion implantation is performed in the second trench, as shown in FIG. Figure 14 As shown, a second conductive type semiconductor ohmic contact region 5 is formed in the second conductive type semiconductor body region 4 .

[0096] Specifically, if Figure 15As shown, in step S210, metal is deposited on the gate-source dielectric layer 10 and the second conductive type semiconductor ohmic contact region 5, and then the excess deposited metal layer is photoetched to form a source metal layer 11; in step S211, the back of the substrate 2 is first thinned, and then metal is deposited on the back of the thinned substrate 2 to form a drain metal layer 1.

[0097] Second, as Figure 15 As shown, the present application further provides a field effect transistor, which is manufactured based on the method for manufacturing a field effect transistor provided in the first aspect, comprising:

[0098] A drain metal layer 1, a substrate 2 and a first conductive type semiconductor drift region 3 sequentially stacked on the drain metal layer 1;

[0099] A first oxide layer 9 a is provided on a side of the first conductive type semiconductor drift region 3 facing away from the substrate 2 , wherein a portion of the first conductive type semiconductor drift region 3 is located between the first oxide layers 9 a ;

[0100] a shield gate polysilicon electrode 8, which is disposed on a side of the first oxide layer 9a facing away from the substrate 2;

[0101] a second oxide layer 9 b disposed on a side of the shielding gate polysilicon electrode 8 facing away from the substrate 2 , wherein the second oxide layer 9 b covers the first oxide layer 9 a and the shielding gate polysilicon electrode 8 , and a portion of the first conductivity type semiconductor drift region 3 is located between the second oxide layers 9 b ;

[0102] A third oxide layer 9c is provided on a side of the second oxide layer 9b facing away from the substrate 2, wherein a portion of the first conductive type semiconductor drift region 3 is located between the third oxide layers 9c;

[0103] a gate polysilicon electrode 7, which is arranged on a side of the second oxide layer 9b facing away from the substrate 2;

[0104] a second conductive type semiconductor body region 4, which is arranged on a side of the first conductive type semiconductor drift region 3 facing away from the substrate 2;

[0105] a second conductive type semiconductor ohmic contact region 5, which is arranged on a side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3, wherein the second conductive type semiconductor ohmic contact region 5 is located within the second conductive type semiconductor body region 4;

[0106] a first conductive type semiconductor source region 6 , which is arranged on a side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3 ;

[0107] a gate-source dielectric layer 10, which is disposed on a side of the first conductive type semiconductor source region 6 away from the second conductive type semiconductor body region 4, and the gate-source dielectric layer 10 covers the gate polysilicon electrode 7, the third oxide layer 9c, and the first conductive type semiconductor source region 6;

[0108] The source metal layer 11 is disposed on a side of the second conductive type semiconductor ohmic contact region 5 away from the second conductive type semiconductor body region 4 , and the source metal layer 11 covers the gate-source dielectric layer 10 and the second conductive type semiconductor ohmic contact region 5 .

[0109] In detail, such as Figure 14 As shown, the shielding gate polysilicon electrode 8 is isolated from the first conductive type semiconductor drift region 3 by the first oxide layer 9a in the horizontal direction; the gate polysilicon electrode 7 is isolated from the first conductive type semiconductor drift region 3, the second conductive type semiconductor body region 4, the second conductive type semiconductor ohmic contact region 5 and the first conductive type semiconductor source region 6 by the third oxide layer 9c, wherein the horizontal direction is the direction parallel to the drain metal layer 1.

[0110] In more detail, Figure 14 As shown, the contact surface between the second conductive type semiconductor body region 4 and the first conductive type semiconductor drift region 3 has a slope, and the doping concentration of the second conductive type semiconductor body region 4 decreases as its volume decreases.

[0111] It should be emphasized that the doping concentration of the heavily doped region of the field effect transistor provided in this application is greater than 1e18 cm -3 , the doping concentration in the lightly doped region is less than 1e17 cm -3 The first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor, and the semiconductor material is silicon or silicon carbide.

[0112] like Figure 14 As shown, the second conductive type semiconductor body region 4 is divided into two parts. According to the volume relationship, the first second conductive type semiconductor body region 4a is heavily doped, and the second second conductive type semiconductor body region 4b is lightly doped. When the field effect transistor is turned on, on the side of the heavily doped first second conductive type semiconductor body region 4a, as the dosage of the second conductive type semiconductor in the body region increases, the source region gradually reduces the voltage and the voltage drops, so that the voltage drop between the second conductive type semiconductor body regions 4 with different doping concentrations and the first conductive type semiconductor source region 6 does not exceed 0.7V, thereby effectively suppressing the turning on of the parasitic transistor of the field effect transistor, enhancing the thermal instability resistance of the field effect transistor, and obtaining a larger safe working area.

[0113] It should be noted that the field effect transistor may not need the shield gate polysilicon electrode 8, and the trench and planar gate field effect transistors are also applicable.

[0114] Thirdly, as Figure 16 As shown, the present application also provides a method for manufacturing a field effect transistor, comprising:

[0115] S1601, providing a substrate 2, the substrate 2 including a front surface and a back surface opposite to each other, and forming a first conductive type semiconductor drift region 3 on the front surface of the substrate 2;

[0116] S1602, forming third trenches with arc surface structures on both sides of the first conductive type semiconductor drift region 3, and forming an insulating dielectric layer 9 in the third trenches;

[0117] S1603, depositing polysilicon on the insulating dielectric layer 9 to form a gate polysilicon electrode 7;

[0118] S1604, performing ion implantation and push-in junction on the side of the first conductive type semiconductor drift region 3 facing away from the substrate 2 to form a second conductive type semiconductor body region 4 with a slope;

[0119] S1605: performing partitioned ion implantation and push-in junction on the side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3 to form a first conductive type semiconductor source region;

[0120] S1606, performing passivation on the gate polysilicon electrode 7, the first conductive type semiconductor source region 6 and a portion of the insulating dielectric layer 9 to form a gate-source dielectric layer 10;

[0121] S1607 , performing photolithography on a side of the inter-gate-source dielectric layer 10 facing away from the inter-gate-source dielectric layer 10 to form a second trench, and performing ion implantation into the second trench to form a second conductive type semiconductor ohmic contact region 5 in the second conductive type semiconductor body region 4 ;

[0122] S1608 , depositing metal on the gate-source dielectric layer 10 and the second conductive type semiconductor ohmic contact region 5 to form a source metal layer 11 ;

[0123] S1609 , depositing metal on the back side of the substrate 2 to form a drain metal layer 1 .

[0124] It should be noted that the position of the third trench is the same as that of the first trench. Since the third trench does not include the shield gate polysilicon electrode 8 , the depth of the third trench is smaller than that of the first trench.

[0125] Fourthly, Figure 17As shown, the present application further provides a field effect transistor, which is manufactured based on the method for manufacturing a field effect transistor provided in the third aspect, comprising:

[0126] A drain metal layer 1, a substrate 2 and a first conductive type semiconductor drift region 3 sequentially stacked on the drain metal layer 1;

[0127] an insulating dielectric layer 9 disposed on a side of the first conductive type semiconductor drift region 3 facing away from the substrate 2 , wherein a portion of the first conductive type semiconductor drift region 3 is located between the insulating dielectric layers 9 ;

[0128] a gate polysilicon electrode 7, which is disposed on a side of the insulating dielectric layer 9 facing away from the substrate 2;

[0129] a second conductive type semiconductor body region 4, which is arranged on a side of the first conductive type semiconductor drift region 3 facing away from the substrate 2;

[0130] a second conductive type semiconductor ohmic contact region 5, which is arranged on a side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3, wherein the second conductive type semiconductor ohmic contact region 5 is located within the second conductive type semiconductor body region 4;

[0131] a first conductive type semiconductor source region 6 , which is arranged on a side of the second conductive type semiconductor body region 4 away from the first conductive type semiconductor drift region 3 ;

[0132] a gate-source dielectric layer 10, which is disposed on a side of the first conductive type semiconductor source region 6 facing away from the first conductive type semiconductor source region 6, and the gate-source dielectric layer 10 covers the gate polysilicon electrode 7, the insulating dielectric layer 9, and the first conductive type semiconductor source region 6;

[0133] The source metal layer 11 is disposed on a side of the second conductive type semiconductor ohmic contact region 5 away from the second conductive type semiconductor body region 4 , and the source metal layer 11 covers the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region 5 .

[0134] The present application provides a method for manufacturing a field-effect transistor and a field-effect transistor. The manufacturing method forms a second conductive type semiconductor body region with different doping concentrations by ion implantation, without significantly increasing the manufacturing process and cost of the field-effect transistor. Due to the difference in doping concentration of the second conductive type semiconductor body region, the turn-on time between cells is different, which avoids the concentration of current and heat, enhances the thermal stability of the field-effect transistor, and increases the safe operating area. Compared with devices with virtual cells, its on-resistance is significantly reduced.

[0135] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a field effect transistor, characterized in that: include: Providing a substrate, the substrate comprising a front surface and a back surface disposed opposite to each other, and generating a first conductive type semiconductor drift region on the front surface of the substrate; forming first trenches on both sides of the first conductive type semiconductor drift region, and forming a first oxide layer in the first trenches; Depositing polysilicon on the first oxide layer to form a shielding gate polysilicon electrode; Performing thermal oxidation growth or deposition on the shield gate polysilicon electrode to form a second oxide layer, wherein the first oxide layer and the second oxide layer partially wrap the shield gate polysilicon electrode; Performing thermal oxidation growth and then etching on the first conductive type semiconductor drift region located on the second oxide layer to form a curved surface structure, performing thermal oxidation growth on the curved surface structure to form a third oxide layer, and depositing polysilicon on the second oxide layer to form a gate polysilicon electrode; Performing ion implantation and push-in junction on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope; Performing thermal oxidation growth on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region to form a first conductive type semiconductor source region; Performing passivation on the gate polysilicon electrode, the first conductive type semiconductor source region, and the third oxide layer to form a gate-source dielectric layer; Performing photolithography on a side of the gate-source dielectric layer away from the first conductive type semiconductor source region to form a second trench, and performing ion implantation on the second trench to form a second conductive type semiconductor ohmic contact region in the second conductive type semiconductor body region; Depositing metal on the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region to form a source metal layer; depositing metal on the back side of the substrate to form a drain metal layer; The first oxide layer, the second oxide layer and the third oxide layer constitute an insulating dielectric layer.

2. The method for manufacturing a field effect transistor according to claim 1, wherein: Forming a first trench in the first conductive type semiconductor drift region and forming a first oxide layer in the first trench, comprising: Disposing a mask on the first conductive type semiconductor drift region, and exposing, developing, and etching the first conductive type semiconductor drift region to obtain the first trench; Thermal oxidation growth is performed on the first trench to form the first oxide layer.

3. The method for manufacturing a field effect transistor according to claim 2, wherein: Ion implantation and push-in junction are performed on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope, comprising: Performing oblique ion implantation on the first conductive type semiconductor drift region based on a preset angle to form an initial second conductive type semiconductor body region; The initial second conductive type semiconductor body region is pushed up to form the second conductive type semiconductor body region with a slope.

4. The method for manufacturing a field effect transistor according to claim 3, wherein: Ion implantation and push-in junction are performed on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope, comprising: Opening a window on the first conductive type semiconductor drift region based on a mask to obtain an ion implantation window; Performing ion implantation on the first conductive type semiconductor drift region based on the ion implantation window to form an initial second conductive type semiconductor body region; The initial second conductive type semiconductor body region is pushed up to form the second conductive type semiconductor body region with a slope.

5. The method for manufacturing a field effect transistor according to claim 4, wherein: The ion implantation window includes a single window or a plurality of windows, and ion implantation is performed on the first conductive type semiconductor drift region based on the ion implantation window to form an initial second conductive type semiconductor body region, including: When the ion implantation window is a single window, ion implantation is performed on the first conductive type semiconductor drift region through the single window to obtain an initial second conductive type semiconductor body region; When the ion implantation window is a plurality of windows, ions are implanted into the first conductive type semiconductor drift region through the plurality of windows to obtain an initial second conductive type semiconductor body region.

6. A field effect transistor, characterized in that: The field effect transistor is manufactured based on the method for manufacturing a field effect transistor according to any one of claims 1 to 5, comprising: A drain metal layer, and a substrate and a first conductive type semiconductor drift region sequentially stacked on the drain metal layer; The first oxide layer is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the first oxide layers; The shielding gate polysilicon electrode is arranged on a side of the first oxide layer facing away from the substrate; The second oxide layer is disposed on a side of the shielding gate polysilicon electrode facing away from the substrate, wherein the second oxide layer covers the first oxide layer and the shielding gate polysilicon electrode, and a portion of the first conductive type semiconductor drift region is located between the second oxide layers; The third oxide layer is disposed on a side of the second oxide layer facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the third oxide layers; The gate polysilicon electrode is arranged on a side of the second oxide layer facing away from the substrate; The second conductive type semiconductor body region is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate; The second conductive type semiconductor ohmic contact region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region, wherein the second conductive type semiconductor ohmic contact region is located within two second conductive type semiconductor body regions; The first conductive type semiconductor source region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region; The gate-source dielectric layer is provided on a side of the first conductive type semiconductor source region away from the first conductive type semiconductor source region, and the gate-source dielectric layer covers the gate polysilicon electrode, the third oxide layer, and the first conductive type semiconductor source region; The source metal layer is arranged on a side of the second conductive type semiconductor ohmic contact region away from the second conductive type semiconductor body region, and the source metal layer covers the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region.

7. The field effect transistor according to claim 6, characterized in that The shielding gate polysilicon electrode is isolated from the first conductive type semiconductor drift region by the first oxide layer in the horizontal direction; the gate polysilicon electrode is isolated from part of the first conductive type semiconductor drift region, part of the second conductive type semiconductor body region and the first conductive type semiconductor source region by the third oxide layer, wherein the horizontal direction is a direction parallel to the drain metal layer.

8. The field effect transistor according to claim 6, wherein: A contact surface between the second conductive type semiconductor body region and the first conductive type semiconductor drift region has a slope, and a doping concentration of the second conductive type semiconductor body region decreases as its volume decreases.

9. A method for manufacturing a field effect transistor, characterized in that: include: Providing a substrate, the substrate comprising a front surface and a back surface disposed opposite to each other, and generating a first conductive type semiconductor drift region on the front surface of the substrate; forming third trenches having a curved surface structure on both sides of the first conductive type semiconductor drift region, and forming an insulating dielectric layer in the third trenches; Depositing polysilicon on the insulating dielectric layer to form a gate polysilicon electrode; Performing ion implantation and push-in junction on a side of the first conductive type semiconductor drift region facing away from the substrate to form a second conductive type semiconductor body region with a slope; Performing thermal oxidation growth on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region to form a first conductive type semiconductor source region; Performing passivation on the gate polysilicon electrode, the first conductive type semiconductor source region and a portion of the insulating dielectric layer to form a gate-source dielectric layer; Performing photolithography on a side of the gate-source dielectric layer away from the first conductive type semiconductor source region to form a second trench, and performing ion implantation on the second trench to form a second conductive type semiconductor ohmic contact region in the second conductive type semiconductor body region; Depositing metal on the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region to form a source metal layer; Metal is deposited on the back side of the substrate to form a drain metal layer.

10. A field effect transistor manufactured based on the method for manufacturing a field effect transistor according to claim 9, characterized in that: include: A drain metal layer, and a substrate and a first conductive type semiconductor drift region sequentially stacked on the drain metal layer; The insulating dielectric layer is provided on a side of the first conductive type semiconductor drift region facing away from the substrate, wherein a portion of the first conductive type semiconductor drift region is located between the insulating dielectric layers; The gate polysilicon electrode is provided on a side of the insulating dielectric layer facing away from the substrate; The second conductive type semiconductor body region is disposed on a side of the first conductive type semiconductor drift region facing away from the substrate; The second conductive type semiconductor ohmic contact region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region, wherein the second conductive type semiconductor ohmic contact region is located within the second conductive type semiconductor body region; The first conductive type semiconductor source region is arranged on a side of the second conductive type semiconductor body region away from the first conductive type semiconductor drift region; The gate-source dielectric layer is provided on a side of the first conductive type semiconductor source region away from the first conductive type semiconductor source region, and the gate-source dielectric layer covers the gate polysilicon electrode, the insulating dielectric layer, and the first conductive type semiconductor source region; The source metal layer is arranged on a side of the second conductive type semiconductor ohmic contact region away from the second conductive type semiconductor body region, and the source metal layer covers the gate-source dielectric layer and the second conductive type semiconductor ohmic contact region.

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