A wcet analysis method and device for embedded multithreaded programs

Abstract

The application relates to the field of embedded technology, in particular to a WCET analysis method and device for an embedded multithreaded program. The method comprises the following steps: recognizing synchronization operations in a multithreaded program under the POSIX thread standard, recording lock-related operation statements, generating an extended parallel program control flow graph to describe synchronization dependency relationships among threads, calculating WCST of a program caused by thread application of critical resources based on the principle of mutual exclusion access of critical resource under lock protection, determining a parallel section in which a program section runs on other cores as an interference set according to the control flow graph of the parallel program, and performing conflict analysis on a shared instruction cache through an abstract interpretation method, and inputting the analysis result into a WCET calculation method IPET as a parameter to obtain a WCET analysis result of the entire parallel program.

Description

Technical Field

[0001] The present application relates to the field of embedded technology, and in particular to a WCET analysis method and device for embedded multi-threaded programs. Background Art

[0002] In real-time systems, the worst-case execution time (WCET) is an important performance evaluation metric that ensures that tasks are reliably executed within the specified time limits. The WCET estimate must possess two properties:

[0003] (1) Safety: This means it should be greater than or equal to any possible execution time;

[0004] (2) Strictness: that is, as close to the actual worst-case execution time as possible.

[0005] To improve the accuracy of WCET analysis, task behavior under specific hardware architectures must be considered. In these architectures, cache has a significant impact on program execution time. Predicting cache hits and misses can result in instruction execution times that differ by nearly a hundred clock cycles. Therefore, the accuracy of cache analysis is crucial to task execution time estimation.

[0006] Due to their high processing efficiency, multi-core processors are becoming increasingly common in real-time operating systems. Although multi-core processors improve performance by allowing multiple tasks to run simultaneously on different cores, they cannot shorten the execution time of a single task and therefore cannot help meet the deadline requirements of real-time applications. To shorten runtime, an effective method is to parallelize the application code, but this also introduces complex synchronization relationships between threads. In existing methods for WCET analysis of multi-core platforms, tasks executed on different cores are often considered independent, and the impact of inter-thread synchronization on the WCET of multi-threaded programs is not considered, which limits the analysis scenarios of tasks.

[0007] At the same time, in multi-core processors, the last-level cache is usually shared by all processing cores, which means that the content of the shared cache depends not only on the task executed on a single core, but also on other tasks executed in parallel.

[0008] In addition, multi-threaded programs usually involve synchronization mechanisms, and the complex partial order relationship between threads makes it more difficult to determine which instructions of different cores will compete for the same cache set. Existing methods usually assume that each instruction in the analyzed thread may compete for shared resources with the entire thread area in the competing thread, which will lead to overly pessimistic WCET analysis results. Summary of the Invention

[0009] To solve the above problems, the application provides a WCET analysis method and device for an embedded multithreaded program.

[0010] Embodiments of the application are implemented as follows:

[0011] In a first aspect, the application provides a WCET analysis method for an embedded multithreaded program, comprising:

[0012] Identify synchronization operations in the multithreaded program under the POSIX thread standard, record lock-related operation statements, generate an extended parallel program control flow graph to describe the synchronization dependency relationship between threads, and calculate the worst-case thread waiting time (WCST) of the program caused by the application of critical resources based on the principle of mutual exclusion of critical resource access under lock protection.

[0013]

[0014] According to the control flow graph of the parallel program, determine the parallel segment of a program segment running on other cores as the interference set, and perform conflict analysis on the shared instruction cache through the abstract interpretation method.

[0015] The analysis results are input as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program.

[0016] In a possible implementation, the identification of synchronization operations in the multithreaded program under the POSIX thread standard and the recording of lock-related operation statements to generate an extended parallel program control flow graph to describe the synchronization dependency relationship between threads further comprise:

[0017] According to the user-given multithreaded program based on the POSIX thread standard, thread-related operations including thread control (thread creation, thread merging) and thread synchronization (lock) are identified by traversal.

[0018] According to the above information, corresponding additional information is added to the control flow graph of the multithreaded program.

[0019] In a possible implementation, the identification of synchronization operations in the multithreaded program under the POSIX thread standard and the recording of lock-related operation statements to generate an extended parallel program control flow graph to describe the synchronization dependency relationship between threads further comprise

[0020] The extended control flow graph can clearly express the synchronization dependency relationship between threads.

[0021] In a possible implementation, the analysis step of the worst-case thread waiting time further comprises:

[0022] ​The worst-case waiting time generation scenario is determined: when a thread attempts to acquire a lock, all other threads simultaneously apply for the lock and compete with it;

[0023] For each lock, a set of threads that can generate a competition relationship is listed, the worst-case execution time of the basic block where the critical section resource is located is calculated separately, and the worst-case waiting time of the program caused by the critical section mutual exclusion in the above worst-case scenario is simulated and recorded as WCST.

[0024] In a possible implementation, the determination of the parallel section of a program segment running on other cores as an interference set, and the conflict analysis of the shared instruction cache by the abstract interpretation method further comprises:

[0025] Based on the traditional abstract interpretation method and fixed point analysis, the analysis results of the first-level cache and the second-level cache of the task executed on a single core are obtained, and the cache state and the cache access state are abstracted in the process;

[0026] Only the programs running in parallel can have shared cache conflicts, so based on the control flow graph of the parallel program, the possible parallel section of each program segment on other cores is divided as an interference set;

[0027] For each program segment, the shared instruction cache conflict analysis is performed according to the interference set division information.

[0028] In a possible implementation, the cache state is abstracted into four categories: Always Hit (AH), Always Miss (AM), First Miss (FM), and Not Classified (NC);

[0029] The cache access state is abstracted into three categories: Always (A), Never (N), and Uncertain (U).

[0030] In a possible implementation, the shared instruction cache conflict analysis further comprises:

[0031] Determine the hit situation of the instructions in the interference set on the shared cache and the cache line mapping situation in the hit state;

[0032] Update the shared cache hit state of a single instruction according to the analysis results, so as to obtain the shared instruction cache conflict information of the entire parallel program.

[0033] In a possible implementation, the analysis results are input as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program, which further comprises:

[0034] The IPET method is implicit path enumeration, and the WCET estimation of each instruction and the maximum execution number of each instruction need to be determined in the algorithm process;

[0035] Then, the execution time of each instruction in the presence of cache is calculated through modeling of the cache architecture.

[0036] According to the control flow graph, the execution number of instructions in a basic block can be obtained.

[0037] In a possible implementation manner, the execution number of instructions in a basic block according to the control flow graph further includes:

[0038] The WCST analysis result needs to be integrated into the IPET analysis framework, and the integration process includes adding corresponding constraints and modifying the execution time of a basic block.

[0039] In the second aspect, the application provides a WCET analysis device for an embedded multithreaded program, which includes:

[0040] The identification module is configured to identify synchronization operations in the multithreaded program under the POSIX thread standard, record lock-related operation statements, and generate an extended parallel program control flow graph to describe the synchronization dependency relationship between threads.

[0041] The simulation module is configured to calculate the worst-case thread waiting time (WCST) caused by the application of critical resources by threads based on the principle of mutual exclusion of critical resource access under lock protection.

[0042] The analysis module is configured to determine a parallel segment of a program segment running on other cores as an interference set according to the control flow graph of the parallel program, and perform conflict analysis on the shared instruction cache through the abstract interpretation method.

[0043] The calculation module is configured to input the analysis result into the WCET calculation method IPET as a parameter to obtain the WCET analysis result of the entire parallel program.

[0044] The technical scheme provided by the application can at least achieve the following beneficial effects:

[0045] The WCET analysis method for the embedded multithreaded program provided in the application is composed of two parts, including the worst-case execution time of the normal code and the worst-case waiting time caused by thread synchronization, a control flow graph of the multithreaded program is first constructed in the framework, the WCST can be obtained according to the critical section mutual exclusion relationship analysis, the influence of the shared instruction cache conflict needs to be considered in the time analysis, a new shared instruction cache interference set partitioning algorithm is proposed, the accurate analysis of the shared cache conflict is realized, and finally the WCET of the whole multithreaded program is automatically obtained by the IPET method. The experimental results prove the feasibility of the framework and improve the analysis accuracy of the shared instruction cache. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1 is a flowchart of a WCET analysis method for an embedded multithreaded program according to an example embodiment of the present application;

[0048] Figure 2 is a tool framework diagram for WCET analysis according to an example embodiment of the present application;

[0049] Figure 3 is a schematic diagram of a program control flow graph representation according to an example embodiment of the present application;

[0050] Figure 4 is a schematic diagram of the worst-case lock contention according to an example embodiment of the present application;

[0051] Figure 5 is a structural diagram of a WCET analysis device for an embedded multithreaded program according to an example embodiment of the present application.

[0052] Reference signs:

[0053] 1, identification module; 2, simulation module; 3, analysis module; 4, calculation module. DETAILED DESCRIPTION

[0054] In order to make the purposes, embodiments and advantages of the present application more clear, below will be a clear and complete description of the exemplary embodiments of the present application in conjunction with the accompanying drawings of the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not intended to limit the present application.

[0055] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the subsequently described embodiments, and is not intended to limit the embodiments of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0056] The terms "first", "second", "third", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit the specific order or sequence, unless otherwise specified. It should be understood that the terms used in this way can be interchanged under appropriate circumstances.

[0057] The terms "include" and "have" and any variations thereof are intended to cover but not exclusive inclusion, for example, a product or device including a series of components does not necessarily limit to all the components clearly listed, but can include other components not clearly listed or inherent to these products or devices.

[0058] Before explaining the WCET analysis method for embedded multithreaded programs provided by the embodiments of the present application, the application scenarios and implementation environments of the embodiments of the present application are introduced.

[0059] In real-time systems, worst-case execution time (WCET) is an important performance evaluation index, which lays the foundation for ensuring that tasks can be reliably executed within the predetermined strict time limit. The WCET estimate must have two properties: (1) safety: which means it should be greater than or equal to any possible execution time, (2) strictness: that is, as close as possible to the actual worst-case execution time. In order to improve the accuracy of WCET analysis, the behavior of tasks under specific hardware architecture must be considered. In these architectures, the cache has a great influence on the execution time of the program. The prediction of cache hits and misses can result in a difference of nearly one hundred clock cycles in instruction execution time. Therefore, the accuracy of cache analysis is crucial to the execution time estimation of tasks.

[0060] Due to the high processing efficiency, multi-core processors are increasingly common in real-time operating systems. Although multi-core processors improve performance by allowing multiple tasks to run simultaneously on different cores, they cannot shorten the execution time of a single task and thus cannot help meet the deadline requirements of real-time applications. To shorten the running time, one effective method is to parallelize the application code, but this also introduces complex synchronization relationships between threads. In existing methods of WCET analysis on multi-core platforms, tasks executed on different cores are often considered independent, without considering the impact of thread synchronization on the WCET of multi-threaded programs, which limits the analysis scenarios of tasks.

[0061] Meanwhile, in multi-core processors, the last-level cache is usually shared by all processing cores, which means that the content in the shared cache depends not only on the task executed on a single core, but also on other tasks executed in parallel. In addition, synchronization mechanisms are often involved in multi-threaded programs, and complex thread inter-ordering relationships make it more difficult to determine which instructions of different cores will compete for the same cache set. Existing methods usually assume that each instruction in the analyzed thread may compete with the entire thread region in the competing thread for shared resources, which can lead to overly pessimistic WCET analysis results.

[0062] Based on this, the present application provides a WCET analysis method and device for embedded multi-threaded programs, which introduces a new interference set partitioning algorithm for shared instruction cache conflict analysis. First, thread operation primitives are identified to obtain the extended control flow graph of the parallel program, which describes related information such as thread synchronization; then the worst-case execution of the program, such as the existence of critical sections, is analyzed, i.e. when a thread attempts to acquire a lock, all other threads simultaneously compete with it, thereby determining the worst-case waiting time (WCST) of the program; in the cache analysis, a new shared instruction cache interference set partitioning algorithm is introduced, which determines the parallel section of the program segment according to the synchronization information in the program and uses it as the cache interference set, and updates the hit situation of each instruction for the shared cache in time through a custom conflict definition strategy; finally, the above analysis results are integrated into the IPET WCET calculation framework to obtain the WCET of the entire multi-threaded program.

[0063] Next, the technical solutions of the present application and how the technical solutions solve the above technical problems will be described in detail through embodiments and in conjunction with the drawings. Each embodiment can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all.

[0064] Figure 1 is a flowchart of a WCET analysis method for embedded multi-threaded programs according to an exemplary embodiment of the present application,Figure 2 is a tool framework for WCET analysis according to an exemplary embodiment of the present application.

[0065] In one exemplary embodiment, as shown in Figure 1 a WCET analysis method for embedded multithreaded programs is provided. In this embodiment, the method can include the following steps:

[0066] Step 100: Identify synchronization operations in the multithreaded program under the POSIX thread standard, and record lock-related operation statements, to generate an extended parallel program control flow graph to describe the synchronization dependency between threads.

[0067] Step 200: Based on the principle of mutual exclusion access of critical region resources protected by locks, calculate the worst-case thread waiting time (WCST) caused by the application of critical resources by threads.

[0068] Step 300: According to the control flow graph of the parallel program, determine the parallel segments running on other cores for a certain program segment, and use them as the interference set to perform conflict analysis on shared instruction caches through abstract interpretation method.

[0069] Step 400: Input the above analysis results as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program.

[0070] As shown in Figure 2 , it specifically includes:

[0071] According to the multithreaded program based on the POSIX thread standard given by the user, the tool first identifies thread-related operations through traversal, including thread control (thread creation, thread merging) and thread synchronization (locks). According to the above information, corresponding additional representations are added to the control flow graph of the multithreaded program. The extended control flow graph can clearly express the synchronization dependency between threads.

[0072] First, the scenario of the worst-case waiting time needs to be determined: when a thread tries to acquire a lock, all other threads simultaneously apply for this lock and compete with it. After determining the specific scenario, the tool counts the set of threads that may have a competition relationship for each lock, and then calculates the worst-case execution time of the basic block where the critical region resource is located. By simulating the above worst-case scenario, the worst-case waiting time caused by critical region mutual exclusion is obtained, which is recorded as WCST.

[0073] Based on the traditional abstract interpretation method and fixed point analysis, the analysis results of the first level cache and the second level cache of the task executed on the single core are obtained, in which the cache state is abstracted into four categories: Always Hit (AH), Always Miss (AM), First Miss (FM) and Not Classified (NC), and the cache access state is abstracted into three categories: Always (A), Never (N) and Uncertain (U). According to the necessary condition of the cache conflict: only the parallel execution of the program segments can cause the shared cache conflict, therefore, the possible parallel segments of each program segment on other cores are divided as the interference set.

[0074] For each program segment, the shared instruction cache conflict analysis is performed according to the interference set division information, the analysis process includes judging the hit of the instruction in the interference set to the shared cache and the cache line mapping in the hit state, and the shared cache hit state of each instruction is updated according to the analysis result.

[0075] The above analysis result is integrated with the WCET calculation method IPET, the IPET algorithm needs the execution time and the execution times of each instruction as the input, the execution time of each instruction in the cache existing condition can be obtained through the cache analysis, the execution times of the instructions are counted in the basic block unit, and finally the WCST is integrated into the analysis framework by writing the constraint, so that the WCET of the multi-threaded program can be obtained.

[0076] Figure 3 is a schematic diagram of the program control flow graph representation shown in an example embodiment of the present application, Figure 4 is a schematic diagram of the worst case lock competition shown in an example embodiment of the present application.

[0077] In a possible implementation, the specific implementation process of the WCET analysis method is as follows:

[0078] The control flow graph of the multi-threaded program is generated:

[0079] The typical control flow graph is a directed acyclic graph, which is composed of basic blocks and edges, and is a basic control structure for describing a program. The control flow Figure 1 is generally used to represent the single core program, and the control flow graph needs to be extended to represent the execution order, conditional branching and concurrent execution relationship between the tasks or sub-tasks of the multi-threaded program.

[0080] Some embodiments of the present application identify thread-related operations, including thread control (creation, merge) and thread synchronization (mutex) in a multi-threaded program given by a user by scanning the program, and map the information to the nodes of a control flow graph. Additional information is marked in basic blocks to represent the synchronization dependency between threads, and the control flow graph is used as a basis for subsequent multi-threaded program analysis. The control flow graph is shown in FIG. 1. Figure 3

[0081] WCST analysis is performed to obtain the worst-case waiting time of the program due to mutual exclusion:

[0082] The scenario for determining the worst-case waiting time is that when a thread attempts to acquire a lock, all other threads simultaneously apply for the lock and compete with it, as shown in FIG. 2. Figure 4

[0083] For each lock, a set of threads that can generate a competition relationship is listed, and the worst-case execution time of the basic block where the critical section resource is located is calculated separately. The worst-case waiting time of the program due to the critical section mutual exclusion in the above worst-case scenario is simulated, and recorded as WCST.

[0084] The cache is modeled, including single-core task, two-level cache analysis, and shared instruction cache conflict analysis based on interference set partitioning algorithm:

[0085] In multi-level cache analysis, the prediction of L-level cache state requires L-1 level cache information. To perform shared cache analysis, first, the Level 1 cache needs to be subjected to Cache Hit Miss Classification (CHMC), and the Abstract Cache State (ACS) of each program point in the task is obtained through abstract interpretation technology. The program point abstract cache state is divided into four categories, as shown in Table 1:

[0086]

[0087] Table 1 Abstract Cache State and Description

[0088] Cache Access Classification (CAC) is also needed to determine whether the access of a memory block will occur at a certain cache level, as shown in Table 2:

[0089] Cache Access Status Description Always (A) Always accesses this level of cache Never (N) Never accesses this level of cache Uncertain (U) Cannot determine if this level of cache will be accessed

[0090] Table 2 Cache Access State and Description

[0091] Both will be used as common indicators to determine whether the cache is hit.

[0092] ​​For each program segment in the thread, determine its possible parallel segments on other cores.

[0093] Interference set partition algorithm:

[0094] Divide the program executed on a single core into three parts: before the critical section, in the critical section, and after the critical section.

[0095] Store the correspondence between a program segment and a parallel segment in the mapping table structure.

[0096] For each instruction in the program segment, take the set of all instructions in its parallel segment as its interference set.

[0097] Shared instruction cache conflict analysis

[0098] First, determine the conflict judgment condition:

[0099] The memory access of the analyzed instruction is in the AH or FM state in the L2 cache and is mapped to a certain cache line, which is assumed to be n.

[0100] There is also an instruction in its interference set that may access the L2 cache and is mapped to the same cache line n.

[0101] The memory accesses of the two are concurrent.

[0102] After this analysis process, the hit situation of the instruction in the L1 cache and the L2 cache can be obtained, and the total execution time can be determined, which is used for subsequent WCET calculation.

[0103] WCET calculation based on the IPET method:

[0104] The IPET method models WCET calculation as an integer linear programming problem, and its formula is:

[0105]

[0106] Where n represents the number of all instructions, ci represents the WCET of the ith instruction, and xi represents the execution frequency of the ith instruction. Through the above analysis, including control flow analysis and modeling of the cache architecture, we preliminarily obtain the WCET of the normal program. Integrating WCST into IPET calculation can obtain the WCET of the parallel program, which only needs to be put into the linear solution equation by writing constraints.

[0107] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence as indicated, these steps are not necessarily executed in the order as indicated. Unless explicitly stated herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0108] Corresponding to the above-mentioned embodiments of the WCET analysis method for embedded multithreaded programs, the same technical concept is adopted, and the present application also provides an embodiment of a WCET analysis device for embedded multithreaded programs.

[0109] Figure 5 is a structural schematic diagram of a WCET analysis device for embedded multithreaded programs according to an exemplary embodiment of the present application.

[0110] In an exemplary embodiment, as shown in Figure 5 the WCET analysis device for embedded multithreaded programs comprises:

[0111] an identification module 1 for identifying synchronization operations in a multithreaded program under the POSIX thread standard and recording lock-related operation statements, and generating an extended parallel program control flow graph to describe the synchronization dependency relationship between threads;

[0112] a simulation module 2 for calculating the worst-case thread waiting time (WCST) caused by the application of critical resources by threads based on the principle of mutual exclusion of critical resource access under lock protection;

[0113] an analysis module 3 for determining a parallel segment running on other cores as an interference set according to the control flow graph of the parallel program, and performing conflict analysis on shared instruction caches through abstract interpretation method;

[0114] a calculation module 4 for inputting the above analysis results as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program.

[0115] It can be seen that:

[0116] Existing real-time systems usually face strict execution deadline, and worst-case execution time (WCET) as a key performance indicator is usually used for time verification. With the development of multi-core processors, parallel programming as a common method to improve system performance also brings new challenges to WCET analysis. Previous studies usually assume that tasks are independent, thus ignoring the influence of thread synchronization on parallel application WCET. At the same time, existing methods consider that all memory accesses of different cores to the same cache set will cause cache conflict, thus leading to overly pessimistic timing estimation.

[0117] The WCET analysis method and device for embedded multi-threaded programs provided by the present application introduce shared instruction cache conflict analysis based on interference set partitioning algorithm, which can be easily integrated with typical static analysis framework, and experimental results prove the correctness of the framework and effectively improve the performance of cache analysis.

[0118] The specific limitations of the WCET analysis device for embedded multi-threaded programs can be referred to the limitations of the WCET analysis method for embedded multi-threaded programs described above, which will not be repeated here. Each module in the above WCET analysis device for embedded multi-threaded programs can be realized by software, hardware and their combinations. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0119] Each technical feature of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0120] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A WCET analysis method for embedded multi-threaded programs, characterized by: include: Identify synchronization operations in multi-threaded programs under the POSIX thread standard, record lock-related operation statements, and generate an extended parallel program control flow graph to describe the synchronization dependencies between threads; Based on the principle of mutually exclusive access to critical section resources protected by locks, the worst-case waiting time (WCST) of the program caused by threads applying for critical resources is calculated; According to the control flow graph of the parallel program, the parallel segments of a certain program segment running on other cores are determined and used as interference sets. The conflict analysis of the shared instruction cache is performed through the abstract interpretation method to obtain the analysis results. The worst-case waiting time of the program, the control flow graph of the parallel program, and the analysis results are input as parameters into the worst-case execution time (WCET) calculation method IPET to obtain the WCET analysis result of the entire parallel program; The method of identifying synchronization operations in a multi-threaded program under the POSIX thread standard, recording lock-related operation statements, and generating an extended parallel program control flow graph to describe synchronization dependencies between threads further includes: Based on the multi-threaded program given by the user based on the POSIX thread standard, it identifies thread-related operations, including thread control and thread synchronization, by traversing; According to the above information, corresponding additional information is added to the control flow graph of the multi-threaded program; The determining of the parallel segments of a program segment running on other cores and using them as interference sets, and performing conflict analysis on the shared instruction cache by an abstract interpretation method further includes: Based on the abstract interpretation method and fixed point analysis, the analysis results of the first-level cache and second-level cache of tasks executed on a single core are obtained. In this process, the cache state and cache access state are abstracted; Based on the control flow graph of the parallel program, for each program segment, its possible parallel segments on other cores are divided and used as the interference set; For each program segment, perform shared instruction cache conflict analysis based on the above interference set partitioning information; The shared instruction cache conflict analysis further includes: Determine the hit status of the interference concentrated instructions on the shared cache and the cache line mapping status in the hit state; The shared cache hit status of a single instruction is updated according to the analysis results, thereby obtaining the shared instruction cache conflict information of the entire parallel program.

2. The WCET analysis method for embedded multi-threaded programs according to claim 1, wherein: The method of identifying synchronization operations in a multi-threaded program under the POSIX thread standard, recording lock-related operation statements, and generating an extended parallel program control flow graph to describe synchronization dependencies between threads also includes: The expanded control flow graph can clearly express the synchronization dependencies between threads.

3. The WCET analysis method for embedded multi-threaded programs according to claim 1, characterized in that: The worst-case waiting time analysis step of the program further comprises: Determine the worst-case wait time scenario: when a thread attempts to acquire a lock, all other threads simultaneously apply for the lock and compete with it; For each lock, list the set of threads that may have contention relationships, calculate the worst-case execution time of the basic block where the critical section resource is located, and simulate the worst-case waiting time of the program caused by the mutual exclusion of the critical section in the above worst-case scenario, and record it as WCST.

4. The WCET analysis method for embedded multi-threaded programs according to claim 1, wherein: The cache status is abstracted into four categories: Always Hit, Always Miss, First Miss, and Not Classified; The cache access status is abstracted into three categories: Always, Never, and Uncertain.

5. The WCET analysis method for embedded multi-threaded programs according to claim 1, characterized in that: The worst-case waiting time of the program, the control flow graph of the parallel program, and the analysis results are input as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program, further comprising: The IPET method is implicit path enumeration, which determines the WCET estimate of each instruction and the maximum number of executions of each instruction during the algorithm. Then, the model is formulated as an integer linear programming problem and solved. By modeling the cache architecture, the execution time required for each instruction in the presence of a cache is calculated. The number of executions of instructions in the basic block is obtained according to the control flow graph.

6. The WCET analysis method for embedded multi-threaded programs according to claim 5, wherein: Methods for obtaining the execution count of instructions in a basic block according to a control flow graph include: The WCST analysis results are integrated into the IPET analysis framework. The integration process includes adding corresponding constraints and modifying the basic block execution time.

7. A WCET analysis device for an embedded multi-threaded program, the device being used to implement the WCET analysis method for an embedded multi-threaded program according to any one of claims 1 to 6, characterized in that: include: An identification module is used to identify synchronization operations in multi-threaded programs under the POSIX thread standard, record lock-related operation statements, and generate an extended parallel program control flow graph to describe the synchronization dependencies between threads; The simulation module is used to calculate the worst-case waiting time (WCST) of a program caused by a thread applying for critical resources based on the principle of mutually exclusive access to critical section resources protected by locks. The analysis module is used to determine the parallel segments of a program segment running on other cores based on the control flow graph of the parallel program, and use this as the interference set to perform conflict analysis on the shared instruction cache through an abstract interpretation method; The calculation module is used to input the worst-case waiting time of the program, the control flow graph of the parallel program and the analysis results as parameters into the WCET calculation method IPET to obtain the WCET analysis results of the entire parallel program.

Images