Driving method, device and equipment of pixel circuit

Abstract

The application discloses a driving method, device and equipment of a pixel circuit, relates to the technical field of display, and can solve the problems of too large amplitude of luminance difference between non-emitting and emitting stages in the picture display process, too long non-emitting time, and too strong flicker caused by non-emitting or weak emitting in part of the period. The application can flexibly and non-uniformly configure the duty cycle of the time length of each level stage in each control period, such as flexibly configuring the time length of one or more level stages for emitting light after anode reset according to whether each control period is used for anode reset, or differentiating the driving of the level stage not used for emitting light in the refresh frame period and the holding frame period based on different reset frequencies and / or different display refresh rates, so that the emitting light of the multiple control periods is uniform or the emitting duty cycle is improved to optimize the screen flicker, better display and eye protection effects are achieved under the premise that the pixel can normally emit light in each control period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving method, device and equipment of pixel circuit. BACKGROUND

[0002] At present, when the display screen of the electronic device displays a picture, the display screen usually adopts pulse width modulation (PWM), direct current (DC) modulation and other dimming strategies for dimming to achieve better display effect and improve user visual experience. For example, the conventional technology usually keeps the error of the light-emitting time length in each light-emitting period in a picture frame within a certain range to achieve consistency of the light-emitting period, thereby improving user visual experience.

[0003] However, since the display screen usually includes other devices such as electroluminance (EL) devices and pixel circuit anodes, or needs to perform data writing, anode reset, gate reset and other operations in some periods, the data writing, gate reset or EL device anode reset will compress the light-emitting time length in one or more periods, or cause part or all of the light-emitting current in a certain period to be used for charging the devices (such as capacitors) instead of pixel light-emitting, thereby causing the problems of too large amplitude of luminance difference between the non-light-emitting and light-emitting stages in the picture display process, too long non-light-emitting time, and too strong flicker feeling caused by non-light-emitting or weak light-emitting in some periods. SUMMARY

[0004] The present application provides a driving method, device and equipment of pixel circuit, which can solve the problems of too large amplitude of luminance difference between the non-light-emitting and light-emitting stages in the picture display process, too long non-light-emitting time, and too strong flicker feeling caused by non-light-emitting or weak light-emitting in some periods, and improve user visual experience in use.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] In a first aspect, a driving method of a pixel circuit is provided. A display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods including a first level stage not used for light emission and a second level stage used for light emission. The plurality of control periods includes a first control period used for anode reset. The pixel circuit includes a light emission control circuit and an anode reset circuit. The anode reset circuit receives an anode reset control signal and controls anode reset according to the first control period. The method includes detecting a screen brightness value; when the screen brightness value is less than a first brightness threshold, configuring a time length of the second level stage in the plurality of control periods according to the first control period; and the light emission control circuit receiving a light emission control signal and controlling light emission according to the time length of the first level stage and the time length of the second level stage in the plurality of control periods.

[0007] Exemplarily, the above method can be applied to a display panel, a display screen, or an electronic device including the display screen, such as a mobile phone, a tablet computer, and the like, without limitation.

[0008] Exemplarily, the first level stage of the control period is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, without limitation.

[0009] The above-mentioned first aspect provides a solution that can flexibly and non-uniformly configure the time length of the level stage (e.g., the second level stage) used for light emission in each control period according to actual situations such as whether each control period is used for anode reset, such as flexibly configuring the time length of one or more second level stages after anode reset, under the premise that the pixel can normally emit light in each control period, to make the light emission of the plurality of control periods uniform, to optimize screen flicker, and to achieve better display and eye protection effects.

[0010] As a possible implementation manner, the plurality of control periods further includes a second control period, and the second control period is not used for anode reset. The above-mentioned configuring the time length of the second level stage in the plurality of control periods according to the first control period includes configuring the time length of the second level stage in the first control period as a first time length and configuring the time length of the second level stage in the second control period as a second time length, and the first time length is greater than the second time length. Based on this, the time length of the second level stage in the control period used for anode reset can be greater than the time length of the second level stage in the control period not used for anode reset, to ensure uniform light emission of a plurality of low level stages of the same picture frame, and to improve the applicability, compatibility, and flexibility of the solution in different scenarios.

[0011] As a possible implementation, the first control period includes at least one second level stage, and the first time length includes a total time length of the at least one second level stage in the first control period. Based on this, the time length of the second level stage in the control period for anode reset can be made greater than the time length of the second level stage in the control period not for anode reset in various ways, such as lengthening the time length of the second level stage in the display driving period for anode reset or increasing the number of second level stages in the display driving periods for anode reset compared with other periods, thereby improving the applicability, compatibility and flexibility of the scheme in different scenarios while ensuring uniform light emission of multiple low level stages in the same picture frame.

[0012] For example, the first control period includes one second level stage, and the time length of the one second level stage in the first control period is greater than the time length of the second level stage in the second control period.

[0013] Alternatively, for example, the first control period includes multiple second level stages, and the sum (i.e. total time length) of the time lengths of the multiple second level stages in the first control period is greater than the time length of the second level stage in the second control period.

[0014] As a possible implementation, the multiple control periods further include a third control period, where the third control period is a control period after the first control period, the third control period is not for anode reset, and the configuring the time length of the second level stage in the multiple control periods according to the first control period includes configuring the time length of the second level stage in the third control period as a third time length, where the third time length is greater than the second time length. Based on this, the time length of the second level stage in the control period not for anode reset of the picture frame can be flexibly adjusted for light emission compensation according to actual conditions, to ensure that the pixels can maintain normal light emission in each control period, and the light emission amounts of the pixels in each control period are the same or close, thereby ensuring uniform light emission of multiple low level stages in the same picture frame.

[0015] As a possible implementation, the third control period includes at least one second level stage, and the third time length includes a total time length of the at least one second level stage in the third control period. Based on this, the applicability, compatibility and flexibility of the scheme in different scenarios can be improved while ensuring uniform light emission of multiple low level stages in the same picture frame in various ways.

[0016] As an example, the third time length is less than or equal to the first time length.

[0017] As a possible implementation manner, the first control period includes at least one control period; and / or, the second control period includes at least one control period; and / or, the third control period includes at least one control period. That is, the first control period can have one or more, the second control period can have one or more, and the third control period can have one or more. Based on this, when there are multiple first control periods, second control periods or third control periods, the operation of configuring the duration of the second level stage for each control period can be performed, so that the duration of the second level stage in the multiple control periods for anode reset is greater than the duration of the second level stage in the control period not used for anode reset, and / or, the duration of the second level stage in the first control period after anode reset is greater than the duration of the second level stage in the other control periods not used for anode reset. While ensuring uniform light emission of multiple low level stages of the same picture frame, the applicability, compatibility and flexibility of the scheme in different scenarios are improved.

[0018] In a second aspect, a driving method of a pixel circuit is provided. The display period of the pixel circuit includes a plurality of consecutive control periods. Each of the plurality of control periods includes a first level stage not used for light emission and a second level stage used for light emission. The plurality of control periods includes a refresh frame period used for display refresh and gate reset. The pixel circuit includes a light emission control circuit and a reset circuit. The reset circuit receives a reset control signal and controls the gate reset and the display refresh according to the refresh frame period. The method includes detecting a screen brightness value; when the screen brightness value is greater than a second brightness threshold, configuring the duration of the first level stage in the plurality of control periods according to a display refresh rate corresponding to the light emission control signal and / or a reset frequency corresponding to the reset control signal; and the light emission control circuit receives the light emission control signal and controls light emission according to the duration of the first level stage and the duration of the second level stage in the plurality of control periods.

[0019] By way of example, the above method can be applied to a display panel, a display screen, or an electronic device including a display screen, such as a mobile phone, a tablet computer, and the like, without limitation.

[0020] By way of example, the display refresh rate is, for example, 120 Hz, 60 Hz, 1 Hz, and the like, without limitation; and the reset frequency is, for example, a source reset frequency or a drain reset frequency, such as 120 Hz, 240 Hz, 360 Hz, and the like, without limitation.

[0021] By way of example, the first level stage of the control period is, for example, a high level stage, and the second level stage is, for example, a low level stage, or the first level stage is, for example, a low level stage, and the second level stage is, for example, a high level stage, without limitation.

[0022] In the scenario of greater than the second brightness threshold, such as a high brightness scenario, the length of the level stage (such as the first level stage) in each control period which is not used for light emission is flexibly and non-uniformly duty cycle configured according to actual conditions, such as differential driving of the first level stage in the refresh frame period and the hold frame period based on different reset frequencies and / or different display refresh rates, the light emission duty cycle is improved to optimize screen flicker under the premise of ensuring normal operation of the pixel in each control period, the duty cycle remains the same under different display refresh rates and / or different reset frequencies, flicker is avoided when the display refresh rate or the reset frequency is switched, better display and eye protection effects are achieved.

[0023] As a possible implementation manner, the plurality of control periods further include a hold frame period, the hold frame period is used for holding display, the display refresh rate corresponding to the light emission control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, and the length of the first level stage in the plurality of control periods is configured according to the display refresh rate corresponding to the light emission control signal and / or the reset frequency corresponding to the reset control signal, including: the length of the first level stage in the refresh frame period is configured as a fourth length, and the length of the first level stage in the hold frame period is configured as a fifth length, wherein the fifth length is less than the fourth length. Based on this, the pixel can be ensured to work normally in each control period, the light emission duty cycle is improved to optimize screen flicker, and better display and eye protection effects are achieved.

[0024] Exemplarily, the display period of the picture frame includes N control periods, N=F1 / F2, F1 is the source reset frequency or the drain reset frequency, and F2 is the display refresh rate, and the length of the first level stage in the plurality of control periods is configured according to the display refresh rate corresponding to the light emission control signal and / or the reset frequency corresponding to the reset control signal, including: the length of the first level stage in N-1 hold frame periods is configured to be less than the length of the first level stage in the refresh frame period.

[0025] As a possible implementation manner, the plurality of control periods further include a holding frame period, the holding frame period is used for holding display, a display refresh rate corresponding to the light emission control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, a reset frequency corresponding to the reset control signal is the first frequency, and the configuring the duration of the first level stage in the plurality of control periods according to the display refresh rate corresponding to the light emission control signal and / or the reset frequency corresponding to the reset control signal includes: configuring the duration of the first level stage in the refresh frame period as a fourth duration, and configuring the duration of the first level stage in the holding frame period as a sixth duration, the sixth duration being less than the fourth duration and greater than the fifth duration. Based on this, not only can the pixel be ensured to work normally in each control period, the light emission duty cycle be improved to optimize screen flicker, but also the duty cycle under different display refresh rates and / or different reset frequencies can be kept equivalent, flicker when the display refresh rate or the reset frequency is switched is avoided, and better display and eye protection effects are achieved.

[0026] As a possible implementation manner, the refresh frame period includes one control period; and / or, the holding frame period includes at least one control period. That is, the refresh frame period can have one, and the holding frame period can have one or more. Based on this, similar operations of configuring the duration of the first level stage can be performed for each control period when the refresh frame period has one, and the holding frame period has one or more, to realize differential driving of the first level stage in the refresh frame period and the holding frame period.

[0027] Of course, in some examples, there can be no holding frame period, and for this case, the operation of configuring the duration of the first level stage can be performed only for the refresh frame period.

[0028] In a third aspect, a display screen is provided, including an integrated circuit, a gate drive unit, and a pixel circuit, wherein a display period of the pixel circuit includes a plurality of consecutive control periods, each of the plurality of control periods includes a first level stage not used for light emission and a second level stage used for light emission, the plurality of control periods includes a first control period used for anode reset, the pixel circuit includes a light emission control circuit and an anode reset circuit; the anode reset circuit is configured to: receive an anode reset control signal, and control anode reset according to the first control period; the integrated circuit is configured to: detect a screen brightness value, and configure a duration of the second level stage in the plurality of control periods according to the first control period when the screen brightness value is less than a first brightness threshold; and the light emission control circuit is configured to: receive a light emission control signal, and control light emission according to the duration of the first level stage and the duration of the second level stage in the plurality of control periods.

[0029] Exemplarily, the integrated circuit such as an integrated circuit (IC) can include, but is not limited to, a gate driven on array (GOA).

[0030] The third aspect provides the scheme, which can flexibly and non-uniformly configure the time length of the second level stage for emitting light in each control period according to actual situations such as whether the anode reset is used in each control period, flexibly configure the time length of one or more second level stages after the anode reset, and make the light emission of the multiple control periods uniform to optimize screen flicker and achieve better display and eye protection effects on the premise that the display screen can normally emit light in each control period.

[0031] As a possible implementation manner, the multiple control periods further include a second control period, the second control period is not used for anode reset, and the integrated circuit is configured to: configure the time length of the second level stage in the first control period as a first time length, and configure the time length of the second level stage in the second control period as a second time length, where the first time length is greater than the second time length. Based on this, the time length of the second level stage in the control period for anode reset can be greater than the time length of the second level stage in the control period not for anode reset, which improves the applicability, compatibility and flexibility of the scheme in different scenes while ensuring the uniform light emission of multiple low level stages of the same picture frame.

[0032] As a possible implementation manner, the first control period includes at least one second level stage, and the first time length includes the total time length of the at least one second level stage in the first control period. Based on this, the time length of the second level stage in the control period for anode reset can be greater than the time length of the second level stage in the control period not for anode reset in various ways, such as lengthening the time length of the second level stage in the display driving period for anode reset or increasing the number of second level stages in the display driving period for anode reset compared with other periods, which improves the applicability, compatibility and flexibility of the scheme in different scenes while ensuring the uniform light emission of multiple low level stages of the same picture frame.

[0033] Exemplarily, the first control period includes one second level stage, and the time length of the one second level stage in the first control period is greater than the time length of the second level stage in the second control period.

[0034] Alternatively, the first control period includes a plurality of second level stages, and a sum of durations of the plurality of second level stages in the first control period (i.e., a total duration) is greater than the duration of the second level stage in the second control period.

[0035] As a possible implementation, the plurality of control periods further includes a third control period, the third control period is a control period after the first control period, the third control period is not used for anode reset, and the integrated circuit is specifically configured to: configure a duration of the second level stage in the third control period as a third duration, where the third duration is greater than the second duration. Based on this, the duration of the second level stage in the control period not used for anode reset of the picture frame can be flexibly adjusted according to actual conditions to perform light emission compensation, so as to ensure that the display screen can maintain normal light emission in each control period, and the light emission amount of each pixel of the display screen in each control period is the same or close, thereby ensuring uniform light emission of the plurality of low level stages of the same picture frame.

[0036] As a possible implementation, the third control period includes at least one second level stage, and the third duration includes a total duration of the at least one second level stage in the third control period. Based on this, the applicability, compatibility and flexibility of the scheme in different scenarios can be improved while ensuring uniform light emission of the plurality of low level stages of the same picture frame in various ways.

[0037] As an example, the third duration is less than or equal to the first duration.

[0038] As a possible implementation, the first control period includes at least one control period; and / or, the second control period includes at least one control period; and / or, the third control period includes at least one control period. That is, the first control period can have one or more, the second control period can have one or more, and the third control period can have one or more. Based on this, when there are multiple first control periods, second control periods or third control periods, similar operations of configuring the duration of the second level stage are performed for each control period, so that the duration of the second level stage in the plurality of control periods used for anode reset is greater than the duration of the second level stage in the control period not used for anode reset, and / or, the duration of the second level stage in the first control period after anode reset is greater than the duration of the second level stage in the other control period not used for anode reset. While ensuring uniform light emission of the plurality of low level stages of the same picture frame, the applicability, compatibility and flexibility of the scheme in different scenarios are improved.

[0039] In a fourth aspect, a display screen is provided, and the display screen comprises: an integrated circuit, a gate driving unit, and a pixel circuit, wherein a display period of the pixel circuit comprises a plurality of continuous control periods, each of the plurality of control periods comprises a first level stage not used for emitting light and a second level stage used for emitting light, the plurality of control periods comprises a refresh frame period used for displaying refresh and gate reset, the pixel circuit comprises an emitting control circuit and a reset circuit; the reset circuit is configured to: receive a reset control signal, and control the gate reset and the display refresh according to the refresh frame period; the integrated circuit is configured to: detect a screen brightness value, and configure a time length of the first level stage in the plurality of control periods according to a display refresh rate corresponding to the emitting control signal and / or a reset frequency corresponding to the reset control signal when the screen brightness value is greater than a second brightness threshold; and the emitting control circuit is configured to: receive the emitting control signal, and control the emitting according to the time length of the first level stage and a time length of the second level stage in the plurality of control periods.

[0040] The scheme provided in the fourth aspect above can flexibly and non-uniformly configure the time length of the level stage (e.g., the first level stage) not used for emitting light in each control period according to actual conditions, such as different reset frequencies and / or different display refresh rates, to differentially drive the first level stage in the refresh frame period and the hold frame period, to improve the light emitting duty cycle to optimize screen flicker under the premise of ensuring that the display screen normally works in each control period, to keep the duty cycle equivalent under different display refresh rates and / or different reset frequencies, to avoid flicker when the display refresh rate or the reset frequency is switched, and to achieve better display and eye protection effects.

[0041] As a possible implementation manner, the plurality of control periods further comprises a hold frame period used for holding display, the display refresh rate corresponding to the emitting control signal is a first refresh rate, and the reset frequency corresponding to the reset control signal is a first frequency, and the integrated circuit is specifically configured to: configure the time length of the first level stage in the refresh frame period as a fourth time length, and configure the time length of the first level stage in the hold frame period as a fifth time length, wherein the fifth time length is less than the fourth time length. Based on this, the display screen can be ensured to normally work in each control period, the light emitting duty cycle can be improved to optimize screen flicker, and better display and eye protection effects can be achieved.

[0042] As a possible implementation manner, the plurality of control periods further include a holding frame period, the holding frame period is used for holding display, a display refresh rate corresponding to the light emission control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, a reset frequency corresponding to the reset control signal is the first frequency, and the integrated circuit is specifically configured to: configure a time length of the first voltage level stage in the refresh frame period as a fourth time length, and configure a time length of the first voltage level stage in the holding frame period as a sixth time length, the sixth time length is less than the fourth time length, and the sixth time length is greater than the fifth time length. Based on this, not only can the pixel be ensured to work normally in each control period, the light emission duty cycle be improved to optimize screen flicker, but also the duty cycle can be kept equivalent under different display refresh rates and / or different reset frequencies, flicker when the display refresh rate or the reset frequency is switched is avoided, and better display and eye protection effects are achieved.

[0043] As a possible implementation manner, the refresh frame period includes one control period; and / or, the holding frame period includes at least one control period. That is, the refresh frame period can have one, the holding frame period can have one or can have a plurality. Based on this, similar operations of configuring the time length of the first voltage level stage can be performed for each control period when the refresh frame period has one, the holding frame period has one or a plurality, so that the first voltage level stage is driven differently in the refresh frame period and the holding frame period.

[0044] Of course, in some examples, there can be no holding frame period, and for this case, the operation of configuring the time length of the first voltage level stage can be performed only for the refresh frame period.

[0045] In a fifth aspect, an electronic device is provided, which includes: a display screen configured to display an interface; a memory configured to store computer program instructions; and a processor configured to execute the computer program instructions to support the electronic device to implement the method in any possible implementation manner of the first aspect or the second aspect.

[0046] In a sixth aspect, a computer readable storage medium is provided, which has stored thereon computer program instructions, and the computer program instructions are executed by a processor to implement the method in any possible implementation manner of the first aspect or the second aspect.

[0047] In a seventh aspect, a computer program product containing instructions is provided, and when the computer program product is run on a computer, the computer is caused to implement the method in any possible implementation manner of the first aspect or the second aspect.

[0048] Eighthly, a chip system is provided, comprising processing circuitry and a storage medium storing computer program instructions; when executed by the processor, the computer program instructions implement the method as described in any possible implementation of the first or second aspect. The chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0049] Figure 1 A schematic diagram illustrating the principle of controlling light emission using a conventional emission (EM) control signal;

[0050] Figure 2 This is a schematic diagram illustrating the light-emitting effect of a pixel driven by a conventional EM control signal.

[0051] Figure 3 A schematic diagram illustrating the principle of controlling light emission using two other conventional EM control signals;

[0052] Figure 4 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;

[0053] Figure 5 This is a schematic diagram of the luminous effect of pixels driven by EM control signals in an embodiment of this application. Figure 1 ;

[0054] Figure 6 This is a schematic diagram of the luminous effect of pixels driven by EM control signals in an embodiment of this application. Figure 2 ;

[0055] Figure 7 This is a schematic diagram of the luminous effect of pixels driven by EM control signals in an embodiment of this application. Figure 3 ;

[0056] Figure 8 This is a schematic diagram of the luminous effect of pixels driven by EM control signals in an embodiment of this application. Figure 4 ;

[0057] Figure 9 This is a schematic diagram of the luminous effect of pixels driven by EM control signals in an embodiment of this application. Figure 5 ;

[0058] Figure 10 Schematic diagram of the principle of light emission control using the EM control signal provided in the embodiments of this application Figure 1 ;

[0059] Figure 11 Schematic diagram of the principle of light emission control using the EM control signal provided in the embodiments of this application Figure 2 ;

[0060] Figure 12 Principle diagram of the EM control signal provided by the embodiment of the present application for light emitting control Figure 3 ;

[0061] Figure 13 A pixel circuit diagram provided by the embodiment of the present application

[0062] Figure 14 A driving timing diagram corresponding to a refresh frame period provided by the embodiment of the present application

[0063] Figure 15 A driving timing diagram corresponding to a refresh frame period provided by the embodiment of the present application Figure 1 ;

[0064] Figure 16 A driving timing diagram corresponding to a refresh frame period provided by the embodiment of the present application Figure 2 ;

[0065] Figure 17 A driving timing diagram corresponding to a refresh frame period provided by the embodiment of the present application Figure 3 ;

[0066] Figure 18 A structure block diagram of a display panel provided by the embodiment of the present application DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, “ / ” represents or, for example, A / B can represent A or B; “and / or” in this text only represents a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent three cases: A exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” means two or more than two.

[0068] Hereinafter, the terms "first", "second", and the like are only used to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity, or content of the described objects. For example, the described object is "field", and the ordinal number before "field" in "first field" and "second field" does not limit the position or order between "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message or not, nor do they limit the order of "first field" and "second field". For another example, the described object is "level", and the ordinal number before "level" in "first level" and "second level" does not limit the priority between "levels". For another example, the quantity of the described object is not limited by the ordinal number, and can be one or more. For example, "first device", where the quantity of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different, for example, the described object is "device", and "first device" and "second device" can be the same type of device or different types of device. For another example, the described object is "information", and "first information" and "second information" can be information of the same content or information of different content. In summary, the use of ordinal numbers and other prefix words in the embodiments of the present application to distinguish between description objects does not limit the described objects, and the description of the described objects is referred to the description of the context in the claims or embodiments, and should not be limited by the use of such prefix words.

[0069] In addition, in the embodiments of the present application, "connection" can be direct connection or indirect connection; in addition, it can mean electrical connection or communication connection; for example, two electrical elements A and B are connected, which can mean that A is directly connected to B, or can mean that A and B are indirectly connected through other electrical elements or connection medium, or can mean that A and B are indirectly connected through other communication devices or communication medium, as long as A and B can communicate with each other.

[0070] As described in the background, the display screen of the existing electronic device, such as active matrix organic light emitting diode (AMOLED), often uses PWM, DC modulation and other dimming strategies for dimming, such as using PWM dimming strategy in low brightness scene and using DC modulation dimming strategy in high brightness scene, to achieve better display effect by adjusting the duty cycle and / or brightness value of the display screen, and to improve the user visual experience. However, the above dimming methods are strategies in ideal situations, and do not consider the actual situation of the display screen when working.

[0071] For example, in a low brightness scene, the existing dimming method does not consider the influence of anode reset and charging of EL capacitor, pixel circuit anode and other devices on the display screen on the display screen lighting time.

[0072] like Figure 1 As shown, taking a 2nit screen brightness value controlled by an emitting (EM) control signal, with the EM control signal using 1440Hz PWM dimming, a display refresh rate of 120Hz, an anode reset frequency of 120Hz, and a display cycle of 12 control cycles per frame as an example, generally, the PWM dimming strategy can control the brightness value to achieve a uniform dimming effect by adjusting the duty cycle. The display refresh rate can be simply understood as the number of times the screen lights up per unit time; the duty cycle can be simply understood as the proportion of time that drives the pixels to emit light to the total time. For example, taking a pulse sequence with a pulse width of 1μs and a control cycle of 4μs as an example, the duty cycle of the pulse sequence is 1μs / 4μs = 0.25. In this context... Figure 1 In this system, the display screen lights up when the EM control signal is low and turns off when the EM control signal is high. It should be noted that... Figure 1 The example of the display screen illuminating when the EM control signal is low is only used as an example. In actual applications, there is no specific limitation. For example, in some embodiments, a high level corresponds to the pixel illuminating and a low level corresponds to the pixel turning off, depending on the specific situation.

[0073] However, adopting Figure 1 The dimming method shown has the following problems: AMOLED and other displays typically include components such as EL capacitors and pixel circuit anodes, such as... Figure 2 As shown, in the first control cycle of a frame, taking the display screen performing an anode reset at a frequency of 120Hz as an example, when the EM control signal switches to a low level, the actual light-emitting time of the display screen in the first control cycle will be shortened because it is necessary to charge the EL capacitor, pixel circuit anode, and other components. Figure 2 In severe cases, the light may not even be emitted at all. This can cause the light to be absent or weakly emitted during certain control cycles in the display process, resulting in low-frequency flicker that can be perceived by the human eye. This is known as the stroboscopic effect visibility measure (SVM), which increases the perceived flicker of the screen.

[0074] For example, in high-brightness scenarios, such as when the screen brightness value is greater than 90 nits, existing dimming methods do not take into account the impact of the refresh frame cycle and the consistency of the length of the high-level phase in the frame cycle on the display's light emission time.

[0075] like Figure 3As shown, taking a screen with a brightness of 500 nits as an example, where the screen emits light through EM control signals and the EM control signal is low, generally, keeping the refresh frame period and the duration of the control signal being low within the hold frame period consistent (or with an acceptable error range) ensures that the duration of screen illumination within both periods remains consistent, thus achieving a uniform dimming effect. Furthermore, for different display refresh rates, such as... Figure 3 The refresh rates shown are 120Hz and 60Hz. The duration of the EM control signal being low within the refresh frame period and the hold frame period are also consistent or within an acceptable range. This ensures that the duty cycle is consistent under different display refresh rates, thereby avoiding brightness differences caused by display refresh rate switching.

[0076] However, adopting Figure 3 The dimming method described has the following problems: In practical applications, because the refresh frame cycle requires gate reset and data writing (such as for display refresh), the high-level phase is relatively long, meaning the display screen is not emitting light for a longer period. Therefore, the duration of the EM low-level phase will inevitably be shortened. If the duration of the EM control signal being low within the refresh frame cycle is to be consistent with the duration within the hold frame cycle, the on-screen time within the hold frame cycle will be shortened. This will cause the display screen to require a higher brightness amplitude when the EM is low to achieve the set brightness target value, and the average light-emitting time ratio within a frame will be lower. Both of these effects will lead to an increase in SVM, i.e., excessive screen flicker.

[0077] It should be noted that, in Figures 1-3 In the example shown, the display screen illuminates when the EM control signal is low and turns off when the EM control signal is high. Of course, in practical applications, a high level can correspond to the display screen illuminating, and a low level to the display screen not illuminating, depending on the specific situation.

[0078] To address the issues of excessive flicker caused by large brightness differences between the non-emitting and emitting phases of the display screen, excessively long non-emitting periods, and large SVM values ​​resulting from non-emitting or weak emitting during certain cycles in existing dimming methods, this application provides a pixel circuit driving method that can solve the screen flicker problem in brightness scenarios such as low-brightness and high-brightness scenes.

[0079] For example, based on the solution provided in the embodiments of this application, in low-brightness scenarios, a non-uniform duty cycle configuration can be adopted in each control cycle of the display cycle (such as the EM cycle, which will be described as an example below) to ensure that the low-level stage can emit light normally after taking into account factors such as anode reset and device charging, and to make the light emission uniform in multiple low-level stages, thereby optimizing screen flicker and achieving better display and eye protection effects.

[0080] For example, based on the scheme provided in the embodiments of the present application, in the high brightness scenario, one or more parameters of the control period corresponding to the picture frame can be adjusted according to the screen brightness value, display refresh rate, reset frequency (such as source reset frequency, drain reset frequency, etc.), such as the duration of the first level stage, and finally the interface is displayed according to the adjusted control period parameters. For example, based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz), the refresh frame period and the holding frame period can be driven differently, such as making the duration of the first level stage (such as the high level stage, hereinafter the first level stage is taken as the high level stage for related introduction) of the refresh frame period and the holding frame period is greater than 1H, while making the duty cycle under different display refresh rates and / or different reset frequencies is high and basically remains the same (such as less than 0.2%), in order to optimize the screen flicker and achieve better display and eye protection effect. Wherein, 1H is the scanning time unit of each row of the display screen, usually between 1-3us.

[0081] Wherein, the display screen described in the embodiments of the present application is the display screen of the electronic device, which can include but is not limited to smart phones, netbooks, tablet computers, smart drawing boards, handwriting boards, smart watches, smart bracelets, phone watches, smart glasses, smart cameras, palm computers, vehicle-mounted computers, personal computers (PC), personal digital assistants (PDA), portable multimedia players (PMP), augmented reality (AR) / virtual reality (VR) devices, smart televisions, projection devices or body sensing game machines in human-computer interaction scenes, etc. Or, the electronic device can also be other types or structures of electronic devices with display screens, which are not limited by the present application.

[0082] As an example, please refer to Figure 4 , Figure 4 A hardware structure schematic diagram of an electronic device provided by the embodiments of the present application is shown.

[0083] As Figure 4 shown, the electronic device can include a processor 410, a memory 420, a charge management module 430, a power management module 440, a battery 450, a display screen 460, etc.

[0084] The processor 410 can include one or more processing units. For example, the processor 410 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a flight control processor, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units can be independent devices or integrated in one or more processors.

[0085] The processor 410 can also include a memory for storing instructions and data. In some embodiments, the memory in the processor 410 is a cache memory. The memory can hold instructions or data that the processor 410 has just used or is using repeatedly. If the processor 410 needs to use the instructions or data again, it can call them directly from the memory. This avoids repeated access and reduces the processor’s 410 waiting time, thus improving the system’s efficiency.

[0086] The charging management module 430 is configured to receive charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 430 can receive charging input from a wired charger through a USB interface. In some wireless charging embodiments, the charging management module 430 can receive wireless charging input through a wireless charging coil. The charging management module 430 can charge the battery 450 while also providing power to the electronic device through the power management module 440.

[0087] The power management module 440 is configured to connect the battery 450, the charging management module 430, and the processor 410. The power management module 440 receives input from the battery 450 and / or the charging management module 430 to provide power to the processor 410, the internal memory 420, the display 460, the camera 393, and the wireless communication module 360, etc. The power management module 440 can also be configured to monitor parameters such as battery capacity, battery cycle count, battery health status (leakage, impedance), etc. In other embodiments, the power management module 440 can also be disposed in the processor 410. In other embodiments, the power management module 440 and the charging management module 430 can also be disposed in the same device.

[0088] In the embodiments of the present application, the power management module 440 receives the input of the battery 450 and / or the charge management module 430, and supplies power to the display screen 460 to support the normal operation of the display screen, such as lighting or extinguishing.

[0089] The electronic device implements the display function through the GPU, the display screen 460, and the AP, etc. The GPU is a microprocessor for image processing, connected to the display screen 460 and the AP. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 410 can include one or more GPUs that execute program instructions to generate or change display information.

[0090] The display screen 460 is used to display images, videos, etc. The display screen 460 includes a display panel. The display panel can adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-OLED, a quantum dot light emitting diode (QLED), etc.

[0091] In the embodiments of the present application, the display screen 460 can display pictures based on the normal operation of the display panel.

[0092] In some embodiments, the display screen can adopt a non-uniform duty cycle configuration in each EM period of a display period in a low-to-medium brightness scene, to ensure that the display screen can normally light up in the first second level stage (such as the low level stage, and the following is described by taking the second level stage as the low level stage as an example) after completing anode reset, device charging, etc., and make the light emission of multiple low level stages in the same display period uniform.

[0093] In some embodiments, the display screen can be driven differently in the refresh frame period and the hold frame period based on different reset frequencies (such as 120Hz, 240Hz, 360Hz) and / or different display refresh rates (such as 1Hz, 60Hz, 120Hz) in a high brightness scene, so that the duty cycles under different display refresh rates and / or different reset frequencies are high and basically remain the same (such as a difference less than 0.2%), to achieve a smaller SVM value, optimize screen flicker, and achieve better display and eye protection effects.

[0094] In some embodiments, as Figure 4As shown, the display screen can include an integrated circuit (such as a driving integrated circuit (IC)), a gate driving unit, and a pixel circuit.

[0095] The pixel circuit includes a light emitting control circuit and a reset circuit.

[0096] The driving IC is configured to: obtain a screen brightness value; and configure a time length of a second level stage in a plurality of control periods according to a period for anode reset (such as a first control period) when the screen brightness value is less than a first brightness threshold; or configure a time length of a first level stage in the plurality of control periods according to a display refresh rate corresponding to the light emitting control signal and / or a reset frequency corresponding to the reset control signal when the screen brightness value is greater than a second brightness threshold. Exemplarily, the gate driving unit can include, but is not limited to, a GOA.

[0097] The light emitting control circuit is configured to control the light emitting of the pixel circuit according to a time length of a first level stage in a plurality of control periods which is not used for light emitting and a time length of a second level stage which is used for light emitting.

[0098] The reset circuit is configured to control whether the plurality of control periods are used for reset according to a reset control signal, such as controlling reset in a first control period, such as an anode reset circuit configured to control whether the plurality of control periods are used for anode reset according to an anode reset control signal, a source reset circuit configured to control whether the plurality of control periods are used for source reset according to a source reset control signal, and a drain reset circuit configured to control whether the plurality of control periods are used for drain reset according to a drain reset control signal.

[0099] The external memory interface 320 can be configured to connect an external storage card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external storage card communicates with the processor 410 through the external memory interface 320 to realize a data storage function.

[0100] The internal can be used to store computer executable program code. Exemplarily, the computer program can include an operating system program and an application program. The executable program code includes instructions. The processor 410 executes various function applications and data processing of the electronic device by running the instructions stored in the memory 420. The memory 420 can include a program storage area and a data storage area. The program storage area can store an operating system, an application program required by at least one function, and the like. The data storage area can store data created during use of the electronic device, and the like. In addition, the memory 420 can include a high-speed random access memory, and can further include a non-volatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash storage (UFS), and the like. The processor 410 executes various function applications and data processing of the electronic device by running the instructions stored in the memory 420 and / or the instructions stored in the memory disposed in the processor.

[0101] It can be understood that the present application Figure 4 The schematic structure does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device can include more or fewer components than the illustration, or combine certain components, or split certain components, or different arrangement of components. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0102] For example, in some examples, the electronic device can further include one or more devices or modules such as a universal serial bus (USB) interface, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a receiver, a microphone, an earphone interface, a sensor module, a key, a motor, an indicator, a camera, and the like, which are not described here.

[0103] The driving method of the pixel circuit provided by the embodiments of the present application will be specifically introduced below in combination with specific scenarios.

[0104] Embodiment 1:

[0105] In embodiment 1, when the electronic device displays a picture frame based on the pixel circuit, the display period of one picture frame usually includes a plurality of continuous control periods. The pixel circuit includes a light-emitting control circuit and an anode reset circuit. The light-emitting control circuit is configured to receive a light-emitting control signal, such as an EM control signal. The anode reset circuit is configured to receive an anode reset control signal. That is, the pixel circuit can receive the EM control signal to control light emission according to the time length of the level phase not used for light emission and the time length of the level phase used for light emission in the plurality of control periods. The anode reset circuit can control whether the plurality of control periods are used for anode reset according to the anode reset control signal.

[0106] In the embodiment 1 of the present application, the pixel circuit is configured with non-uniform duty cycles in each control period to ensure that the pixel can normally emit light in each low level stage, and the light emission amount in each low level stage is the same or close, thereby ensuring uniform light emission in multiple low level stages in the same display period.

[0107] In some embodiments, the scheme provided in the embodiment 1 can be applied to a scene with a screen brightness value less than a first brightness threshold. For example, the first brightness threshold is 90 nit, i.e., the scheme provided in the embodiment 1 can be applied to a low-to-medium brightness scene, and the specific value of the first brightness threshold is not limited.

[0108] In some embodiments, the multiple control periods included in the display period of the pixel circuit have the same duration, and each of the multiple control periods includes a first level stage and a second level stage, i.e., each control period includes a first level stage and a second level stage, wherein the first level stage is an anode reset level stage, and the second level stage is a light emission level stage. In the embodiment 1 of the present application, the duration of the second level stage in the multiple control periods can be configured according to the control period (e.g., the first control period) for anode reset in the multiple control periods, and then the light emission is controlled according to the duration of the first level stage and the duration of the second level stage in the multiple control periods.

[0109] In some embodiments, the first level stage is a high level stage, and the second level stage is a low level stage, or the first level stage is a low level stage, and the second level stage is a high level stage, which is not limited in the embodiment of the present application. The following embodiments take the first level stage as a high level stage and the second level stage as a low level stage as an example.

[0110] As a possible implementation, the first control period can include at least one control period, and the second control period can include at least one control period. That is, the first control period can have one or more, and the second control period can have one or more, wherein the first control period is used for anode reset, and the second control period is not used for anode reset. Based on this, similar operations of configuring the duration of the second level stage can be performed for each first control period and each second control period, such as configuring the duration of the second level stage in each first control period and each second control period according to each first control period, and then controlling the light emission according to the duration of the first level stage and the duration of the second level stage in multiple control periods (including each first control period and each second control period). For example, the duration of the second level stage in the first control period can be configured as a first duration, and the duration of the second level stage in the second control period can be configured as a second duration, so that the first duration is greater than the second duration. Based on this, the duration of the first second level stage after anode reset can be greater than the duration of the second level stage in the control period without anode reset, so as to ensure that the duration of each second level stage is sufficient to charge the EL capacitor, the pixel circuit anode and other devices, and to maintain sufficient light emission, and the light emission of each second level stage is the same or close.

[0111] For example, in the case of light emission control by the EM control signal at a screen brightness value of 2 nit, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, the display period of one frame of picture includes 12 EM cycles, the first level stage is a high level stage, and the second level stage is a low level stage, the EM control signal and the light emission effect of the pixel can be as shown in Figure 5 , wherein Figure 5 , each of the 12 EM cycles (such as Figure 5 EM cycle 1, EM cycle 2, …, EM cycle 12) includes a high level stage and a low level stage, such as the timing EM control signal respectively includes Figure 5 high level stage 1, low level stage 1, high level stage 2, low level stage 2, high level stage 3, low level stage 3, …, high level stage 12, low level stage 12. As Figure 5As shown, the length of the low level phase in the EM cycle 1 (i.e. the first control cycle) for anode reset (i.e. the first length) is longer than the length of the low level phase in other EM cycles (i.e. the second control cycle) (i.e. the second length), so after the anode reset is completed, the electronic device can switch to the low level phase to start charging the EL capacitor, pixel circuit anode and other devices, thereby ensuring that the luminous quantity of the pixel in the first low level phase is equal to or close to the luminous quantity of the pixel in other low level phases.

[0112] As an example, the first length has the following relationship with the length of the low level phase in the control cycle with the shortest low level phase in the display cycle (denoted as "length Min"): (first length-length Min) / length Min> (or ≥) the first preset threshold. Exemplarily, the first preset threshold is a value in 10%-100%, such as 60%. Of course, the embodiments of the present application do not limit the specific first preset threshold, which is determined according to the specific situation in actual application.

[0113] In some embodiments, the first control cycle includes a second level phase. For this case, the first length is the length of the second level phase in the first control cycle.

[0114] In some embodiments, the first control cycle includes a plurality of second level phases. For this case, the first length includes the total length (i.e. the sum of lengths) of the plurality of second level phases in the first control cycle.

[0115] For example, taking the case of luminous control by the EM control signal at a screen brightness value of 2 nit, the EM control signal using 1440Hz PWM dimming, the display refresh rate being 120Hz, the anode reset frequency being 120Hz, the display cycle of one frame of picture including 12 EM cycles, the first level phase being a high level phase and the second level phase being a low level phase, the luminous effect diagram of the EM control signal driving the pixel can be as shown in Figure 6 As shown, the 12 EM cycles (such as Figure 6 EM cycle 1, EM cycle 2, …, EM cycle 12) each include a high level phase and a low level phase (for the convenience of reading the diagram, the high and low level phases of each EM cycle are not shown in Figure 6 , which can be referred to in Figure 5 ). As shown in Figure 6As shown, compared to the duration of the low-level phase in other EM cycles (such as the second control cycle mentioned above), the EM cycle 1 used for anode reset (i.e., the first control cycle mentioned above) has two low-level phases, and the total duration of these two low-level phases (i.e., the first duration mentioned above) is longer. Therefore, in EM cycle 1 (i.e., the first control cycle mentioned above), after the anode reset is completed, the electronic device can switch to the low-level phase in advance to start charging the EL capacitor, pixel circuit anode, and other devices, and start emitting light when entering the next low-level phase in the same EM cycle, thereby ensuring that the amount of light emitted by the pixel in the first light-emitting phase is equal to or close to the amount of light emitted by the pixel in other low-level phases.

[0116] Additionally, it should be noted that this application Figure 5 and Figure 6 The example shown uses a single anode reset within one display cycle as an example. In practical applications, the solution provided in this application is equally applicable to situations where multiple anode resets are performed within one display cycle (e.g., 2 times, 3 times, etc., without quantity limitation). That is, one display cycle may include multiple first control cycles, and the duration of the second level phase in multiple first control cycles used for anode reset can be configured based on the solution provided in this application.

[0117] For example, taking a screen brightness of 2 nits as an example, where the luminous emission is controlled by an EM control signal, the EM control signal uses 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 360Hz, the display cycle of one frame includes 12 EM cycles, and the first level phase is a high level phase and the second level phase is a low level phase, the schematic diagram of the EM control signal driving the pixel's luminous emission effect might be as follows: Figure 7 As shown, there are 12 EM cycles (such as...) Figure 7 The EM cycles shown (EM cycle 1, EM cycle 2, ..., EM cycle 3) each include a high-level phase and a low-level phase (for ease of reading the diagram, ...). Figure 7 The various high and low level stages are not shown in the diagram; please refer to [reference needed]. Figure 5 ).like Figure 7 As shown, compared to the duration of the low-level phase in other EM cycles (such as the second control cycle mentioned above), the duration of the low-level phase in EM cycles 1, EM cycles 5, and EM cycles 9 (i.e., the multiple first control cycles mentioned above) used for anode reset is longer. Therefore, after each anode reset, the electronic device can switch to the low-level phase in advance to start charging the EL capacitor, pixel circuit anode, and other devices, thereby ensuring that the light emission of the pixel in the first low-level phase after each anode reset is equal to or close to the light emission of the pixel in other low-level phases.

[0118] For example, in the case of the light emitting control by the EM control signal at the 2 nit screen brightness value, the 1440 Hz PWM dimming of the EM control signal, the display refresh rate of 120 Hz, the anode reset frequency of 360 Hz, and the display period of one frame of picture including 12 EM periods, the first level stage being the high level stage and the second level stage being the low level stage, the light emitting effect diagram of the EM control signal driving the pixel can be as shown in FIG. 12, where the 12 EM periods (e.g., EM period 1, EM period 2, …, EM period 12) each include a high level stage and a low level stage (for the convenience of reading the diagram, the high level stages and the low level stages in each EM period are not shown in FIG. 12, and the reader can refer to the section of FIG. 11 for the details). Figure 8 Figure 8 Figure 8 Figure 5 Figure 8 As shown in FIG. 12, compared with the length of the low level stage (i.e., the second length described above) of the other EM periods (e.g., the second control period described above), the EM period 1, the EM period 5, and the EM period 9 (i.e., the first control period described above) for the anode reset each have two low level stages, and the total length of the two low level stages in each period (i.e., the first length described above) is longer. Therefore, after each anode reset, the electronic device can switch to the low level stage to start charging the devices such as the EL capacitor and the anode of the pixel circuit in advance, and start light emitting when entering the next low level stage, thereby ensuring that the light emitting amount of the pixel in the first light emitting stage after the anode reset is equal to or close to the light emitting amount of the pixel in the other low level stages.

[0119] In addition, it should be noted that the examples shown in the present application Figure 5 and Figure 6 only take the length of the first light emitting stage (i.e., the second level stage) after the anode reset as an example, and in actual application, the light emitting amount of the other one or more light emitting stages after the anode reset can also be ensured by the method provided in the embodiments of the present application.

[0120] As a possible implementation manner, the length of the second level stage in the third control period can be configured as a third length, so that the third length is greater than the second length, where the third control period is not used for the anode reset. As an example, the third control period can be the control period after the first control period, such as the first control period after the first control period. Based on this, the second second level stage after the anode reset can be ensured to have sufficient light emitting amount, and the light emitting amounts of the second level stages are the same or close.

[0121] ​​​​As an example, the third control period can include at least one control period, that is, the third control period can have one or more. Based on this, the operation of configuring the duration of the second level stage can be performed for each third control period, for example, the duration of the second level stage in each third control period can be configured according to the first control period, and then the light emission is controlled according to the duration of the first level stage and the duration of the second level stage in multiple control periods (including each third control period).

[0122] As an example, the third duration is less than or equal to the first duration.

[0123] For example, the light emission is controlled by the EM control signal at a screen brightness value of 2 nit, the EM control signal adopts 1440Hz PWM dimming, the display refresh rate is 120Hz, the anode reset frequency is 120Hz, the display period of one frame of picture includes 12 EM cycles, the first level stage is the high level stage, and the second level stage is the low level stage. The light emission effect diagram of the EM control signal driving the pixel can be as shown in Figure 9 , wherein the 12 EM cycles (such as Figure 9 EM cycle 1, EM cycle 2, …, EM cycle 12) each include a high level stage and a low level stage (for the convenience of reading the figure, the high and low level stages are not shown in Figure 9 , and for this, please refer to Figure 5 ). As shown in Figure 9 , compared with the duration of the low level stage (i.e. the second duration described above) of other EM cycles (such as the second control period described above), the duration of the low level stage (i.e. the third duration described above) in the EM cycle 1 (i.e. the first control period described above) and the EM cycle 1 after the EM cycle 1 (i.e. the third control period described above) for anode reset is longer, so after completing the anode reset, the electronic device can switch to the low level stage to start charging the devices such as EL capacitor, pixel circuit anode, etc. in advance, so that the light emission amount of the pixel in the first low level stage after the anode reset is equal to or close to the light emission amount of the pixel in other low level stages; and as shown in Figure 9 , the electronic device can enter the second low level stage after the anode reset in advance to perform light emission compensation, so as to ensure that the light emission amount in this stage is equal to or close to the light emission amount of the pixel in other low level stages.

[0124] In some embodiments, in the example shown in Figure 9 , the duration of the low level stage (i.e. the low level stage 1) in the EM cycle 1 and the duration of the low level stage (i.e. the low level stage 2) in the EM cycle 2 can be the same or different, and so on.

[0125] It should be noted that the present application Figure 5 ,Figure 6 and Figure 9 The examples shown in FIGS. 1-3 only illustrate the light-emitting effect of the pixel driven by the EM control signal with 1440Hz PWM dimming, 120Hz display refresh rate, 120Hz anode reset frequency, and one frame of display period including 12 EM periods. The present application Figure 7 and Figure 8 The examples shown in FIGS. 1-3 only illustrate the light-emitting effect of the pixel driven by the EM control signal with 1440Hz PWM dimming, 120Hz display refresh rate, 120Hz anode reset frequency, and one frame of display period including 12 EM periods. The present application

[0126] It can be understood that, based on the scheme provided in Embodiment 1 of the present application, the electronic device flexibly configures the duty cycle in each control period of the display period to be non-uniform, such as making the time length of the low level stage of some insufficient brightness control period longer than that of other low level stages, to ensure that each pixel of the display screen can maintain normal light emission in each low level stage, and make the light emission amount of each low level stage the same or close, thereby ensuring uniform light emission of multiple low level stages in the same display period.

[0127] For example, compared with the EM control signal shown in FIG. 1, Figure 2 the EM control signal shown in FIG. 2, Figure 5 and Figure 7 the time length of the first low level stage after anode reset is longer than that of other low level stages, so that after charging the EL capacitor, the pixel circuit anode and other devices, there is still sufficient low level duration to ensure the light emission amount of the pixel in this stage, so that the light emission amount is equal to or close to that of the pixel in other low level stages. Based on this, compared with the display effect shown in FIG. 1, Figure 2 the display effect shown in FIG. 2, Figure 5 and Figure 7 in the first low level stage after anode reset, each pixel of the display screen normally emits light and the light-emitting effect is basically consistent with that of other low level stages in the same display period.

[0128] For another example, compared with the EM control signal shown in FIG. 1, Figure 2 the EM control signal shown in FIG. 3, Figure 6 and Figure 8The first low level stage after anode reset in the EM control signal is used to charge the EL capacitor, the anode of the pixel circuit and other devices, and the first low level stage after anode reset in the original EM control signal is used for light emission. Therefore, after the charging of the EL capacitor, the anode of the pixel circuit and other devices is completed, there is still sufficient low level duration to ensure the light emission of the pixel in this stage, so that the light emission of the pixel is equal to or close to the light emission of the pixel in other low level stages. Based on this, compared with the display effect shown in the prior art, the display effect shown in the embodiment of the present application is more uniform. Figure 2 The display effect shown in the embodiment of the present application is more uniform. Figure 6 In the first EM period, each pixel of the display screen normally emits light and is basically consistent with the light emission effect of other low level stages in the same display period. Figure 8 In the first EM period, the fifth EM period and the ninth EM period, each pixel of the display screen normally emits light and is basically consistent with the light emission effect of other low level stages in the same display period.

[0129] For example, compared with the display effect shown in the prior art, the display effect shown in the embodiment of the present application is more uniform. Figure 2 The EM control signal shown in the embodiment of the present application is more uniform. Figure 9 The first low level stage and the second low level stage after anode reset in the EM control signal are longer than other low level stages, so that after the charging of the EL capacitor, the anode of the pixel circuit and other devices is completed, there is still sufficient low level duration to ensure the light emission of the pixel in the first low level stage, so that the light emission of the pixel is equal to or close to the light emission of the pixel in other low level stages; and by entering the second low level stage after anode reset in advance, the light emission in the second low level stage can be ensured to be equal to or close to the light emission of the pixel in other low level stages. Based on this, compared with the display effect shown in the prior art, the display effect shown in the embodiment of the present application is more uniform. Figure 2 The display effect shown in the embodiment of the present application is more uniform. Figure 9 In the first low level stage and the second low level stage after anode reset, each pixel of the display screen normally emits light and is basically consistent with the light emission effect of other low level stages in the same picture frame.

[0130] Embodiment 2:

[0131] In the embodiment 2, when the electronic device displays a picture frame based on the pixel circuit, a display period of one picture frame usually includes a plurality of continuous control periods. Among them, the pixel circuit includes a light-emitting control circuit and a reset circuit (such as a source reset circuit or a drain reset circuit of a driving thin film transistor (DTFT)), the light-emitting control circuit is configured to receive a light-emitting control signal, such as an EM control signal; the reset circuit is configured to receive a reset control signal, such as a source reset circuit configured to receive a source reset control signal or a drain reset circuit configured to receive a drain reset control signal; that is, the pixel circuit can receive the EM control signal to control the light-emitting according to the time length of the level stage not used for light-emitting and the time length of the level stage used for light-emitting in the plurality of control periods; the reset circuit can control whether the plurality of control periods are used for reset according to the reset control signal, such as controlling whether the plurality of control periods are used for source reset according to the source reset control signal or controlling whether the plurality of control periods are used for drain reset according to the drain reset control signal.

[0132] In some embodiments, the plurality of control periods included in the display period of the pixel circuit have the same time length, and each of the plurality of control periods includes a first level stage and a second level stage, that is, each control period includes a first level stage and a second level stage, wherein the first level stage is a level stage used for reset (such as a source reset circuit or a drain reset circuit), and the second level stage is a level stage used for light-emitting.

[0133] In some embodiments, the first level stage is a high level stage, and the second level stage is a low level stage; or the first level stage is a low level stage, and the second level stage is a high level stage, which is not limited in the embodiments of the present application. The following embodiments take the first level stage as a high level stage and the second level stage as a low level stage as an example.

[0134] In the embodiment 1 of the present application, the electronic device configures the time length of the first level stage in the plurality of control periods of the display period based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light-emitting control signal, and then controls the light-emitting according to the time length of the first level stage and the time length of the second level stage in the plurality of control periods.

[0135] As an example, the plurality of control periods include a refresh frame period and a hold frame period, such as one refresh frame period and one or more hold frame periods. The refresh frame period is used for display refresh and gate reset, and the hold frame period is used for display holding. The electronic device can perform differential driving in the refresh frame period and each hold frame period (for the case of multiple hold frame periods) in the display period of a picture frame based on the reset frequency corresponding to the reset control signal and / or the display refresh rate corresponding to the light emission control signal, such as adjusting the duration of the first level stage in each hold frame period based on different reset frequencies and / or different refresh rates.

[0136] After adjusting the duration of the first level stage in each hold frame period, the electronic device can perform display refresh and reset when entering the first level stage of the refresh frame period, and control light emission according to the duration of the first level stage and the duration of the second level stage in the first level stage and the second level stage in the plurality of control periods (including the refresh frame period and the hold frame period), such as not emitting light when entering the first level stage of the refresh frame period, emitting light when entering the second level stage of the refresh frame period, then not emitting light when entering the first level stage of the hold frame period, and emitting light when entering the second level stage of the hold frame period.

[0137] In some examples, the plurality of control periods include a refresh frame period but do not include a hold frame period. For this case, the electronic device can only set the duration of the first level stage in the refresh frame period.

[0138] For example, in Embodiment 2, the duration of the first level stage (such as the high level stage) in the hold frame period in the display period can be reduced based on different reset frequencies and / or different display refresh rates, so that the duty cycles under different display refresh rates and / or different reset frequencies are all maintained at a high level to optimize screen flicker, and so that the duty cycles under different display refresh rates and / or different reset frequencies are substantially equivalent (such as a difference less than a preset threshold) to achieve better display and eye protection effects.

[0139] In some embodiments, the scheme provided in Embodiment 2 can be applied to a scenario in which the screen brightness value is greater than a second brightness threshold, where the second brightness threshold is greater than the first brightness threshold. For example, the second brightness threshold is 90 nit, and the scheme provided in Embodiment 2 can be applied to a high brightness scenario. The specific value of the second brightness threshold is not specifically limited.

[0140] It can be understood that, taking the light-emitting control signal as an example of the EM control signal, one display period of a picture frame usually includes multiple EM periods. For example, the number N of EM periods included in one display period is F1 / F2, where 1 EM period is a refresh frame period, N-1 EM periods are hold frame periods, F1 is the source reset frequency or the drain reset frequency, and F2 is the display refresh rate. In the refresh frame period of the display period, display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are usually performed, and in the hold frame period of the display period, display refresh, gate reset, source reset / drain reset, threshold compensation, etc. are usually not performed.

[0141] For example, taking the source reset frequency or the drain reset frequency as 360 Hz and the display refresh rate as 120 Hz, N = 360 Hz / 120 Hz = 3, that is, one display period of a picture frame includes 3 EM periods, where the first EM period is a refresh frame period, and the other 2 EM periods are hold frame periods; for example, taking the source reset frequency or the drain reset frequency as 360 Hz and the display refresh rate as 60 Hz, N = 360 Hz / 60 Hz = 6, that is, one display period of a picture frame includes 6 EM periods, where the first EM period is a refresh frame period, and the other 5 EM periods are hold frame periods; and so on. For example, taking the source reset frequency or the drain reset frequency as 360 Hz and the display refresh rate as 1 Hz, N = 360 Hz / 1 Hz = 360, that is, one display period of a picture frame includes 360 EM periods, where the first EM period is a refresh frame period, and the other 359 EM periods are hold frame periods.

[0142] For example, taking the source reset frequency or the drain reset frequency as 240 Hz and the display refresh rate as 120 Hz, N = 240 Hz / 120 Hz = 2, that is, one display period of a picture frame includes 2 EM periods, where the first EM period is a refresh frame period, and the second EM period is a hold frame period; for example, taking the source reset frequency or the drain reset frequency as 240 Hz and the display refresh rate as 60 Hz, N = 240 Hz / 60 Hz = 4, that is, one display period of a picture frame includes 4 EM periods, where the first EM period is a refresh frame period, and the other 3 EM periods are hold frame periods; and so on. For example, taking the source reset frequency or the drain reset frequency as 240 Hz and the display refresh rate as 1 Hz, N = 240 Hz / 1 Hz = 240, that is, one display period of a picture frame includes 240 EM periods, where the first EM period is a refresh frame period, and the other 239 EM periods are hold frame periods.

[0143] It should be noted that the embodiments of the present application do not limit whether the display period includes the hold frame period, and in some cases, one display period of a picture frame can also not include the hold frame period.

[0144] For example, taking the source reset frequency or the drain reset frequency as 120 Hz and the display refresh rate as 120 Hz as an example, N = 120 Hz / 120 Hz = 1, that is, one display period of a picture frame includes 1 EM period, and the 1 EM period is a refresh frame period; taking the source reset frequency or the drain reset frequency as 120 Hz and the display refresh rate as 60 Hz as an example, N = 120 Hz / 60 Hz = 2, that is, one display period of a picture frame includes 2 EM periods, and the 1st EM period is a refresh frame period and the 2nd EM period is a hold frame period; taking the source reset frequency or the drain reset frequency as 120 Hz and the display refresh rate as 1 Hz as an example, N = 120 Hz / 1 Hz = 120, that is, one display period of a picture frame includes 120 EM periods, and the 1st EM period is a refresh frame period and the other 119 EM periods are hold frame periods.

[0145] In a conventional method, the time length of the first level stage (for example, the high level stage) in the refresh frame period and the hold frame period is usually consistent, and the time length of the second level stage (for example, the low level stage) is also usually consistent, so as to ensure that the time length of the display screen emitting light in the refresh frame period and the hold frame period is consistent, and then a uniform dimming effect is achieved. However, the conventional method needs to occupy a relatively long time for display refresh, gate reset, source reset / drain reset, threshold compensation and the like in the refresh frame period, and the result is that the total time length of the display period in the bright screen is shortened, which will cause the SVM to increase, that is, the problem of too strong flicker of the picture.

[0146] In order to solve the above problem, in some embodiments, the electronic device can configure the time length of the first level stage (for example, the high level stage) in the refresh frame period and the hold frame period to be less than the time length of the first level stage in the refresh frame period, and at the same time, the total time length of the second level stage in the display period under different display refresh rates / reset frequencies is equal or close. It can be understood that after reducing the time length of the first level stage in the hold frame period, the time length of the second level stage in the hold frame period is increased accordingly, the total time length of the display period in the bright screen is increased, the SVM is reduced, the screen flicker is optimized, and better display and eye protection effects are achieved.

[0147] As an example, the electronic device can configure the time length of the first level stage in the refresh frame period in the display period as a fourth time length, and configure the time length of the first level stage in the hold frame period as a fifth time length, where the fifth time length is less than the fourth time length. Taking the fourth time length as 80H as an example, the fifth time length is, for example, a value between 36H and 75H. In some embodiments, the difference between the fourth time length and the fifth time length is greater than or equal to 1H.

[0148] For example, when the first voltage level stage is a high voltage level stage and the second voltage level stage is a low voltage level stage, in some embodiments, the magnitude of the decrease in the length of the high voltage level stage in the sustain frame period compared to the length of the high voltage level stage in the refresh frame period can be related to one or more of the following factors: the specific properties of the display screen, the display refresh rate, the source reset frequency, or the drain reset frequency, etc. For example, the specific properties of the display screen, such as the type, structure, or material of the display panel, etc.; the display refresh rate, such as 120Hz, 60Hz, 1Hz, etc., without limitation; the source reset frequency or the drain reset frequency, such as 120Hz, 240Hz, 360Hz, etc., without limitation.

[0149] In some embodiments, when the screen brightness value, the specific properties of the display screen, and other factors such as the reset frequency remain unchanged, the magnitude of the adjustment in the length of the first voltage level stage in the sustain frame period is different for different display refresh rates.

[0150] For example, when the screen brightness value, the specific properties of the display screen, and other factors such as the reset frequency remain unchanged, the length of the high voltage level stage in the refresh frame period is a fourth length and the length of the high voltage level stage in the sustain frame period is a fifth length when the display refresh rate is a first refresh rate, and the length of the high voltage level stage in the refresh frame period is the fourth length and the length of the high voltage level stage in the sustain frame period is a sixth length when the display refresh rate is a second refresh rate. The first refresh rate is greater than the second refresh rate, the sixth length is greater than the fifth length, and the fifth length and the sixth length are, for example, a value between 36H and 75H.

[0151] In some embodiments, when the screen brightness value, the specific properties of the display screen, and other factors such as the display refresh rate remain unchanged, the magnitude of the adjustment in the length of the first voltage level stage in the sustain frame period is different for different reset frequencies.

[0152] For example, when the screen brightness value, the specific properties of the display screen, and other factors such as the display refresh rate remain unchanged, the length of the high voltage level stage in the refresh frame period is a fourth length and the length of the high voltage level stage in the sustain frame period is a seventh length when the reset frequency is a first frequency, and the length of the high voltage level stage in the refresh frame period is the fourth length and the length of the high voltage level stage in the sustain frame period is an eighth length when the reset frequency is a second frequency. The first frequency is greater than the second frequency, the eighth length is less than the fourth length, the ninth length is less than the fourth length, the eighth length is different from the ninth length, and the eighth length and the ninth length are, for example, a value between 36H and 75H. For example, the eighth length is less than or equal to the ninth length.

[0153] Exemplarily, taking 500 nit screen brightness value, EM control signal using 1440 Hz PWM dimming, reset frequency being 360 Hz, the first level stage being the high level stage, the second level stage being the low level stage, and the time length of the high level stage in the refresh frame period being 80H as an example, the time length of the high level stage in the refresh frame period and the hold frame period under different display refresh rates can be as shown in the following Table 1:

[0154] Table 1

[0155]

[0156] In addition, exemplarily, taking 500 nit screen brightness value, EM control signal using 1440 Hz PWM dimming, reset frequency being 240 Hz, the first level stage being the high level stage, the second level stage being the low level stage, and the time length of the high level stage in the refresh frame period being 80H as an example, the time length of the high level stage in the refresh frame period and the hold frame period under different display refresh rates can be as shown in the following Table 2:

[0157] Table 2

[0158]

[0159] In addition, exemplarily, taking 500 nit screen brightness value, EM control signal using 1440 Hz PWM dimming, reset frequency being 120 Hz, the first level stage being the high level stage, the second level stage being the low level stage, and the time length of the high level stage in the refresh frame period being 80H as an example, the time length of the high level stage in the refresh frame period and the hold frame period under different display refresh rates can be as shown in the following Table 3:

[0160] Table 3

[0161]

[0162] It should be noted that Table 1, Table 2 and Table 3 are only used as example values of dynamic adjustment of the hold frame period under different reset frequencies and display refresh rates, and in actual application, the adjustment range of the hold frame period compared with the refresh frame period can also be other differences, which are not limited in the embodiments of the present application, and are determined according to actual conditions.

[0163] In addition, Table 1, Table 2 and Table 3 respectively show example values of dynamic adjustment of the hold frame period when the reset frequency is 360 Hz, 240 Hz and 120 Hz, and the display refresh rate is 120 Hz, 60 Hz and 1 Hz, respectively, and in actual application, the reset frequency can also be 480 Hz, 600 Hz, 720 Hz and other frequencies, and the display refresh rate can also be 180 Hz, 240 Hz and other values, which are not limited in the embodiments of the present application, and are determined according to actual conditions.

[0164] It is understood that, based on the solution provided in Embodiment 2 of this application, after optimizing (e.g., shortening) the duration of the high-level phase in the hold frame period, the high-level phase in the refresh frame period, which requires display refresh, gate reset, source / drain reset, and threshold compensation, is longer than that in the hold frame period, which does not require display refresh, gate reset, source / drain reset, and threshold compensation. Therefore, not only can normal display refresh, gate reset, source / drain reset, and threshold compensation be guaranteed in the refresh frame period, but a high and comparable duty cycle can also be maintained under different display refresh rates and / or different reset frequencies to optimize SVM and achieve better high-brightness display effects. For example, compared to similar... Figure 3 The scheme shown in Embodiment 2 of this application, which ensures that the duration of the high-level phase is equal in each EM cycle of the display period, can achieve a higher duty cycle. Furthermore, the scheme provided in Embodiment 2 of this application maintains the difference in duty cycle of the display period under different reset frequencies and / or different display refresh rates within a range of less than 0.2% by differently configuring the duration of the high-level phase in the refresh frame cycle and the hold frame cycle.

[0165] For example, please refer to Figure 10 , Figure 10 Taking the scheme shown in Table 1 as an example, a schematic diagram of the driving principle of an EM driving signal provided in an embodiment of this application is illustrated. Taking a source reset frequency or drain reset frequency of 360Hz as an example, ... Figure 10 As shown, when the display refresh rate is 120Hz, according to the formula N = F1 / F2, the display cycle of one frame includes 3 (i.e., N = 360Hz / 120Hz = 3) EM cycles, of which 1 is the refresh frame cycle and the other 2 (i.e., N-1 = 2) are hold frame cycles; when the display refresh rate is 60Hz, according to the formula N = F1 / F2, the display cycle of one frame includes 6 (i.e., N = 360Hz / 60Hz = 6) EM cycles, of which 1 is the refresh frame cycle and the other 5 (i.e., N-1 = 5) are hold frame cycles; when the display refresh rate is 1Hz, according to the formula N = F1 / F2, the display cycle of one frame includes 360 (i.e., N = 360Hz / 1Hz = 360) EM cycles, of which 1 is the refresh frame cycle and the other 359 (i.e., N-1 = 359) are hold frame cycles. Since gate reset, source / drain reset, threshold compensation, etc., do not occur during the frame period, it is unnecessary to maintain the same high-level phase duration as in the refresh frame period. Figure 10As shown, after the duration of the high level stage of the refresh frame period is optimized (e.g., reduced) based on the scheme provided in Embodiment 2 of the present application, the duration of the high level stage of the refresh frame period, which needs to perform display refresh, gate reset, source reset / drain reset, threshold compensation and the like, is longer than that of the hold frame period, which does not need to perform display refresh, gate reset, source reset / drain reset and the like. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation and the like in the refresh frame period be ensured, but also the difference between the duty cycles of the display period at different display refresh rates when the source reset frequency or the drain reset frequency is 360Hz can be maintained within a very small range through the differential configuration of the duration of the high level stage in the refresh frame period and the hold frame period.

[0166] As an example, the duty cycle r of the display period can be calculated based on the following formula: r = [120 / F2*number of rows of light emitting array - first duration - second duration*(F1 / F2-1)] / (120 / F2*number of rows of light emitting array), where F1 is the source reset frequency or the drain reset frequency, F2 is the display refresh rate, and the number of rows of light emitting array is, for example, the number of rows of screen light emitting array, or for the case where the display screen includes front and rear porch light emitting arrays, the number of rows of light emitting array = number of rows of screen light emitting array + number of rows of front and rear porch light emitting arrays.

[0167] As shown in Table 1, taking the number of rows of light emitting array as 3120 as an example, in the case where the source reset frequency or the drain reset frequency is 360Hz, after the duration of the high level stage of the hold frame period is optimized (e.g., reduced) based on the scheme provided in Embodiment 2 of the present application, the duty cycle of the display screen is 95.13% when the display refresh rate is 120Hz, the duty cycle of the display screen is 95.11% when the display refresh rate is 60Hz, and the duty cycle of the display screen is 95.18% when the display refresh rate is 1Hz. The duty cycle can be maintained within the range of 95.1% to 95.2%, which is greatly improved compared to the duty cycle (e.g., 94%) of the similar scheme. Figure 3 Since high-brightness scenes have higher requirements for luminance values, the scheme shown in Table 1 can maintain a higher duty cycle to optimize the SVM and achieve better high-brightness display effects. Moreover, as shown in Table 1, the difference between the duty cycles of the display period at different display refresh rates is maintained within a range of less than 0.2%, so that the overall picture display effect is not greatly different for users when the display refresh rate changes.

[0168] For example, please refer to Figure 11 , Figure 11 For example, taking the scheme shown in Table 2 as an example, a light emitting control principle diagram of an EM control signal is shown. Taking the source reset frequency or the drain reset frequency as 240Hz as an example, as shown in Figure 11As shown, when the display refresh rate is 120Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 2 (i.e. N=240Hz / 120Hz=2) EM periods, one of which is a refresh frame period, and the other one (i.e. N-1=1) is a holding frame period; when the display refresh rate is 60Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 4 (i.e. N=240Hz / 60Hz=4) EM periods, one of which is a refresh frame period, and the other 3 (i.e. N-1=3) are holding frame periods; when the display refresh rate is 1Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 240 (i.e. N=240Hz / 1Hz=240) EM periods, one of which is a refresh frame period, and the other 239 (i.e. N-1=239) are holding frame periods. Since no gate reset, source reset / drain reset, threshold compensation, etc. is performed in the holding frame period, it is unnecessary to maintain the time length of the high level stage consistent with that in the refresh frame period, such as Figure 11 As shown, based on the scheme provided in Embodiment 2 of the present application, the time length of the high level stage in the holding frame period is optimized (e.g. reduced), and compared with the holding frame period which does not need to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc., the time length of the high level stage in the refresh frame period which needs to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer. Based on this, not only can normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period be ensured, but also by differentiating the time length of the high level stage in the refresh frame period and the holding frame period, the difference between the duty cycles of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 240Hz can be maintained within a range of less than 0.2%.

[0169] As shown in Table 2, taking the number of light emitting array rows as 3120 as an example, in the case where the source reset frequency or the drain reset frequency is 240Hz, based on the scheme provided in Embodiment 2 of the present application, the time length of the high level stage in the holding frame period is optimized (e.g. shortened), and when the display refresh rate is 120Hz, the duty cycle of the display screen is 96.28%, when the display refresh rate is 60Hz, the duty cycle of the display screen is 96.27%, and when the display refresh rate is 1Hz, the duty cycle of the display screen is 96.28%, the duty cycle can be maintained between 96.2% and 96.3%, compared with similar Figure 3The duty cycle of the scheme shown (such as 94.9%) is greatly improved. Since the high brightness scene has a higher requirement for the brightness value, a higher duty cycle can be maintained based on the scheme shown in Table 2 to optimize the SVM and achieve better high brightness display effect. Moreover, as shown in Table 2, the difference in the duty cycle of the display period under different display refresh rates is maintained within a range of less than 0.2%, so that the overall picture display effect can be ensured to be not much different for the user when the display refresh rate changes.

[0170] For example, please refer to Figure 12 , Figure 12 For example, taking the scheme shown in Table 3 as an example, a driving principle schematic diagram of a light emitting control signal provided by an embodiment of the present application is shown. Taking the source reset frequency or the drain reset frequency as 120Hz for example, as shown in Figure 12 , when the display refresh rate is 120Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 1 (i.e. N=120Hz / 120Hz=1) EM period, which is a refresh frame period; when the display refresh rate is 60Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 2 (i.e. N=120Hz / 60Hz=2) EM periods, of which 1 is a refresh frame period and the other 1 (i.e. N-1=1) is a hold frame period; when the display refresh rate is 1Hz, according to the above formula N=F1 / F2, it can be known that the display period of one frame of picture includes 120 (i.e. N=120Hz / 1Hz=120) EM periods, of which 1 is a refresh frame period and the other 119 (i.e. N-1=119) is a hold frame period. Since the hold frame period does not perform gate reset, source reset / drain reset, threshold compensation, etc., it is not necessary to maintain the time length of the high level stage consistent with that in the refresh frame period, as shown in Figure 12 , after the time length of the high level stage in the hold frame period is optimized (such as reduced) based on the scheme provided by Embodiment 2 of the present application, the time length of the high level stage in the refresh frame period which needs to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc. is longer than that in the hold frame period which does not need to perform display refresh, gate reset, source reset / drain reset, threshold compensation, etc. Based on this, not only can the normal display refresh, gate reset, source reset / drain reset, threshold compensation, etc. in the refresh frame period be ensured, but also the difference in the duty cycle of the display period under different display refresh rates when the source reset frequency or the drain reset frequency is 120Hz can be maintained within a range of less than 0.2% through the differential configuration of the time length of the high level stage in the refresh frame period and the hold frame period.

[0171] As shown in Table 3, taking the number of light-emitting array rows as 3120 as an example, in the case where the source reset frequency or the drain reset frequency is 120 Hz, the duration of the high level stage in the refresh frame period is optimized (e.g., reduced) based on the scheme provided in Embodiment 2 of the present application, and when the display refresh rate is 120 Hz, the duty cycle of the display screen is 97.44%, when the display refresh rate is 60 Hz, the duty cycle of the display screen is 97.60%, and when the display refresh rate is 1 Hz, the duty cycle of the display screen is 97.59%, the duty cycle can be maintained between 97.4% and 97.6%, which is greatly improved compared to the duty cycle of the similar Figure 3 As shown in Table 3, taking the number of light-emitting array rows as 3120 as an example, in the case where the source reset frequency or the drain reset frequency is 120 Hz, the duration of the high level stage in the refresh frame period is optimized (e.g., reduced) based on the scheme provided in Embodiment 2 of the present application, and when the display refresh rate is 120 Hz, the duty cycle of the display screen is 97.44%, when the display refresh rate is 60 Hz, the duty cycle of the display screen is 97.60%, and when the display refresh rate is 1 Hz, the duty cycle of the display screen is 97.59%, the duty cycle can be maintained between 97.4% and 97.6%, which is greatly improved compared to the duty cycle of the similar

[0172] It should be noted that, Figure 10 , Figure 11 , Figure 12 Only taking the case where the screen brightness value is 500 nit, the EM control signal adopts 1440 Hz PWM dimming, and the duration of the high level stage of the refresh frame period is 80H as an example, the driving principle schematic of the light-emitting control signal under different source reset frequencies or drain reset frequencies and different display refresh rates is shown, in actual applications, the screen brightness value can also be other values such as 21 nit, 249 nit, 1200 nit, etc., the dimming frequency of the EM control signal can also be other values, and the duration of the high level stage of the refresh frame period can also be other values, the embodiments of the present application are not limited thereto, and are determined according to specific circumstances.

[0173] As a possible implementation manner, the process of driving the pixel circuit by the EM control signal can be divided into the following four stages:

[0174] Stage 1: gate reset (also referred to as “gate initialization”) stage.

[0175] Stage 1 is usually performed in the first level stage of the refresh frame period, taking the case where the first level stage of the refresh frame period is the high level stage and the second level stage of the refresh frame period is the low level stage as an example, the gate reset stage is usually performed in the high level stage of the refresh frame period.

[0176] In some embodiments, the first level stage can also be used for data writing, such as interface data of a picture to be displayed, for display refresh, without limitation.

[0177] Taking the pixel circuit as shown in Figure 13The driving timing of the pixel circuit corresponding to the refresh frame period is shown in FIG. 6. Figure 14 For example, the first level stage is a high level stage and the second level stage is a low level stage, please refer to FIG. 6. Figure 14 , Figure 14 FIG. 6 shows a driving timing diagram of a pixel circuit provided by an embodiment of the present application. In FIG. 6, Figure 14 T1-T8 are thin film transistors (TFTs), and Figure 14 T1 can be a DTFT, N1-N3 are nodes in the circuit, C1 is a capacitor, Em is a light emitting control signal received by the circuit, S1n-S4n are control signals received by the circuit for resetting and data writing, ELVDD and ELVSS are working voltages, Vinit1-Vinit3 are reset voltages, and Vdata is used to control the current flowing through the TFT to drive the pixel circuit to emit light with different brightness. As shown in FIG. 6, Figure 14 In the refresh frame period, Figure 13 EM is first set to high level to close the light emitting path, and then S2n and S4n are sequentially switched from low level to high level to realize Figure 13 the initialization of the N1 node.

[0178] For example, in the refresh frame period, Figure 13 the switching frequency of EM can be 360Hz, and then the light emitting control signal received by the light emitting control circuit (such as the circuit including the circuit receiving the light emitting control signal (EM signal) and the TFTs T5 and T6 shown in FIG. 6) can be as shown in FIG. 6; for another example, Figure 13 the switching frequency of EM can be 240Hz, and then the light emitting control signal received by the light emitting control circuit can be as shown in FIG. 6; for another example, Figure 10 the switching frequency of EM can be 120Hz, and then the light emitting control signal received by the light emitting control circuit can be as shown in FIG. 6. Figure 13 Figure 11 Figure 13 Figure 12

[0179] In some embodiments, Figure 13 the switching frequency of EM can be the same as the drain reset frequency or the source reset frequency, but the embodiments of the present application are not limited thereto, for example, in some embodiments, the switching frequency of EM can also be different from the drain reset frequency and the source reset frequency, which can be determined according to specific conditions.

[0180] Stage 2: threshold compensation and data writing stage.

[0181] Stage 2 is mainly used for threshold compensation and data writing of T1, for example, T1 can be a DTFT, and the data can be brightness data, etc.​​​​

[0182] As shown in the pixel circuit in FIG. 1, the driving timing of the pixel circuit corresponding to the refresh frame period is as shown in FIG. 2, and the first level stage is a high level stage and the second level stage is a low level stage. Figure 13 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 14 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 14 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 13 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written.

[0183] Stage 3: Drain and anode reset stage.

[0184] As shown in the pixel circuit in FIG. 1, the driving timing of the pixel circuit corresponding to the refresh frame period is as shown in FIG. 2, and the first level stage is a high level stage and the second level stage is a low level stage. Figure 13 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 14 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 14 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written. Figure 13 As shown in FIG. 2, in the refresh frame period, when S2n is at a high level and S1n is at a low level, the threshold of T1 as shown in FIG. 1 is compensated and the luminance data is written.

[0185] For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 13 For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 10 For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 13 For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 11 For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 13 For example, the switching frequency of S3n can be maintained at 360 Hz, that is, the reset frequency of the N2 node is 360 Hz, and the luminous control signal received by the luminous control circuit can be as shown in FIG. 6. Figure 12 In the present embodiment, when S3n is at a low level, the anode of the circuit as shown in FIG. 1 is reset, and the anode reset is consistent with the reset frequency of the N2 node, such as both being 360 Hz. Figure 13 In the present embodiment, when S3n is at a low level, the anode of the circuit as shown in FIG. 1 is reset, and the anode reset is consistent with the reset frequency of the N2 node, such as both being 360 Hz. Figure 13 In the present embodiment, when S3n is at a low level, the anode of the circuit as shown in FIG. 1 is reset, and the anode reset is consistent with the reset frequency of the N2 node, such as both being 360 Hz.

[0186] Stage 4: Luminous stage.

[0187] The stage 4 is usually performed in the second voltage level stage of the refresh frame period. For example, the first voltage level stage of the refresh frame period is the high voltage level stage, the second voltage level stage of the refresh frame period is the low voltage level stage, and the pixel emits light in the low voltage level stage.

[0188] For example, the pixel circuit is as shown in Figure 13 The driving timing of the pixel circuit corresponding to the refresh frame period is as shown in Figure 14 For example, the first voltage level stage is the high voltage level stage, and the second voltage level stage is the low voltage level stage. As shown in Figure 14 In the refresh frame period, the EM is set to the low voltage level and the Figure 13 T5 and T6 are turned on, at this time, the pixel emits light.

[0189] For example, in the refresh frame period, the switching frequency of the EM is the same as the drain reset frequency, for example, 360 Hz. As shown in Figure 13 The light emission control signal received by the light emission control circuit can be as shown in Figure 10 For example, in the refresh frame period, the switching frequency of the EM is the same as the drain reset frequency, for example, 240 Hz. As shown in Figure 13 The light emission control signal received by the light emission control circuit can be as shown in Figure 11 For example, in the refresh frame period, the switching frequency of the EM is the same as the drain reset frequency, for example, 120 Hz. As shown in Figure 13 The light emission control signal received by the light emission control circuit can be as shown in Figure 12

[0190] It should be noted that Figure 13 Only as an example of a pixel circuit, other types of pixel circuits can also be used in actual applications; and Figure 14 Only the pixel circuit as shown in Figure 13 is used as an example to introduce a possible driving timing of the refresh frame. In actual applications, the pixel circuit can also be driven by other driving timing. The pixel circuit and the driving timing are not limited in the embodiments of the present application, and are determined according to specific conditions.

[0191] It can be understood that, as shown in Figure 14 In the refresh frame period, the first voltage level stage (for example, the high voltage level stage) needs to last for a long time because of the reset and threshold compensation, for example, as shown in Figure 14 ​As shown in FIG. 8OH, in the holding frame period, since only light emission needs to be performed, reset, threshold compensation, etc. do not need to be performed as in the refresh frame period, the duration of the first level stage (e.g. high level stage) of the holding frame period can be adaptively dynamically adjusted compared to the refresh frame period, while ensuring normal light emission of the pixel circuit, the light emission duty cycle is improved to optimize screen flicker, and the duty cycles at different display refresh rates and / or different reset frequencies are kept substantially the same (e.g. difference less than a preset threshold), avoiding flicker when the display refresh rate or reset frequency is switched, achieving better display and eye protection effects.

[0192] For example, for a pixel circuit as shown in FIG. 1, the first level stage is a high level stage, the second level stage is a low level stage, and the drain reset frequency (or source reset frequency for some other pixel circuits) is 360 Hz, the driving timing of the pixel circuit corresponding to the holding frame period can be as shown in FIG. 8OH. Figure 13 For example, for a pixel circuit as shown in FIG. 1, the first level stage is a high level stage, the second level stage is a low level stage, and the drain reset frequency (or source reset frequency for some other pixel circuits) is 360 Hz, the driving timing of the pixel circuit corresponding to the holding frame period can be as shown in FIG. 8OH. Figure 15 As shown in FIG. 8OH, in the holding frame period, first Figure 15 As shown in FIG. 8OH, in the holding frame period, first Figure 13 The pixel circuit as shown in FIG. 8OH can set EM to high level and keep S1n at high level, S2n and S4n at low level, then Figure 13 The pixel circuit as shown in FIG. 8OH can set EM to low level and keep S3n at high level, then Figure 13 The pixel circuit as shown in FIG. 8OH can set EM to low level and keep S3n at high level, then Figure 13 The pixel circuit as shown in FIG. 8OH can set EM to low level and keep S3n at high level, then Figure 14 Based on this, compared to the driving timing of the refresh frame period as shown in FIG. 8OH, by reducing the duration of the first level stage (i.e. high level stage) of the holding frame period from 80H to a range of 36H-50H, not only can the reset function of the pixel circuit in the holding frame period be ensured, but also the duty cycle can be improved to achieve a smaller SVM value (e.g. reduced to 0.23, etc. without limitation), thereby optimizing screen flicker, and the total duty cycle of EM at different display refresh rates is less than a preset threshold, e.g. the duty cycle is maintained between 95.1%-95.2% as shown in Table 1, to achieve better display and eye protection effects.

[0193] As an example, for a screen brightness value of 500 nit, EM control signal of 360 Hz, source reset frequency or drain reset frequency of 360 Hz, and duration of high level stage of refresh frame period of 80H, as shown in Table 1, if the display refresh rate is 120 Hz, the duration of the first level stage (e.g. high level stage) of the holding frame period can be 36H; if the display refresh rate is 60 Hz, the duration of the first level stage (e.g. high level stage) of the holding frame period can be 45H; if the display refresh rate is 1 Hz, the duration of the first level stage (e.g. high level stage) of the holding frame period can be 50H.

[0194] Alternatively, for example, pixel circuitry such as Figure 13 As shown, the first level phase is a high level phase, the second level phase is a low level phase, and the drain reset frequency (which may also be the source reset frequency for some other pixel circuits) is 240Hz. For example, the driving timing of the pixel circuit corresponding to the frame period might be as follows: Figure 16 As shown. Figure 16 As shown, during the hold frame period, firstly Figure 13 The pixel circuit shown can set EM to a high level while keeping S1n high, S2n, and S4n low, and then... Figure 13 The pixel circuit shown can be enabled when S3n is set to low. Figure 13 As shown, T7 and T8 are turned on and remain on for 32 hours. Afterwards, while EM is set low and S3n is held high, [the following is a separate, unrelated instruction:] T7 and T8 are turned on and remain on for 32 hours. Figure 13 As shown, T5 and T6 are turned on, and the pixels emit light. Based on this, compared to Figure 14 The driving timing of the refresh frame cycle shown can be reduced from 80H to 36H~58H by decreasing the duration of the first level phase (i.e., the high level phase) of the hold frame cycle from 80H. This not only ensures the reset function of the pixel circuit during the hold frame cycle, but also increases the duty cycle to achieve a smaller SVM value (such as reducing it to 0.18, etc., without limitation). This optimizes screen flicker and ensures that the difference in the total duty cycle of EM is less than the preset threshold under different display refresh rates. For example, the duty cycle is maintained between 96.2% and 96.3% as shown in Table 2, so as to achieve better display and eye protection effects.

[0195] As an example, taking a screen brightness of 500 nits, an EM control signal of 240Hz, a source reset frequency or drain reset frequency of 240Hz, and a high-level phase duration of 80H in the refresh frame cycle as an example, as shown in Table 2, if the display refresh rate is 120Hz, the duration of the first level phase (such as the high-level phase) in the frame cycle can be 36H; if the display refresh rate is 60Hz, the duration of the first level phase (such as the high-level phase) in the frame cycle can be 51H; if the display refresh rate is 1Hz, the duration of the first level phase (such as the high-level phase) in the frame cycle can be 58H.

[0196] Alternatively, exemplarily, the pixel circuitry of the display screen, such as Figure 13 As shown, the first level phase is a high level phase, the second level phase is a low level phase, and the drain reset frequency (which may also be the source reset frequency for some other pixel circuits) is 120Hz. For example, the driving timing of the pixel circuit corresponding to the frame period might be as follows: Figure 17 As shown. Figure 17 As shown, during the hold frame period, firstly Figure 13 The pixel circuit shown can set EM to a high level while keeping S1n high, S2n, and S4n low, and then...Figure 13 The pixel circuit shown can be enabled when S3n is set low. Figure 13 As shown, T7 and T8 are turned on and remain on for 32 hours. Afterwards, while EM is set low and S3n is held high, [the following is a separate, unrelated instruction:] T7 and T8 are turned on and remain on for 32 hours. Figure 13 As shown, T5 and T6 are turned on, and the pixels emit light. Based on this, compared to Figure 14 The driving timing of the refresh frame cycle shown can be improved by reducing the duration of the first level phase (i.e., the high level phase) of the hold frame cycle from 80H to the range of 70H to 75H. This not only ensures the reset function of the pixel circuit during the hold frame cycle, but also increases the duty cycle to optimize screen flicker. The difference in the total duty cycle of EM under different display refresh rates is less than the preset threshold. As shown in Table 3, the duty cycle is maintained between 97.4% and 97.6%, so as to achieve better display and eye protection effects.

[0197] As an example, taking a screen brightness of 500 nits, an EM control signal of 120Hz, a source reset frequency or drain reset frequency of 120Hz, and a high-level phase duration of 80H in the refresh frame cycle as an example, as shown in Table 3, if the display refresh rate is 60Hz, the duration of the first level phase (such as the high-level phase) in the frame cycle can be 70H; if the display refresh rate is 1Hz, the duration of the first level phase (such as the high-level phase) in the frame cycle can be 75H.

[0198] It needs to be explained that, Figure 15 , Figure 16 , Figure 17 Only with Figure 13 The pixel circuit shown is used as an example to illustrate three different driving timing examples for holding frame periods. In practical applications, other types of pixel circuits can also be used, and other driving timings can be used to drive the pixel circuit for a specific pixel circuit. The embodiments of this application do not limit the pixel circuit and driving timing, but depend on the specific situation.

[0199] It should be understood that the various solutions in the embodiments of this application can be used in a reasonable combination, and the explanations or descriptions of the various terms appearing in the embodiments can be referenced or explained to each other in the various embodiments, without limitation.

[0200] It should also be understood that, in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0201] It can be understood that, in order to realize the functions of any one of the above-mentioned embodiments, the electronic device and the like comprises a hardware structure and / or a software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed herein, the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is realized in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0202] The embodiments of the present application can divide the functional modules of the electronic device and the like, for example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated module can be realized in the form of hardware or software functional module. Exemplarily, as shown in Figure 18 The display panel of the electronic device can include an integrated circuit 1810 (such as a driving IC), a gate driving unit 1820, and a pixel circuit 1830, wherein the pixel circuit 1830 includes a light-emitting control circuit and a reset circuit; the light-emitting control circuit is configured to receive a light-emitting control signal and control light-emitting according to the time length of the first level stage and the time length of the second level stage in a plurality of control periods; the reset circuit is configured to receive a reset control signal to control anode reset, gate reset, source reset, or drain reset. The integrated circuit 1810 is configured to: obtain a screen brightness value; and when the screen brightness value is less than a first brightness threshold, configure the time length of the second level stage in the plurality of control periods according to a first control period for anode reset; or when the screen brightness value is greater than a second brightness threshold, configure the time length of the first level stage in the plurality of control periods according to a display refresh rate corresponding to the light-emitting control signal and / or a reset frequency corresponding to the reset control signal

[0203] It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division manner. It should also be understood that each module in the electronic device and the like can be realized in the form of software and / or hardware, and is not specifically limited. In other words, the electronic device and the like is presented in the form of functional modules. The "module" here can refer to an application specific integrated circuit (ASIC), a circuit, a processor and a memory executing one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above-mentioned functions.

[0204] In an alternative, when data transmission is implemented by using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are implemented in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disk (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0205] The steps of methods or algorithms described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable media, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. Alternatively, the processor and the storage medium can reside as discrete components in a computing device. Indeed, the functions of the processor and the storage medium can be provided through the platforms, such as Google and the like, and / or software modules that execute on such platforms.

[0206] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for description, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

Claims

1. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a light-emitting control circuit and an anode reset circuit, the light-emitting control circuit receives a light-emitting control signal, the light-emitting control signal comprises a plurality of control periods, the plurality of control periods comprise a first control period and a second control period, the first control period and the second control period each comprise a first level stage not used for light-emitting and a second level stage used for light-emitting, in the first control period, the anode reset circuit performs anode reset according to an anode reset control signal, in the second control period, the anode reset circuit does not perform the anode reset according to the anode reset control signal, and the method comprises: When the screen brightness is medium or low brightness, the length of the second level stage in the first control period is configured as a first length, and the length of the second level stage in the second control period is configured as a second length, the first length being greater than the second length; The light-emitting control circuit controls light-emitting according to the length of the first level stage and the length of the second level stage in the plurality of control periods.

2. The method of claim 1, wherein, The first control period comprises at least one second level stage, and the first length comprises the total length of the at least one second level stage in the first control period.

3. The method according to claim 1 or 2, characterized in that, The plurality of control periods further comprise a third control period, the third control period being a control period after the first control period, in the third control period, the anode reset circuit does not perform the anode reset according to the anode reset control signal, and the method further comprises: The length of the second level stage in the third control period is configured as a third length, the third length being greater than the second length.

4. The method of claim 3, wherein, The third control period comprises at least one second level stage, and the third length comprises the total length of the at least one second level stage in the third control period.

5. The method of claim 3, wherein, The third length is less than or equal to the first length.

6. The method of any one of claims 1-2, 4, wherein: The first level stage is a high level stage, and the second level stage is a low level stage; or The first level stage is a low level stage, and the second level stage is a high level stage.

7. The method of any one of claims 1-2, 4, wherein: The first control period comprises at least one control period; and / or The second control period comprises at least one control period; and / or The third control period comprises at least one control period. The method further comprises:

8. The method of any one of claims 1-2, 4, wherein, When the screen brightness is high brightness, the length of the second level stage in the first control period and the length of the second level stage in the second control period are configured to be the same. ​ 9. A driving method of a pixel circuit, characterized by, The pixel circuit comprises a light-emitting control circuit and a reset circuit, the light-emitting control circuit receives a light-emitting control signal, the light-emitting control signal comprises a plurality of control periods, the plurality of control periods comprise a refresh frame period and a holding frame period, the refresh frame period and the holding frame period each comprise a first level stage not used for light-emitting and a second level stage used for light-emitting, in the refresh frame period, the reset circuit performs gate reset and display refresh according to a reset control signal, in the holding frame period, the reset circuit does not perform the gate reset and the display refresh according to the reset control signal, and the method comprises: When the screen brightness is high brightness, if the display refresh rate corresponding to the light-emitting control signal is a first refresh rate, the reset frequency corresponding to the reset control signal is a first frequency, the time length of the first level stage in the refresh frame period is configured as a fourth time length, and the time length of the first level stage in the holding frame period is configured as a fifth time length, the fifth time length is less than the fourth time length; if the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate is less than the first refresh rate, the reset frequency corresponding to the reset control signal is the first frequency, the time length of the first level stage in the refresh frame period is configured as the fourth time length, and the time length of the first level stage in the holding frame period is configured as a sixth time length, the sixth time length is less than the fourth time length, and the sixth time length is greater than the fifth time length; the difference between the light-emitting duty cycles of the screen under the first refresh rate and the second refresh rate is less than a preset threshold value; The light-emitting control circuit controls light-emitting according to the time length of the first level stage and the time length of the second level stage in the plurality of control periods.

10. The method of claim 9, wherein, the first level stage is a high level stage, and the second level stage is a low level stage; or, the first level stage is a low level stage, and the second level stage is a high level stage.

11. The method of claim 9 or 10, wherein, the refresh frame period comprises one control period; and / or, the holding frame period comprises at least one control period.

12. The method of claim 9 or 10, wherein, The method further comprises: when the screen brightness is medium-low brightness, the time length of the first level stage in the refresh frame period and the time length of the first level stage in the holding frame period are configured to be the same.

13. An integrated circuit, characterized by The integrated circuit is configured to generate a light emitting control signal, output the light emitting control signal to a pixel circuit, the pixel circuit comprising a light emitting control circuit and an anode reset circuit, the light emitting control signal comprising a plurality of control periods, the plurality of control periods comprising a first control period and a second control period, the first control period and the second control period each comprising a first level phase not used for light emitting and a second level phase used for light emitting, the light emitting control circuit being configured to control light emitting according to a time length of the first level phase and a time length of the second level phase in the plurality of control periods, in the first control period, the anode reset circuit performs anode reset according to an anode reset control signal, in the second control period, the anode reset circuit does not perform the anode reset according to the anode reset control signal; when the screen brightness is medium or low, the time length of the second level phase in the first control period is configured as a first time length, the time length of the second level phase in the second control period is configured as a second time length, the first time length is greater than the second time length, and the light emitting control signal is used for the light emitting control circuit to control light emitting according to the time length of the first level phase and the time length of the second level phase in the plurality of control periods.

14. The integrated circuit of claim 13, wherein, The first control period comprises at least one second level phase, and the first time length comprises a total time length of the at least one second level phase in the first control period.

15. The integrated circuit of claim 13 or 14, wherein, The plurality of control periods further comprises a third control period, the third control period being a control period after the first control period, in the third control period, the anode reset circuit does not perform the anode reset according to the anode reset control signal, and the integrated circuit is further configured to: configure a time length of the second level phase in the third control period as a third time length, the third time length being greater than the second time length.

16. The integrated circuit of claim 15, wherein, The third control period comprises at least one second level phase, and the third time length comprises a total time length of the at least one second level phase in the third control period.

17. The integrated circuit of claim 15, wherein, The third time length is less than or equal to the first time length.

18. The integrated circuit of any one of claims 13-14, 16, wherein: the first level phase is a high level phase, and the second level phase is a low level phase; or the first level phase is a low level phase, and the second level phase is a high level phase.

19. The integrated circuit of any one of claims 13-14, 16, wherein: the first control period comprises at least one control period; and / or the second control period comprises at least one control period; and / or the third control period comprises at least one control period. The integrated circuit is further configured to:

20. The integrated circuit of any of claims 13-14, 16, wherein, when the screen brightness is high, configure the time length of the second level phase in the first control period and the time length of the second level phase in the second control period to be the same. ​ 21. A display screen, characterized by The display screen comprises an integrated circuit, a gate driving unit and a pixel circuit, the pixel circuit comprises a light-emitting control circuit and an anode reset circuit, the light-emitting control circuit receives a light-emitting control signal, the light-emitting control signal comprises a plurality of control periods, each of the plurality of control periods comprises a first control period and a second control period, the first control period and the second control period comprise a first level stage not used for light-emitting and a second level stage used for light-emitting; The anode reset circuit is configured to perform anode reset according to an anode reset control signal in the first control period, and not perform the anode reset according to the anode reset control signal in the second control period; The integrated circuit is configured to, when the screen brightness is medium or low, configure a time length of the second level stage in the first control period as a first time length, and configure a time length of the second level stage in the second control period as a second time length, the first time length being greater than the second time length; The light-emitting control circuit is configured to control light-emitting according to a time length of the first level stage and a time length of the second level stage in the plurality of control periods.

22. The display screen of claim 21, wherein, The first control period comprises at least one second level stage, and the first time length comprises a total time length of the at least one second level stage in the first control period.

23. The display screen of claim 21 or 22, wherein, The plurality of control periods further comprises a third control period, the third control period being a control period after the first control period, in the third control period, the anode reset circuit does not perform the anode reset according to the anode reset control signal, and the integrated circuit is further configured to: configure a time length of the second level stage in the third control period as a third time length, the third time length being greater than the second time length.

24. The display screen of claim 23, wherein, The third control period comprises at least one second level stage, and the third time length comprises a total time length of the at least one second level stage in the third control period.

25. The display screen of claim 23, wherein, The third time length is less than or equal to the first time length.

26. The display screen of any one of claims 21-22 and 24, wherein: The first level stage is a high level stage, and the second level stage is a low level stage; or The first level stage is a low level stage, and the second level stage is a high level stage.

27. The display screen of any one of claims 21-22 and 24, wherein: The first control period comprises at least one control period; and / or The second control period comprises at least one control period; and / or The third control period comprises at least one control period. The integrated circuit is further configured to:

28. The display screen of any of claims 21-22, 24, wherein, when the screen brightness is high, configure the time length of the second level stage in the first control period and the time length of the second level stage in the second control period to be the same. ​ 29. An integrated circuit, comprising: The integrated circuit is configured to generate a light emission control signal, and output the light emission control signal to a pixel circuit, the pixel circuit comprising a light emission control circuit and a reset circuit, the light emission control signal comprising a plurality of control periods, the plurality of control periods comprising a refresh frame period and a holding frame period, the refresh frame period and the holding frame period each comprising a first level stage not used for light emission and a second level stage used for light emission, the light emission control circuit being configured to control light emission according to a time length of the first level stage and a time length of the second level stage in the plurality of control periods, in the refresh frame period, the reset circuit performing gate reset and display refresh according to a reset control signal, and in the holding frame period, the reset circuit not performing the gate reset and the display refresh according to the reset control signal; when the screen brightness is high, if a display refresh rate corresponding to the light emission control signal is a first refresh rate, a time length of the first level stage in the refresh frame period is configured as a fourth time length, and a time length of the first level stage in the holding frame period is configured as a fifth time length, the fifth time length being less than the fourth time length; if a display refresh rate corresponding to the light emission control signal is a second refresh rate, the second refresh rate being less than the first refresh rate, a time length of the first level stage in the refresh frame period is configured as a fourth time length, and a time length of the first level stage in the holding frame period is configured as a sixth time length, the sixth time length being less than the fourth time length and greater than the fifth time length; a difference between light emission duty cycles of the screen under the first refresh rate and the second refresh rate is less than a preset threshold, and the light emission control signal is used for the light emission control circuit to control light emission according to a time length of the first level stage and a time length of the second level stage in the plurality of control periods.

30. The integrated circuit of claim 29, wherein the first level stage is a high level stage, and the second level stage is a low level stage; or the first level stage is a low level stage, and the second level stage is a high level stage.

31. The integrated circuit of claim 29 or 30, wherein the refresh frame period comprises one control period; and / or the holding frame period comprises at least one control period.

32. The integrated circuit of claim 29 or 30, wherein when the screen brightness is medium or low, a time length of the first level stage in the refresh frame period and a time length of the first level stage in the holding frame period are configured to be the same. The display screen comprises an integrated circuit, a gate driving unit, and a pixel circuit, the pixel circuit comprising a light emission control circuit and a reset circuit, the light emission control circuit receiving a light emission control signal, the light emission control signal comprising a plurality of control periods, the plurality of control periods comprising a refresh frame period and a holding frame period, the refresh frame period and the holding frame period each comprising a first level stage not used for light emission and a second level stage used for light emission, the pixel circuit comprising the light emission control circuit and the reset circuit. ​ 33. A display screen, characterized by ​ The reset circuit is configured to: perform gate reset and display refresh according to a reset control signal in the refresh frame period, and not perform the gate reset and the display refresh according to the reset control signal in the holding frame period; The integrated circuit is configured to: when the screen brightness is high brightness, if the display refresh rate corresponding to the light-emitting control signal is a first refresh rate and the reset frequency corresponding to the reset control signal is a first frequency, configure the time length of the first voltage level stage in the refresh frame period as a fourth time length and configure the time length of the first voltage level stage in the holding frame period as a fifth time length, the fifth time length being less than the fourth time length; if the display refresh rate corresponding to the light-emitting control signal is a second refresh rate, the second refresh rate being less than the first refresh rate, and the reset frequency corresponding to the reset control signal is the first frequency, configure the time length of the first voltage level stage in the refresh frame period as the fourth time length and configure the time length of the first voltage level stage in the holding frame period as a sixth time length, the sixth time length being less than the fourth time length and greater than the fifth time length; a difference between light-emitting duty cycles of the screen at the first refresh rate and the second refresh rate is less than a preset threshold value; The light-emitting control circuit is configured to: control light-emitting according to the time length of the first voltage level stage and the time length of the second voltage level stage in the plurality of control periods.

34. The display screen of claim 33, wherein the first voltage level stage is a high voltage level stage and the second voltage level stage is a low voltage level stage; or the first voltage level stage is a low voltage level stage and the second voltage level stage is a high voltage level stage.

35. The display screen of claim 33 or 34, wherein the refresh frame period includes one control period; and / or the holding frame period includes at least one control period.

36. The display screen of claim 33 or 34, wherein, The integrated circuit is further configured to: when the screen brightness is medium or low brightness, configure the time length of the first voltage level stage in the refresh frame period and the time length of the first voltage level stage in the holding frame period to be the same.

37. An electronic device, comprising: The electronic device includes: a display screen configured to display an interface; a memory configured to store computer program instructions; a processor configured to execute the computer program instructions to support the electronic device to implement the method of any one of claims 1-8 or 9-12.

38. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer program instructions, and the computer program instructions are executed by a processing circuit to implement the method of any one of claims 1-8 or 9-12.

39. A computer program product comprising instructions, wherein: When the computer program product is executed on a computer, the computer is caused to execute the method of any one of claims 1-8 or 9-12.

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