A data transmission system, method, device and storage medium

Abstract

The present invention discloses a data transmission system, method, device and storage medium, and relates to the field of chip technology. The system includes: a protocol conversion module, which is used to perform communication protocol conversion processing on access requests issued by an access source end, and send it to an interconnection arbitration module; an interruption crossing module, which is used to summarize and process interruption requests issued by an interruption source end, and send it to an interconnection arbitration module; an interconnection arbitration module, which is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to a communication interface module; a communication interface module, which is used to send the target request to the opposite end chip. The technical solution of the embodiment of the present invention not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a data transmission system, method, device and storage medium. Background Art

[0002] With the continuous development of chip technology, die interconnection has become a common layout method in chips, and high-speed interconnection technology between die has become the focus of people's attention.

[0003] In the prior art, data transmission across chips is usually based on traditional ball grid array (BGA) packaging and chip scale package (CSP), which connect two chips through solder joints, or based on through silicon via (TSV) packaging to achieve vertical connection between chips.

[0004] However, the ball grid array and chip size packaging methods cannot meet the high-bandwidth data transmission requirements, and the hardware cost of the through silicon via packaging method is too high. At the same time, the above packaging methods do not have the scheduling capabilities for different types of functional requests, which leads to low data transmission efficiency and serious transmission delays in the data transmission process. Summary of the invention

[0005] The present invention provides a data transmission system, method, device and storage medium to solve the problem of low data transmission efficiency of interconnected core particles.

[0006] According to one aspect of the present invention, there is provided a data transmission system, which is configured in a core particle and includes: a protocol conversion module, an interruption crossing module, an interconnection arbitration module and a communication interface module; the interconnection arbitration module is respectively connected to the protocol conversion module, the interruption crossing module and the communication interface module;

[0007] The protocol conversion module is used to perform communication protocol conversion processing on the access request sent by the access source end, and send the converted access request to the interconnection arbitration module;

[0008] The interruption crossing module is used to aggregate the interruption requests sent by the interruption source end and send the aggregated interruption requests to the interconnection arbitration module;

[0009] The interconnection arbitration module is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to the communication interface module;

[0010] The communication interface module is used to send the target request to the opposite-end core particle.

[0011] The access request includes a system maintenance request, a task scheduling request and a storage network request; wherein the arbitration priorities of the system maintenance request, the summary interrupt request, the task scheduling request and the storage network request decrease in sequence.

[0012] The interconnect arbitration module is further used to obtain matching single processing thresholds according to the number of requests and / or arbitration priorities of each request type, and perform polling arbitration processing on the obtained requests according to the single processing thresholds.

[0013] The protocol conversion module is further used to add a source identification bit in the access request and configure a matching source identification in the source identification bit, so that the interconnection arbitration module arbitrates each acquired request based on the source identification; the interruption crossing module is further used to add the source identification bit in the aggregated interruption request and configure a matching source identification in the source identification bit, so that the interconnection arbitration module arbitrates each acquired request based on the source identification.

[0014] The interconnection arbitration module specifically includes a priority management unit, a source identification storage unit and a data management unit; the source identification storage unit is respectively connected to the priority management unit and the data management unit in communication; the priority management unit is used to determine the target request according to the source identification of each request, store the source identification of the target request in the source identification storage unit, and send the target request to the opposite-end chip through the communication interface module; the data management unit is used to obtain target data matching the target request according to the source identification stored in the source identification storage unit, and send the target data to the opposite-end chip through the communication interface module.

[0015] The protocol conversion module is also used to perform cross-clock domain processing and data splitting processing on the acquired storage network request, and perform configuration parameter update processing on the split storage network request.

[0016] The interruption crossing module is also used to obtain the identity information of the current chip in response to detecting the power-on signal; if the current chip is determined to be a slave chip, start the interruption request triggering function; if the current chip is determined to be a master chip, turn off the interruption request triggering function.

[0017] The interrupt crossing module includes a register unit and a switch unit that match the interrupt source end one by one; the interrupt crossing module is also used to respond to the target interrupt request issued by the target interrupt source end, set the target register unit that matches the target interrupt source end, and after issuing the target interrupt request, disconnect the target switch unit that matches the target interrupt source end, until a response result matching the target interrupt request issued by the opposite end chip is obtained, then close the target switch unit, and set the target register unit again.

[0018] The communication interface module is also used to send the request sent by the opposite-end chip to the interconnection arbitration module; the interconnection arbitration module is also used to parse and process the acquired request, and if it is determined that the current request is an access request, send the current request to the protocol conversion module, so that the current request is sent to the corresponding access destination through the protocol conversion module; if it is determined that the current request is an interrupt request, send the current request to the interruption crossing module, so that the current request is sent to the interruption destination through the interruption crossing module.

[0019] According to another aspect of the present invention, a data transmission method is provided, which is applied to the data transmission system according to any embodiment of the present invention, comprising:

[0020] The protocol conversion module performs communication protocol conversion processing on the access request sent by the access source end, and sends the converted access request to the interconnection arbitration module;

[0021] The interruption crossing module aggregates the interruption requests sent by the interruption source end, and sends the aggregated interruption requests to the interconnection arbitration module;

[0022] The interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module;

[0023] The communication interface module sends the target request to the peer core particle.

[0024] According to another aspect of the present invention, there is provided a data transmission device, which is applied to the data transmission system according to any embodiment of the present invention, comprising:

[0025] A conversion execution module, configured in the protocol conversion module, for performing communication protocol conversion processing on the access request sent by the access source, and sending the converted access request to the interconnection arbitration module;

[0026] A summary execution module, configured in the interruption crossing module, for summarizing the interruption requests sent by the interruption source end and sending the summarized interruption requests to the interconnection arbitration module;

[0027] An arbitration execution module, configured in the interconnection arbitration module, for arbitrating each request obtained according to the arbitration priority, and sending the arbitrated target request to the communication interface module;

[0028] The sending execution module is configured in the communication interface module and is used to send the target request to the opposite end core particle.

[0029] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method described in any embodiment of the present invention when executed.

[0030] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the data transmission method according to any embodiment of the present invention is implemented.

[0031] According to the technical solution of the embodiment of the present invention, the protocol conversion module performs communication protocol conversion processing on the access request sent by the access source end, and sends it to the interconnection arbitration module; the interruption crossing module summarizes the interruption request sent by the interruption source end, and sends it to the interconnection arbitration module; the interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module; the communication interface module sends the target request to the opposite end chip. This not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a structural diagram of a data transmission system provided according to Embodiment 1 of the present invention;

[0035] Figure 2is a structural diagram of an interconnection arbitration module of a data transmission system provided in accordance with Embodiment 2 of the present invention;

[0036] Figure 3 is a schematic diagram of the structure of an interruption ride-through module of a data transmission system provided in accordance with Embodiment 3 of the present invention;

[0037] Figure 4 is a schematic diagram of the flow of interrupt requests provided according to Embodiment 3 of the present invention;

[0038] Figure 5 is a schematic diagram of the structure of a chip provided according to a fourth embodiment of the present invention;

[0039] Figure 6 is a flowchart of a data transmission method provided according to Embodiment 5 of the present invention;

[0040] Figure 7 It is a structural diagram of a data transmission device provided according to Embodiment 6 of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Embodiment 1

[0044] Figure 1 A structural diagram of a data transmission system provided in Embodiment 1 of the present invention is shown in FIG. Figure 1As shown, the data transmission system includes: a protocol conversion module 100, an interruption crossing module 200, an interconnection arbitration module 300 and a communication interface module 400; the interconnection arbitration module 300 is respectively connected to the protocol conversion module 100, the interruption crossing module 200 and the communication interface module 400 for communication; the protocol conversion module 100 is used to perform communication protocol conversion processing on the access request sent by the access source end, and send the converted access request to the interconnection arbitration module 300.

[0045] The access source end is a functional device connected to the current chip, which is used to send an access request to the opposite chip connected to the chip through the current chip; different access sources send different types of access requests, and the communication protocol types of different types of access requests may be the same or different; when the protocol conversion module 100 obtains the access request sent by the access source end, it converts the communication protocol of the access request to adapt to the data transmission requirements between the chips.

[0046] For example, when the chiplets are interconnected through the Universal Chiplet Interconnect Express (UCIE) protocol, that is, the communication interface module 400 of the current chiplet and the counterpart chiplet transmit data through the UCIE protocol, the protocol conversion module 100 converts the current access request into an access request under the UCIE protocol, and sends the access request after the protocol conversion to the interconnection arbitration module 300.

[0047] The interruption crossing module 200 is used to aggregate the interruption requests issued by the interruption source end and send the aggregated interruption request to the interconnection arbitration module 300. The interruption source end is also a functional device connected to the current chiplet, which is used to send an interruption request to the opposite chiplet connected to the chiplet through the current chiplet; the interruption crossing module 200 is connected to multiple interruption source ends in communication, and may obtain interruption requests issued by one or more interruption source ends at the current moment. After determining the identity information of the interruption source end that issued the interruption request, the interruption crossing module 200 records each interruption request by generating an aggregated interruption request.

[0048] For example, when the interrupt crossing module 200 is respectively communicated with 64 interrupt source ends (i.e., interrupt source end 0 to interrupt source end 63), the interrupt crossing module 200 can use a 64-bit number to indicate whether each interrupt source end has issued an interrupt request, and each bit matches an interrupt source end; if an interrupt request is issued, the bit is 1; if no interrupt request is issued, the bit is 0; the interrupt crossing module 200 generates a new interrupt request based on the above interrupt bit, that is, a summary interrupt request, and then sends the summary interrupt request to the interconnection arbitration module 300.

[0049] In particular, in order to adapt to the data transmission requirements between chiplets, the interrupt crossing module 200 actually also performs communication protocol conversion on the interrupt request. Taking the above technical solution as an example, the interrupt crossing module 200 transmits data with the interrupt source end based on the communication protocol A, and the aggregated interrupt request generated by it is actually a request under the UCIE protocol, thereby ensuring that the aggregated interrupt request can be sent to the opposite chiplet via the communication interface module 400.

[0050] The interconnect arbitration module 300 is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to the communication interface module 400; the communication interface module 400 is used to send the target request to the opposite chip. Different types of access requests are pre-configured with different levels of arbitration priorities, and the arbitration priorities of interrupt requests and access requests are also different. The interconnect arbitration module 300 sorts the obtained access requests and aggregated interrupt requests according to the arbitration priorities of each request that has been received but not issued, and determines the target request with the highest arbitration priority in the sorting result, and then sends the target request to the opposite chip through the communication interface module 400; wherein, the communication interface module 400 is connected to the opposite chip through multiple communication interfaces, and it can select one or more idle communication interfaces to send the target request to the opposite chip.

[0051] Optionally, in an embodiment of the present invention, the access request includes a system maintenance request, a task scheduling request, and a storage network request; wherein the arbitration priorities of the system maintenance request, the summary interrupt request, the task scheduling request, and the storage network request are successively lower. A system maintenance request is a maintenance request issued when a system processing abnormality occurs. It is not only directly related to the operational stability and operational safety of the system, but also has a small amount of data, does not occupy too much bandwidth, and does not affect the transmission of other requests. Therefore, it is configured as the highest priority; the interrupt request itself is a processing mechanism for emergencies, so it is also configured as a higher priority, that is, the second highest priority.

[0052] Task scheduling request is the way that the current chip starts the peer chip to execute related tasks by sending task start instructions. Since it is a general task processing mechanism, it is configured as medium priority; storage network request is the data read and write operation between the current chip and the peer chip. Since its data volume is large, it needs to occupy a large transmission bandwidth, so it is configured as low priority to avoid the existence of a large number of storage network requests, resulting in long-term occupation of a large transmission bandwidth, and then causing other types of requests to always fail to obtain arbitration; therefore, different arbitration priorities are configured according to different request types, realizing orderly scheduling of different types of functional requests, and ensuring timely response and processing of various functional requests.

[0053] Optionally, in an embodiment of the present invention, the interconnect arbitration module 300 is further used to obtain matching single processing thresholds according to the number of requests and / or arbitration priority of each request type, and perform polling arbitration processing on the obtained requests according to the single processing threshold. Specifically, when the interconnect arbitration module 300 obtains a large number of requests, in order to ensure a balanced response to each request type, different types of requests can be used in turn as requests selected to be issued after arbitration at the current moment in a polling manner; for example, the single processing threshold can be configured to 1, that is, in a polling manner, one request under each request type is used as the target request after arbitration.

[0054] At the same time, if the number of requests under a request type is larger, the request accumulation phenomenon is more likely to occur under this type. In this case, a single processing threshold with a larger value can be assigned to the request type; if the number of requests under a request type is smaller, a single processing threshold with a smaller value can be assigned to the request type; that is, the number of requests under the current request type can be configured to be positively correlated with the single processing threshold; each time a request type is polled, a corresponding number of requests are continuously processed under the request type according to the corresponding single processing threshold.

[0055] In addition, as described in the above technical solution, the single processing threshold can also be configured to be positively correlated with the arbitration priority, that is, the higher the arbitration priority under the current request type, the larger the corresponding single processing threshold; the lower the arbitration priority under the current request type, the smaller the corresponding single processing threshold; the single processing threshold of the current request type can also be calculated based on the number of requests and arbitration priority of the current request type, as well as the request number weight and arbitration priority weight, thereby avoiding the request accumulation phenomenon under one or more request types, ensuring the timely response of each request, and improving the efficiency of request arbitration.

[0056] Optionally, in an embodiment of the present invention, the protocol conversion module 100 is further used to add a source identification bit in the access request, and configure a matching source identification bit in the source identification bit, so that the interconnection arbitration module 300 arbitrates each obtained request based on the source identification; the interrupt crossing module 200 is further used to add the source identification bit in the aggregated interrupt request, and configure a matching source identification bit in the source identification bit, so that the interconnection arbitration module 300 arbitrates each obtained request based on the source identification.

[0057] Specifically, when the protocol conversion module 100 obtains an access request, it adds a source identification bit of a specified number of bits in the request, and configures a source identification in the source identification bit; wherein the source identification is used to indicate the source of the current request, and also indicates the type of the current request; taking the above technical solution, the access request includes a system maintenance request, a task scheduling request, and a storage network request as an example, and combined with the summary interrupt request, the core particle includes a total of four types of requests, then different requests can be represented by two bits, for example, "00" represents a system maintenance request, "01" represents a task scheduling request, "10" represents a storage network request, and "11" represents a summary interrupt request.

[0058] Similarly, when the interruption crossing module 200 obtains the aggregate access request, it also adds a specified number of source identification bits in the request and configures the source identification "11" in the source identification bits; the interconnection arbitration module 300 determines the arbitration priority of each request based on the source identification of each request, and then obtains the data information under the specified request source in a targeted manner according to the arbitration result, thereby ensuring that the interconnection arbitration module 300 performs accurate arbitration processing operations and improving the arbitration processing efficiency of the interconnection arbitration module 300.

[0059] Optionally, in an embodiment of the present invention, the protocol conversion module 100 is also used to perform cross-clock domain processing and data splitting processing on the acquired storage network request, and perform configuration parameter update processing on the split storage network request. Specifically, since the storage network data is 1024 bits, and the transmission bandwidth under the UCIE protocol is usually 256 bits, the protocol conversion module 100 first needs to use asynchronous FIFO logic to perform cross-clock domain processing on the storage network request; then split a beat of 1024 bits of data into 4 beats of 256 bits of data; at the same time, it is necessary to modify the configuration parameters of the storage network request issued thereby.

[0060] For example, the "size" parameter and the "length" parameter; "size" indicates the size of the valid data in each beat. Since one beat is 256 bits, or 32 bytes, the "size" value is calculated to be 5; "length" indicates the length of the transmitted data. Since the data is changed from one beat to four beats, the "length" value becomes four times the original value. This realizes the conversion of transmission data between different bandwidths and ensures the transmission response to high-bandwidth transmission data. In addition, for maintenance system requests and task scheduling requests, since they are the same as the transmission bandwidth and transmission frequency within the data transmission system, the protocol conversion module 100 only needs to complete the conversion process of the communication protocol.

[0061] Optionally, in an embodiment of the present invention, the communication interface module is also used to send the request sent by the opposite-end chip to the interconnection arbitration module; the interconnection arbitration module is also used to parse and process the obtained request, and if it is determined that the current request is an access request, send the current request to the protocol conversion module, so that the current request is sent to the corresponding access destination through the protocol conversion module; if it is determined that the current request is an interrupt request, send the current request to the interrupt crossing module, so that the current request is sent to the interrupt destination through the interrupt crossing module.

[0062] Specifically, if the current chiplet is used as a request receiver, first, the communication interface module 400 forwards the request sent by the opposite chiplet to the interconnection arbitration module 300; secondly, the interconnection arbitration module 300 parses the current request, and if it is determined to be an interrupt request, the request is sent to the interruption crossing module 200, so that the current request is sent to the interruption destination through the interruption crossing module 200; if it is determined to be an access request, the request is sent to the protocol conversion module 100, so that the current request is sent to the access destination through the protocol conversion module 100; thereby completing the data transmission process across chiplets.

[0063] In addition, after completing the interrupt request response, the interrupt destination sends the response result to the interconnection arbitration module 300 through the interrupt crossing module 200; after completing the access request response, the access destination sends the response result to the interconnection arbitration module 300 through the protocol conversion module 100; the interconnection arbitration module 300 performs arbitration processing based on the above technical solution, thereby feeding back each response result obtained by arbitration to the opposite end chiplet in turn through the communication interface module 400.

[0064] According to the technical solution of the embodiment of the present invention, the protocol conversion module performs communication protocol conversion processing on the access request sent by the access source end, and sends it to the interconnection arbitration module; the interruption crossing module summarizes the interruption request sent by the interruption source end, and sends it to the interconnection arbitration module; the interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module; the communication interface module sends the target request to the opposite end chip. This not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

[0065] Embodiment 2

[0066] Figure 2 A schematic diagram of the structure of an interconnection arbitration module 300 in a data transmission system provided in the second embodiment of the present invention is shown in FIG. Figure 2As shown, the interconnection arbitration module 300 includes a priority management unit 301, a source identification storage unit 302 and a data management unit 303; the source identification storage unit 302 is respectively communicated with the priority management unit 301 and the data management unit 303; the priority management unit 301 is used to determine the target request according to the source identification of each request, and store the source identification of the target request in the source identification storage unit 302, and send the target request to the opposite end chip through the communication interface module 400.

[0067] Taking the interconnection arbitration module 300 obtaining a write request as an example, the priority management unit 301 extracts the source identifier "00" from the source identifier of the write request, which indicates that the request type of the write request is a system maintenance request. At this time, the priority management unit 301 forwards the write request to the protocol conversion module 100 to send the write request to the peer chip through the communication interface module 400; at the same time, the extracted source identifier "00 is stored in the source identifier storage unit 302.

[0068] The data management unit 303 is used to obtain the target data matching the target request according to the source identifier stored in the source identifier storage unit 302, and send the target data to the opposite end chip through the communication interface module 400. The data management unit 303 directionally obtains the write data sent by the system maintenance request source (i.e., request source 1) through the write request data channel 1; wherein the write request data channel 1 is a data transmission channel matching the system maintenance request source; and then forwards the write data to the protocol conversion module 100 to send the write request to the opposite end chip through the protocol conversion module 100, until the last data of the transmission is sent (for example, the "wlast signal" is detected to be 1), indicating that the write data of this write request has been sent.

[0069] In addition, the interconnection arbitration module 300 may further include an identification mapping unit 304. Since the write request issued by the current chip has a source identification, the response result fed back by the opposite chip also has the source identification. At this time, the identification mapping unit 304 determines the request source of the feedback write response according to the source identification in the response result, and feeds back the write response result to the request source through the write response channel corresponding to the request source. Thus, the interconnection arbitration module 300 realizes the directional reception and forwarding of read and write data based on the source identification configured in the request, ensures the orderly execution of the arbitration processing results, and improves the data transmission efficiency between interconnected chiplets.

[0070] According to the technical solution of the embodiment of the present invention, the priority management unit determines the target request according to the source identifier of each request, stores the source identifier of the target request in the source identifier storage unit, and sends the target request to the opposite chip through the communication interface module; the data management unit obtains the target data matching the target request according to the source identifier stored in the source identifier storage unit, and sends the target data to the opposite chip through the communication interface module. Thus, the interconnected arbitration module realizes the directional reception and forwarding of read and write data based on the source identifier configured in the request, ensures the orderly execution of the arbitration processing results, and improves the data transmission efficiency between interconnected chiplets.

[0071] Embodiment 3

[0072] Figure 3 A structural schematic diagram of an interrupt crossing module 200 in a data transmission system provided in Embodiment 3 of the present invention, the interrupt crossing module 200 includes a register unit 201 and a switch unit 202 that match the interrupt source end one by one; the interrupt crossing module 200 is also used to respond to a target interrupt request issued by a target interrupt source end, set the target register unit 201 that matches the target interrupt source end, and after issuing the target interrupt request, disconnect the target switch unit 202 that matches the target interrupt source end, until a response result matching the target interrupt request issued by a core particle on the other end is obtained, and then close the target switch unit 202 and set the target register unit 201 again.

[0073] Specifically, the interrupt crossing module 200 configures a register unit 201 and a switch unit 202 for each interrupt source end. If an interrupt source end (i.e., the target interrupt source end) issues an interrupt request (i.e., the target interrupt request), the interrupt source end pulls the signal high, thereby generating a level interrupt; the corresponding target register unit 201 is set to 1; if the target switch unit 202 is in an open state at this time, it means that the interrupt generated by the current interrupt source end has not been responded to by the chip on the other end, and the current interrupt request will not be sent to the summary unit 203 at this time; if the target switch unit 202 is in a closed state at this time, the current interrupt request will be sent to the summary unit 203 through the target switch unit 202.

[0074] After the target interrupt request is issued, before the response result issued by the opposite chip matching the target interrupt request is obtained, the target switch unit 202 is always in a closed state, and the first register is always set to 1; after the response result issued by the opposite chip matching the target interrupt request is obtained, the target switch unit 202 is in an open state, and the target register unit is set to 0, which means that the interrupt request previously generated by the current interrupt source has been responded to by the opposite chip, and the interrupt request issued again by the current interrupt source can be smoothly transmitted to the summary unit 203 through the target register unit 201 and the target switch unit 202.

[0075] Optionally, in an embodiment of the present invention, the interrupt traversal module 200 is further used to obtain the identity information of the current core particle in response to detecting a power-on signal; if the current core particle is determined to be a slave core particle, the interrupt request trigger function is enabled; if the current core particle is determined to be a master core particle, the interrupt request trigger function is disabled. Specifically, for two interconnected core particles, the slave core particle will usually report an interrupt request to the master core particle, and the master core particle will perform a response process for the interrupt request through the interrupt destination. In order to prevent the master core particle from sending an interrupt request to the slave core particle, the interrupt enable parameter of the slave core particle can be increased.

[0076] When the chip is powered on, the interrupt enable parameter of the slave chip is enabled by default, and the interrupt enable parameter of the master chip is not enabled, so that the interrupt request obtained by the master chip cannot be transmitted to the slave chip; Figure 4 The white frame in the figure indicates that when the chip is powered on, the interrupt request can be transmitted from the slave chip to the master chip. Figure 4 The gray box in the figure indicates that the interrupt request cannot be transmitted from the master chip to the slave chip when the chip is powered on; this ensures the one-way transmission of the interrupt request and avoids abnormalities in the business processing logic of the interconnected chip when the master chip sends an interrupt request to the slave chip.

[0077] According to the technical solution of the embodiment of the present invention, the interruption crossing module responds to the target interruption request sent by the target interruption source, sets the target register unit matching the target interruption source, and disconnects the target switch unit matching the target interruption source after sending the target interruption request, until the response result matching the target interruption request sent by the opposite end chip is obtained, the target switch unit is closed, and the target register unit is set again. In this way, orderly management of interruption requests is achieved, and the transmission efficiency of interruption requests is improved.

[0078] Embodiment 4

[0079] Figure 5A schematic diagram of the structure of a chip provided in Embodiment 4 of the present invention, the chip includes a master core particle and a slave core particle, the slave core particle includes a first protocol conversion module 100, a first interruption crossing module 200, a first interconnection arbitration module 300 and a first communication interface module 400; the master core particle includes a second protocol conversion module 100, a second interruption crossing module 200, a second interconnection arbitration module 300 and a second communication interface module 400.

[0080] The second protocol conversion module 100 obtains the first access request sent by the first access source, performs communication protocol conversion on it, and sends the converted first access request to the second interconnection arbitration module 300; the second interconnection arbitration module 300 arbitrates each request obtained according to the arbitration priority, and sends the arbitrated first access request as the target request to the second communication interface module 400.

[0081] The second communication interface module 400 sends the first access request to the first communication interface module 400; the first communication interface module 400 sends the first access request sent by the main chip to the first interconnection arbitration module 300; the first interconnection arbitration module 300 parses the first access request and sends it to the first protocol conversion module 100 according to its request type, so as to send the first access request to the matching access source end through the first protocol conversion module 100.

[0082] The first interrupt crossing module 200 obtains the first interrupt request sent by the first interrupt source, aggregates it to generate a first aggregate interrupt request, and sends the first aggregate interrupt request to the first interconnect arbitration module 300; the first interconnect arbitration module 300 arbitrates each request obtained according to the arbitration priority, and sends the arbitrated first aggregate interrupt request as the target request to the first communication interface module 400.

[0083] The first communication interface module 400 sends the first summary interrupt request to the second communication interface module 400; the second communication interface module 400 sends the first summary interrupt request sent from the chiplet to the second interconnect arbitration module 300; the second interconnect arbitration module 300 parses the first summary interrupt request and sends it to the first interrupt penetration module 200 according to its request type, so as to send the first summary interrupt request to the matching access interrupt destination through the first interrupt penetration module 200 for interrupt processing.

[0084] The technical solution of the embodiment of the present invention, the above-mentioned chip based on interconnected core particles, not only reduces the hardware cost of the data transmission system in the core particles, meets the high-bandwidth data transmission requirements of the core particle interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

[0085] Embodiment 5

[0086] Figure 6 This is a flowchart of a data transmission method provided in Embodiment 5 of the present invention. The method can be executed by a data transmission device. The data transmission device can be implemented in the form of hardware and / or software. The data transmission device can be configured in the data transmission system in any embodiment of the present invention. The data transmission system can be configured in a core particle. Figure 6 As shown, the method includes:

[0087] S101, the protocol conversion module performs communication protocol conversion processing on an access request sent by an access source, and sends the converted access request to the interconnection arbitration module.

[0088] S102: The interruption crossing module aggregates the interruption requests sent by the interruption source, and sends the aggregated interruption requests to the interconnection arbitration module.

[0089] S103: The interconnection arbitration module arbitrates each acquired request according to the arbitration priority, and sends the arbitrated target request to the communication interface module.

[0090] S104: The communication interface module sends the target request to the peer core particle.

[0091] According to the technical solution of the embodiment of the present invention, the protocol conversion module performs communication protocol conversion processing on the access request sent by the access source end, and sends it to the interconnection arbitration module; the interruption crossing module summarizes the interruption request sent by the interruption source end, and sends it to the interconnection arbitration module; the interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module; the communication interface module sends the target request to the opposite end chip. This not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

[0092] Embodiment 6

[0093] Figure 7 : is a structural block diagram of a data transmission device provided by Embodiment 6 of the present invention, and the device specifically includes:

[0094] The conversion execution module 701 is configured in the protocol conversion module, and is used to perform communication protocol conversion processing on the access request sent by the access source, and send the converted access request to the interconnection arbitration module;

[0095] A summary execution module 702, configured in the interruption crossing module, is used to summarize the interruption requests sent by the interruption source end and send the summarized interruption requests to the interconnection arbitration module;

[0096] An arbitration execution module 703, configured in the interconnection arbitration module, is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to the communication interface module;

[0097] The sending execution module 704 is configured in the communication interface module and is used to send the target request to the opposite end chiplet.

[0098] According to the technical solution of the embodiment of the present invention, the protocol conversion module performs communication protocol conversion processing on the access request sent by the access source end, and sends it to the interconnection arbitration module; the interruption crossing module summarizes the interruption request sent by the interruption source end, and sends it to the interconnection arbitration module; the interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module; the communication interface module sends the target request to the opposite end chip. This not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

[0099] The above device can execute the data transmission method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the data transmission method provided by any embodiment of the present invention.

[0100] Embodiment 6

[0101] In some embodiments, the data transmission method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the data transmission method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the data transmission method in any other appropriate manner (e.g., by means of firmware).

[0102] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0103] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0104] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0105] To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0106] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0107] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data transmission system, characterized in that: Configured in the core particle, including: a protocol conversion module, an interruption crossing module, an interconnection arbitration module and a communication interface module; the interconnection arbitration module is respectively connected to the protocol conversion module, the interruption crossing module and the communication interface module; The protocol conversion module is used to perform communication protocol conversion processing on the access request sent by the access source end, and send the converted access request to the interconnection arbitration module; The interruption crossing module is used to aggregate the interruption requests sent by the interruption source end and send the aggregated interruption requests to the interconnection arbitration module; The interconnection arbitration module is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to the communication interface module; The communication interface module is used to send the target request to the opposite-end core particle.

2. The data transmission system according to claim 1, characterized in that: The access request includes a system maintenance request, a task scheduling request and a storage network request; wherein the arbitration priorities of the system maintenance request, the summary interrupt request, the task scheduling request and the storage network request decrease in sequence.

3. The data transmission system according to claim 1, characterized in that: The interconnect arbitration module is further used to obtain matching single processing thresholds according to the number of requests and / or arbitration priorities of each request type, and perform polling arbitration processing on the obtained requests according to the single processing thresholds.

4. The data transmission system according to claim 1, characterized in that: The protocol conversion module is further used to add a source identification bit to the access request and configure a matching source identification bit in the source identification bit, so that the interconnect arbitration module performs arbitration processing on each acquired request based on the source identification; The interruption crossing module is further used to add the source identification bit to the summary interruption request and configure a matching source identification in the source identification bit, so that the interconnection arbitration module performs arbitration processing on each acquired request based on the source identification.

5. The data transmission system according to claim 4, characterized in that: The interconnection arbitration module specifically includes a priority management unit, a source identification storage unit and a data management unit; the source identification storage unit is respectively connected to the priority management unit and the data management unit for communication; The priority management unit is used to determine the target request according to the source identifier of each request, store the source identifier of the target request in the source identifier storage unit, and send the target request to the opposite end chiplet through the communication interface module; The data management unit is used to obtain target data matching the target request according to the source identifier stored in the source identifier storage unit, and send the target data to the opposite-end chiplet through the communication interface module.

6. The data transmission system according to claim 2, characterized in that: The protocol conversion module is also used to perform cross-clock domain processing and data splitting processing on the acquired storage network request, and perform configuration parameter update processing on the split storage network request.

7. The data transmission system according to claim 1, characterized in that: The interruption crossing module is also used to obtain the identity information of the current chip in response to detecting the power-on signal; if the current chip is determined to be a slave chip, start the interruption request triggering function; if the current chip is determined to be a master chip, turn off the interruption request triggering function.

8. The data transmission system according to claim 1, characterized in that: The interruption crossing module includes a register unit and a switch unit which are matched one by one with the interruption source end; The interrupt crossing module is also used to respond to a target interrupt request issued by a target interrupt source, set a target register unit that matches the target interrupt source, and after issuing the target interrupt request, disconnect the target switch unit that matches the target interrupt source, until a response result matching the target interrupt request issued by the opposite end chip is obtained, then close the target switch unit, and set the target register unit again.

9. The data transmission system according to claim 1, characterized in that: The communication interface module is further used to send the request sent by the opposite end chiplet to the interconnection arbitration module; The interconnection arbitration module is further used to parse and process the acquired request, and if it is determined that the current request is an access request, send the current request to the protocol conversion module, so as to send the current request to the corresponding access destination through the protocol conversion module; If it is determined that the current request is an interrupt request, the current request is sent to the interruption crossing module, so that the current request is sent to the interruption destination end through the interruption crossing module.

10. A data transmission method, characterized in that: A data transmission system applied to any one of claims 1 to 9, comprising: The protocol conversion module performs communication protocol conversion processing on the access request sent by the access source, and sends the converted access request to the interconnection arbitration module; The interruption crossing module aggregates the interruption requests sent by the interruption source end, and sends the aggregated interruption requests to the interconnection arbitration module; The interconnection arbitration module arbitrates each request obtained according to the arbitration priority, and sends the arbitrated target request to the communication interface module; The communication interface module sends the target request to the peer core particle.

11. A data transmission device, characterized in that: A data transmission system applied to any one of claims 1 to 9, comprising: A conversion execution module, configured in the protocol conversion module, for performing communication protocol conversion processing on the access request sent by the access source, and sending the converted access request to the interconnection arbitration module; A summary execution module, configured in the interruption crossing module, for summarizing the interruption requests sent by the interruption source end and sending the summarized interruption requests to the interconnection arbitration module; An arbitration execution module, configured in the interconnection arbitration module, for arbitrating each request obtained according to the arbitration priority, and sending the arbitrated target request to the communication interface module; The sending execution module is configured in the communication interface module and is used to send the target request to the opposite end core particle.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data transmission method according to claim 10 when executed.

13. According to another aspect of the present invention, there is provided a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the data transmission method according to claim 10 is implemented.

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