Ethernet Synchronous Communication Method and Device Based on FPGA and Dynamic Phase Shift

Abstract

The present invention discloses an Ethernet synchronous communication method and device based on FPGA and dynamic phase shift. By performing packet splitting on the data to be transmitted received by the sending end, compressing and encapsulating multiple data packets, and using the FPGA to control the dynamic phase shift algorithm, phase encoding is performed on the clock signals of each encapsulated data packet to generate a clock synchronization frame. It is transmitted to the receiving end in parallel through multiple-channel Ethernet. The receiving end estimates the phase error based on the synchronization header information of each encoded data packet, and performs dynamic phase compensation on the clock signals of multiple encoded data packets according to the estimation result. Based on the synchronization header information after dynamic phase compensation, multiple encoded data packets are parsed and reorganized to be restored to the original transmitted data. This method not only reduces the synchronization delay that may occur in high-speed data transmission through dynamic phase compensation, but also reasonably allocates and utilizes network communication resources through multiple-channel parallel transmission, effectively avoiding resource waste and a large amount of resource occupation.

Description

Technical Field

[0001] The present invention relates to the field of Ethernet communication technology, and particularly to an Ethernet synchronous communication method and device based on FPGA and dynamic phase shift. Background Art

[0002] As a widely used local area network technology, Ethernet plays a crucial role in the modern communication field. With the rapid development of information technology, the application scenarios of Ethernet have been continuously expanded, covering many fields such as data centers, industrial automation, intelligent transportation, aerospace, etc. In these application scenarios, higher requirements are put forward for the rate, reliability, and synchronization of Ethernet communication. For example, in a data center, high-speed and stable data transmission is required between a large number of servers to achieve efficient cloud computing and big data processing; in an industrial automation production line, precise synchronous communication between devices is crucial for ensuring the stability of the production process and product quality.

[0003] Traditional Ethernet synchronization technologies mainly achieve clock synchronization based on timestamp protocols (such as NTP, PTP). However, these technologies have certain limitations in some cases. On the one hand, timestamp protocols rely on time servers in the network. When the network experiences congestion, delay, or failure, the accuracy of clock synchronization will be affected. On the other hand, with the continuous increase of Ethernet communication rate, traditional synchronization technologies may have an increased synchronization delay when dealing with high-speed data transmission, making it difficult to meet some application scenarios with extremely high requirements for synchronization accuracy.

[0004] At the same time, the resources for network communication are limited. However, in the case of high-speed transmission of a large amount of data currently, it is difficult to reasonably allocate and utilize the resources of network communication, which is likely to cause resource waste and a large amount of resource occupation. Summary of the Invention

[0005] In view of this, the present invention provides an Ethernet synchronous communication method and device based on FPGA and dynamic phase shift, which solves the technical problems that traditional synchronization technologies may have an increased synchronization delay when dealing with high-speed data transmission, and it is difficult to reasonably allocate and utilize the resources of network communication, which is likely to cause resource waste and a large amount of resource occupation.

[0006] The first aspect of the present invention provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, including:

[0007] Packetize the data to be transmitted received by the sending end to obtain multiple data packets;

[0008] Compress multiple of the data packets, and encapsulate the multiple compressed data packets to obtain multiple encapsulated data packets; the encapsulated data packets include synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end;

[0009] Use an FPGA to control a dynamic phase shift algorithm to perform phase encoding on the clock signal of each of the encapsulated data packets to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets;

[0010] Transmit the multiple encoded data packets to the receiving end in parallel through a multi-channel Ethernet;

[0011] The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the multiple encoded data packets according to the phase error estimation result;

[0012] The receiving end parses and reorganizes the multiple encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation, and restores them to the originally transmitted data.

[0013] Preferably, the step of compressing multiple of the data packets, and encapsulating the multiple compressed data packets to obtain multiple encapsulated data packets includes:

[0014] Perform clustering division on multiple of the data packets to obtain multiple clusters; each cluster includes a clustering center data packet and other data packets except the clustering center data packet;

[0015] Construct a feature hyperplane according to the clustering center data packet, and project other data packets in the same cluster as each clustering center data packet onto the orthogonal complement space of the feature hyperplane to obtain an orthogonal projection matrix of the other data packets;

[0016] Perform topological weighted encoding according to non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection encoding matrix;

[0017] Preprocess the other data packets corresponding to the orthogonal projection encoding matrix to obtain a matrix of the other data packets;

[0018] Perform a projection compression operation on the matrix of the other data packets corresponding to the orthogonal projection encoding matrix according to the orthogonal projection encoding matrix to obtain compressed data packets;

[0019] Encapsulate each clustering center data packet and the compressed data packets corresponding to other data packets in the same cluster as the clustering center data packet to obtain multiple of the encapsulated data packets.

[0020] Preferably, the method further includes:

[0021] Pack the orthogonal projection coding matrix corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and use the sequence number of the data packet corresponding to the orthogonal projection coding matrix as the key to obtain a key-value mapping data packet;

[0022] Transmit the key-value mapping data packet into the virtual container of the target device to obtain a container image, which is used to forward the key-value mapping data packet corresponding to the key specified in the request information in the request information to the receiving end in response to the request information of the receiving end.

[0023] Preferably, the clock signal of each of the encapsulated data packets is phase-encoded by an FPGA-controlled dynamic phase shift algorithm to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain a plurality of encoded data packets, including:

[0024] For each of the encapsulated data packets, extract the data feature information of the encapsulated data packet;

[0025] According to the data feature information, the clock signal of the encapsulated data packet is encoded in a multi-dimensional phase space by an FPGA-controlled dynamic phase shift algorithm to obtain a four-dimensional phase encoding matrix; wherein, the dimensions of the four-dimensional phase encoding matrix include phase, cumulative phase adjustment amount, phase weighted average amount, and phase temperature drift amount;

[0026] Perform initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain the clock synchronization frame;

[0027] Embed the clock synchronization frame in the synchronization header information, and during the embedding process, insert a phase synchronization header into the synchronization header information to obtain the encoded data packet; wherein, the phase synchronization header is used to predict the phase of the next encoded data packet.

[0028] Preferably, the step of parallelly transmitting the plurality of encoded data packets to the receiving end through a multi-channel Ethernet includes:

[0029] For each of the encoded data packets, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features;

[0030] For each channel in the Ethernet, extract the multi-dimensional channel features of the channel, and construct a channel tensor of the channel according to the multi-dimensional channel features;

[0031] Based on the data packet tensor and the channel tensor, perform routing selection on the encoded data packet through a deep learning algorithm to obtain a transmission channel corresponding to each encoded data packet.

[0032] Determine a transmission characteristic tensor based on the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein, the transmission characteristic tensor is used to characterize the transmission coefficients of the encoded data packets on the transmission channel.

[0033] Determine the transmission power and transmission time slots of each encoded data packet on the transmission channel corresponding to the encoded data packet according to the transmission characteristic tensor.

[0034] Transmit a plurality of the encoded data packets to the receiving end through their corresponding transmission channels according to the transmission power and the transmission time slots.

[0035] Preferably, the receiving end estimates a phase error according to the synchronization header information of each encoded data packet, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result, including:

[0036] The receiving end extracts a four-dimensional phase encoding matrix in the synchronization header information of each encoded data packet.

[0037] Determine a phase error between the phase in the four-dimensional phase encoding matrix and a preset reference phase through a time-to-digital converter.

[0038] Input the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and output a phase temperature drift compensation amount.

[0039] Compensate the phase temperature drift amount through the phase temperature drift compensation amount.

[0040] Compensate the phase, the accumulated phase adjustment amount, and the phase weighted average amount in the four-dimensional phase encoding matrix according to the compensated phase temperature drift amount and the phase error.

[0041] Preferably, the receiving end analyzes and reorganizes the plurality of encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation, and restores the data to the originally transmitted data, including:

[0042] The receiving end extracts the synchronization header information of the encoded data packets after dynamic phase compensation for phase synchronization.

[0043] Determine the sequence number of the encoded data packet according to the encoded data packet after phase synchronization.

[0044] Generate the request information according to the sequence number of the encoded data packet, and send the request information to the target device.

[0045] The target device responds to the request information, and according to the sequence number of the encoded data packet included in the request information, finds the key-value mapping data packet corresponding to the sequence number in the virtual container;

[0046] The container image forwards the key-value mapping data packet to the receiving end;

[0047] The receiving end performs an inverse projection operation on the corresponding encoded data packet through the key-value mapping data packet to obtain the original transmitted data of the encoded data packet;

[0048] Reorder the original transmitted data of each encoded data packet according to the sequence numbers of each encoded data packet to obtain the original transmitted data.

[0049] In a second aspect, the present invention provides an Ethernet synchronization communication device based on FPGA and dynamic phase shift, including:

[0050] A data packet splitting module, configured to split the data to be transmitted received by the sending end to obtain a plurality of data packets;

[0051] A data encapsulation module, configured to perform compression processing on the plurality of data packets, and encapsulate the plurality of data packets after compression processing to obtain a plurality of encapsulated data packets; the encapsulated data packets include synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end;

[0052] A phase encoding module, configured to perform phase encoding on the clock signal of each encapsulated data packet through an FPGA-controlled dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain a plurality of encoded data packets;

[0053] A data transmission module, configured to transmit the plurality of encoded data packets to the receiving end in parallel through a multi-channel Ethernet;

[0054] A phase compensation module, configured to estimate the phase error at the receiving end according to the synchronization header information of each encoded data packet, and perform dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result;

[0055] A data recombination module, configured to parse and recombine the plurality of encoded data packets at the receiving end according to the synchronization header information of the encoded data packets after dynamic phase compensation to restore the original transmitted data.

[0056] In a third aspect, the present invention provides an electronic device, characterized in that the electronic device includes a memory and a processor, and a computer program is stored in the memory. When the computer program is executed by the processor, the processor is caused to execute the steps of the Ethernet synchronization communication method based on FPGA and dynamic phase shift as described in the first aspect.

[0057] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, characterized in that when the computer program is executed, the steps of the Ethernet synchronization communication method based on FPGA and dynamic phase shift as described in the first aspect are implemented.

[0058] As can be seen from the above technical solutions, the present invention performs packet splitting on the data to be transmitted received by the sending end, compresses and encapsulates multiple data packets to improve the transmission rate. The FPGA is used to control the dynamic phase shift algorithm to perform phase encoding on the clock signals of each encapsulated data packet to generate a clock synchronization frame. Subsequently, it is transmitted to the receiving end in parallel through a multi-channel Ethernet. The receiving end estimates the phase error based on the synchronization header information of each encoded data packet, and performs dynamic phase compensation on the clock signals of multiple encoded data packets according to the estimation result. Based on the synchronization header information after dynamic phase compensation, multiple encoded data packets are parsed and recombined to be restored to the original transmitted data. This method not only reduces the synchronization delay that may occur in high-speed data transmission through dynamic phase compensation, but also reasonably allocates and utilizes network communication resources through multi-channel parallel transmission, effectively avoiding resource waste and a large amount of resource occupation. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0060] Figure 1 It is a flowchart of an Ethernet synchronization communication method based on FPGA and dynamic phase shift provided by an embodiment of the present invention;

[0061] Figure 2 It is a schematic structural diagram of an Ethernet synchronization communication device based on FPGA and dynamic phase shift provided by an embodiment of the present invention;

[0062] Figure 3 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0063] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0064] The embodiment of the present application provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, which is applicable to the situation of Ethernet synchronous communication. This method can be executed by an Ethernet synchronous communication device, which can be implemented in the form of hardware and / or software, and the Ethernet synchronous communication device can be configured in a computer device.

[0065] As Figure 1 shown, the embodiment of the present application provides an Ethernet synchronous communication method based on FPGA and dynamic phase shift, including the following steps S1 to S6. Among them:

[0066] Step S1: Split the data to be transmitted received by the sending end into multiple data packets.

[0067] Among them, the packet splitting rule for splitting the data to be transmitted received by the sending end can be set according to factors such as the type, size, priority, and transmission requirements of the data. Through a reasonable packet splitting rule, a large amount of data can be split into multiple smaller data packets, which is convenient for subsequent compression processing and encapsulation operations, and is also beneficial to improving the flexibility and efficiency of data transmission.

[0068] Step S2: Perform compression processing on the multiple data packets, and encapsulate the multiple compressed data packets to obtain multiple encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end.

[0069] Among them, it can be understood that performing compression processing on the multiple data packets can reduce the size of the data packets, reduce the bandwidth occupation of data transmission, and improve the transmission efficiency.

[0070] The synchronization header information refers to the key information used for data synchronization at the receiving end, which contains specific identifiers or sequences for clock synchronization. This synchronization header information is embedded in the encapsulated data packets, so that when the receiving end receives the data packets, it can accurately perform clock synchronization based on the synchronization header information to ensure the correct parsing and recombination of the data.

[0071] When encapsulating a data packet, in addition to including the synchronization header information, other necessary metadata can be added according to actual needs, such as the data packet's sequence number, checksum information, etc., so that the receiving end can process and verify the data packet more efficiently.

[0072] Step S3: Phase-encode the clock signal of each encapsulated data packet by controlling the dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets.

[0073] Among them, FPGA (field programmable gate array) as a hardware accelerator can process data streams in real time, while the dynamic phase shift algorithm achieves precise synchronization between data packets by finely adjusting the phase of the clock signal.

[0074] In this step, the clock signal of each encapsulated data packet is processed by the dynamic phase shift algorithm controlled by the FPGA and converted into a clock synchronization frame containing phase information. This clock synchronization frame is then embedded in the synchronization header information and together with the rest of the encapsulated data packet, it forms a coded data packet. In this way, each coded data packet not only contains the data to be transmitted, but also comes with key information for clock synchronization at the receiving end, ensuring the accuracy and reliability of data transmission.

[0075] Step S4: Transmit the multiple encoded data packets in parallel to the receiving end via a multi-channel Ethernet.

[0076] Among them, the multi-channel Ethernet transmission method is to distribute the coded data packets to multiple parallel channels for transmission, which can make full use of network bandwidth resources and improve the throughput of data transmission. In this step, each coded data packet is assigned to a specific channel for transmission, which is usually determined by factors such as the priority, size and channel load of the data packet. Through parallel transmission, not only can the data transmission speed be accelerated, but also the data pressure of a single channel can be reduced, and the stability and reliability of the entire transmission system can be improved.

[0077] Step S5: The receiving end estimates the phase error according to the synchronization header information of each coded data packet, and performs dynamic phase compensation on the clock signals of the multiple coded data packets according to the phase error estimation result.

[0078] It can be understood that the phase error estimation based on the synchronization header information of each coded data packet can ensure that the receiving end can accurately identify and correct the phase deviation that may occur during the transmission of the data packet. Through the clock synchronization frame embedded in the synchronization header information, the phase error is calculated by comparing the local clock of the receiving end with the clock synchronization frame in the data packet, and the impact of environmental perception on the phase is considered. Based on this, dynamic phase compensation is performed on the data packet to eliminate the phase deviation and ensure accurate reception and analysis of the data.

[0079] Step S6: The receiving end parses and reorganizes multiple encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation, and restores them to the originally transmitted data.

[0080] Among them, the receiving end can sort and verify the encoded data packets according to metadata such as the sequence number and check information in the synchronization header information to ensure the integrity and correctness of the data packets. During the parsing process, the receiving end extracts the data part in the encoded data packet and reorganizes it according to the sequence of the data to restore the originally transmitted data, that is, the data to be transmitted received by the sending end.

[0081] It should be noted that in the embodiments of the present application, the data to be transmitted received by the sending end is processed by packetizing, compressed and encapsulated for multiple data packets to improve the transmission rate. The FPGA is used to control the dynamic phase shift algorithm to perform phase encoding on the clock signal of each encapsulated data packet to generate a clock synchronization frame. Subsequently, it is transmitted to the receiving end in parallel through a multi-channel Ethernet. The receiving end estimates the phase error based on the synchronization header information of each encoded data packet, and performs dynamic phase compensation on the clock signals of multiple encoded data packets according to the estimation result. Based on the synchronization header information after dynamic phase compensation, multiple encoded data packets are parsed and reorganized to restore the originally transmitted data. This method not only reduces the synchronization delay that may occur in high-speed data transmission through dynamic phase compensation, but also rationally allocates and utilizes network communication resources through multi-channel parallel transmission, effectively avoiding resource waste and large resource occupation.

[0082] In some embodiments, multiple data packets are compressed, and the compressed multiple data packets are encapsulated to obtain multiple encapsulated data packets, including:

[0083] Step S201: Cluster and partition multiple data packets to obtain multiple clusters; each cluster includes a cluster center data packet and other data packets except the cluster center data packet.

[0084] Among them, the clustering and partitioning can divide similar data packets into the same cluster according to the characteristics of the data packets, such as size, type or content, etc. Each cluster contains a cluster center data packet and other data packets except the cluster center data packet. The cluster center data packet usually represents the main characteristics or attributes of the cluster and can be used as the representative of the cluster. By clustering and partitioning the data packets, the compression and encapsulation process of the data packets can be further optimized, and the efficiency and quality of data transmission can be improved.

[0085] The clustering algorithm can adopt algorithms such as the K-means algorithm, hierarchical clustering algorithm or DBSCAN algorithm.

[0086] Step S202: Construct a feature hyperplane based on the cluster center data packets, and project other data packets in the same cluster as each cluster center data packet onto the orthogonal complement space of the feature hyperplane to obtain the orthogonal projection matrix of the other data packets.

[0087] Among them, the cluster center data packet C and other data packets are respectively subjected to singular value decomposition to obtain a set of orthogonal bases for the column space of the cluster center data packet C. The orthogonal bases are used to construct the feature hyperplane, and the matrix obtained by the singular value decomposition of each data packet is projected onto the orthogonal complement space of this hyperplane: In the formula, is the orthogonal projection matrix of the i-th data packet, is the i-th data packet, , R is the space, L is the data packet length, M is the feature dimension, is a diagonal matrix (the diagonal elements are the singular values of the data packet).

[0088] Among them, this projection ensures the reversible recovery of the original data: In the formula, is the coefficient vector.

[0089] Step S203: Perform topological weighted coding based on the non-zero elements of the orthogonal projection matrix to obtain the orthogonal projection coding matrix.

[0090] Among them, the operation of topological weighted coding is expressed as: In the formula, A is the element after encoding the non-zero elements, is the element before encoding the non-zero elements, is a function based on the topological information , can be understood as a certain probability distribution or weight function of this element under the given topological information, used to measure its topological importance, is the topological feature related to the element , including the position of this element in the tensor, the relationship with adjacent elements, and the local structure it is in. Among them, the topological information can be determined by calculating the neighborhood relationship between pixels, edge detection, etc., which will not be elaborated here, is a hyperparameter greater than 0, used to adjust the influence degree of the exponential term in the weight, is the norm of the element .

[0091] Step S204: Preprocess the other data packets corresponding to the orthogonal projection coding matrix to obtain the matrix of the other data packets.

[0092] Among them, convert the other data packets corresponding to the orthogonal projection coding matrix into matrix form, that is , whose dimension and structure correspond to the orthogonal projection coding matrix to facilitate subsequent data processing.

[0093] Step S205: Perform a projection compression operation on matrices of other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet.

[0094] Among them, the matrix of other data packets corresponding to the orthogonal projection coding matrix is ​​projected through the orthogonal projection coding matrix, that is: Where Y is the matrix of the data packet after projection, is the transpose of the orthogonal projection encoding matrix.

[0095] It can be understood that by performing projection compression operations on matrices of other data packets corresponding to the orthogonal projection coding matrix through the orthogonal projection coding matrix, the data packets are converted into a new space defined by the orthogonal projection coding matrix, achieving data dimensionality reduction, occupying less storage space, and thus achieving data compression. When the original data is needed, the data can be restored by the inverse operation.

[0096] Step S206: Encapsulate each cluster center data packet and the compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet to obtain a plurality of encapsulated data packets.

[0097] It can be understood that the embodiment of the present application performs data compression on data packets of different clusters, and the cluster center data packet of each cluster represents the main features of the cluster. Therefore, in the encapsulation process, the cluster center data packet is encapsulated together with its corresponding compressed data packet, which can retain the main information of the data packet and reduce data redundancy. In this way, after receiving the encapsulated data packet, the receiving end can quickly understand the main content and features of the data packet based on the cluster center data packet, thereby improving the efficiency of data parsing and reorganization.

[0098] In some embodiments, the method further comprises:

[0099] Step S21, packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet;

[0100] Wherein, each orthogonal projection coding matrix and its corresponding data packet (in the form before or after compression) are combined to form a data packet unit.

[0101] Then, a unique sequence number is assigned to each such data packet unit, which is derived from the original data packet, ensuring the traceability between the data packet unit and the original data. This sequence number serves as a key, forming a key-value pair together with the data packet unit. All such sets of key-value pairs together form a key-value mapping data packet.

[0102] The key-value mapping data packet facilitates data storage and management, and also provides convenience for subsequent data retrieval and processing. When accessing or processing a specific data packet, it is only necessary to quickly locate the corresponding data packet according to the sequence number (i.e., the key), greatly improving the efficiency of data processing.

[0103] Step S22: Transmit the key-value mapping data packet into the virtual container of the target device to obtain a container image, which is used to forward the key-value mapping data packet corresponding to the key specified in the request message to the receiving end in response to the request message of the receiving end.

[0104] A container image is a lightweight, executable software package that contains resources such as code, runtime, system tools, and system libraries required to run an application. By placing the key-value mapping data packet in the container image, the consistency and portability of the data packet in different environments can be ensured.

[0105] When building a container image, first, the key-value mapping data packet and related dependencies and configuration files, etc., need to be packaged together to form a complete image file. This image file can then be deployed to any target device that supports container technology without caring about the differences in the underlying operating systems, achieving cross-platform data sharing and processing.

[0106] Among them, encapsulating the key-value mapping data packet into a container image realizes flexible deployment and efficient transmission of data. When the receiving end needs to access a specific data packet, it sends a request message to the target device, specifying the key (i.e., the sequence number of the data packet) to be obtained. After receiving the request, the target device quickly locates the corresponding key-value mapping data packet according to the mapping relationship in the container image and forwards it to the receiving end. This process not only improves the efficiency of data access but also ensures the security and integrity of the data.

[0107] In addition, the container image also has a version control function, which can conveniently manage and update the key-value mapping data packet. Whenever the data packet changes, a new version of the container image can be created and deployed and updated when needed, thus realizing continuous integration and continuous delivery of data.

[0108] Therefore, by transmitting the key-value mapping data packet into the virtual container of the target device and obtaining a container image in the embodiments of the present application, the flexibility and portability of the data can be greatly improved.

[0109] In some embodiments, the clock signal of each encapsulated data packet is phase-encoded by an FPGA-controlled dynamic phase shift algorithm to obtain a clock synchronization frame, and the clock synchronization frame is embedded in the synchronization header information to obtain a plurality of encoded data packets, including:

[0110] Step S301: For each encapsulated data packet, extract the data feature information of the encapsulated data packet.

[0111] Among them, the data feature information of the encapsulated data packet includes the size of the data packet, the data priority, the generation time of the data packet, and the source of the data packet.

[0112] Step S302: According to the data feature information, perform multi-dimensional phase space encoding on the clock signal of the encapsulated data packet through an FPGA-controlled dynamic phase shift algorithm to obtain a four-dimensional phase encoding matrix; among them, the dimensions of the four-dimensional phase encoding matrix include phase, cumulative phase adjustment amount, phase weighted average amount, and phase temperature drift amount.

[0113] Specifically, through the phase modulator integrated inside the FPGA, the clock signal of the encapsulated data packet is adjusted according to the data feature information. For example, for a data packet with a high priority, a larger phase shift can be given to ensure its priority processing. The larger the data packet, the larger the phase shift can be given to ensure its priority processing. The more important the source of the data packet, the larger the phase shift can be given to ensure its priority processing.

[0114] By mapping the clock signal of the encapsulated data packet into a multi-dimensional phase space, each dimension represents different phase information.

[0115] The phase dimension records the basic phase information of the clock signal;

[0116] The cumulative phase adjustment amount dimension is used to record the phase deviation that may accumulate during the transmission of the data packet; considering the generation time and size of the data packet, the cumulative phase adjustment amount is calculated. For example, for a data packet with a later generation time or a larger data packet, the cumulative phase adjustment amount can be appropriately increased.

[0117] Among them, the cumulative phase adjustment amount = +a1×data packet size + a2×data packet generation time, where a1 and a2 are both weights, is the phase.

[0118] The phase weighted average amount dimension smooths the phase information to reduce the influence of noise and interference; among them, data packets from different data packet sources can be given different weights to reflect their importance.

[0119] Among them, the phase weighted average amount is: In the formula, is the phase weighted average, s is the number of data feature dimensions, is the weight, is the phase.

[0120] The dimension of the phase temperature drift is due to the fact that the internal temperature of the FPGA may affect the phase of the clock signal. The internal temperature of the FPGA can be monitored in real time through a temperature sensor, and adjusted according to the relationship between temperature and phase drift to ensure the stability of the clock signal.

[0121] The phase temperature drift is: Phase temperature drift = In the formula, is the temperature drift coefficient, is the current ambient temperature, is the reference stability.

[0122] Step S303: Perform initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain a clock synchronization frame.

[0123] Among them, by monitoring the phase deviation change rate of the encapsulated data packet during transmission, and using the phase compensation module inside the FPGA, the four-dimensional phase encoding matrix is dynamically adjusted. The phase deviation change rate reflects the trend of phase offset of the data packet during transmission. By predicting this trend, the phase encoding can be pre-compensated to reduce the synchronization error.

[0124] Specifically, the operation of performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate is expressed as: In the formula, is the four-dimensional phase encoding matrix after pre-compensation, is the original four-dimensional phase encoding matrix, is the compensation coefficient, is the phase deviation, is the time.

[0125] Step S304: Embed the clock synchronization frame into the synchronization header information, and insert a phase synchronization header into the synchronization header information during the embedding process to obtain an encoded data packet; among them, the phase synchronization header is used to predict the phase of the next encoded data packet.

[0126] Among them, a phase synchronization header is inserted during data packet encapsulation. The phase synchronization header is used to predict the phase of the next encoded data packet, ensuring clock synchronization during data packet transmission. The phase synchronization header contains important information about the phase of the clock signal. The receiving end can adjust the phase of the received data packets based on this information to match the clock signal of the sending end, thereby achieving precise clock synchronization. By embedding the clock synchronization frame and the phase synchronization header, clock synchronization during data packet transmission is ensured, improving the reliability and stability of data transmission.

[0127] Among them, the expression of the phase synchronization header is: In the formula, is the phase synchronization header code, is the preamble, is the cyclic redundancy check code, is the absolute phase mark of the current data packet, is the predicted value of the phase of the next data packet based on LSTM.

[0128] Among them, LSTM (Long Short-Term Memory network) can process time series data and capture long-term dependencies. Here, by training on relevant data such as the phase information of previous data packets, LSTM can predict the phase change value of the next data packet. . The receiving end can use this predicted value to adjust the clock in advance, improving the accuracy and timeliness of clock synchronization and reducing the impact of phase errors on data transmission.

[0129] In some embodiments, multiple encoded data packets are transmitted in parallel to the receiving end through a multi-channel Ethernet, including:

[0130] Step S401: For each encoded data packet, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features.

[0131] Among them, extracting the multi-dimensional data packet features of the encoded data packet includes the size of the data packet, the transmission priority of the data packet, the generation timestamp of the data packet, the source address and destination address of the data packet, the checksum of the data packet, and the protocol type to which the data packet belongs, etc.

[0132] Integrate the feature information of the encoded data packet into a multi-dimensional array, that is, the data packet tensor. Each dimension of the data packet tensor represents different features of the data packet, and these features together constitute a complete description of the data packet during transmission. The data packet tensor of the encoded data packet is expressed as: In the formula, is the data packet tensor, is the length of the encoded data packet, is the dimension of the multi-dimensional data packet features.

[0133] Step S402: For each channel in the Ethernet, extract the multi-dimensional channel features of the channel, and construct the channel tensor of the channel according to the multi-dimensional channel features.

[0134] Among them, model the transmission characteristics of each channel, extract the multi-dimensional channel features of the channel. The multi-dimensional channel features include the bandwidth, delay, jitter, packet loss rate, and availability of the channel, etc. These features reflect the performance of the channel during data transmission.

[0135] Integrate the feature information of the channel into a multi-dimensional array, that is, the channel tensor. Each dimension of the channel tensor represents different characteristics of the channel, and these characteristics together constitute a complete description of the channel during data transmission. The tensor representation of the channel in the Ethernet is: In the formula, is the channel tensor, is the number of channels, is the dimension of the multi-dimensional channel features.

[0136] Step S403: Based on the packet tensor and the channel tensor, perform routing selection on the encoded packets through a deep learning algorithm to obtain the transmission channel corresponding to each encoded packet. Specifically, use the packet tensor and the channel tensor as the training data set of the deep learning model. Through training on the training data set, the deep learning model can discover the best matching relationship between the packet tensor and the channel tensor.

[0137] During the training phase, the model will receive a large number of packets and channel samples marked with correct routing selections, and continuously adjust the model parameters through the backpropagation algorithm to minimize the prediction error. Once the model training is completed, it can perform fast routing selection on the newly arrived encoded packets.

[0138] The deep learning model contains multiple hidden layers inside. These hidden layers gradually extract the high-level features of the packets and channels through complex non-linear transformations. These high-level features are used to make routing decisions at the output layer of the model, that is, to determine which channel each encoded packet should be transmitted through.

[0139] After the deep learning model training is completed, by inputting the packet tensor of the packet, the channel tensor corresponding to the packet and the channel label corresponding to the channel tensor can be output.

[0140] It can be understood that through the deep learning algorithm, the optimal transmission channel can be intelligently selected according to the current network conditions and packet characteristics, so as to maximize the efficiency and reliability of data transmission. This data-driven routing selection method has stronger adaptability and higher performance than the traditional rule-based or heuristic methods.

[0141] Step S404: Determine the transmission characteristic tensor according to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein, the transmission characteristic tensor is used to characterize the transmission coefficients of each encoded data packet on the transmission channel.

[0142] Among them, by comprehensively considering the information of the data packet tensor and the channel tensor, the transmission characteristic tensor is calculated. The transmission characteristic tensor is a multi-dimensional array, and each element of it represents the transmission coefficient of the corresponding encoded data packet on the corresponding transmission channel. The transmission coefficient is expressed as: In the formula, is the transmission coefficient between the u-th data packet and the g-th transmission channel, is the weight, is the m-th feature of the u-th data packet, is the d-th feature of the g-th transmission channel.

[0143] Step S405: Determine the transmission power and transmission time slot of each encoded data packet on the transmission channel corresponding to the encoded data packet according to the transmission characteristic tensor.

[0144] Among them, the goal of adjusting the transmission power is to minimize the power consumption as much as possible on the premise of ensuring the correct transmission of the data packet, so as to improve the transmission utilization rate. The power can be adjusted according to the transmission coefficient in the transmission characteristic tensor in combination with the relationship between the bit error rate and the signal-to-noise ratio (SNR). Assume that the initial power of the u-th data packet on the g-th channel is , and the power after adjustment according to the transmission coefficient is , and the following formula can be used to determine the transmission power: In the formula, g() is the adjustment linear function, is the target bit error rate, is the current bit error rate.

[0145] The goal of adjusting the transmission time slot is to reasonably allocate channel resources, avoid conflicts and interference between data packets, and improve the transmission efficiency. The transmission time slot can be adjusted according to the transmission coefficient in the transmission characteristic tensor in combination with the priority of the data packet and the bandwidth of the channel.

[0146] Sort the data packets according to the transmission coefficient, and the data packets with larger transmission coefficients are transmitted first. Then, according to the bandwidth of the channel and the length of the data packet, calculate the transmission time slot required for each data packet. For example, the transmission time slot required for the u-th data packet on the g-th channel is: In the formula, is the transmission time slot required for the u-th data packet on the g-th channel, is the length of the data packet, is the bandwidth of the g-th transmission channel.

[0147] Step S406: Transmit multiple encoded data packets to the receiving end through their corresponding transmission channels according to the transmission power and transmission time slots.

[0148] Among them, by allocating the encoded data packets and their corresponding transmission channels according to the transmission power and transmission time slots, the encoded data packets can be put into a queue in the order of their transmission time slots. When a certain time slot arrives, the encoded data packet corresponding to this time slot is sent through its corresponding transmission channel. At the same time, adjust the transmission power of the sending end according to the transmission power to ensure that the data packets can be correctly transmitted to the receiving end.

[0149] In some embodiments, the receiving end estimates the phase error according to the synchronization header information of each encoded data packet, and dynamically compensates the clock signals of multiple encoded data packets according to the phase error estimation result, including:

[0150] Step S501: The receiving end extracts the four-dimensional phase encoding matrix in the synchronization header information of each encoded data packet.

[0151] Step S502: Determine the phase error between the phase in the four-dimensional phase encoding matrix and the preset reference phase through a time-to-digital converter.

[0152] Among them, the receiving end needs to accurately measure the phase error between the received signal and the reference signal. The phase error between the rising edges of two signals can be accurately measured through a time-to-digital converter (TDC). Specifically: In the formula, is the phase error, is the clock frequency, () is the actual phase of the received signal and the reference phase The time difference between them.

[0153] Step S503: Input the phase temperature drift amount in the four-dimensional phase encoding matrix into the pre-trained LSTM phase temperature drift prediction model, and output the phase temperature drift compensation amount.

[0154] Among them, since the four-dimensional phase encoding matrix contains the current phase temperature drift compensation amount predicted by LSTM, by inputting the phase temperature drift amount in the four-dimensional phase encoding matrix into the pre-trained LSTM phase temperature drift prediction model, the phase temperature drift compensation amount of the receiving end is output.

[0155] Step S504: Compensate the phase temperature drift amount with the phase temperature drift compensation amount.

[0156] Among them, the actually measured phase temperature drift amount at the receiving end is added to the phase temperature drift compensation amount to obtain the compensated phase temperature drift amount, thereby reducing the phase error caused by temperature drift and further improving the accuracy and stability of clock synchronization.

[0157] Step S505: Compensate the phase, the accumulated phase adjustment amount, and the phase weighted average amount in the four-dimensional phase encoding matrix according to the compensated phase temperature drift amount and the phase error.

[0158] Among them, the compensated phase temperature drift amount obtained through the foregoing steps is used to correspondingly adjust the phase in the four-dimensional phase encoding matrix. The compensation operation can be expressed as: In the formula, is the compensated phase, is the original phase, is the phase temperature drift compensation amount; and are both weights, is a constant that controls the degree of attenuation, is the order, and the order can be set based on experience and generally takes an integer greater than 2, which is used to characterize the non-linear relationship between the phase and temperature.

[0159] The compensated phase is then used to adjust the accumulated phase adjustment amount and the phase weighted average amount to ensure the overall phase synchronization accuracy.

[0160] It can be understood that through the phase compensation measure, the receiving end can perform precise dynamic phase compensation on the clock signal of the received encoded data packet, thereby effectively reducing the phase error caused by various interference factors (such as temperature drift, phase deviation change, etc.) during the transmission process. This not only improves the clock synchronization accuracy of data transmission but also enhances the stability and reliability of data transmission, providing a strong guarantee for the performance of the Ethernet synchronization communication method and device based on FPGA and dynamic phase shift in practical applications.

[0161] In some embodiments, the receiving end parses and reorganizes multiple encoded data packets according to the synchronization header information of the encoded data packet after dynamic phase compensation to restore the originally transmitted data, including:

[0162] Step S601: The receiving end extracts the synchronization header information of the encoded data packet after dynamic phase compensation for phase synchronization.

[0163] Among them, the receiving end first parses the phase synchronization header in the synchronization header information, and uses the phase information therein to adjust the phase of the received data packet to ensure that the data packet is synchronized with the clock signal of the sending end. The process of phase synchronization involves comparing and adjusting the phase of the received data packet with the predicted phase of the sending end. Through precise phase control, data transmission errors caused by phase deviation can be significantly reduced.

[0164] Step S602: Determine the sequence number of the encoded data packet according to the phase-synchronized encoded data packet.

[0165] Among them, by parsing the sequence number field in the synchronization header information, the receiving end can identify the order of each data packet. The sequence number ensures the orderliness of the data packets during transmission. Even if data packets are lost or out of order during transmission, the receiving end can reorder them according to the sequence number and restore the original order of the data.

[0166] Step S603: Generate a request message according to the sequence number of the encoded data packet, and send the request message to the target device.

[0167] Step S604: The target device responds to the request message. According to the sequence number of the encoded data packet contained in the request message, it searches for the key-value mapped data packet corresponding to the sequence number in the virtual container. After receiving the request message, the target device will parse the sequence number in the request message and search for the key-value mapped data packet corresponding to the sequence number in the virtual container it maintains. The virtual container is a logically data structure used to store and manage data packets and their related information, such as sequence numbers, data packet contents, check codes, etc.

[0168] It can be understood that through the key-value mapping method, the target device can quickly locate the required data packet and improve the efficiency of data retrieval.

[0169] Step S605: Forward the key-value mapped data packet to the receiving end through the container image.

[0170] Step S606: The receiving end performs an inverse projection operation on the corresponding encoded data packet through the key-value mapped data packet to obtain the original transmitted data of the encoded data packet.

[0171] Among them, due to the aforementioned process of compressing multiple data packets, a projection operation is performed on the data packets. At the same time, this projection operation is reversible. Therefore, the receiving end uses the information in the received key-value mapped data packet to perform an inverse projection process on the previously received encoded data packet, and gradually restores the original data of the encoded data packet before transmission.

[0172] Before this reverse projection processing, the receiving end will also use information such as check codes to verify the integrity of the data packets, ensuring that no errors occur during data transmission. If an error is detected, the receiving end will attempt error correction or request the sending end to resend the erroneous data packets. Finally, through the reverse projection operation, the receiving end can successfully recover the originally transmitted data and complete the entire data transmission process. This process not only ensures the reliability of data transmission but also improves the efficiency of data transmission.

[0173] Step S607: Reorder the originally transmitted data of each encoded data packet according to the sequence number of each encoded data packet to obtain the originally transmitted data.

[0174] Among them, after the receiving end successfully recovers the originally transmitted data of all encoded data packets, it will reorder these data according to the sequence numbers of the encoded data packets. The sequence number, as a key identifier of the data packet, ensures the orderliness of the data packet during transmission and reception. Through the reordering operation, the receiving end can restore these data to their original order at the sending end, thereby ensuring the integrity and consistency of the data.

[0175] During the reordering process, the receiving end will check the sequence number of each data packet and sort them according to the size of the sequence number. If there are situations where the sequence numbers are discontinuous or repeated, the receiving end will perform corresponding processing, such as requesting the sending end to resend the missing or repeated data packets to ensure the integrity and accuracy of the data.

[0176] After completing the reordering, the receiving end can obtain the originally transmitted data.

[0177] Based on the same inventive concept, an embodiment of the present application also provides an Ethernet synchronization communication device based on FPGA and dynamic phase shift for implementing the above-mentioned Ethernet synchronization communication method involving FPGA and dynamic phase shift.

[0178] The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more embodiments of the Ethernet synchronization communication device based on FPGA and dynamic phase shift provided below can refer to the limitations on the Ethernet synchronization communication method based on FPGA and dynamic phase shift in the above text, and will not be elaborated here.

[0179] As Figure 2 shown, an embodiment of the present application provides an Ethernet synchronization communication device based on FPGA and dynamic phase shift, including:

[0180] A data packet splitting module 100, configured to split the data to be transmitted received by the sending end into multiple data packets;

[0181] A data encapsulation module 200, which is used to compress multiple data packets and encapsulate the compressed multiple data packets to obtain multiple encapsulated data packets; the encapsulated data packets include synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end;

[0182] A phase encoding module 300, which is used to perform phase encoding on the clock signal of each encapsulated data packet through an FPGA-controlled dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets;

[0183] A data transmission module 400, which is used to parallelly transmit multiple encoded data packets to the receiving end through a multi-channel Ethernet;

[0184] A phase compensation module 500, which is used for the receiving end to estimate the phase error according to the synchronization header information of each encoded data packet, and perform dynamic phase compensation on the clock signals of multiple encoded data packets according to the phase error estimation result;

[0185] A data recombination module 600, which is used for the receiving end to parse and recombine multiple encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation, and restore them to the original transmitted data.

[0186] In some embodiments, the data encapsulation module 200 is used for:

[0187] Performing clustering division on multiple data packets to obtain multiple clusters; each cluster includes a clustering center data packet and other data packets except the clustering center data packet;

[0188] Constructing a feature hyperplane according to the clustering center data packet, and projecting other data packets in the same cluster as each clustering center data packet onto the orthogonal complement space of the feature hyperplane to obtain an orthogonal projection matrix of other data packets;

[0189] Performing topological weighted encoding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection encoding matrix;

[0190] Preprocessing the other data packets corresponding to the orthogonal projection encoding matrix to obtain a matrix of other data packets;

[0191] Performing a projection compression operation on the matrix of other data packets corresponding to the orthogonal projection encoding matrix according to the orthogonal projection encoding matrix to obtain compressed data packets;

[0192] Encapsulating each clustering center data packet and the compressed data packets corresponding to other data packets in the same cluster as the clustering center data packet to obtain multiple encapsulated data packets.

[0193] In some embodiments, the device further includes: a data mirroring module, which is used for:

[0194] Pack the orthogonal projection coding matrix corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and use the serial number of the data packet corresponding to the orthogonal projection coding matrix as the key to obtain a key-value mapping data packet;

[0195] Transmit the key-value mapping data packet into the virtual container of the target device to obtain a container image, which is used to forward the key-value mapping data packet corresponding to the specified key in the request information to the receiving end in response to the request information of the receiving end.

[0196] In some embodiments, the phase encoding module 300 is used for:

[0197] For each encapsulated data packet, extract the data feature information of the encapsulated data packet;

[0198] According to the data feature information, perform multi-dimensional phase space encoding on the clock signal of the encapsulated data packet through the FPGA-controlled dynamic phase shift algorithm to obtain a four-dimensional phase encoding matrix; wherein, the dimensions of the four-dimensional phase encoding matrix include phase, cumulative phase adjustment amount, phase weighted average amount, and phase temperature drift amount;

[0199] Perform initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain a clock synchronization frame;

[0200] Embed the clock synchronization frame into the synchronization header information, and insert a phase synchronization header into the synchronization header information during the embedding process to obtain an encoded data packet; wherein, the phase synchronization header is used to predict the phase of the next encoded data packet.

[0201] In some embodiments, the data transmission module 400 is used for:

[0202] For each encoded data packet, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features;

[0203] For each channel in the Ethernet, extract the multi-dimensional channel features of the channel, and construct a channel tensor of the channel according to the multi-dimensional channel features;

[0204] Based on the data packet tensor and the channel tensor, perform routing selection on the encoded data packet through a deep learning algorithm to obtain the transmission channel corresponding to each encoded data packet.

[0205] According to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet, determine the transmission characteristic tensor; wherein, the transmission characteristic tensor is used to characterize the transmission coefficient of each encoded data packet on the transmission channel;

[0206] Determine the transmission power and transmission time slot of each encoded data packet on the transmission channel corresponding to the encoded data packet according to the transmission characteristic tensor;

[0207] According to the transmission power and transmission time slots, multiple encoded data packets are transmitted to the receiving end through their corresponding transmission channels.

[0208] In some embodiments, the phase compensation module 500 is configured to:

[0209] The receiving end extracts the four-dimensional phase encoding matrix in the synchronization header information of each encoded data packet;

[0210] Determine the phase error between the phase in the four-dimensional phase encoding matrix and the preset reference phase through a time-to-digital converter;

[0211] Input the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and output the phase temperature drift compensation amount;

[0212] Compensate the phase temperature drift amount through the phase temperature drift compensation amount;

[0213] Compensate the phase, the cumulative phase adjustment amount, and the phase weighted average amount in the four-dimensional phase encoding matrix according to the compensated phase temperature drift amount and the phase error.

[0214] In some embodiments, the data reorganization module 600 is used for:

[0215] The receiving end extracts the synchronization header information of the encoded data packet after dynamic phase compensation for phase synchronization;

[0216] Determine the sequence number of the encoded data packet according to the phase-synchronized encoded data packet;

[0217] Generate a request message according to the sequence number of the encoded data packet, and send the request message to the target device;

[0218] The target device responds to the request message, and according to the sequence number of the encoded data packet included in the request message, finds the key-value mapping data packet corresponding to the sequence number in the virtual container;

[0219] Forward the key-value mapping data packet to the receiving end through the container image;

[0220] The receiving end performs a back-projection operation on the corresponding encoded data packet through the key-value mapping data packet to obtain the originally transmitted data of the encoded data packet;

[0221] Reorder the originally transmitted data of each encoded data packet according to the sequence numbers of the encoded data packets to obtain the originally transmitted data.

[0222] Such as Figure 3As shown in the figure, an embodiment of the present application provides an electronic device. The electronic device 10 includes a memory 20 and a processor 30. A computer program is stored in the memory 20. When the computer program is executed by the processor 30, the processor 30 is caused to execute the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift in the above embodiment.

[0223] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift in the above embodiment are implemented.

[0224] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, electronic devices, and computer storage media can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0225] It should be noted that the terms "including" and "having" in the description and claims of the present invention and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0226] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps do not necessarily have to be executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily have to be sequential, but can be executed alternately or alternately with at least some of the steps or stages in other steps or other steps.

[0227] In several embodiments provided by the present invention, it should be understood that the disclosed systems, electronic devices, computer storage media, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0229] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0230] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (English full name: Read-Only Memory, English abbreviation: ROM), random access memories (English full name: Random Access Memory, English abbreviation: RAM), magnetic disks, or optical discs that can store program codes.

[0231] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An Ethernet synchronous communication method based on FPGA and dynamic phase shift, characterized in that: include: The data to be transmitted received by the sending end is divided into packets to obtain multiple data packets; Compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; The encapsulated data packet includes synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; including: Clustering the plurality of data packets to obtain a plurality of clusters; each of the clusters includes a cluster center data packet and other data packets except the cluster center data packet; Constructing a feature hyperplane according to the cluster center data packets, and projecting other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain an orthogonal projection matrix of the other data packets; Performing topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix; Preprocessing other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of the other data packets; Performing a projection compression operation on the matrix of the other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet; Encapsulating each of the cluster center data packets and compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet to obtain a plurality of encapsulated data packets; Performing phase encoding on the clock signal of each encapsulated data packet by controlling a dynamic phase shift algorithm through FPGA to obtain a clock synchronization frame, and embedding the clock synchronization frame into the synchronization header information to obtain a plurality of encoded data packets; Transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The receiving end parses and reassembles a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restores the coded data to the originally transmitted data.

2. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: Also includes: Packing the orthogonal projection coding matrices corresponding to each compressed data packet and the data packet corresponding to the orthogonal projection coding matrix, and using the serial number of the data packet corresponding to the orthogonal projection coding matrix as a key to obtain a key-value mapping data packet; The key-value mapping data packet is transmitted to the virtual container of the target device to obtain a container image, and the container image is used to respond to the request information of the receiving end and forward the key-value mapping data packet corresponding to the key specified in the request information to the receiving end.

3. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: The method controls the dynamic phase shift algorithm through FPGA to perform phase encoding on the clock signal of each encapsulated data packet to obtain a clock synchronization frame, and embeds the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets, including: For each of the encapsulated data packets, extracting data feature information of the encapsulated data packet; According to the data feature information, a clock signal of the encapsulated data packet is multi-dimensionally phase-space encoded by controlling a dynamic phase shift algorithm through an FPGA to obtain a four-dimensional phase encoding matrix; wherein the dimensions of the four-dimensional phase encoding matrix include a phase, an accumulated phase adjustment amount, a phase weighted average amount, and a phase temperature drift amount; Performing initial phase offset pre-compensation on the four-dimensional phase encoding matrix according to the phase deviation change rate to obtain the clock synchronization frame; The clock synchronization frame is embedded in the synchronization header information, and during the embedding process, a phase synchronization header is inserted into the synchronization header information to obtain the encoded data packet; wherein the phase synchronization header is used to predict the phase of the next encoded data packet.

4. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 1, characterized in that: The step of transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet comprises: For each of the encoded data packets, extract the multi-dimensional data packet features of the encoded data packet, and construct a data packet tensor of the encoded data packet according to the multi-dimensional data packet features; For each channel in the Ethernet, extract the multidimensional channel features of the channel, and construct a channel tensor of the channel according to the multidimensional channel features; Based on the data packet tensor and the channel tensor, routing the encoded data packets is performed by a deep learning algorithm to obtain a transmission channel corresponding to each encoded data packet; Determine a transmission characteristic tensor according to the data packet tensor of the encoded data packet and the channel tensor of the transmission channel corresponding to the encoded data packet; wherein the transmission characteristic tensor is used to characterize the transmission coefficient of each encoded data packet on the transmission channel; Determine, according to the transmission characteristic tensor, the transmission power and transmission time slot of each of the encoded data packets on the transmission channel corresponding to the encoded data packet; According to the transmission power and the transmission time slot, a plurality of the encoded data packets are transmitted to the receiving end through their corresponding transmission channels.

5. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 3, characterized in that: The receiving end estimates the phase error according to the synchronization header information of each of the encoded data packets, and performs dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result, including: The receiving end extracts a four-dimensional phase coding matrix from the synchronization header information of each of the coded data packets; Determining a phase error between a phase in the four-dimensional phase encoding matrix and a preset reference phase by a time-to-digital converter; Inputting the phase temperature drift amount in the four-dimensional phase encoding matrix into a pre-trained LSTM phase temperature drift prediction model, and outputting the phase temperature drift compensation amount; Compensating the phase temperature drift amount by using the phase temperature drift compensation amount; The phase, the accumulated phase adjustment amount and the phase weighted average amount in the four-dimensional phase encoding matrix are compensated according to the compensated phase temperature drift amount and the phase error.

6. The Ethernet synchronous communication method based on FPGA and dynamic phase shift according to claim 2, characterized in that: The receiving end parses and reassembles a plurality of the encoded data packets according to the synchronization header information of the encoded data packets after dynamic phase compensation to restore the data to the original transmitted data, including: The receiving end extracts the synchronization header information of the coded data packet after dynamic phase compensation to perform phase synchronization; Determining a sequence number of the encoded data packet according to the phase-synchronized encoded data packet; generating the request information according to the serial number of the encoded data packet, and sending the request information to the target device; The target device responds to the request information and searches for a key-value mapping data packet corresponding to the serial number in the virtual container according to the serial number of the encoded data packet included in the request information; Forwarding the key-value mapping data packet to the receiving end through the container image; The receiving end performs a reverse projection operation on the corresponding coded data packet through the key-value mapping data packet to obtain the original transmitted data of the coded data packet; The originally transmitted data of each of the encoded data packets are reordered according to the sequence number of each of the encoded data packets to obtain the originally transmitted data.

7. An Ethernet synchronous communication device based on FPGA and dynamic phase shift, characterized in that: include: A data packetization module is used to packetize the data to be transmitted received by the sending end to obtain multiple data packets; A data encapsulation module, used for compressing the plurality of data packets, and encapsulating the compressed data packets to obtain a plurality of encapsulated data packets; the encapsulated data packets contain synchronization header information, and the synchronization header information is used for clock synchronization at the receiving end; The data encapsulation module is used to: Clustering multiple data packets to obtain multiple clusters; each cluster includes a cluster center data packet and other data packets except the cluster center data packet; Construct a feature hyperplane based on the cluster center data packets, and project other data packets in the same cluster as each cluster center data packet to the orthogonal complementary space of the feature hyperplane to obtain the orthogonal projection matrix of other data packets; Perform topological weighted coding according to the non-zero elements of the orthogonal projection matrix to obtain an orthogonal projection coding matrix; Preprocessing other data packets corresponding to the orthogonal projection coding matrix to obtain matrices of other data packets; Performing a projection compression operation on matrices of other data packets corresponding to the orthogonal projection coding matrix according to the orthogonal projection coding matrix to obtain a compressed data packet; Encapsulating each cluster center data packet and compressed data packets corresponding to other data packets in the same cluster as the cluster center data packet to obtain multiple encapsulated data packets; A phase encoding module, used to perform phase encoding on the clock signal of each encapsulated data packet through FPGA control of a dynamic phase shift algorithm to obtain a clock synchronization frame, and embed the clock synchronization frame into the synchronization header information to obtain multiple encoded data packets; A data transmission module, used for transmitting the plurality of encoded data packets in parallel to the receiving end via a multi-channel Ethernet; A phase compensation module, used for the receiving end to estimate the phase error according to the synchronization header information of each of the encoded data packets, and to perform dynamic phase compensation on the clock signals of the plurality of encoded data packets according to the phase error estimation result; The data reassembly module is used for the receiving end to parse and reassemble a plurality of coded data packets according to the synchronization header information of the coded data packets after dynamic phase compensation, and restore them to the originally transmitted data.

8. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the steps of the Ethernet synchronous communication method based on FPGA and dynamic phase shift as described in any one of claims 1 to 6 are implemented.

Images