FPGA lookup table circuit and implementation method

Abstract

The present invention relates to the field of integrated circuit technology, and discloses an FPGA lookup table circuit and implementation method. The lookup table circuit includes: a first decoder for acquiring a first address input signal of a lookup table, decoding the first address input signal to obtain first decoded data; a first selector for acquiring multi-bit RAM data, selecting and processing the RAM multi-bit data using the first decoded data to obtain output multi-bit data; a second decoder for acquiring a second address input signal of the lookup table, decoding the second address input signal to obtain second decoded data; and a second selector for selecting and processing the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table. The present invention consumes fewer components, saves logic resources and area occupied by LUTs in FPGAs, and has the effect of enhancing versatility.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an FPGA lookup table circuit and an implementation method thereof. Background Art

[0002] LUT (Lookup Table) is an important component of FPGA (Field-Programmable Gate Array). LUT can be regarded as a RAM (Random Access Memory) with multiple address lines. By inputting the address signal to look up the table, the content pre-written in the RAM at that address is output, thus realizing a logical operation on the signal.

[0003] The relevant lookup table adopts an architecture consisting of RAM and its supporting multi-level selectors, and each level of selectors is controlled by a 1-bit input terminal; however, with the increase in the scale of programmable logic devices and the improvement of functional requirements, the relevant lookup table has encountered problems such as insufficient operating speed, increased power consumption and increased on-chip area. The above problems have become key factors restricting the overall performance of FPGA chips. Summary of the Invention

[0004] In view of this, the present invention provides an FPGA lookup table circuit and implementation method to solve the problems of insufficient operating speed, increased power consumption and increased on-chip area of ​​related lookup tables.

[0005] In a first aspect, the present invention provides an FPGA lookup table circuit, the lookup table circuit comprising a first decoder, a second decoder, a first selector, and a second selector; wherein the output of the first decoder is connected to the input of the first selector, the output of the second decoder is connected to the input of the second selector, and the output of the first selector is connected to the input of the second selector;

[0006] a first decoder, configured to obtain a first address input signal from the lookup table, decode the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector;

[0007] a first selector, configured to obtain RAM multi-bit data, select and process the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector;

[0008] a second decoder, configured to obtain a second address input signal from the lookup table, decode the second address input signal to obtain second decoded data, and transmit the second decoded data to a second selector;

[0009] The second selector is used to select and process the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

[0010] The FPGA lookup table circuit provided by the embodiment of the present invention forms a dual-decoder LUT addressing structure by arranging a first decoder, a second decoder, a first selector, and a second selector in the lookup table circuit. Compared with an LUT with a multi-stage selector structure, the dual-decoder LUT addressing structure consumes fewer devices, saving area resources and overall power consumption. At the same time, the dual-decoder LUT addressing structure has excellent symmetry and can be arranged in an orderly and regular manner, saving logic resources and area occupied by LUTs in the FPGA, thereby facilitating the optimization of layout space on the FPGA chip. The dual decoder is used as the control unit of the two-stage selector, and each stage selector is controlled by a multi-bit input terminal. This can shorten the difference between the fastest and slowest signal delays to the delay size of one selector, thereby curbing the delay performance degradation of each port, having the effect of enhancing versatility and being flexible and friendly to chip hardware wiring, software interaction, etc.

[0011] In an optional implementation, the first decoder is specifically configured to perform an inversion operation on the first address input signal to obtain an inverted signal, and arrange and combine the first address input signal and the inverted signal to obtain first decoded data.

[0012] The FPGA lookup table circuit provided in an embodiment of the present invention utilizes a first decoder to decode the divided first address input signal. Since the number of input bits of the divided first address input signal is relatively small, the decoding complexity of the first decoder is effectively reduced, and the addressing speed of the FPGA lookup table circuit is improved.

[0013] In an optional embodiment, the first selector is specifically configured to select the RAM multi-bit data corresponding to the input port based on the first decoded data, obtain the output multi-bit data, and transmit the output multi-bit data to the second selector;

[0014] The FPGA lookup table circuit provided by the embodiment of the present invention controls the selection control logic of the first selector through the first decoding data, thereby improving the flexibility of the selection control, effectively improving the working performance of the selector, and reducing the overall power consumption and area of ​​the FPGA.

[0015] In an optional embodiment, the second selector is specifically used to select the output multi-bit data corresponding to the input port based on the low-level data when one bit of data in the second decoded data is low-level data and the remaining bit data are all high-level data, so as to obtain single-bit output data of the lookup table; wherein the single-bit data in the output multi-bit data corresponds one-to-one to the input port of the second selector.

[0016] The FPGA lookup table circuit provided in the embodiment of the present invention controls the selection control logic of the second selector through the second decoding data, thereby controlling the second selector to output single-bit output data, thereby realizing the addressing function of the lookup table and accelerating the comprehensive transmission rate of the addressing signal in the lookup table.

[0017] In an optional implementation, both the first decoder and the second decoder are 3-8 decoders.

[0018] In the FPGA lookup table circuit provided by an embodiment of the present invention, both the first decoder and the second decoder adopt 3-8 decoders, and a dual 3-8 decoder is used as the addressing configuration. The total number of logic levels of the six input-output paths is small, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output path.

[0019] In an optional implementation, both the first selector and the second selector adopt one-hot code multiplexers, which reduces decoding delay and improves selection speed.

[0020] The FPGA lookup table circuit provided in an embodiment of the present invention adopts a one-hot code multiplexer as the first selector and the second selector. The first selector and the second selector are controlled by multi-bit input terminals, thereby improving the flexibility of use, effectively improving working performance, and reducing overall power consumption and area.

[0021] In an optional embodiment, the method further includes:

[0022] The first buffer is connected to the input end of the first selector and is used for obtaining the RAM multi-bit data and inputting the RAM multi-bit data into the first selector.

[0023] The FPGA lookup table circuit provided in an embodiment of the present invention uses a first buffer to obtain RAM multi-bit data and inputs the RAM multi-bit data into a first selector, thereby achieving caching of the RAM multi-bit data. This ensures that the FPGA lookup table circuit does not lose important data due to external interruptions, while also ensuring the integrity of the lookup table task.

[0024] In an optional embodiment, the method further includes:

[0025] The second buffer is connected to the output end of the second selector, and is used for obtaining the single-bit output data of the lookup table and transmitting the single-bit output data of the lookup table to the lookup table outlet.

[0026] The FPGA lookup table circuit provided in an embodiment of the present invention uses a second buffer to obtain single-bit output data of the lookup table, and transmits the single-bit output data of the lookup table to the lookup table outlet, so that the single-bit output data of the lookup table arrives at the receiving device synchronously, thereby ensuring the accuracy and consistency of data reception.

[0027] In a second aspect, the present invention provides an FPGA, comprising: an FPGA lookup table circuit according to the first aspect or any corresponding embodiment thereof.

[0028] In a third aspect, the present invention provides a method for implementing an FPGA lookup table circuit, which is applied to the FPGA lookup table circuit of the first aspect or any corresponding embodiment thereof, the method comprising:

[0029] The first decoder obtains a first address input signal from the lookup table, decodes the first address input signal to obtain first decoded data, and transmits the first decoded data to the first selector;

[0030] The first selector obtains the RAM multi-bit data, selects and processes the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmits the output multi-bit data to the second selector;

[0031] The second decoder obtains a second address input signal from the lookup table, decodes the second address input signal to obtain second decoded data, and transmits the second decoded data to the second selector;

[0032] The second selector selects and processes the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a structural block diagram of an FPGA lookup table circuit according to an embodiment of the present invention;

[0035] Figure 2 2 is a schematic structural diagram of an FPGA lookup table circuit according to an embodiment of the present invention;

[0036] Figure 3 The figure is a flow chart of a method for implementing an FPGA lookup table circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0038] In this embodiment, a FPGA lookup table circuit is provided, such as Figure 1 As shown, the lookup table circuit includes a first decoder 101, a second decoder 102, a first selector 103 and a second selector 104; wherein, the output end of the first decoder 101 is connected to the input end of the first selector 103, the output end of the second decoder 102 is connected to the input end of the second selector 104, and the output end of the first selector 103 is connected to the input end of the second selector 104.

[0039] The first decoder 101 is configured to obtain a first address input signal of the lookup table, decode the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector 103 .

[0040] Specifically, the FPGA lookup table is a storage cell array consisting of an address signal and RAM multi-bit data corresponding to the address signal.

[0041] Furthermore, the address input signal of the lookup table is obtained, and the address input signal of the lookup table is divided to obtain a first address input signal and a second address input signal; wherein, the address of the lookup table has a total of n bits, and the n-bit address is reasonably divided into two parts according to actual conditions, for example, the upper m bits are assigned to the first decoder 101, and the lower k bits (where n = m + k) are assigned to the second decoder 102; for example, if the lookup table address has 8 bits, the upper 4 bits can be divided as the first address input signal to the first decoder 101, and the lower 4 bits can be divided as the second address input signal to the second decoder 102.

[0042] The first selector 103 is configured to obtain RAM multi-bit data, select and process the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector 104 .

[0043] The second decoder 102 is configured to obtain a second address input signal from the lookup table, decode the second address input signal to obtain second decoded data, and transmit the second decoded data to the second selector 104 .

[0044] Specifically, the first decoder 101 and the second decoder 102 are respectively used as control units of the two-stage selector, and each stage of the selector is controlled by a multi-bit input terminal (ie, output data of the first decoder 101 and the second decoder 102).

[0045] The second selector 104 is configured to select and process the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

[0046] This embodiment provides an FPGA lookup table circuit. A first decoder, a second decoder, a first selector, and a second selector are provided in the lookup table circuit to form a dual-decoder LUT addressing structure. Compared to a LUT with a multi-stage selector structure, the dual-decoder LUT addressing structure consumes fewer devices, saving area resources and overall power consumption. Furthermore, the dual-decoder LUT addressing structure has excellent symmetry and can be arranged in an orderly and regular manner, saving logic resources and area occupied by LUTs in the FPGA, thereby facilitating optimization of layout space on the FPGA chip. Furthermore, the dual decoder is used as the control unit for a two-stage selector, with each stage of the selector controlled by a multi-bit input. This shortens the delay difference between the fastest and slowest signals to the delay of a single selector, thereby curbing delay performance degradation at each port. This enhances versatility and is flexible and user-friendly for chip hardware wiring and software interaction.

[0047] In some optional implementations, the first decoder 101 is specifically configured to perform an inversion operation on the first address input signal to obtain an inverted signal, and arrange and combine the first address input signal and the inverted signal to obtain first decoded data.

[0048] For example, the first decoder 101 arranges and combines three input signals (ie, first address input signals) and their inverted signals. Each three signals serve as inputs of a NAND gate device, and a total of eight outputs (ie, first decoded data) can be generated.

[0049] Among them, the first decoder 101 decodes the m-bit first address input signal through the internal combinational logic circuit; taking a 4-bit address input signal as an example, a 4-bit binary number can represent 16 different states, so the first decoder 101 can generate 16 different selection signals, and the decoding logic can be constructed internally through multiple basic logic gates such as AND gates and OR gates; wherein, the selection signal can be transmitted to the first selector 103 as the first decoding data, which is used to control the selection logic of the first selector 103. By adjusting the level state of the input signal of the first decoder 101 or the second decoder 102, it can be determined which path of the first selector 103 or the second selector 104 is turned on, thereby realizing a directional selection function.

[0050] Furthermore, the function of the second decoder 102 is the same as that of the first decoder 101 .

[0051] This embodiment provides an FPGA lookup table circuit, which utilizes a first decoder to decode the divided first address input signal. Since the number of input bits of the divided first address input signal is relatively small, the decoding complexity of the first decoder is effectively reduced, and the addressing speed of the FPGA lookup table circuit is improved.

[0052] In some optional implementations, the first selector 103 is specifically configured to select RAM multi-bit data corresponding to the input port based on the first decoded data, obtain output multi-bit data, and transmit the output multi-bit data to the second selector 104 .

[0053] Specifically, the first selector 103 includes an input port, an output port, and a selection control circuit composed of a logic gate circuit; wherein the input port receives the RAM multi-bit data in the lookup table and the first decoded data sent by the output end of the first decoder 101, and the selection control port in the selection control circuit controls the on and off of the input port according to the level state of the first decoded data, that is, when the first decoded data is at a low level, the data of the input port corresponding to the first decoded data is used as the output, otherwise, the data is cut off; the first selector 103 includes multiple output ports, and the selection control circuit is used to control the output port to send the output multi-bit data to the second selector 104.

[0054] Furthermore, the selection control circuit utilizes logic gates such as AND gates and OR gates to implement the selection function.

[0055] For example, the first selector 103 uses mux8, which has eight parallel switches, each switch is connected to one bit of data. If the first decoded data is at a low level, the path corresponding to the switch is selected for RAM single-bit data transmission; if the first decoded data is at a high level, the path corresponding to the switch is disconnected and data transmission is stopped.

[0056] The FPGA lookup table circuit provided in this embodiment controls the selection control logic of the first selector through the first decoding data, thereby improving the flexibility of the selection control, effectively improving the working performance of the selector, and reducing the overall power consumption and area of ​​the FPGA.

[0057] In some optional embodiments, the second selector 104 is specifically used to select the output multi-bit data corresponding to the input port based on the low-level data when one bit of data in the second decoded data is low-level data and the remaining bit data are all high-level data, so as to obtain single-bit output data of the lookup table; wherein the single-bit data in the output multi-bit data corresponds one-to-one to the input port of the second selector 104.

[0058] Specifically, the second selector 104 includes input and output ports and a selection control circuit composed of logic gate circuits. The input port and selection control circuit are the same as those of the first selector 103. The second selector 104 includes an output port.

[0059] Furthermore, the output multi-bit data (ie, control bits) generated by the second decoder 102 reaches the second selector 104 , and only one bit is at a low level, so that the second selector 104 has only one selected bit.

[0060] This embodiment provides an FPGA lookup table circuit, which controls the selection control logic of the second selector through the second decoding data, and further controls the second selector to output single-bit output data, thereby realizing the addressing function of the lookup table and accelerating the comprehensive transmission rate of the addressing signal in the lookup table.

[0061] In some optional implementations, both the first decoder 101 and the second decoder 102 are 3-8 decoders.

[0062] Specifically, in the actual use scenarios of FPGAs, the path delays of all fast and slow ports need to be considered. Therefore, comprehensively improving the signal transmission rate from the address input to the LUT output and reducing the propagation delay are the keys to improving LUT performance and thus increasing the chip's operating speed. Taking the six-input lookup table (LUT6) as an example, using dual 3-8 decoders as the addressing configuration, the total number of logic levels of the six input-output paths is relatively small, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output path.

[0063] Furthermore, the 3-8 decoder is a digital logic circuit with 3 input terminals and 8 output terminals. The input terminal receives a 3-bit binary code. The data conversion process of the 3-8 decoder is realized through an internal logic gate circuit. When the input 3-bit binary number changes, the high-level signal at the output terminal will also switch accordingly between the 8 output lines to ensure that each input combination has a unique output corresponding.

[0064] Furthermore, the first decoder 101 and the second decoder 102 may also adopt decoders of types such as 2-4 decoder and 4-7 decoder, and different types of decoders may be selected according to the number of bits of the input signal.

[0065] This embodiment provides an FPGA lookup table circuit, in which both the first decoder and the second decoder adopt 3-8 decoders, and use dual 3-8 decoders as the addressing configuration. The total number of logic levels of the six input-output paths is small, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output path.

[0066] In some optional implementations, the first selector 103 and the second selector 104 both use one-hot code multiplexers.

[0067] Specifically, the one-hot code multiplexer is a unique multiplexer that uses a one-hot code as a selection signal to control the data transmission path. As a binary encoding method, the one-hot code is characterized by only one bit in the code being 1, while the rest are all 0. In the one-hot code multiplexer, each bit of the one-hot code corresponds to an input channel. When a bit in the one-hot code is set to 1, the input channel corresponding to that bit is selected, and the data it carries will be transmitted to the output end through the input channel, allowing the one-hot code multiplexer to efficiently and accurately realize data transmission path selection.

[0068] This embodiment provides an FPGA lookup table circuit, which uses a one-hot code multiplexer as the first selector and the second selector. The first selector and the second selector are controlled by multi-bit input terminals, thereby increasing flexibility of use, effectively improving working performance, and reducing the overall power consumption and area of ​​the lookup table.

[0069] In some optional embodiments, the method further includes:

[0070] The first buffer 105 is connected to the input end of the first selector 103 , and is used to obtain the RAM multi-bit data and input the RAM multi-bit data into the first selector 103 .

[0071] Specifically, a buffer is a logic gate circuit used to amplify and transmit signals. It is usually used to connect different logic circuits to achieve signal transmission and level adaptation between modules. The buffer can enhance the driving capability of the signal, so that the signal can stably drive more logic gates or transmit longer distances.

[0072] The FPGA lookup table circuit provided in this embodiment uses a first buffer to obtain RAM multi-bit data and inputs the RAM multi-bit data into a first selector, thereby achieving caching of the RAM multi-bit data, ensuring that the FPGA lookup table circuit does not lose important data due to external interruptions, and also ensuring the integrity of the lookup table task.

[0073] In some optional embodiments, the method further includes:

[0074] The second buffer 106 is connected to the output end of the second selector 104 and is used to obtain the single-bit output data of the lookup table and transmit the single-bit output data of the lookup table to the output of the lookup table.

[0075] The FPGA lookup table circuit provided in an embodiment of the present invention uses a second buffer to obtain single-bit output data of the lookup table, and transmits the single-bit output data of the lookup table to the lookup table outlet, so that the single-bit output data of the lookup table arrives at the receiving device synchronously, thereby ensuring the accuracy and consistency of data reception.

[0076] The working process of the FPGA lookup table circuit is described below through an embodiment.

[0077] Example 1:

[0078] like Figure 2 As shown, the first decoder and the second decoder use decoder3_8 (3-8 decoder), and the first selector and the second selector both use mux8 (a multiplexer). Then the working process of doubledecoder3_8LUT6 (using LUT6 of double 3-8 decoder) includes:

[0079] Divide the address in LUT6 to obtain the address input signals inb_0, inb_1 and inb_2 of the first decoder and the address input signals inb_3, inb_4 and inb_5 of the second decoder;

[0080] The first decoder decoder3_8 decodes inb_0, inb_1 and inb_2 to obtain decoded data ctrl1_38[7:0], and inputs the decoded data into the first selector mux8;

[0081] Input the RAM multi-bit data tb[0:56] in LUT6 into the first selector mux8;

[0082] The first selector uses the decoded data ctrl1_38[7:0] to perform selection logic control on tb[0:56], and outputs multi-bit data to the second selector mux8;

[0083] The second decoder decoder3_8 decodes inb_3, inb_4 and inb_5 to obtain decoded data ctrl2_38[7:0], and inputs the decoded data into the second selector mux8;

[0084] The second selector uses the decoded data ctrl2_38[7:0] to perform selection logic control on the output multi-bit data to obtain single-bit output data f.

[0085] The beneficial effects of the above embodiment 1 are:

[0086] 1) To address the problems faced by LUTs, dual decoder control is used to implement the addressing function of the lookup table; the first and second decoders are used as the control units of the two-stage selector, and one-hot code selectors are used as the first and second selectors. Each stage of the selector is controlled by a multi-bit input terminal, which increases the flexibility of use, effectively improves working performance, and reduces overall power consumption and area.

[0087] 2) In actual FPGA usage scenarios, the path delay of all fast and slow ports needs to be considered. Therefore, comprehensively improving the signal transmission rate from the address input to the LUT output and reducing the propagation delay are key to improving LUT performance and thus increasing chip operating speed. Taking LUT6 as an example, using dual 3-8 decoders as the addressing configuration, the total number of logic levels of the six input-output paths is relatively small, thereby shortening the signal propagation path length and reducing the comprehensive propagation delay of the input-output path.

[0088] 3) Each LUT has multiple address inputs. Due to the limitations of device structure combinations, the propagation delay of the signal from each address input to the LUT output varies. The dual-decoder LUT addressing structure can shorten the difference between the fastest and slowest signal delays to the delay of a single selector, curbing the delay performance degradation of each port. This has the effect of enhancing versatility and is flexible and friendly to chip hardware routing and software interaction.

[0089] 4) The logic resources occupied by each LUT in the FPGA are determined by the number of components and the regularity of their arrangement. Compared with LUTs with multi-stage selector structures, the dual-decoder LUT addressing structure consumes fewer components, saving area resources and overall power consumption. At the same time, the dual-decoder LUT addressing structure has excellent physical symmetry and can be arranged in an orderly and regular manner, which is conducive to optimizing on-chip layout space.

[0090] In this embodiment, a FPGA is also provided, including: Figure 1 An FPGA lookup table circuit in the illustrated embodiment.

[0091] In this embodiment, a method for implementing an FPGA lookup table circuit is also provided, which is applied to the FPGA lookup table circuit. Figure 3 Shown, including:

[0092] In step S301 , a first decoder obtains a first address input signal from a lookup table, decodes the first address input signal to obtain first decoded data, and transmits the first decoded data to a first selector.

[0093] In step S302 , the first selector obtains RAM multi-bit data, selects and processes the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmits the output multi-bit data to the second selector.

[0094] In step S303 , the second decoder obtains the second address input signal from the lookup table, decodes the second address input signal to obtain second decoded data, and transmits the second decoded data to the second selector.

[0095] In step S304 , the second selector selects the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

[0096] This embodiment of the present invention is a method for implementing an FPGA lookup table circuit. Figure 1 The embodiment shown is an FPGA lookup table circuit, so the specific implementation of steps S301 to S304 can refer to the above Figure 1 The corresponding description of the illustrated embodiment will not be repeated here.

[0097] It is understood that the effects and beneficial effects of the method of this embodiment are similar to those of Figure 1 The functions and beneficial effects of an FPGA lookup table circuit in the illustrated embodiment correspond to each other and will not be described in detail here.

[0098] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0099] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0100] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0101] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0102] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0103] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0104] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An FPGA lookup table circuit, characterized in that: The lookup table circuit includes a first decoder, a second decoder, a first selector, and a second selector; wherein the output end of the first decoder is connected to the input end of the first selector, the output end of the second decoder is connected to the input end of the second selector, and the output end of the first selector is connected to the input end of the second selector; The first decoder is configured to obtain a first address input signal from a lookup table, decode the first address input signal to obtain first decoded data, and transmit the first decoded data to the first selector; The first selector is configured to obtain RAM multi-bit data, select and process the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmit the output multi-bit data to the second selector; The second decoder is configured to obtain a second address input signal from the lookup table, decode the second address input signal to obtain second decoded data, and transmit the second decoded data to the second selector; The second selector is configured to select and process the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

2. The FPGA lookup table circuit according to claim 1, wherein: The first decoder is specifically configured to perform an inversion operation on the first address input signal to obtain an inversion signal, and to arrange and combine the first address input signal and the inversion signal to obtain the first decoded data.

3. The FPGA lookup table circuit according to claim 1, wherein: The first selector is specifically configured to select the RAM multi-bit data corresponding to the input port based on the first decoded data, obtain the output multi-bit data, and transmit the output multi-bit data to the second selector.

4. The FPGA lookup table circuit according to claim 1, wherein: The second selector is specifically used to select the output multi-bit data corresponding to the input port based on the low-level data when one bit of the second decoded data is low-level data and the remaining bit data are all high-level data, so as to obtain the single-bit output data of the lookup table; wherein the single-bit data in the output multi-bit data corresponds one-to-one to the input port of the second selector.

5. The FPGA lookup table circuit according to claim 1, wherein: The first decoder and the second decoder both adopt 3-8 decoders.

6. The FPGA lookup table circuit according to claim 1, wherein: The first selector and the second selector both adopt one-hot code multiplexers.

7. The FPGA lookup table circuit according to claim 1, wherein: Also includes: The first buffer is connected to the input end of the first selector and is used to obtain the RAM multi-bit data and input the RAM multi-bit data into the first selector.

8. The FPGA lookup table circuit according to claim 1, wherein: Also includes: The second buffer is connected to the output end of the second selector, and is used to obtain the single-bit output data of the lookup table and transmit the single-bit output data of the lookup table to the lookup table output.

9. An FPGA, characterized in that: include: The FPGA lookup table circuit according to any one of claims 1 to 8.

10. A method for implementing an FPGA lookup table circuit, characterized in that: Applied to the FPGA lookup table circuit according to any one of claims 1 to 8, the method comprising: The first decoder obtains a first address input signal from the lookup table, decodes the first address input signal to obtain first decoded data, and transmits the first decoded data to the first selector; The first selector obtains RAM multi-bit data, selects and processes the RAM multi-bit data using the first decoded data to obtain output multi-bit data, and transmits the output multi-bit data to the second selector; The second decoder obtains a second address input signal from the lookup table, decodes the second address input signal to obtain second decoded data, and transmits the second decoded data to the second selector; The second selector selects and processes the output multi-bit data using the second decoded data to obtain single-bit output data of the lookup table.

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