Coding method, decoding method, device, system and chip

Abstract

The invention discloses a coding method, a decoding method, a device, a system and a chip, and relates to the technical field of communication. The coding method comprises the steps that a first chip combines to-be-transmitted first signals of n periods to obtain second signals, the first signals of the n periods comprise data information and / or control information, and n is an integer greater than 1; the first chip encodes the second signal to obtain at least one code block; the first chip sends at least one code block through a serial channel, and the serial channel is used for connecting the MAC layer and the PHY. The second signal comprises n first signals, and the number of the first signals included in the second signal is large, so that the method can convert the signal with the low data bit width into the signal with the high data bit width. After the second signal is coded to obtain at least one code block, the at least one code block comprises more first signals. Therefore, compared with a mode of transmitting a code block comprising a plurality of repeated signals, the method has the advantage that the signal transmission efficiency is higher.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to an encoding method, a decoding method, a device, a system, and a chip. Background Art

[0002] In the field of communication technologies, a signal sending end can encode a signal to obtain an encoding result and transmit the encoding result to a signal receiving end. The signal receiving end decodes the received encoding result to recover the signal. Summary of the Invention

[0003] This application provides an encoding method, a decoding method, a device, a system, and a chip for improving signal transmission efficiency.

[0004] In a first aspect, an encoding method is provided. The method includes: a first chip merges n cycles of a first signal to be transmitted to obtain a second signal, where the n cycles of the first signal include at least one of data information or control information, and n is a positive integer greater than 1; the first chip encodes the second signal to obtain at least one code block; and the first chip sends the at least one code block through a serial channel, where the serial channel is used to connect a media access control (MAC) layer and a physical layer (PHY).

[0005] In this method, by merging n cycles of the first signal to obtain the second signal, the second signal includes a larger number of the first signals, that is, this method can convert the first signal with a lower data bit width into the second signal with a higher data bit width. And when encoding the second signal to obtain at least one code block, the at least one code block includes a larger number of the first signals, and the efficiency of this method for transmitting signals is higher. When the second signal includes multiple types of information, the multiple types of information can be serially transmitted through the serial channel, and the number of channels required for transmitting the multiple types of information is less, and the cost is lower.

[0006] In a possible implementation, the first chip encodes a second signal to obtain at least one code block, including: the first chip encodes the second signal and a third signal to be transmitted, and obtains a plurality of code blocks, where the third signal includes management information; the first chip sends at least one code block through a serial channel, including: the first chip sends a plurality of code blocks through a serial channel. When the method also encodes the third signal, the plurality of code blocks obtained by encoding can include various types of information. Among them, a serial channel for transmitting a plurality of code blocks can be implemented through one pin or a group of pins, so that the number of pins included in the first chip for implementing this serial channel can be relatively small. When at least one of data information or control information is transmitted through a serial channel, and management information is also transmitted through this serial channel, since the data information, control information, and management information can be transmitted through the same serial channel, the cost of transmitting the data information, control information, and management information by this method is relatively low.

[0007] In a possible implementation, at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication for indicating the signal type included in the second signal. That is to say, the type indication for indicating the signal type can be included in the second code block other than the first code block. A chip that subsequently receives the first code block and the second code block can directly obtain the type indication from the second code block, and obtain the signal type of the second signal according to the type indication, and the efficiency of obtaining the signal type of the second signal is relatively high.

[0008] In a possible implementation, a plurality of code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal. In this implementation, there is no need for an additional type indication to indicate the signal type included in the second signal, and the overhead for indicating the signal type is relatively small.

[0009] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame. Thus, the second code block can be transmitted during an interpacket gap (IPG) of the Ethernet frame or when there is no Ethernet frame. By transmitting the second code block instead of an idle code block in at least one of the cases of an Ethernet frame interpacket gap or no Ethernet frame, the interface rate for transmitting code blocks can be kept unchanged when transmitting the second code block, thereby keeping the power consumption of transmitting code blocks unchanged. Moreover, since this method transmits the second code block instead of an idle code block during an Ethernet frame interpacket gap or when there is no Ethernet frame, and the second code block includes a type indication or includes a type indication and management information, the information transmission efficiency of this method is relatively high.

[0010] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. At least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission. Since this method transmits the second code block to replace the first code block associated with the preamble, this implementation can keep the interface rate for transmitting code blocks unchanged when transmitting the second code block, thereby keeping the power consumption of transmitting code blocks unchanged. Moreover, in the case of deleting the code blocks transmitted during the Ethernet frame interpacket gap to compensate for the clock difference of the adjusted interface, since the second code block is used to replace the first code block associated with the preamble for transmission in this implementation rather than being transmitted during the Ethernet frame interpacket gap, the second code block will not be deleted due to the compensation adjustment of the clock difference, and the transmission reliability of the second code block is relatively high.

[0011] In a possible implementation, a first chip sends at least one code block through a serial channel, including: the first chip negotiates with a chip located at the other end of the serial channel for a clock used to transmit at least one code block; the first chip sends at least one code block through the serial channel according to the negotiated clock. By negotiating with the peer chip for the clock used to transmit code blocks, the frequency of the clock used in this method for transmitting code blocks can be adapted to the situations of the chips at both ends of the serial channel. Thus, when sending code blocks according to the negotiated clock, the chip located at the other end of the serial channel can receive the code blocks according to the negotiated clock, ensuring the reliability of code block transmission.

[0012] In a possible implementation, at least one code block includes a plurality of first code blocks and a plurality of second code blocks. The frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method. In this case, the frequency point of the clock for negotiation can be adapted to the situation of the code blocks to be transmitted, thereby ensuring the reliability of transmitting the code blocks according to the negotiated clock.

[0013] In a possible implementation, the first chip is a PHY chip, and the third signal further includes physical layer channel status indication information. Therefore, the types of information included in the third signal are relatively rich. Moreover, in the case of directly transmitting the physical layer channel status indication information, the chip receiving the plurality of coded code blocks does not need to perform logical operations on other information except the physical layer channel status indication information to infer the physical layer channel status indication information. This method can be applied to point-to-multipoint scenarios.

[0014] In a possible implementation, the serial channel is a channel between improved serial gigabit media independent interfaces (SGMII). For example, both the first chip and the second chip receiving at least one code block include interfaces improved based on SGMII, and the serial channel can be a channel between SGMII.

[0015] In a second aspect, a decoding method is provided. The method includes: the second chip receives at least one code block through a serial channel, the at least one code block is obtained by encoding a second signal, the second signal is obtained by combining the first signals of n periods to be transmitted, the first signals of n periods include at least one of data information or control information, the serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1; the second chip decodes the at least one code block to obtain the second signal; the second chip splits the second signal to obtain n signals.

[0016] In this method, the second signal is obtained by combining the first signals of n periods. The second signal includes a relatively large number of first signals, that is, this method can convert the second signal with a relatively high data bit width into the first signal with a relatively low data bit width. And when receiving at least one code block obtained by encoding the second signal, the at least one code block includes a relatively large number of first signals, and the signal receiving efficiency of this method is relatively high. In the case where the second signal includes multiple types of information, the multiple types of information can be serially received through the serial channel, and the number of channels required to receive the multiple types of information is relatively small, and the cost is relatively low.

[0017] In a possible implementation, the second chip receives at least one code block through a serial channel, including: the second chip receives a plurality of code blocks through the serial channel, the plurality of code blocks are obtained by encoding a second signal and a third signal to be transmitted, and the third signal includes management information; the second chip decodes at least one code block to obtain the second signal, including: the second chip decodes the plurality of code blocks to obtain the second signal and the third signal. When the method also receives code blocks obtained by encoding the third signal, the method can receive multiple types of information. Among them, a serial channel for receiving a plurality of code blocks can be implemented by one pin or a group of pins, so that the number of pins included in the second chip for implementing the serial channel can be relatively small. When receiving at least one of data information or control information through a serial channel and also receiving management information through this serial channel, since the data information, control information, and management information can be received through the same serial channel, the cost of the method for receiving the data information, control information, and management information is relatively low.

[0018] In a possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indication for indicating the signal type included in the second signal; the second chip decodes at least one code block to obtain the second signal, including: the second chip obtains the second signal from the first code block; the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal based on the type indication included in the second code block; the second chip splits the second signal according to the signal type included in the second signal to obtain n signals. In this implementation, the type indication for indicating the signal type is included in the second code block other than the first code block, and the second chip can directly obtain the type indication from the second code block, obtain the signal type of the second signal according to the type indication, and the efficiency of obtaining the signal type of the second signal is relatively high.

[0019] In a possible implementation, a plurality of code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal; the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal according to the type of the first code block; the second chip splits the second signal according to the signal type included in the second signal to obtain n signals. In this implementation, there is no need for an additional type indication to indicate the signal type included in the second signal, and the overhead for indicating the signal type is relatively small.

[0020] In a possible implementation, a plurality of code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame. Thus, the second code block can be transmitted during an Ethernet frame gap or when there is no Ethernet frame. By transmitting the second code block instead of an idle code block in at least one of the cases of an Ethernet frame gap or no Ethernet frame, the interface rate for transmitting code blocks can be kept unchanged when transmitting the second code block, thereby keeping the power consumption of transmitting code blocks unchanged. Moreover, since this method receives the second code block instead of an idle code block during an Ethernet frame gap or when there is no Ethernet frame, and the second code block includes a type indication or includes a type indication and management information, the efficiency of receiving information by this method is relatively high.

[0021] In a possible implementation, a plurality of code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks. At least one first code block includes a first code block associated with a preamble of the Ethernet frame. The second code block is used to replace the first code block associated with the preamble for transmission. Since the second code block is used to replace the first code block associated with the preamble for transmission in this way, this implementation can keep the interface rate for transmitting code blocks unchanged when transmitting the second code block, thereby keeping the power consumption of transmitting code blocks unchanged. Moreover, in the case of deleting the code blocks transmitted during an Ethernet frame gap to compensate for the clock difference of the adjusted interface, since the second code block is used to replace the first code block associated with the preamble for transmission instead of being transmitted during an Ethernet frame gap in this implementation, the second code block will not be deleted due to the compensation adjustment of the clock difference, and the transmission reliability of the second code block is relatively high.

[0022] In a possible implementation, a second chip receives at least one code block through a serial channel, including: the second chip negotiates a clock for transmitting at least one code block with a chip located at the other end of the serial channel; the second chip receives at least one code block through the serial channel according to the negotiated clock. By negotiating the clock for transmitting code blocks with the peer chip, the frequency of the clock used when transmitting code blocks by this method can be adapted to the situation of the chips at both ends of the serial channel. Thus, when transmitting code blocks according to the negotiated clock, the chip located at the other end of the serial channel can receive the code blocks according to the negotiated clock, ensuring the reliability of code block transmission.

[0023] In a possible implementation, at least one code block includes a plurality of first code blocks and a plurality of second code blocks. The frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method. In this case, the frequency point of the clock for negotiation can be adapted to the situation of the code blocks to be transmitted, thereby ensuring the reliability of transmitting the code blocks according to the negotiated clock.

[0024] In a possible implementation, the second chip is a MAC chip, and the third signal further includes a physical layer channel status indication signal. Therefore, the types of information included in the third signal are relatively rich. Moreover, in the case of directly transmitting the physical layer channel status indication information, the second chip does not need to perform logical operations on other information except the physical layer channel status indication information to infer the physical layer channel status indication information, and this method can be applied to the point-to-multipoint scenario.

[0025] In a possible implementation, the serial channel is the channel between improved SGMIIs. That is to say, both the first chip and the second chip include interfaces improved based on SGMII, and the serial channel can be the channel between SGMIIs.

[0026] In a third aspect, there is provided an encoding device, which is applied to the first chip. The device includes: a merging module, configured to merge the first signals of n periods to be transmitted to obtain a second signal, where the first signals of n periods include at least one of data information or control information, and n is a positive integer greater than 1; an encoding module, configured to encode the second signal to obtain at least one code block; a sending module, configured to send at least one code block through a serial channel, and the serial channel is used to connect the MAC layer and the PHY.

[0027] In a possible implementation, the encoding module is configured to encode the second signal and the third signal to be transmitted to obtain a plurality of code blocks, and the third signal includes management information; the sending module is configured to send the plurality of code blocks through one serial channel.

[0028] In a possible implementation, at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication, where the type indication is used to indicate the signal type included in the second signal.

[0029] In a possible implementation, the plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal.

[0030] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0031] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. At least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0032] In a possible implementation, a sending module is configured to negotiate a clock for transmitting at least one code block with a chip located at the other end of the serial channel; and send at least one code block through the serial channel according to the negotiated clock.

[0033] In a possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0034] In a possible implementation, the first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

[0035] In a possible implementation, the serial channel is a channel between improved SGMIIs.

[0036] In a fourth aspect, a decoding device is provided. The device is applied to a second chip and includes: a receiving module, configured to receive at least one code block through a serial channel. The at least one code block is obtained by encoding a second signal, and the second signal is obtained by combining the first signals of n periods to be transmitted. The first signals of n periods include at least one of data information or control information. The serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1; a decoding module, configured to decode the at least one code block to obtain the second signal; and a splitting module, configured to split the second signal to obtain n signals.

[0037] In a possible implementation, the receiving module is configured for the second chip to receive multiple code blocks through the serial channel. The multiple code blocks are obtained by encoding the second signal and the third signal to be transmitted. The third signal includes management information; and the decoding module is configured to decode the multiple code blocks to obtain the second signal and the third signal.

[0038] In a possible implementation, at least one code block includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a type indication for indicating the signal type included in the second signal. A decoding module is configured to obtain the second signal from the first code block. A splitting module is configured to obtain the signal type included in the second signal based on the type indication included in the second code block, and split the second signal according to the signal type included in the second signal to obtain n signals.

[0039] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The type of the first code block is used to indicate the signal type included in the second signal. A splitting module is configured to obtain the signal type included in the second signal according to the type of the first code block, and split the second signal according to the type included in the second signal to obtain n signals.

[0040] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. One Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0041] In a possible implementation, multiple code blocks include a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. One Ethernet frame is associated with at least one first code block among the multiple code blocks. At least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0042] In a possible implementation, a receiving module is configured to negotiate a clock for transmitting at least one code block with a chip located at the other end of the serial channel, and receive at least one code block through the serial channel according to the negotiated clock.

[0043] In a possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks. The frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0044] In a possible implementation, the second chip is a MAC chip, and the third signal further includes a physical layer channel status indication signal.

[0045] In a possible implementation, the serial channel is a channel between improved SGMIIs.

[0046] In a fifth aspect, a communication system is provided. The communication system includes a first chip and a second chip. The first chip is configured to execute any of the encoding methods in the first aspect, and the second chip is configured to execute any of the decoding methods in the second aspect.

[0047] In a sixth aspect, a chip is provided. The chip includes: a MAC layer circuit configured to execute any of the encoding methods in the first aspect, or any of the decoding methods in the second aspect.

[0048] In a seventh aspect, another chip is provided. The chip includes: a PHY circuit configured to execute any of the encoding methods in the first aspect, or any of the decoding methods in the second aspect.

[0049] It should be understood that for the beneficial effects achieved by the technical solutions and corresponding possible implementation manners in the third to seventh aspects of this application, reference can be made to the technical effects of the technical solutions and their corresponding possible implementation manners in the first to second aspects described above, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a schematic diagram of the transmission rate of SGMII compatible with 100 Mbps in a related art;

[0051] Figure 2 is a schematic diagram of the signal transmitted by MII in a related art;

[0052] Figure 3 is a schematic diagram of an implementation environment taking the scenario of MII as an example provided by an embodiment of this application;

[0053] Figure 4 is a flowchart of an encoding method provided by an embodiment of this application;

[0054] Figure 5 is a schematic diagram of transmitting management information in a related art;

[0055] Figure 6 is a schematic diagram of a sequence to be encoded provided by an embodiment of this application;

[0056] Figure 7 is a schematic diagram of the process of encoding a second signal and a third signal to obtain multiple code blocks provided by an embodiment of this application;

[0057] Figure 8 is a schematic diagram of a sequence to be encoded provided by an embodiment of this application;

[0058] Figure 9 is a schematic diagram of a code block sequence obtained by encoding provided by an embodiment of this application;

[0059] Figure 10 It is a schematic diagram of the position of a second code block provided by an embodiment of the present application;

[0060] Figure 11 It is another schematic diagram of the position of a second code block provided by an embodiment of the present application;

[0061] Figure 12 It is yet another schematic diagram of the position of a second code block provided by an embodiment of the present application;

[0062] Figure 13 It is a schematic diagram of a second code block including management information provided by an embodiment of the present application;

[0063] Figure 14 It is a flowchart of a decoding method provided by an embodiment of the present application;

[0064] Figure 15 It is a schematic diagram of an improved SGMII architecture provided by an embodiment of the present application;

[0065] Figure 16 It is a schematic diagram of the structure of an encoding device provided by an embodiment of the present application;

[0066] Figure 17 It is a schematic diagram of the structure of a decoding device provided by an embodiment of the present application;

[0067] Figure 18 It is a schematic diagram of the structure of a computer system provided by an embodiment of the present application;

[0068] Figure 19 It is another schematic diagram of the structure of a computer system provided by an embodiment of the present application. Detailed implementation manners

[0069] The terms used in the implementation part of the present application are only for explaining the embodiments of the present application and are not intended to limit the present application. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0070] In the field of communication technology, signals can be transmitted between a MAC chip and a PHY chip through a media independent interface (MII) to achieve network communication. Among them, MII is applicable to transmission scenarios with a rate of 10 megabits per second (Mbps) or 100 Mbps. For example, MII is applicable to the industrial Internet of Things scenario. The MII defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard is a parallel interface. MII includes 18 pins, and these 18 pins are used to transmit data information, control information, and management information. The specific way of pin transmission information of MII can refer to the relevant content in the IEEE 802.3 standard, which will not be elaborated here. However, in order to reduce the packaging cost and allocate pins for supporting functions other than network communication, the number of pins included in the chip for supporting network communication is usually limited. Therefore, it is necessary to reduce the number of pins of MII for implementing network communication.

[0071] In a related technology, SGMII is used to implement signal transmission between a MAC chip and a PHY chip. Among them, the number of pins of SGMII is less than that of MII. For 1000 baseband (BASE)-twisted pair (T) Ethernet, SGMII supports signal transmission between the MAC chip and the PHY chip in 1000BASE-T Ethernet through a serializer / deserializer (serdes) serial interface. SGMII can also be compatible with the rates of 10 / 100BASE-T Ethernet. That is to say, in the case of being compatible with the rate of 10BASE-T Ethernet, SGMII can be compatible with a rate of 10 Mbps, and in the case of being compatible with the rate of 100BASE-T Ethernet, SGMII can be compatible with a rate of 100 Mbps.

[0072] However, SGMII actually is compatible with the rates of 10 Mbps or 100 Mbps at the rate of gigabit Ethernet (GE). For example, the native GE rate supported by SGMII is 1000 Mbps, and SGMII supports the rates of 10 Mbps and 100 Mbps by replicating bytes 100 times and 10 times respectively. Figure 1 is a schematic diagram of the transmission rate of 100 Mbps compatible with SGMII in a related technology, as Figure 1As shown, the data to be transmitted at a transmission rate of 100 Mbps includes d0, d1, and d2. For each piece of data to be transmitted at a transmission rate of 100 Mbps, each piece of data is copied 10 times, and then the copied data is transmitted through SGMII to achieve SGMII compatibility with a rate of 100 Mbps. However, when using SGMII to be compatible with a lower rate, the copied data will result in higher transmission costs and power consumption. Also, since the copied data is duplicate data, the solutions of related technologies will lead to the transmission of more duplicate data, and the efficiency of transmitting data is low.

[0073] Furthermore, since the data bit width of SGMII is different from that of MII, if SGMII is directly used to replace MII, the difference in data bit width will result in a data bit width mismatch. Figure 2 is a schematic diagram of the signal transmitted by MII in a related technology, as Figure 2 shown, the receive data valid (RX_DV) signal indicates that 4-bit 0101, D1, D2, / F / , and D4 to D7 are valid data, and the receive error (RX_ER) signal indicates that / F / is error data, and D1, D2, D4 to D7 are all error-free data. Among them, D1, D2, / F / , and D4 to D7 are all 4 bits. For the error data / F / transmitted by MII, if SGMII is used to replace MII, since the data bit width of SGMII is 8 bits, the data transmitted by SGMII to replace the error data / F / will meet the requirement of a data bit width of 8 bits by squeezing D2 or D4. That is, the 8-bit data bit width of SGMII cannot match the 4-bit data bit width of MII.

[0074] The embodiments of the present application provide an encoding method and a decoding method for improving the transmission efficiency of signals. The encoding method and the decoding method provided by the embodiments of the present application can be applied to the scenario of transmitting signals via MII. In the case of being applied to this scenario, the above signals are the signals transmitted by MII. In addition, the above encoding method and decoding method can also be applied to other scenarios other than MII. For example, the implementation environment to which the encoding method and the decoding method are applied includes Chip 1 and Chip 2. Chip 1 and Chip 2 are connected through a serial channel. The serial channel is used to connect the MAC layer and the PHY. The serial channel is a channel between other interfaces other than MII. The encoding method and the decoding method can both be applied to Chip 1 or Chip 2.

[0075] Figure 3 is a schematic diagram of an implementation environment taking the scenario of MII as an example provided by the embodiments of the present application. The encoding method and the decoding method can be applied to the Figure 3 shown implementation environment. Refer to Figure 3, the implementation environment includes a first device 301 and a second device 302. Among them, the first device 301 includes a MAC chip 3011 and at least one PHY chip 3012( Figure 3 taking the example that the first device 301 includes multiple PHY chips 3012), signals are transmitted between the MAC chip 3011 and each PHY chip 3012 through MII. The second device 302 includes a MAC chip 30211 and a PHY chip 3022, and signals are transmitted between the MAC chip 30211 and the PHY chip 3022 through MII. Signals can be transmitted between the PHY chip 3012 and the PHY chip 3022. In some embodiments, the second device 302 includes an MCU 3021 and a PHY chip 3022, and the MCU 3021 includes a MAC chip 30211. In some embodiments, one or more of the MAC chip 3011, the PHY chip 3012, the MAC chip 30211, and the PHY chip 3022 can be located in a separate chip, or in a separate die, or in one or more cores of a multi-core chip.

[0076] The encoding method and decoding method provided by the embodiments of the present application can be applied to signal transmission between the MAC chip 3011 and the PHY chip 3012, and can also be applied to signal transmission between the MAC chip 30211 and the PHY chip 3022. Figure 3 The numbers of the first device 301, the MAC chip 3011, the PHY chip 3012, the second device 302, the MCU 3021, the MAC chip 30211, and the PHY chip 3022 shown are only examples, and the embodiments of the present application do not limit this. The above first device 301 can be a switch or a device applied to an IoT terminal, and the second device 302 can be an IoT terminal or a device applied to an IoT terminal. For example, the IoT terminal includes any one of a pressure gauge or a flow meter in an industrial Internet of Things. Exemplarily, the above first device 301 and second device 302 can be single pair ethernet (SPE) devices or advanced physical layer (APL) devices.

[0077] The encoding method provided by the embodiments of the present application can be as Figure 4 shown. Next, in combination with Figure 3 the implementation environment shown, this method will be described. This method can be applied to a first chip, and the first chip can be Figure 3 the MAC chip or the PHY chip shown. As Figure 4 shown, this method includes but is not limited to S401 to S403.

[0078] S401, the first chip combines the first signals of n cycles to be transmitted to obtain a second signal. The first signals of n cycles include at least one of data information or control information, and n is a positive integer greater than 1.

[0079] Exemplarily, the first signal is a signal to be transmitted through MII. In this case, the data bit width of the first signal is 4 bits. For example, the first signal includes a transmit error (TX_ER) signal, a transmit enable (TX_EN) signal, and a transmit data (TXD) signal to be transmitted through MII. Among them, the data bit width of the TXD signal is 4 bits, and the TXD signal is represented as TXD<3:0>. The TX_ER signal and the TX_EN signal can identify whether TXD<3:0> is a data signal or a control signal, that is, the TX_ER signal and the TX_EN signal can identify whether the information included in TXD<3:0> is data information or control information.

[0080] In a possible implementation manner, combining the first signals of n cycles to obtain a second signal includes: combining the first signals of n cycles in a reference order to obtain a second signal. The reference order can be determined based on experience or actual requirements. For example, the reference order is the acquisition order of the first signals of n cycles, or other order other than the acquisition order of the first signals of n cycles. Thus, the combination order of the first signals of n cycles is relatively flexible. When the reference order is the acquisition order of the first signals of n cycles, after the second signal is subsequently sent to the receiving end, the receiving end can directly obtain the acquisition order of the first signals of n cycles according to the arrangement order of the first signals of n cycles in the second signal, and then obtain at least one of the data information or control information included in the first signals of n cycles according to the acquisition order of the first signals of n cycles. In this case, there is no need to adjust the order of the first signals of n cycles in the second signal to obtain the acquisition order of the first signals of n cycles, and the efficiency of obtaining the acquisition order of the first signals of n cycles is relatively high.

[0081] Exemplarily, regardless of which case the reference order is, the data bit width of the second signal is n times the data bit width of the first signal. For example, when the first signal is a signal to be transmitted through MII and n is equal to 2, the first signals of two cycles are combined to obtain a second signal, and the data bit width of the second signal is 8 bits. Since the data bit width of SGMII is 8 bits, the second signal can be transmitted through SGMII, so that this method can be compatible with SGMII defined by the IEEE 802.3 standard.

[0082] S402, the first chip encodes the second signal to obtain at least one code block.

[0083] Regarding the specific manner of encoding the second signal, the embodiments of the present application do not limit this. For example, according to the 8-bit (bit, B) / 10B method, the second signal is encoded to obtain at least one code block. Thus, the at least one code block is a code block encoded in the 8B / 10B manner. In the case where the at least one code block is encoded in 8B / 10B, the at least one code block can be directly transmitted through the serial channel between SGMIIs. In the embodiments of the present application, the at least one code block can also be obtained by any one of the 8B / 9B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. Thus, the manner of encoding the second signal and the third signal is relatively flexible.

[0084] Exemplarily, the type of the first code block is used to indicate the signal type included in the second signal. Thus, based on the type of the first code block, the signal type included in the second signal can be determined without an additional type indication to indicate the signal type included in the second signal, and the overhead of indicating the signal type included in the second signal is relatively low. In a possible implementation manner, the first signal in n periods includes multiple types of information. For example, the first signal in n periods includes data information and control information, or the first signal in n periods includes multiple types of control information. In this case, the second signal is encoded according to the information type included in the first signal in n periods to obtain at least one code block. That is to say, in the case where the first signal in n periods includes multiple types of information, the type of the first code block obtained by encoding the second signal can be determined according to the correspondence between the preset information type and the code block type.

[0085] Taking n equal to 2 and using the 8B / 10B encoding method as an example, the correspondence between the information type and the code block type is shown in Table 1. In Table 1, the data bit width of the first signal is 4 bits. Therefore, the two first signals included in the second signal are respectively referred to as the first half-byte and the second half-byte.

[0086] Table 1

[0087]

[0088] As can be seen from the content of Table 1, when both half - bytes are data information, the two half - bytes are encoded into an 8B / 10B - encoded data code block. When the first half - byte is data information and the second half - byte is control information, the two half - bytes are encoded into an 8B / 10B - encoded control code block, and the type of the control code block is the same as the type of the control information. When the first half - byte is control information and the second half - byte is data information, the two half - bytes are encoded into an 8B / 10B - encoded control code block, and the type of the control code block is the same as the type of the control information.

[0089] When the two half - bytes are respectively control information, if the types of the two control information are the same, the two half - bytes are encoded into an 8B / 10B - encoded control code block, and the type of the control code block is the same as the type of the control information. If the types of the two control information are different, the two half - bytes can be encoded into an 8B / 10B - encoded control code block, or encoded into two 8B / 10B - encoded control code blocks. The types of control information have priorities. When the two half - bytes are encoded into an 8B / 10B - encoded control code block, the type of the encoded control code block can be the same as the type with higher priority. When the two half - bytes are encoded into two 8B / 10B - encoded control code blocks, the types of the two control code blocks are respectively the same as the types of the two control information. Since encoding the two half - bytes into two 8B / 10B - encoded code blocks will result in an increase in the number of bits, the increased bits caused by encoding occupy the encoding bit - width backward. That is, the signals that need to be encoded subsequently are postponed to avoid missing the signals that need to be encoded.

[0090] Exemplarily, the second encoded signal is a byte - aligned second signal, so that the second signal can meet the application conditions of 8B / 10B encoding, and thus the second signal can be 8B / 10B encoded.

[0091] In a possible implementation, at least one code block includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a type indication for indicating the signal type included in the second signal. In this implementation, the signal type included in the second signal is indicated by a separate code block, thereby ensuring the indication of various types of signals in the second signal. In this implementation, since the signal type included in the second signal is indicated by the type indication, the type of the first code block may not be used to indicate the signal type included in the second signal. Exemplarily, one first code block includes one second signal, one second signal includes n periods of a first signal, the type indication includes at least one indication bit, and the at least one indication bit is used to indicate the type of the n*m first signals included in m first code blocks, where m is a positive integer. Thus, when m is greater than or equal to 2, the type indication included in one second code block can indicate the types of the first signals included in multiple first code blocks, and the number of first signals indicated by the type indication is relatively flexible and diverse.

[0092] In the embodiments of the present application, the manner in which at least one indication bit indicates the type of n*m first signals includes, but is not limited to, the following manner one and manner two.

[0093] Manner one: The at least one indication bit indicates the type of n*m first signals in the form of a bitmap.

[0094] For example, the number of indication bits is n*m, and the n*m indication bits are used to indicate the type of the n*m first signals included in m first code blocks in the form of a bitmap. One indication bit corresponds to one first signal, and the value of the indication bit is used to indicate the type of the first signal corresponding to the indication bit. For example, when the value of the indication bit is a first value, the indication bit is used to indicate that the first signal corresponding to the indication bit is a data signal; when the value of the indication bit is a second value, the indication bit is used to indicate that the second signal corresponding to the indication bit is a control signal. The first value and the second value can be determined according to experience or actual requirements. For example, the first value is 0, the second value is 1, or the first value is 1, the second value is 0.

[0095] Manner two: The at least one indication bit indicates the type of n*m first signals through an overall value.

[0096] For example, a case of the overall value of at least one indication bit corresponds to a case of the types of n*m first signals. Thus, according to the overall value of at least one indication bit, the types of n*m first signals can be determined. For example, a chip that subsequently receives multiple code blocks can obtain the correspondence between values and types. After the chip receives multiple code blocks, based on the overall value of at least one indication bit, it queries the correspondence between values and types to obtain the types of n*m first signals corresponding to this overall value. The embodiments of the present application do not limit the manner in which the chip obtains the correspondence between values and types. For example, the chip stores the correspondence between values and types, so as to directly obtain the stored correspondence between values and types. For another example, the chip sends a request instruction to a device that stores the correspondence between values and types. The request instruction is used to request to obtain the correspondence between values and types, and the chip receives the correspondence between values and types sent by the device based on the request instruction. Among them, the device storing this correspondence can be a chip or a device.

[0097] Combining the above method 1 and method 2, it can be seen that in the embodiments of the present application, the manner in which at least one indication bit indicates the types of n*m first signals is relatively flexible and diverse.

[0098] Exemplarily, when at least one code block obtained by encoding a second signal includes a first code block and a second code block, and the second code block includes type indication, the encoding method of the first code block corresponds to the types of the n first signals included in the first code block. For example, when the n first signals include at least one data information, the first code block is encoded according to the data type. When the n first signals all include control information and the control types are the same, the first code block is encoded according to the control type. When the n first signals all include control information and the control types are different, the first code block is encoded according to the data type.

[0099] In some embodiments, a first chip encodes a second signal to obtain at least one code block, including: the first chip encodes the second signal and a third signal to be transmitted, and the third signal includes management information. By encoding the second signal and the third signal, the obtained multiple code blocks can include at least one of data information or control information, and the multiple code blocks can also include management information, so that the types of information included in the multiple code blocks are relatively rich. Exemplarily, the management signal includes management data input output (MDIO) information.

[0100] In the related art, whether it is MII or SGMII, management information is transmitted through an independent channel. Figure 5 It is a schematic diagram of transmitting management information in the related art, whereFigure 5 The switching chip of the shown switch includes a MAC chip, and the MAC chip is not shown in Figure 5 . As Figure 5 shown, the switching chip is connected to multiple PHY chips, and the switching chip is also connected to a complex programmable logic device (CPLD) or a microcontroller unit (MCU). The switching chip respectively establishes channels for transmitting management information with X PHY chips through the CPLD or the MCU, where X is a positive integer. That is to say, the switching chip realizes establishing channels for transmitting management information with X PHY chips through the CPLD or the MCU. Among them, the management information includes MDIO information. Since the management information is transmitted through independent channels, the device cost of transmitting management information in the related art is relatively high.

[0101] In the method provided in the embodiment of the present application, when at least one of data information or control information is transmitted through a serial channel, the management information can also be transmitted through this serial channel. Since the data information, control information, and management information can be transmitted through the same serial channel, there is no need to transmit the data information, control information, and management information through multiple channels respectively, and the cost of transmitting the data information, control information, and management information by this method is relatively low.

[0102] In a possible implementation manner, when the first chip is a PHY chip, the third signal further includes physical layer channel status indication information. When the third signal includes physical layer channel status indication information, the chip that subsequently receives the code block encoded with the second signal and the third signal can determine the status of the physical layer channel based on the physical layer channel status indication information. Exemplarily, the physical layer channel status indication information includes information included in at least one of a carrier sense (CRS) signal or a collision detected (COL) signal.

[0103] In the related art, when directly using SGMII to implement signal transmission between a MAC chip and a PHY chip, the SGMII at the sending end does not transmit COL signals and CRS signals, and the SGMII at the receiving end obtains COL signals and CRS signals through logical operations on TX_EN signals and RX_DV signals. However, in a point-to-multipoint scenario, since real COL signals and CRS signals, or virtual COL signals and CRS signals are required to indicate the status of the physical link, channels for transmitting COL signals and CRS signals need to be added in the SGMII, resulting in a relatively high device cost of the SGMII.

[0104] Since the method provided by the embodiments of the present application can directly transmit the physical layer channel state indication information without performing logical operations on other information except the physical layer channel state indication information to infer the physical layer channel state indication information, this method can be applied to the point-to-multipoint scenario. For the relevant content of MDIO information, the information included in the CRS signal, and the information included in the COL signal, reference can be made to the IEEE 802.3 standard, and the embodiments of the present application will not elaborate on this.

[0105] Regarding the manner of encoding the second signal and the third signal to be transmitted, the embodiments of the present application do not limit this. For example, in the 8B / 10B manner, the second signal and the third signal to be transmitted are encoded to obtain a plurality of code blocks. When the plurality of code blocks are all encoded in 8B / 10B, the plurality of encoded code blocks can be directly transmitted through the serial channel between SGMIIs. In the embodiments of the present application, the plurality of code blocks can also be obtained in any one of the 8B / 9B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. Thus, the manner of encoding the second signal and the third signal is relatively flexible.

[0106] In a possible implementation manner, the plurality of code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. In this implementation manner, the second signal and the third signal are separately encoded in two code blocks. In this case, the type of the first code block can be used to indicate the signal type included in the second signal. The principle of the manner in which the type of the first code block indicates the signal type included in the second signal is the same as that in the foregoing, and will not be elaborated here.

[0107] Exemplarily, when the type of the first code block is used to indicate the signal type included in the second signal, the second code block can only include the third signal, so that the number of bits used for the second code block to include the third signal can be relatively large. When the second code block is transmitted, the transmission efficiency of the third signal is relatively high. In some embodiments, when the number of the first code blocks is multiple, the second code block can be located between the multiple first code blocks, or before the multiple first code blocks, or after the multiple first code blocks. Thus, the position of the second code block is relatively flexible. When the number of the first code blocks and the number of the second code blocks are both multiple, the multiple first code blocks and the multiple second code blocks can be arranged periodically. For example, one period includes a first number of first code blocks and a second number of second code blocks. The first number and the second number can be set based on experience or actual requirements, and the embodiments of the present application do not limit this.

[0108] In some embodiments, when the number of bits included in the second code block is equal to or greater than the number of bits of the management information, one second code block can include all the bits of the management information. Thus, all the bits included in the management information can be obtained based on one second code block. When the number of bits included in the second code block is less than the number of bits of the management information, multiple second code blocks include the bits of the management information. In this case, all the bits of the management information can be obtained based on the multiple second code blocks. In the embodiments of the present application, the relationship between the number of bits included in the second code block and the number of bits of the management information is relatively flexible.

[0109] Exemplarily, when the multiple first code blocks and the multiple second code blocks are arranged periodically, the second signal and the third signal appear periodically in the coding sequence for encoding. Figure 6 is a schematic diagram of a sequence to be encoded provided by an embodiment of the present application. As Figure 6 shown, the sequence to be encoded is a coding sequence for 8B / 10B encoding. In the coding sequence, the second signal and the third signal appear periodically. The second signal includes n periods of the first signal, and the third signal includes 8 bits of the management information. Thus, among the multiple code blocks obtained based on the Figure 6 shown sequence to be encoded, the first code block and the second code block appear alternately.

[0110] In a possible implementation manner, when encoding the second signal and the third signal to obtain multiple code blocks and the multiple code blocks include the first code block and the second code block, the second code block further includes a type indication, and the type indication is used to indicate the signal type included in the second signal. That is, the second code block includes the type indication and the third signal. In this implementation manner, since the signal type included in the second signal is indicated by the type indication, the type of the second signal does not need to be indicated by the type of the first code block. The manner in which the type indication is used to indicate the signal type included in the second signal is the same as the principle of the manner in which the type indication is used to indicate the signal type included in the second signal in the foregoing text, and will not be elaborated here.

[0111] Figure 7 is a schematic diagram of a process of encoding the second signal and the third signal to obtain multiple code blocks provided by an embodiment of the present application. Among them, Figure 7 taking the encoding method as 8B / 10B encoding as an example. Refer to Figure 7 . The first signal includes the TX_ER signal, the TX_EN signal, and TXD<3:0>. The TX_ER signal and the TX_EN signal can identify whether TXD<3:0> is a data signal or a control signal. That is, the TX_ER signal and the TX_EN signal can identify whether the information included in TXD<3:0> is data information or control information. The third signal includes MDIO information. In Figure 7Among them, taking n equal to 2 as an example, the first signals of 2 periods include the first signal of the a-th period and the first signal of the (a + 1)-th period, where a is a positive integer. The first signals of 2 periods are combined to obtain a second signal. The second signal includes 8 bits, that is, the second signal includes one byte, and this byte includes the 7th bit to the 0th bit.

[0112] The second signal and the third signal to be encoded are as Figure 7 shown in the sequence to be encoded in. The sequence to be encoded includes a second signal, a type indication for indicating the signal type included in the second signal, and a third signal. Exemplarily, when the second signal includes 8 bits, the sum of the number of bits of the type indication and the third signal for encoding into one second code block is less than or equal to 8 bits. As Figure 7 shown, the type indication for encoding into one second code block includes 2 bits. Among them, the first 1 bit of the 2 bits is used to indicate the information type of the first 4 bits in the second signal, and the last 1 bit of the 2 bits is used to indicate the information type of the last 4 bits in the second signal. The number of bits of the third signal for encoding into one second code block is 2 bits.

[0113] When the sum of the number of bits of the type indication and the third signal for encoding into one second code block is less than 8 bits, the second code block further includes other bits in addition to the bits of the type indication and the third signal. The other bits can be the bits of the information that needs to be included in the second code block for transmission. The embodiments of the present application do not limit this. For example, referring to Figure 7 In, the 8 bits for encoding into one second code block include 2 bits of type indication, 2 bits of management information, and other 4 bits. Among them, the positions of the 2 bits of type indication, the 2 bits of management information, and the other 4 bits can be as Figure 7 shown. After obtaining the second signal and the third signal, the second signal and the third signal are encoded. Referring to Figure 7 In, the second signal and the third signal are encoded to obtain a first code block and a second code block. The first code block includes the second signal, and the second code block includes the type indication and the third signal.

[0114] In some embodiments, when the second signal includes 8 bits, the sum of the number of bits of the type indication and the third signal for encoding into one second code block is equal to 8 bits. Figure 8 is a schematic diagram of a sequence to be encoded provided by an embodiment of the present application. Among them, the third signal includes MDIO information, the information included in the CRS signal, and the information included in the COL signal. For the convenience of description, Figure 8The 8 bits to be encoded into a second code block are denoted as / indicated / . The 7th bit of the / indicated / is used to indicate the information type of the first half-byte of the first byte, the 6th bit of the / indicated / is used to indicate the information type of the second half-byte of the first byte, the 5th bit of the / indicated / is used to indicate the information type of the first half-byte of the second byte, and the 4th bit of the / indicated / is used to indicate the information type of the second half-byte of the second byte. Here, the first byte and the second byte are respectively used to be encoded into a first code block, and both the first byte and the second byte are obtained by combining two cycles of the first signal.

[0115] Please continue to refer to Figure 8 , the 3rd bit of the / indicated / is the information included in the CRS signal, the 2nd bit of the / indicated / is the information included in the COL signal, and the 1st bit and the 0th bit of the / indicated / are both MDIO signals. Exemplarily, when the second code block includes a type indication, the second code block is adjacent to the first code block whose type indication indicates the signal type included in the second signal. For example, the type indication included in the second code block is used to indicate the signal type included in the second signal in at least one first code block, the second code block is adjacent to the at least one first code block, and the second code block may be located after the at least one first code block. When the second code block is adjacent to the at least one first code block, the bits used to encode the second code block are adjacent to the bits used to encode the at least one first code block. For example, as Figure 8 shown, the bits used to encode two first code blocks include a first byte and a second byte, and the / indicated / used to encode the second code block is adjacent to and after the second byte.

[0116] In Figure 8 the shown sequence to be encoded, the 8 bits to be encoded into a first code block may include multiple information types. For example, refer to Figure 8, when both of the two half - bytes included in the 8 - bit to be encoded as the first code block are data information, the information type included in the 8 - bit is represented as / dd / . When the 8 - bit to be encoded as the first code block includes data information and control information, with the first 4 bits being data information and the last 4 bits being control information, the information type included in the 8 - bit is represented as / d k / . When the 8 - bit to be encoded as the first code block includes data information and control information, with the first 4 bits being control information and the last 4 bits being data information, the information type included in the 8 - bit is represented as / k d / . When the 8 - bit to be encoded as the first code block includes control information and the control information types of the first 4 bits and the last 4 bits are the same, the information type included in the 8 - bit is represented as / k k / . When the 8 - bit to be encoded as the first code block includes control information and the control information types of the first 4 bits and the last 4 bits are different, the information type included in the 8 - bit is represented as / k1 k2 / . The cases of / k d / , / kk / , and / k1 k2 / are not shown in Figure 8 shown.

[0117] Exemplarily, the control code block obtained by encoding the second signal can be used for at least one of the operations of delimiting or identifying a serial sequence, where the control code block refers to the code block obtained by encoding the second signal including control information, and the serial sequence includes multiple code blocks obtained by encoding the second signal. For example, the serial sequence includes multiple code blocks obtained only by encoding the second signal, or includes multiple code blocks obtained by encoding the second signal and the third signal. Taking 8B / 10B encoding of the second signal as an example, the control code block obtained by encoding the second signal includes one or more 8B / 10 - encoded control code blocks, where one or more 8B / 10B - encoded control code blocks are used for at least one of delimiting or identifying the serial sequence. For example, one or more 8B / 10B - encoded control code blocks include at least one of / I / code, / S / code, / T / code, or / LI / code. Among them, the / I / code is used to indicate the Ethernet frame is idle, the / S / code is used to indicate the start of the Ethernet frame, the / T / code is used to indicate the end of the Ethernet frame, and the / LI / code is used to indicate low power consumption. Figure 8 The / I / and / S / shown are the / I / code and the / S / code respectively.

[0118] One or more 8B / 10Bb encoded control code blocks are obtained through encoding. The code blocks encoded by the method of the embodiments of the present application can retain the "comma" field in the 8B / 10B encoding defined by the IEEE 802.3 standard. Thus, after the encoded code blocks are sent to the device at the receiving end, the device at the receiving end can more easily identify the boundaries of the 8B / 10B encoding. For example, the K28.5 encoding in the / I / code contains the "comma" field, which is a unique identifier in the 8B / 10B encoding. For another example, the / S / code and the / T / code directly indicate the start and end of an Ethernet frame respectively, reducing the complexity of determining the start and end of an Ethernet frame.

[0119] Figure 9 FIG. is a schematic diagram of a sequence of code blocks obtained by encoding provided by the embodiments of the present application, where the sequence of code blocks includes multiple code blocks. As Figure 9 shown, the sequence of code blocks includes code blocks identifying Ethernet frame idle, Ethernet frame start, Ethernet frame data, Ethernet frame end, and Ethernet frame interval. Figure 9 The sequence of code blocks shown can be a sequence of code blocks associated with an Ethernet frame. Figure 9 The number of code blocks included in the sequence of code blocks shown is only for illustrative purposes and is not used to limit the number of code blocks included in the sequence of code blocks. Exemplarily, the code block identifying Ethernet frame idle, the code block identifying Ethernet frame start, and the code block identifying Ethernet frame end are the same as the code blocks identifying Ethernet frame idle, the code block identifying Ethernet frame start, and the code block identifying Ethernet frame end obtained by 8B / 10B encoding defined by IEEE 802.3 respectively.

[0120] In Figure 9 FIG., a square box represents an 8B / 10B encoded code block. For any part of the first half or the second half of the code block, if the part is obtained based on data information, the part can be identified by / d / ; if the part is obtained based on control information, the part can be identified by / k / . Refer to Figure 9 FIG., when both parts of the code block are obtained based on data information, the code block can be identified by / d d / ; when the front and back parts of the code block are obtained based on data information and control information respectively, the code block can be identified by / d k / .

[0121] In a possible implementation, when multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame. Since the second code block includes a third signal and the third signal includes management information, by transmitting the second code block before or after the first code block associated with the same Ethernet frame, the management information can be transmitted during the Ethernet frame interval or when there is no Ethernet frame transmission.

[0122] Since the Ethernet frame interval defined by the IEEE 802.3 standard and the idle code blocks transmitted when there is no Ethernet frame are such that, by transmitting the second code block instead of the idle code block in at least one of the cases of the Ethernet frame interval or when there is no Ethernet frame, the interface rate for transmitting code blocks can be kept unchanged when transmitting the second code block, thereby keeping the power consumption for transmitting code blocks unchanged. Moreover, since this method transmits the second code block instead of the idle code block during the Ethernet frame interval or when there is no Ethernet frame transmission, and the second code block includes a type indication or includes a type indication and management information, the efficiency of information transmission of this method is relatively high. The situation of the first code block associated with the Ethernet frame can refer to the content of the code block including the second signal in the foregoing text, which will not be elaborated here.

[0123] Figure 10 It is a schematic diagram of the position of a second code block provided by an embodiment of the present application. As Figure 10 shown, different from transmitting idle code blocks during the Ethernet frame interval, the code block transmitted during the Ethernet frame interval is a second code block including management information, Figure 10 and other code blocks except the second code block in it are all code blocks associated with the Ethernet frame. Figure 11 It is another schematic diagram of the position of a second code block provided by an embodiment of the present application. As Figure 11 shown, different from transmitting idle code blocks when there is no Ethernet frame, a second code block including management information is transmitted when there is no Ethernet frame, Figure 11 and other code blocks except the second code block in it are all idle code blocks.

[0124] In another possible implementation, multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, at least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission. Compared with the previous implementation, the second code block including management information is transmitted at the position of the preamble of the Ethernet frame, rather than during the Ethernet frame interval or when there is no Ethernet frame.

[0125] Since this method transmits by replacing the first code block associated with the preamble with the second code block, this implementation can also keep the interface rate for transmitting code blocks unchanged when transmitting the second code block, thereby keeping the power consumption for transmitting code blocks unchanged. Moreover, since the Ethernet frame interval may be used to compensate for the clock difference between interfaces, the code blocks transmitted during the Ethernet frame interval may be deleted when the Ethernet frame interval is used to compensate for the clock difference. By replacing the first code block associated with the preamble with the second code block, it is possible to avoid deleting the second code block including management information when deleting the code blocks transmitted during the Ethernet frame interval, and the transmission reliability of the second code block is relatively high.

[0126] Exemplarily, the management information included in the second code block is the management information of the first Ethernet frame, the first code block associated with the preamble replaced by the second code block is the first code block associated with the preamble of the second Ethernet frame, and the transmission order of the first code block associated with the first Ethernet frame is before the transmission order of the first code block associated with the second Ethernet frame. The situation of the first code block of the code block associated with the Ethernet frame can refer to the content of the code block including the second signal in the previous text, which will not be elaborated here.

[0127] Figure 12 It is another schematic diagram of the position of the second code block provided by the embodiment of the present application. As Figure 12 shown, the IEEE802.3 standard stipulates that the format of the Ethernet frame includes a preamble, a start frame delimiter (SFD), data, and a frame check sequence (FCS). Among them, the preamble includes 7 bytes, and the SFD includes 1 byte. In the embodiment of the present application, the 7-byte preamble and the 1-byte SFD are collectively referred to as the preamble. The Ethernet frame uses a start of packet delimiter (SPD) as the start boundary of the Ethernet frame. The SPD is encoded as the / S / code through 8B / 10B encoding. The / S / code is used to replace the code block obtained by encoding the first byte of the preamble of the Ethernet frame, and the second code block is used to replace the code block obtained by encoding the other bytes of the preamble except the first byte. As Figure 12 shown, the data and FCS of the Ethernet frame can be encoded into the first code block. Exemplarily, the code block transmitted before the Ethernet frame can be an idle code block.

[0128] Exemplarily, when the second code block is transmitted before or after the first code block associated with the same Ethernet frame, or when the second code block is used to replace the first code block associated with the preamble of the Ethernet frame for transmission, the second code block is a control code block or a control code block group whose control type is not explicitly defined in the coding method. Thus, based on this control code block or control code block group, it can be determined that this code block is the second code block, that is, this second code block is used as the starting identifier of multiple second code blocks. Exemplarily, the second code block is the / K / code or the / K / D / code block group whose control type is not explicitly defined in the 8B / 10B coding. Thus, based on the / K / code or the / K / D / code block group, it can be determined that this code block is the second code block including management information.

[0129] In a possible implementation, when the number of second code blocks is multiple, the multiple second code blocks further include data code blocks, and the data code blocks include management information. For example, the number of data code blocks including management information is 4. Thus, when the second code block is identified by the / K / code, the number of second code blocks including management information is 5; when the second code block is identified by the / K / D / code block group, the number of second code blocks including management information is 6. When the multiple second code blocks further include data code blocks, the second code block used as the starting identifier is located before the data code blocks included in the multiple second code blocks.

[0130] Figure 13 It is a schematic diagram of a second code block including management information provided by an embodiment of the present application. As Figure 13 shown, when the number of second code blocks is 5, the 5 second code blocks include the / K / code and 4 data code blocks; when the number of second code blocks is 6, the 6 second code blocks include the / K / D / code block group and 4 data code blocks. Figures 10 to 12 The cases of the 5 second code blocks or 6 second code blocks shown are Figure 13 the same as the principle of the second code block shown and will not be elaborated.

[0131] Exemplarily, in the case of no Ethernet frame transmission, after sending an idle code block and a second code block to the device on the receiving side, the device can achieve code block alignment based on the coding sequence of the idle code block, and then obtain the second code block including management information based on the second code block used as the starting identifier. In the case of Ethernet frame transmission, after sending a first code block and a second code block to the device on the receiving side, the device can achieve code block alignment based on the coding sequence of the first code block, and then obtain the second code block including management information based on the second code block used as the starting identifier.

[0132] S403, the first chip sends at least one code block through a serial channel, and the serial channel is used to connect the MAC layer and the PHY.

[0133] Exemplarily, the serial channel is used to connect the reconciliation sublayer (RS) and the physical coding sublayer (PCS), or the serial channel is used to connect RS and the physical layer signaling (PLS). In some embodiments, the serial channel is used to implement data transmission between the MAC sublayer and the PHY, or implement data transmission between the STA and the PHY. Exemplarily, the serial channel is a channel between improved SGMIIs. For example, the chips on both sides of the serial channel each include an improved SGMII, and the two improved SGMIIs are connected through the serial channel. Among them, the improved SGMII refers to an MII implemented based on SGMII and capable of applying the encoding method and decoding method provided by the embodiments of the present application. For the structure of the improved SGMII, reference can be made to the relevant content in Figure 15 described later, which will not be elaborated here for the time being.

[0134] In a possible implementation manner, when multiple code blocks are encoded, the first chip sends at least one code block through the serial channel, including: the first chip sends multiple code blocks through one serial channel. When the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, and the second code block includes a third signal, by using one serial channel to transmit multiple code blocks, it is possible to implement the transmission of at least one of data information or control information and management information on the same channel.

[0135] When multiple code blocks are transmitted through one serial channel, the first chip and the subsequent second chip that receives multiple code blocks only need to set fewer pins to implement the serial channel, thereby implementing the transmission of at least one of data information or control information and management information. For example, the serial channel is implemented by one pin or a group of pins. Thus, if the serial channel is implemented by one pin, the pin is used to send multiple code blocks. If the serial channel is implemented by multiple pins, the differential signals transmitted through the multiple pins can be obtained based on the multiple code blocks first, and then the differential signals are transmitted through the multiple pins to implement the transmission of multiple code blocks through one serial channel.

[0136] Compared with the method of separately establishing a channel for transmitting management information and channels for transmitting data information and control information, the method provided by the embodiments of the present application can implement the transmission of data information, control information, and management information by establishing one channel, and the equipment cost required for establishing the channel is relatively low. Moreover, since there is no need to transmit data information, control information, and management information through multiple channels separately, the cost of transmitting data information, control information, and management information by this method is relatively low.

[0137] In a possible implementation, the first chip sends at least one code block through a serial channel, including: the first chip negotiates with the chip located at the other end of the serial channel for the clock used to transmit at least one code block; the first chip sends at least one code block through the serial channel according to the negotiated clock. By negotiating the clock for transmitting the code block, this method can adjust the frequency of the clock used for transmission. Since SGMII has a fixed frequency for the clock used for code block transmission because it replicates data for byte alignment, the frequency of the clock used in the method provided in the embodiments of the present application is more flexible than the frequency of the clock used by SGMII. Moreover, by negotiating with the peer chip for the clock used to transmit the code block, the frequency of the clock used when this method transmits the code block can be adapted to the conditions of the chips at both ends of the serial channel. Thus, when sending the code block according to the negotiated clock, the information located at the other end of the serial channel can receive the code block according to the negotiated clock, ensuring the reliability of code block transmission.

[0138] Exemplarily, the process of negotiating the clock provided in the embodiments of the present application is compatible with the auto-negotiation function of SGMII defined by the IEEE 802.3 standard. For example, the first chip negotiates with the chip located at the other end of the serial channel for the clock used to transmit at least one code block, including: the first chip determines the frequency point of the clock for negotiation, and negotiates with the chip located at the other end of the serial channel based on the determined frequency point; in the case of successful negotiation, determine this frequency point as the frequency point of the clock used to transmit the code block; in the case of unsuccessful negotiation, the first chip adjusts the frequency point of the clock for negotiation, and negotiates with the chip located at the other end of the serial channel based on the adjusted frequency point until the negotiation is successful.

[0139] In a possible implementation, the first chip negotiates with the chip located at the other end of the serial channel according to the auto-negotiation format of SGMII defined by the IEEE 802.3 standard. The first frequency point of the clock for negotiation determined by the first chip can be the highest-frequency main frequency point among the multiple main frequency points supported by the first chip, so that when the negotiation is successful, the rate of transmitting the code block is relatively high. Of course, the first frequency point of the clock for negotiation can also be other main frequency points except the highest-frequency main frequency point among the multiple main frequency points. Exemplarily, the multiple main frequency points include at least two of the main frequency points with a rate of 10 Mbps, the main frequency points with a rate of 100 Mbps, or the main frequency points with a rate of 1000 Mbps.

[0140] In some embodiments, after the negotiation is passed, the first chip further determines the interface type of the chip located at the other end of the serial channel, and transmits the code blocks in the manner of transmitting code blocks according to the determined interface type. For example, when the negotiation based on the main frequency point with a rate of 1000 Mbps is passed, if the first chip determines that the interface of the chip located at the other end of the serial channel is SGMII, it transmits the code blocks in the manner of transmitting code blocks according to SGMII.

[0141] Exemplarily, the first chip periodically negotiates with the chip located at the other end of the channel for the clock used to transmit the code blocks, so as to avoid the negotiation failure caused by the inconsistent power-on times of the chips at both ends of the serial channel. For example, when a certain chip among the chips at both ends is not powered on, the negotiations based on multiple main frequency points all fail, while when the chips at both ends are powered on, the negotiations based on one or more of the multiple main frequency points can pass. Therefore, by periodically negotiating the clock, this method can avoid the negotiation failure caused by the inconsistent power-on times and ensure the negotiation effect.

[0142] Exemplarily, when at least one code block includes multiple first code blocks and multiple second code blocks, the frequency point of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method. In this case, the frequency point of the clock used for negotiation can be adapted to the situation of the code blocks to be transmitted, thus ensuring the reliability of transmitting the code blocks according to the negotiated clock. Exemplarily, the frequency point R of the clock used for negotiation is obtained according to the following formula 1.

[0143] R = F * E * (C + D) / C (Formula 1)

[0144] Wherein, F represents the transmission rate corresponding to the data information in the first signal, E represents the coding efficiency of the coding method, C represents the number of first code blocks, and D represents the number of second code blocks. When the coding method is 8B / 10B coding, E is equal to 1.25. When the multiple first code blocks and multiple second code blocks are arranged periodically, the above (C + D) / C can be obtained based on the code block situation in one period. For example, by dividing the number of code blocks in one period by the number of first code blocks in this period, the (C + D) / C can be obtained.

[0145] In the method provided by the embodiments of the present application, the second signal is obtained by combining the first signals of n cycles. The second signal includes a relatively large number of first signals. That is to say, this method can convert the first signal with a lower data bit width into the second signal with a higher data bit width. Therefore, when encoding the second signal to obtain at least one code block and transmitting at least one code block, the at least one code block includes a relatively large number of first signals. Compared with the method of transmitting code blocks including multiple repeated signals, the efficiency of signal transmission of this method is higher. When the second signal includes multiple types of information, the multiple types of information can be serially transmitted through the same serial channel, and the number of channels required to transmit the multiple types of information is less, and the cost is lower.

[0146] When this method also encodes the third signal, the multiple code blocks obtained by encoding can include multiple types of information. When a serial channel for transmitting multiple code blocks is implemented by one pin or a group of pins, the number of pins included in the first chip for implementing this serial channel can be less. When transmitting at least one of data information or control information through a serial channel, and also transmitting management information through this serial channel, since the data information, control information, and management information can be transmitted through the same serial channel without transmitting the data information, control information, and management information through multiple channels respectively, the cost of transmitting the data information, control information, and management information of this method is lower.

[0147] Furthermore, this method can negotiate the clock for transmitting the code block, so that the frequency points of the clock for transmitting the code block are more diverse, and the frequency of the clock used when transmitting the code block can be adapted to the situation of the chips at both ends of the serial channel. Thus, when sending the code block according to the negotiated clock, the information at the other end of the serial channel can receive the code block according to the negotiated clock, ensuring the reliability of code block transmission. When the rate of the frequency point of the negotiated clock is relatively low, the power consumption of transmitting the code block by this method is lower.

[0148] The encoding method provided by the embodiments of the present application has been described above. The embodiments of the present application also provide a decoding method, and this method can be as Figure 14 shown. This method can be applied to the second chip, and the second chip can be the Figure 3 shown MAC chip or PHY chip. As Figure 14 shown, this method includes but is not limited to S1401 to S1403.

[0149] S1401. The second chip receives at least one code block through a serial channel. The at least one code block is obtained by encoding a second signal. The second signal is obtained by combining the first signals of n periods to be transmitted. The first signals of n periods include at least one of data information or control information. The serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1.

[0150] Exemplarily, the serial channel is a channel between improved SGMIIs. In a possible implementation, the second chip receives at least one code block through the serial channel, including: the second chip negotiates a clock for transmitting the at least one code block with the chip at the other end of the serial channel; the second chip receives the at least one code block through the serial channel according to the negotiated clock. The way the second chip negotiates the clock is the same as the principle of the way the first chip negotiates the clock in the previous encoding method, which will not be elaborated here. Exemplarily, the at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method. For example, the frequency point of the clock for negotiation is determined according to Formula 1 above.

[0151] In a possible implementation, the second chip receives at least one code block through the serial channel, including: the second chip receives multiple code blocks through the serial channel. The multiple code blocks are obtained by encoding the second signal and the third signal to be transmitted. The third signal includes management information. Exemplarily, when the second chip is a MAC chip, the third signal further includes a physical layer channel status indication signal. For the code blocks obtained by encoding the second signal and the code blocks obtained by encoding the second signal and the third signal, refer to the relevant descriptions in the previous encoding method, which will not be elaborated here.

[0152] S1402. The second chip decodes the at least one code block to obtain the second signal.

[0153] Exemplarily, when the at least one code block includes a first code block and a second code block, and the first code block includes the second signal, and the second code block includes a type indication for indicating the signal type included in the second signal, the second chip decodes the at least one code block to obtain the second signal, including: the second chip obtains the second signal from the first code block.

[0154] Exemplarily, when the second chip receives multiple code blocks obtained by encoding the second signal and the third signal, the second chip decodes the at least one code block to obtain the second signal, including: the second chip decodes the multiple code blocks to obtain the second signal and the third signal.

[0155] S1403. The second chip splits the second signal to obtain n signals.

[0156] In a possible implementation, when at least one code block includes a second code block and the second code block includes a type indication, the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal based on the type indication included in the second code block; the second chip splits the second signal according to the signal type included in the second signal to obtain n signals.

[0157] Exemplarily, a first code block includes a second signal, a second signal includes n cycles of a first signal, the type indication includes at least one indication bit, and the at least one indication bit is used to indicate the types of the n*m first signals included in m first code blocks, where m is a positive integer. The second chip obtains the signal type included in the second signal based on the type indication included in the second code block, including: the second chip obtains the types of the n*m first signals included in m first code blocks based on the at least one indication bit.

[0158] In some embodiments, the number of indication bits is n*m, and the n*m indication bits are used to indicate the types of the n*m first signals included in m first code blocks in the form of a bitmap; the second chip obtains the types of the n*m first signals included in m first code blocks based on the at least one indication bit, including: the second chip obtains the type of the first signal corresponding to each indication bit based on the value of each indication bit among the n*m indication bits.

[0159] In other embodiments, the overall value of the at least one indication bit is used to indicate the types of the n*m first signals included in m first code blocks; the second chip obtains the types of the n*m first signals included in m first code blocks based on the at least one indication bit, including: the second chip obtains the type of each first signal among the n*m first signals based on the overall value of the at least one indication bit.

[0160] Exemplarily, when the signal type included in the second signal is indicated by the type indication, the n signals obtained are the n first signals used to merge into the second signal.

[0161] In a possible implementation, when multiple code blocks include a first code block and a second code block, and the first code block includes a second signal and the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal, the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal according to the type of the first code block; the second chip splits the second signal according to the signal type of the second signal to obtain n signals.

[0162] Exemplarily, when the first code block is a data code block, the type of the first code block is used to indicate that the signal type included in the second signal is a data signal. In this case, the obtained n signals are n first signals used to merge to obtain the second signal.

[0163] Exemplarily, when the first code block is a control code block, the type of the first code block is used to indicate that the signal type included in the second signal is a control signal, and the type of the control signal is the same as the type of the control code block. In this case, the obtained n signals are n control signals. Among them, the type of the n control signals is the same as the type of the control signals among the n first signals used to merge to obtain the second signal.

[0164] In the method provided in the embodiments of the present application, the second signal is obtained by merging the first signals in n periods. The number of first signals included in the second signal is large, that is, the method can convert the second signal with a higher data bit width into the first signal with a lower data bit width. When receiving at least one code block obtained by encoding the second signal, the number of first signals included in the at least one code block is large. Compared with the method of receiving a code block including multiple repeated signals, the signal receiving efficiency of this method is high. When the second signal includes multiple types of information, the multiple types of information can be serially received through the same serial channel, and the number of channels required to receive the multiple types of information is small, and the cost is low.

[0165] When the method also receives a code block obtained by encoding a third signal, the method can receive multiple types of information. When a serial channel for receiving multiple code blocks is implemented by one pin or a group of pins, the number of pins included in the second chip for implementing the serial channel can be small. When receiving at least one of data information or control information through a serial channel, and also receiving management information through this serial channel, since the data information, control information, and management information can be received through the same serial channel, there is no need to receive the data information, control information, and management information through multiple channels respectively, and the cost of receiving the data information, control information, and management information is low.

[0166] Furthermore, the method can negotiate the clock for receiving the code block, so that the frequency points of the clock for receiving the code block are more diverse, and the frequency of the clock used when receiving the code block can be adapted to the situation of the chips at both ends of the serial channel. The information located at the other end of the serial channel can receive the code block according to the negotiated clock, and the second chip can receive the code block according to the negotiated clock, ensuring the reliability of the code block transmission. When the rate of the negotiated clock frequency point is low, the power consumption of the method for receiving the code block is low.

[0167] Figure 15 It is a schematic diagram of an improved SGMII architecture provided by the embodiments of the present application, asFigure 15 As shown, both the MAC chip and the PHY chip include an improved SGMII. As Figure 15 shown, the improved SGMII includes an SGMII, a double nibble width adjustment module, an indication insertion module, a management module, an indication extraction module, a channel status module, and a clock division module. Among them, the double nibble width adjustment module is respectively connected to the indication insertion module and the indication extraction module, the indication insertion module and the indication extraction module are both connected to the management module, the indication insertion module and the indication extraction module are also both connected to the SGMII, and the SGMII is also connected to the clock division module. In the MAC chip, the channel status module is connected to the indication extraction module. In the PHY chip, the channel status module is connected to the indication insertion module.

[0168] The SGMII includes an encoding module, a decoding module, a serialization module, a deserialization module, and an auto-negotiation module. Among them, the encoding module is respectively connected to the indication insertion module and the serialization module, the decoding module is respectively connected to the indication extraction module and the deserialization module, the auto-negotiation module is respectively connected to the encoding module and the decoding module, and the clock division module is connected to the auto-negotiation module. Exemplarily, the improved SGMII in the MAC chip and the improved SGMII in the PHY chip are connected through a pair of serial channels. As Figure 15 shown, this pair of serial channels includes a serial channel between the serialization module in the MAC chip and the deserialization module in the PHY chip, and also includes a serial channel between the serialization module in the PHY chip and the deserialization module in the MAC chip. Among them, the connection between the serialization module and the deserialization module can be referred to as a serdes connection. By using the serial channel to implement signal transmission between the MAC module and the PHY module, the signals to be transmitted in parallel through the MII defined by the IEEE 802.3 standard can be serially transmitted via the serial channel.

[0169] Please continue to refer to Figure 15, in the MAC chip, the transmitting side of the improved SGMII includes a TX_ER signal, a TX_EN signal, a TXD signal, and a transmit data reference clock (TX_CLK) signal. Among them, the TX_ER signal and the TX_EN signal are used to identify whether the data in the TXD signal is data information or control information. The double nibble-width adjustment module combines the nibble signals in two cycles on the transmitting side into a byte signal and carries an indication signal of the information type included in the corresponding nibble signal. The nibble signal is the first signal in the foregoing method embodiment, and the byte signal is the second signal in the foregoing method embodiment. The indication insertion module receives the byte signal and the indication signal. The indication insertion module also receives a management signal sent by the management module, and the management signal includes management information. For example, the management information includes a management frame defined by the IEEE 802.3 standard. Exemplarily, the management module receives an MDIO signal and a management data clock (MDC) signal, obtains a management frame based on the MDIO signal and the MDC signal, and sends the management signal including the management frame to the indication insertion module at a rate adapted to the indication insertion module. The indication insertion module obtains a sequence to be encoded according to the received byte signal, indication signal, and management signal, and sends the sequence to be encoded to the encoding module. The encoding module encodes the sequence to be encoded to obtain a plurality of code blocks, and sends the plurality of code blocks to the serialization module. The serialization module sends the plurality of code blocks in the form of a serial code block stream.

[0170] In the PHY chip, after the improved SGMII receives the serial code block stream sent by the receiving serial channel, the deserialization module deserializes the serial code block stream to obtain a plurality of code blocks. The decoding module decodes the plurality of code blocks to obtain a sequence to be encoded. The indication extraction module obtains a byte signal, an indication signal, and a management signal from the sequence to be encoded, sends the indication signal and the byte signal to the double nibble-width adjustment module, and sends the management signal to the management module. The double nibble-width adjustment module splits the byte signal into nibble signals in two cycles according to the indication signal, and outputs the nibble signals in two cycles in order. The output nibble signal is the receive data (RXD) signal transmitted by the MII defined by the IEEE 802.3 standard. The management module converts the management signal into an MDIO signal and an MDC signal defined by the IEEE 802.3 standard. Exemplarily, as Figure 15 shown, the PHY chip also receives a receive data reference clock (RX_CLK) signal.

[0171] In the PHY chip, the improved way of sending SGMII signals has the same principle as that in the MAC chip. In the MAC chip, the improved way of receiving SGMII signals has the same principle as that in the PHY chip. Please continue to refer to Figure 15 For the improved SGMII in the PHY chip, the channel status indication module sends CRS signals and COL signals to the indication insertion module at a rate adapted to the indication insertion module. Thus, when the indication insertion module receives the CRS signals and COL signals, a sequence to be encoded is obtained based on the received byte signals, indication signals, management signals, CRS signals, and COL signals. For the improved SGMII in the MAC chip, the indication extraction module obtains CRS signals and COL signals from the sequence to be encoded and sends the CRS signals and COL signals to the channel status module. The channel status module outputs the CRS signals and COL signals.

[0172] Whether it is the improved SGMII in the MAC chip or the improved SGMII in the PHY chip, the clock division module is used to obtain the frequency point of the clock for negotiation and send the frequency point to the auto-negotiation module, and the auto-negotiation module is used to negotiate the clock for transmitting code blocks.

[0173] The embodiment of the present application also provides an encoding device. Figure 16 It is a schematic structural diagram of an encoding device provided by the embodiment of the present application. This device is applied to the first chip and is based on Figure 16 the multiple modules shown, and this device can execute Figure 4 all or part of the operations in the encoding method shown. It should be understood that this device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiment of the present application does not limit this. As Figure 16 shown, this device includes a merging module 1601, an encoding module 1602, and a sending module 1603.

[0174] Among them, the merging module 1601 is used to merge the first signals of n periods to be transmitted to obtain a second signal. The first signals of n periods include at least one of data information or control information, and n is a positive integer greater than 1. The encoding module 1602 is used to encode the second signal to obtain at least one code block. The sending module 1603 is used to send at least one code block through a serial channel, and the serial channel is used to connect the MAC layer and the PHY.

[0175] In a possible implementation manner, the encoding module 1602 is used to encode the second signal and the third signal to be transmitted to obtain multiple code blocks, and the third signal includes management information. The sending module 1603 is used to send multiple code blocks through one serial channel.

[0176] In a possible implementation, at least one code block includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a type indication for indicating the signal type included in the second signal.

[0177] In a possible implementation, a plurality of code blocks includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The type of the first code block is used to indicate the signal type included in the second signal.

[0178] In a possible implementation, a plurality of code blocks includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0179] In a possible implementation, a plurality of code blocks includes a first code block and a second code block. The first code block includes a second signal, and the second code block includes a third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks. At least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0180] In a possible implementation, the sending module 1603 is configured to negotiate a clock for transmitting at least one code block with a chip located at the other end of the serial channel; and send at least one code block through the serial channel according to the negotiated clock.

[0181] In a possible implementation, at least one code block includes a plurality of first code blocks and a plurality of second code blocks. The frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0182] In a possible implementation, the first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

[0183] In a possible implementation, the serial channel is a channel between improved SGMIIs.

[0184] In the device provided in the embodiment of the present application, a second signal is obtained by combining the first signals of n cycles. The second signal includes a relatively large number of first signals, that is, the device can convert the first signal with a lower data bit width into the second signal with a higher data bit width. Thus, when encoding the second signal to obtain at least one code block and transmitting at least one code block, the at least one code block includes a relatively large number of first signals. Compared with the method of transmitting a code block including multiple repeated signals, the device has a higher signal transmission efficiency. When the second signal includes multiple types of information, the multiple types of information can be serially transmitted through the same serial channel, and the number of channels required to transmit the multiple types of information is less, and the cost is lower.

[0185] When the device also encodes a third signal, the multiple code blocks obtained by encoding can include multiple types of information. When a serial channel for transmitting multiple code blocks is implemented through one pin or a group of pins, the number of pins included in the device for implementing the serial channel can be less. When at least one of data information or control information is transmitted through a serial channel, and management information is also transmitted through this serial channel, since the data information, control information, and management information can be transmitted through the same serial channel, there is no need to transmit the data information, control information, and management information through multiple channels respectively, and the cost of transmitting the data information, control information, and management information is lower.

[0186] Furthermore, the device can negotiate the clock for transmitting the code block, so that the frequency points of the clock for transmitting the code block are more diverse, and the frequency of the clock used when transmitting the code block can be adapted to the situation of the chips at both ends of the serial channel. Thus, when sending the code block according to the negotiated clock, the information at the other end of the serial channel can receive the code block according to the negotiated clock, ensuring the reliability of the code block transmission. When the rate of the frequency point of the negotiated clock is relatively low, the power consumption of the device for transmitting the code block is lower.

[0187] The embodiment of the present application also provides a decoding device. Figure 17 It is a schematic structural diagram of a decoding device provided by the embodiment of the present application. This device is applied to a second chip and is based on Figure 17 the multiple modules shown, this device can execute Figure 14 all or part of the operations in the decoding method shown. It should be understood that this device may include more additional modules than the shown modules or omit some of the shown modules, and the embodiment of the present application does not limit this. As Figure 17 shown, this device includes a receiving module 1701, a decoding module 1702, and a splitting module 1703.

[0188] Among them, a receiving module 1701 is configured to receive at least one code block through a serial channel. The at least one code block is obtained by encoding a second signal, and the second signal is obtained by combining the first signals of n periods to be transmitted. The first signals of the n periods include at least one of data information or control information. The serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1. A decoding module 1702 is configured to decode the at least one code block to obtain the second signal. A splitting module 1703 is configured to split the second signal to obtain n signals.

[0189] In a possible implementation manner, the receiving module 1701 is configured to receive, by a second chip, a plurality of code blocks through a serial channel. The plurality of code blocks are obtained by encoding a second signal and a third signal to be transmitted. The third signal includes management information. The decoding module 1702 is configured to decode the plurality of code blocks to obtain the second signal and the third signal.

[0190] In a possible implementation manner, the at least one code block includes a first code block and a second code block. The first code block includes the second signal. The second code block includes a type indication, and the type indication is used to indicate the signal type included in the second signal. The decoding module 1702 is configured to obtain the second signal from the first code block. The splitting module 1703 is configured to obtain the signal type included in the second signal based on the type indication included in the second code block, and split the second signal according to the signal type included in the second signal to obtain n signals.

[0191] In a possible implementation manner, the plurality of code blocks include a first code block and a second code block. The first code block includes the second signal. The second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal. The splitting module 1703 is configured to obtain the signal type included in the second signal according to the type of the first code block, and split the second signal according to the signal type included in the second signal to obtain n signals.

[0192] In a possible implementation manner, the plurality of code blocks include a first code block and a second code block. The first code block includes the second signal. The second code block includes the third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0193] In a possible implementation manner, the plurality of code blocks include a first code block and a second code block. The first code block includes the second signal. The second code block includes the third signal. The first signal is related to an Ethernet frame. An Ethernet frame is associated with at least one first code block among the plurality of code blocks. At least one first code block includes a first code block associated with a preamble of the Ethernet frame. The second code block is used to replace the first code block associated with the preamble for transmission.

[0194] In a possible implementation, the receiving module 1701 is configured to negotiate a clock for transmitting at least one code block with a chip located at the other end of the serial channel; and receive at least one code block through the serial channel according to the negotiated clock.

[0195] In a possible implementation, at least one code block includes a plurality of first code blocks and a plurality of second code blocks, and the frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0196] In a possible implementation, the second chip is a MAC chip, and the third signal further includes a physical layer channel state indication signal.

[0197] In a possible implementation, the serial channel is a channel between improved SGMIIs.

[0198] In the device provided in the embodiment of the present application, the second signal is obtained by combining the first signals of n periods. The second signal includes a relatively large number of first signals, that is, the device can convert the second signal with a relatively high data bit width into the first signal with a relatively low data bit width. When receiving at least one code block obtained by encoding the second signal, the at least one code block includes a relatively large number of first signals. Compared with the method of receiving a code block including a plurality of repeated signals, the signal receiving efficiency of the device is relatively high. When the second signal includes multiple types of information, the multiple types of information can be serially received through the same serial channel, and the number of channels required for receiving the multiple types of information is relatively small, and the cost is relatively low.

[0199] When the device further receives a code block obtained by encoding the third signal, the method can receive multiple types of information. When a serial channel for receiving a plurality of code blocks is implemented by one pin or a group of pins, the number of pins included in the device for implementing the serial channel can be relatively small. When receiving at least one of data information or control information through a serial channel and also receiving management information through this serial channel, since the data information, control information, and management information can be received through the same serial channel without receiving the data information, control information, and management information through multiple channels respectively, the cost of receiving the data information, control information, and management information is relatively low.

[0200] Furthermore, the device can negotiate the clock for receiving code blocks, resulting in a diverse range of frequency points for the clock used to receive code blocks. Moreover, the frequency of the clock used for receiving code blocks can be adapted to the chips at both ends of the serial channel. Information located at the other end of the serial channel can receive code blocks according to the negotiated clock, and the device can receive code blocks according to the negotiated clock, ensuring the reliability of code block transmission. When the rate of the frequency point of the negotiated clock is relatively low, the power consumption of the device for receiving code blocks is relatively low.

[0201] It should be understood that when the above Figure 16 and Figure 17 provided device realizes its functions, only the above division of each functional module is used for illustration. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the method embodiment belong to the same concept, and the specific implementation process can be seen in the method embodiment, which will not be elaborated here.

[0202] See Figure 18 , Figure 18 which is a schematic structural diagram of a computer system provided by an embodiment of the present application. Exemplarily, as Figure 18 shown, the computer system is computer system 1800. The computer system 1800 can be a network device, a routing device, or a switching device. Figure 18 The computer system 1800 shown is used to execute the above Figure 4 shown encoding method or Figure 14 shown decoding method. The computer system 1800 is, for example, a server, etc., and the computer system 1800 can be implemented by a general bus architecture.

[0203] As Figure 18 shown, the computer system 1800 includes at least one processor 1801, a memory 1803, and at least one communication interface 1804.

[0204] The processor 1801 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the methods provided in the embodiments of the present application. For example, the processor 1801 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination of the above three. The processor 1801 may implement or execute various logic blocks, modules, and circuits described in connection with the disclosure of the embodiments of the present application, or may be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.

[0205] Optionally, the computer system 1800 further includes a bus. The bus is used to transfer information between the components of the computer system 1800. The bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 18 only a thick line is shown in [description], but it does not mean that there is only one bus or one type of bus.

[0206] The memory 1803 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, such as an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1803 exists independently, for example, and is connected to the processor 1801 via a bus. The memory 1803 can also be integrated with the processor 1801.

[0207] The communication interface 1804 uses any device such as a transceiver to communicate with other devices or communication networks, which can be an Ethernet, a radio access network (RAN), or a wireless local area network (WLAN), etc. The communication interface 1804 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 1804 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiments of the present application, the communication interface 1804 can be used for the computer system 1800 to communicate with other devices.

[0208] In a specific implementation, as an embodiment, the processor 1801 can include one or more CPUs, such as Figure 18 CPU0 and CPU1 shown in. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0209] In a specific implementation, as an embodiment, the computer system 1800 may include multiple processors, such as Figure 18 the processors 1801 and 1805 shown therein. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processors herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0210] In a specific implementation, as an embodiment, the computer system 1800 may further include an output device and an input device. The output device communicates with the processor 1801 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 1801 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0211] In some embodiments, the memory 1803 is used to store the program code 1810, and the processor 1801 may execute the program code 1810 stored in the memory 1803. The program code 1810 may include one or more software modules. Optionally, the processor 1801 itself may also store program code or instructions.

[0212] In a specific embodiment, the computer system 1800 of the embodiments of the present application may include the first chip and / or the second chip in each of the above method embodiments, and the first chip and / or the second chip may be implemented by the processor 1801 in the computer system 1800.

[0213] The computer system 1800 may also correspond to the above Figure 16 and Figure 17 shown device, Figure 16 or Figure 17 each functional module in the shown device may be implemented by a circuit in the processor 1800.

[0214] Among them, Figure 4 the steps of the shown encoding method and Figure 14 the steps of the shown decoding method are completed by the integrated logic circuit of the hardware in the processor of the computer system 1800. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware processor.

[0215] Figure 19It is a schematic structural diagram of another computer system provided by an embodiment of the present application. The computer system is used to execute the above-mentioned Figure 4 encoding method shown and Figure 14 decoding method shown. Exemplarily, the computer system is a server, and the server may vary greatly due to different configurations or performances. The computer system may include one or more processors 1901, and the one or more processors 1901 are used to implement the first chip and / or the second chip in the method embodiment. As Figure 19 shown, the computer system may further include one or more memories 1902, wherein at least one computer program is stored in the one or more memories 1902, and the at least one computer program is loaded and executed by the one or more processors 1901. Exemplarily, the processor 1901 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The computer system may further include other components for implementing the functions of the device, which will not be elaborated here.

[0216] An embodiment of the present application further provides a communication device, which includes: a transceiver module for performing Figure 4 operations related to receiving and / or sending in the encoding method shown; a processing module for performing Figure 4 other operations in the encoding method except for operations related to receiving and / or sending. An embodiment of the present application further provides another communication device, which includes: a transceiver module for performing Figure 14 operations related to receiving and / or sending in the decoding method shown; a processing module for performing Figure 14 other operations in the decoding method except for operations related to receiving and / or sending.

[0217] An embodiment of the present application provides a chip, which includes: a MAC layer circuit, and the MAC layer circuit is used to execute Figure 4 the encoding method shown and / or Figure 14 the decoding method shown. An embodiment of the present application further provides another chip, which includes: a PHY circuit, and the PHY circuit is used to execute Figure 4 the encoding method shown and / or Figure 14 the decoding method shown.

[0218] An embodiment of the present application further provides a communication system, which includes a first chip and a second chip; the first chip is used to execute Figure 4 the encoding method shown, and the second chip is used to execute Figure 14 the decoding method shown.

[0219] It should be understood that the above-mentioned processor can be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor can be a processor that supports the advanced RISC machines (ARM) architecture.

[0220] Furthermore, in an alternative embodiment, if one or more of the above computer systems, communication devices, chips or communication systems further include a memory, the memory can include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory can also include a non-volatile random access memory. For example, the memory can also store information about the device type.

[0221] The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM) or flash memory. The volatile memory can be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0222] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program or a computer program product. The computer program or computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0223] To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0224] The computer program code for implementing the method of the embodiments of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable annotation content storage devices, so that when the program codes are executed by the computer or other programmable annotation content storage devices, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0225] In the context of the embodiments of the present application, the computer program code or relevant data can be carried by any suitable carrier, so that the device, apparatus or processor can execute the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc. Examples of signals can include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0226] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0227] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there can be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices or modules, and can also be electrical, mechanical or other forms of connections.

[0228] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

[0229] In addition, the functional modules in the various embodiments of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0230] The terms "first", "second", etc. in the present application are used to distinguish the same items or similar items with basically the same functions and effects. It should be understood that there is no logical or temporal dependence relationship between "first", "second", and "nth", and the quantity and execution order are not limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, the first chip can be called the second chip, and similarly, the second chip can be called the first chip.

[0231] It should also be understood that in various embodiments of the present application, the magnitude of the serial numbers of the various processes does not mean the order of execution, and the order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0232] In the present application, the meaning of the term "at least one" is one or more, and the meaning of the term "a plurality" is two or more. For example, a plurality of code blocks means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0233] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0234] It should also be understood that when the term "comprises" (also referred to as "includes", "including", "comprises", and / or "comprising") is used in this specification, it specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0235] It should also be understood that, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" can be interpreted to mean "when it is determined..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0236] It should be understood that determining B based on A does not mean determining B solely based on A, and B can also be determined based on A and / or other information.

[0237] It should also be understood that throughout the specification, the references to "one embodiment", "an embodiment", "a possible implementation" mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment", "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner.

[0238] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present application shall be included within the protection scope of the present application.

Claims

1. A coding method, characterized in that, The method includes: The first chip combines the first signals of n periods to be transmitted to obtain a second signal, where the first signals of the n periods include at least one of data information or control information, and n is a positive integer greater than 1; The first chip encodes the second signal to obtain at least one code block; The first chip sends the at least one code block through a serial channel, and the serial channel is used to connect the Media Access Control (MAC) layer and the Physical (PHY) layer.

2. The method according to claim 1, characterized in that, The first chip encodes the second signal to obtain at least one code block, including: The first chip encodes the second signal and a third signal to be transmitted to obtain a plurality of code blocks, where the third signal includes management information; The first chip sends the at least one code block through a serial channel, including: The first chip sends the plurality of code blocks through one serial channel.

3. The method according to claim 1, characterized in that, The at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication for indicating the signal type included in the second signal.

4. The method according to claim 2, characterized in that, The plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal.

5. The method according to claim 2, characterized in that, The plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the plurality of code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

6. The method according to claim 2, characterized in that, The plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the plurality of code blocks. The at least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

7. The method according to any one of claims 1-6, characterized in that, The first chip sends the at least one code block through a serial channel, including: The first chip negotiates with the chip at the other end of the serial channel for the clock used to transmit the at least one code block; The first chip sends the at least one code block through the serial channel according to the negotiated clock.

8. The method according to claim 7, characterized in that, The at least one code block includes a plurality of first code blocks and a plurality of second code blocks. The frequency point of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

9. The method according to any one of claims 2, 4-6, characterized in that, The first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

10. The method according to any one of claims 1-9, characterized in that, The serial channel is a channel between improved Serial Gigabit Media Independent Interface (SGMII).

11. A decoding method, characterized in that, The method includes: The second chip receives at least one code block through a serial channel, where the at least one code block is obtained by encoding a second signal, and the second signal is obtained by combining the first signals of n periods to be transmitted, and the first signals of the n periods include at least one of data information or control information. The serial channel is used to connect the Media Access Control (MAC) layer and the Physical (PHY) layer, and n is a positive integer greater than 1; The second chip decodes the at least one code block to obtain the second signal; The second chip splits the second signal to obtain n signals.

12. The method according to claim 11, characterized in that, The second chip receiving at least one code block through a serial channel includes: The second chip receives a plurality of code blocks through the serial channel, and the plurality of code blocks are obtained by encoding the second signal and a third signal to be transmitted, and the third signal includes management information; The second chip decoding the at least one code block to obtain the second signal includes: The second chip decodes the plurality of code blocks to obtain the second signal and the third signal.

13. The method according to claim 11, characterized in that, The at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication for indicating the signal type included in the second signal. The second chip decoding the at least one code block to obtain the second signal includes: The second chip obtains the second signal from the first code block; The second chip splitting the second signal to obtain n signals includes: The second chip obtains the signal type included in the second signal based on the type indication included in the second code block; The second chip splits the second signal according to the signal type included in the second signal to obtain n signals.

14. The method according to claim 12, wherein The plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal. The second chip splitting the second signal to obtain n signals includes: The second chip obtains the signal type included in the second signal according to the type of the first code block; The second chip splits the second signal according to the signal type included in the second signal to obtain n signals.

15. The method according to claim 12, wherein The plurality of code blocks includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the plurality of code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

16. The method according to claim 12, wherein The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The at least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

17. The method according to any one of claims 11-16, wherein The second chip receives at least one code block through a serial channel, including: The second chip negotiates a clock for transmitting the at least one code block with a chip located at the other end of the serial channel; The second chip receives the at least one code block through the serial channel according to the negotiated clock.

18. The method according to claim 17, wherein The at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

19. The method according to any one of claims 12, 14-16, wherein The second chip is a MAC chip, and the third signal further includes a physical layer channel status indication signal.

20. The method according to any one of claims 11-19, wherein The serial channel is a channel between improved Serial Gigabit Media Independent Interface (SGMII).

21. An encoding device, wherein The device is applied to a first chip, and the device includes: A merging module, configured to merge the first signals of n periods to be transmitted to obtain a second signal. The first signals of the n periods include at least one of data information or control information, and n is a positive integer greater than 1; An encoding module, configured to encode the second signal to obtain at least one code block; A sending module, configured to send the at least one code block through a serial channel, and the serial channel is used to connect the Media Access Control (MAC) layer and the Physical layer (PHY).

22. The device according to claim 21, wherein The encoding module is configured to encode the second signal and the third signal to be transmitted to obtain multiple code blocks, and the third signal includes management information; the sending module is configured to send the multiple code blocks through a serial channel.

23. The device according to claim 21, wherein The at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication, and the type indication is used to indicate the signal type included in the second signal.

24. The device according to claim 22, wherein The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal.

25. The device according to claim 22, wherein The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

26. The device according to claim 22, wherein The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The at least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

27. The device according to any one of claims 21-26, wherein The sending module is configured to negotiate a clock for transmitting the at least one code block with a chip located at the other end of the serial channel; and transmit the at least one code block through the serial channel according to the negotiated clock.

28. The device according to claim 27, whereinThe at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

29. The device according to any one of claims 22, 24 - 26, characterized in that, The first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

30. The device according to any one of claims 21 - 29, characterized in that, The serial channel is a channel between improved Serial Gigabit Media Independent Interface (SGMII).

31. A decoding device, characterized in that, The device is applied to a second chip, and the device includes: A receiving module, configured to receive at least one code block through a serial channel. The at least one code block is obtained by encoding a second signal, and the second signal is obtained by combining the first signals of n periods to be transmitted. The n periods of the first signals include at least one of data information or control information. The serial channel is used to connect the Media Access Control (MAC) layer and the Physical Layer (PHY), and n is a positive integer greater than 1; A decoding module, configured to decode the at least one code block to obtain the second signal; A splitting module, configured to split the second signal to obtain n signals.

32. The device according to claim 31, characterized in that, The receiving module is configured to receive, by the second chip through the serial channel, multiple code blocks, where the multiple code blocks are obtained by encoding the second signal and a third signal to be transmitted, and the third signal includes management information; the decoding module is configured to decode the multiple code blocks to obtain the second signal and the third signal.

33. The device according to claim 31, characterized in that, The at least one code block includes a first code block and a second code block. The first code block includes the second signal, and the second code block includes a type indication for indicating the signal type included in the second signal; the decoding module is configured to obtain the second signal from the first code block; the splitting module is configured to obtain the signal type included in the second signal based on the type indication included in the second code block; and split the second signal according to the signal type included in the second signal to obtain n signals.

34. The device according to claim 32, characterized in that, The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The type of the first code block is used to indicate the signal type included in the second signal. The splitting module is configured to obtain the signal type included in the second signal according to the type of the first code block, and split the second signal according to the signal type included in the second signal to obtain n signals.

35. The device according to claim 32, characterized in that, The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame.

36. The device according to claim 32, characterized in that, The multiple code blocks include a first code block and a second code block. The first code block includes the second signal, and the second code block includes the third signal. The first signal is related to an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The at least one first code block includes a first code block associated with the preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

37. The device according to any one of claims 31 - 36, characterized in that, The receiving module is configured to negotiate a clock for transmitting the at least one code block with a chip located at the other end of the serial channel, and receive the at least one code block through the serial channel according to the clock determined by the negotiation.

38. The device according to claim 37, characterized in that, The at least one code block includes multiple first code blocks and multiple second code blocks. The frequency point of the clock for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

39. The device according to any one of claims 32, 34 - 36, characterized in that, The second chip is a MAC chip, and the third signal further includes a physical layer channel status indication signal.

40. The device according to any one of claims 31 - 39, characterized in that, The serial channel is a channel between improved Serial Gigabit Media Independent Interfaces (SGMII).

41. A chip, characterized in that, The chip includes: a Media Access Control (MAC) layer circuit, and the MAC layer circuit is configured to execute the encoding method according to any one of claims 1-10, or the decoding method according to any one of claims 11-20.

42. A chip, characterized in that, The chip includes: a Physical Layer (PHY) circuit, and the PHY circuit is configured to execute the encoding method according to any one of claims 1-10, or the decoding method according to any one of claims 11-20.

43. A communication system, characterized in that, The communication system includes a first chip and a second chip. The first chip is configured to execute the encoding method according to any one of claims 1-10, and the second chip is configured to execute the decoding method according to any one of claims 11-20.

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