Power synthesis amplifier

Abstract

The invention discloses a power synthesis amplifier which comprises two power amplification structures, and each power amplification structure is composed of an input matching circuit, a driving stage amplifier DA, an inter-stage matching circuit, a power stage amplifier PA and an output matching circuit. The input end of the power synthesis amplifier is connected by a T-junction power distribution network; the output end of the power synthesis amplifier is connected with the T-junction power synthesis network. The output power of the power amplifier is improved by adopting a two-path synthesis technology, specifically, the power amplifier can be expanded to multiple paths according to needs, and an output power synthesis network adopts a current type synthesis network, so that the amplitude-phase balance of two paths of output signals and the current processing capability of a circuit are ensured, and the output efficiency is improved; the output-stage matching circuit adopts a transformer with a high coupling coefficient to reduce signal loss, the input and inter-stage matching networks adopt a transformer with a low coupling coefficient to play a role in expanding bandwidth, and the multi-stage matching circuit can be widely applied to the technical field of mobile communication and radar detection.

Description

Technical Field

[0001] The present invention relates to the technical fields of wireless communication and radar detection, and particularly relates to a power combining amplifier. Background Art

[0002] With the continuous development of wireless communication and radar detection technologies, people have put forward higher requirements for high-performance wireless communication and radar systems. As a core module in wireless communication and radar systems, the performance of a radio frequency transmitter affects the performance of the entire wireless communication and radar system, and the performance of a radio frequency transmitter is often determined by a power amplifier. Due to advantages such as easy integration and low cost, the silicon-based process has become one of the main processes adopted for radio frequency transceiver chips. In the silicon-based process, as the process technology becomes more and more advanced, the allowable operating voltage of transistors becomes lower and lower. Therefore, the output swing of transistors is greatly limited, making it difficult for the power amplifier to generate output power that meets actual requirements. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve the problem that the silicon-based power amplifier has limited transistor swing, resulting in the difficulty of the power amplifier to meet the requirements of large output power. To solve the above problem, a power combining amplifier is provided.

[0004] The purpose of the present invention is achieved in the following manner: A power combining amplifier, the power combining amplifier includes two power amplification structures. The signal of the power combining amplifier is input from the RFin terminal, and after impedance tuning by a parallel capacitor, it is divided into two power amplification structures by a T-shaped power distribution network. The output terminal of the power combining amplifier performs power combination by a T-shaped power combining network, and after impedance tuning by a parallel capacitor, the signal is output at the RFout terminal.

[0005] The signal input terminal RFin of the power combining amplifier is connected to the T-shaped power distribution network. The signal is divided into two paths via the power distribution point A. One end of the impedance tuning capacitor C1 is connected to the RFin port, and the other end is grounded.

[0006] Each of the two power amplification structures includes an input matching circuit, a driver stage amplifier DA, an inter-stage matching circuit, a power stage amplifier PA, and an output matching circuit connected in sequence.

[0007] The input matching circuit is composed of a transformer TF1. One end of the primary coil of TF1 is connected to GND and the other end is connected to the power splitting point A. The center tap of the secondary coil of TF1 is connected to VB1, which is used to provide a gate voltage bias for the driver stage amplifier DA.

[0008] The drive - stage amplifier DA adopts the topology of a differential common - source amplifier. Among them, MOS transistors M1 and M2 are amplifying transistors. The gates of MOS transistors M1 and M2 are the signal input terminals IN1+ and IN1-, which are respectively connected to the two ports of the secondary coil of transformer TF2. The sources of MOS transistors M1 and M2 are grounded. The drains of MOS transistors M1 and M2 are the signal output terminals OUT1- and OUT1+ respectively. MOS transistors M3 and M4 act as MOS capacitors. The gate of M3 is connected to the IN1- terminal of the gate of M2, the gate of M4 is connected to the IN1+ terminal of the gate of M1, the source - drain of M3 is connected to the signal output terminal OUT1-, and the source - drain of M4 is connected to the signal output terminal OUT1+.

[0009] The inter - stage matching circuit is composed of transformer TF2. The two ports of the primary coil of transformer TF2 are respectively connected to the signal output terminals OUT1- and OUT1+ of the drive - stage amplifier. The center tap of the primary coil is connected to VDD1 to supply power to the drive - stage amplifier. The two ports of the secondary coil of transformer TF2 are respectively connected to the signal input terminals of the power - stage amplifier PA. The center tap of the secondary coil is connected to VB2, which is used to provide the gate - voltage bias for the common - source amplifying transistor of the power - stage amplifier PA.

[0010] The power - stage amplifier PA adopts the topology of a differential common - source and common - gate amplifier. MOS transistors M5 and M6 are common - source transistors, M7 and M8 are common - gate transistors, and M9 and M10 are MOS capacitor transistors. The gates of M5 and M6 are the signal input terminals IN2+ and IN2- respectively. The signal input terminals IN2+ and IN2- are respectively connected to the two ports of the secondary coil of the inter - stage matching transformer TF2. The sources of M5 and M6 are grounded. The drains of M5 and M6 are respectively connected to the sources of the common - gate transistors M7 and M8. The drains of the common - gate transistors M7 and M8 are the signal output terminals OUT2- and OUT2+ respectively. The gates of the common - gate transistors M7 and M8 are connected to the bias - voltage VB terminal. The gates of the neutralization capacitor transistors M9 and M10 are respectively connected to the IN2- of the gate of M6 and the IN2+ of the gate of M5. The source and drain of M9 are connected to the drain of M5, and the source and drain of M10 are connected to the drain of M6.

[0011] The output matching circuit is composed of transformer TF3. The two ends of the primary coil of TF3 are respectively connected to the signal output terminals OUT2- and OUT2+ of the power - stage amplifier PA. The center tap of the primary coil is connected to the power supply VDD2 to supply power to the power - stage amplifier PA. One port of the secondary coil is connected to GND, and the other port is connected to the power - combining point B.

[0012] The two power - amplified signals of the power - combining amplifier are combined into one path at the power - combining B point by a T - type power - combining network and then output through the output port RFout. One end of the impedance - tuning capacitor C2 is connected to the RFout port, and the other end is grounded.

[0013] Advantages of the present invention: The present invention adopts a two-way power combining method, which has obvious advantages in output power compared with traditional single-way power amplifiers, and the power combining amplifier can be expanded into multi-way power combining according to actual needs. In addition, the output power combining network uses a transformer plus a T-shaped network for current-type power combining, which has better amplitude-phase balance and current handling ability compared with the voltage-type power combining network, improving the power combining efficiency. The transformer of the output stage matching circuit of the present invention uses a transformer with a high coupling coefficient, reducing the loss of signal power. The transformers of the input stage matching circuit and the inter-stage matching circuit use transformers with a low coupling coefficient, making the two resonance points of the transformer approach each other, ensuring the relative stability of the in-band impedance, and improving the bandwidth of the power amplifier. At the same time, the driver stage amplifier DA and the power stage amplifier PA of the present invention adopt a differential form. The swing of the differential amplifier is twice that of the single-ended amplifier, increasing the output power and suppressing the common-mode signal, improving the linearity of the power amplifier. Description of the Drawings

[0014] Figure 1 It is a block diagram of the power combining amplifier provided by an embodiment of the present invention; Figure 2 It is a block diagram of the driver stage amplifier DA provided by an embodiment of the present invention; Figure 3 It is a block diagram of the power stage amplifier PA provided by an embodiment of the present invention; Figure 4 It is a three-dimensional model diagram of the input matching transformer TF1 provided by an embodiment of the present invention; Figure 5 It is a three-dimensional model diagram of the inter-stage matching transformer TF2 provided by an embodiment of the present invention; Figure 6 It is a three-dimensional model diagram of the transformer-type output power combining network provided by an embodiment of the present invention; Figure 7 It is the output power under the simulation of the power combining amplifier at 20 GHz provided by an embodiment of the present invention; Figure 8 It is the additional efficiency under the simulation of the power combining amplifier at 20 GHz provided by an embodiment of the present invention.

[0015] Figure 9 It is the power gain under the simulation of the power combining amplifier in the 18 - 22 GHz frequency band provided by an embodiment of the present invention. Detailed Embodiments

[0016] The present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0017] It should be noted that the following detailed description is exemplary and is intended to provide further illustration of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0018] As Figure 1 shown, the power combining amplifier provided by the present invention includes two power amplification structures. The input end of the power combining amplifier is impedance-tuned by a shunt capacitor and then divided into two power amplification structures at point A through a T-type power distribution network. The output end of the power combining amplifier combines the power at point B through a T-type power combining network and outputs a signal at the RFout end after impedance tuning through a shunt capacitor.

[0019] Each of the two power amplifier structures includes an input matching circuit, a driver stage amplifier DA, an inter-stage matching circuit, a power stage amplifier PA, and an output matching circuit connected in sequence.

[0020] The input matching circuit is composed of a transformer TF1. One end of the primary coil of TF1 is connected to GND and the other end is connected to the power distribution point A. The center tap of the secondary coil of TF1 is connected to VB1 to provide a gate voltage bias for the driver stage amplifier DA.

[0021] As Figure 2 shown, the driver stage amplifier DA adopts a differential common-source amplifier topology. MOS transistors M1 and M2 are amplification transistors. The gates of MOS transistors M1 and M2 are the signal input terminals IN1+ and IN1-, respectively, and are connected to the two ports of the secondary coil of the transformer TF2. The sources of MOS transistors M1 and M2 are grounded. The drains of MOS transistors M1 and M2 are the signal output terminals OUT1- and OUT1+, respectively. MOS transistors M3 and M4 serve as MOS capacitor transistors to act as neutralizing capacitors to improve the stability of the driver stage amplifier DA. The gate of M3 is connected to the IN1- terminal of the gate of M2, the gate of M4 is connected to the IN1+ terminal of the gate of M1, the source-drain of M3 is connected to the signal output terminal OUT1-, and the source-drain of M4 is connected to the signal output terminal OUT1+.

[0022] As Figure 1 shown, the inter-stage matching circuit is composed of a transformer TF2. The two ports of the primary coil of the transformer TF2 are respectively connected to the signal output terminals OUT1- and OUT1+ of the driver stage amplifier. The center tap of the primary coil is connected to VDD1 to supply power to the driver stage amplifier. The two ports of the secondary coil of the transformer TF2 are respectively connected to the signal input terminals of the power stage amplifier PA. The center tap of the secondary coil is connected to VB2 to provide a gate voltage bias for the common-source amplifier transistor of the power stage amplifier PA.

[0023] AsFigure 3 As shown in the figure, the power amplifier PA adopts the topology of a differential cascode amplifier. MOS transistors M5 and M6 are cascode transistors, M7 and M8 are common-gate transistors, and M9 and M10 are MOS capacitor transistors. The gates of M5 and M6 are respectively the signal input terminals IN2+ and IN2-. The signal input terminals IN2+ and IN2- are respectively connected to the two ports of the secondary coil of the inter-stage matching transformer TF2. The sources of M5 and M6 are grounded, and the drains of M5 and M6 are respectively connected to the sources of the common-gate transistors M7 and M8; the drains of the common-gate transistors M7 and M8 are respectively the signal output terminals OUT2- and OUT2+; the gates of the common-gate transistors M7 and M8 are connected to the bias voltage VB terminal; the gates of the neutralizing capacitor transistors M9 and M10 are respectively connected to the gate signal input terminal IN2- of M6 and the gate signal input terminal IN2+ of M5. The source and drain of M9 are connected to the drain of M5, and the source and drain of M10 are connected to the drain of M6.

[0024] As Figure 1 shown in the figure, the output matching circuit is composed of a transformer TF3. The two ends of the primary coil of TF3 are respectively connected to the signal output terminals OUT2- and OUT2+ of the power amplifier PA. The center tap of the primary coil is connected to the power supply VDD2 for supplying power to the power amplifier PA; one port of the secondary coil is connected to GND, and the other port is connected to the power combining point B.

[0025] Figure 6 This is the three-dimensional model diagram of the transformer-type output power combining network provided by the embodiment of the present invention. The output matching transformer adopts a high-coupling coefficient transformer to reduce the loss of signal power and improve the transmission efficiency. The two-way output power is integrated into one way through a T-junction.

[0026] Figure 4 This is the three-dimensional view of the input matching transformer TF1 provided by the embodiment of the present invention. Figure 5 This is the three-dimensional view of the inter-stage matching transformer TF2 provided by the embodiment of the present invention. The input matching network and the inter-stage matching network adopt transformers with low coupling coefficients. By using the characteristic that the two resonance peaks of the transformer are closer as the coupling coefficient decreases, the gain of the matching network is stable within the target frequency band, the 3dB bandwidth is increased, and the broadband of the power amplifier is effectively extended.

[0027] Figure 7 This is the output power under the simulation of the power combining amplifier at 20 GHz provided by the embodiment of the present invention. It can be seen from the simulation curve that the saturated output power is 22.28 dBm, and it has a relatively high saturated output power.

[0028] Figure 8The additional efficiency under the simulation of the power combining amplifier at 20 GHz provided by the embodiment of the present invention. It can be seen from the simulation curve that the peak power added efficiency is 20.3%. It can be seen that this embodiment meets the requirement of high efficiency.

[0029] Figure 9 The power gain under the simulation of the power combining amplifier in the 18 - 22G frequency band provided by the embodiment of the present invention. It can be seen from the simulation curve that the power gain is greater than 25 dB. It can be seen that this embodiment meets the requirement of high gain.

[0030] The present invention adopts a two - way power combining method, which has obvious advantages in output power compared with the traditional single - way power amplifier, and the power combining amplifier can be expanded into a multi - way power combining according to actual needs. In addition, the output power combining network uses a transformer plus T - junction form for current - type power combining, which has better amplitude - phase balance and current handling ability compared with the voltage - type power combining network, improving the power combining efficiency. The transformer of the output - stage matching circuit of the present invention uses a transformer with a high coupling coefficient, reducing the loss of signal power. The transformers of the input - stage matching circuit and the inter - stage matching circuit use transformers with a low coupling coefficient, making the two resonance points of the transformer close to each other, ensuring the relative smoothness of the in - band gain and improving the bandwidth of the power amplifier. At the same time, the driver - stage amplifier DA and the power - stage amplifier PA of the present invention adopt a differential form. The swing of the differential amplifier is twice that of the single - ended amplifier, increasing the output power and suppressing the common - mode signal, improving the linearity of the power amplifier.

[0031] The above - mentioned are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the overall concept of the present invention, several changes and improvements can still be made, and these should also be regarded as the protection scope of the present invention.

Claims

1. A power combining amplifier, characterized in that: The power combining amplifier includes two power amplification structures. The signal of the power combining amplifier is input from the RFin terminal, and after impedance tuning by a shunt capacitor, it is divided into two power amplification structures through a T-type power distribution network. The output terminal of the power combining amplifier combines the power of the two power amplification structures through a T-type power combining network, and after impedance tuning by a shunt capacitor, the signal is output at the RFout terminal.

2. The power combining amplifier according to claim 1, characterized in that: The signal input terminal RFin is connected to the T-type power distribution network. The signal is divided into two paths via the power distribution point A. One end of the impedance tuning capacitor C1 is connected to the RFin port, and the other end is grounded.

3. The power combining amplifier according to any one of claims 1 or 2, characterized in that: Each of the power amplification structures of the power combining amplifier includes an input matching circuit, a driver stage amplifier DA, an inter-stage matching circuit, a power stage amplifier PA, and an output matching circuit connected in sequence.

4. The power combining amplifier according to claim 3, wherein: The input matching circuit is composed of a transformer TF1. One end of the primary coil of TF1 is connected to GND and the other end is connected to the power distribution point A. The center tap of the secondary coil of TF1 is connected to VB1 to provide a gate voltage bias for the driver stage amplifier DA.

5. The power combining amplifier according to claim 3, wherein: The driver stage amplifier DA adopts the topology of a differential common-source amplifier. The MOS transistors M1 and M2 are amplification transistors. The gates of the MOS transistors M1 and M2 are the signal input terminals IN1+ and IN1-, respectively, and are connected to the two ports of the secondary coil of the transformer TF2. The sources of the MOS transistors M1 and M2 are grounded. The drains of the MOS transistors M1 and M2 are the signal output terminals OUT1- and OUT1+, respectively. The MOS transistors M3 and M4 act as MOS capacitor functions. The gate of M3 is connected to the IN1- terminal of the gate of M2, the gate of M4 is connected to the IN1+ terminal of the gate of M1, the source-drain of M3 is connected to the signal output terminal OUT1-, and the source-drain of M4 is connected to the signal output terminal OUT1+.

6. The power combining amplifier according to claim 3, wherein: The inter-stage matching circuit is composed of a transformer TF2. The two ports of the primary coil of the transformer TF2 are respectively connected to the signal output terminals OUT1- and OUT1+ of the driver stage amplifier. The center tap of the primary coil is connected to VDD1 to supply power to the driver stage amplifier. The two ports of the secondary coil of the transformer TF2 are respectively connected to the signal input terminals of the power stage amplifier PA. The center tap of the secondary coil is connected to VB2 to provide a gate voltage bias for the common-source amplifier transistor of the power stage amplifier PA.

7. The power combining amplifier according to claim 3, characterized in that: The power amplifier PA adopts a differential cascode amplifier topology. MOS transistors M5 and M6 are common-source transistors, M7 and M8 are cascode transistors, and M9 and M10 are MOS capacitor transistors. The gates of M5 and M6 are respectively the signal input terminals IN2+ and IN2-. The signal input terminals IN2+ and IN2- are respectively connected to the two ports of the secondary coil of the inter-stage matching transformer TF2. The sources of M5 and M6 are grounded, and the drains of M5 and M6 are respectively connected to the sources of the cascode transistors M7 and M8. The drains of the cascode transistors M7 and M8 are respectively the signal output terminals OUT2- and OUT2+. The gates of the cascode transistors M7 and M8 are connected to the bias voltage VB terminal. The gates of the neutralization capacitor transistors M9 and M10 are respectively connected to the gate signal input terminal IN2- of M6 and the gate signal input terminal IN2+ of M5. The source and drain of M9 are connected to the drain of M5, and the source and drain of M10 are connected to the drain of M6.

8. The power combining amplifier according to claim 3, wherein: The output matching circuit is composed of a transformer TF3. The two ends of the primary coil of TF3 are respectively connected to the signal output terminals OUT2- and OUT2+ of the power amplifier PA. The center tap of the primary coil is connected to the power supply VDD2 for supplying power to the power amplifier PA. One port of the secondary coil is connected to GND, and the other port is connected to the power combining point B.

9. The power combining amplifier according to claim 1, wherein: The two-way power amplification structure is power-combined into one way at point B by a T-type power combining network and then output through the output port RFout. One end of the impedance tuning capacitor C2 is connected to the RFout port, and the other end is grounded.

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