Display panel, manufacturing method thereof and display device

Abstract

The embodiment of the invention provides a display panel, and belongs to the technical field of display. The display panel comprises a display area and a peripheral area, and the display panel comprises a driving backboard and a light-emitting functional layer which are stacked. The driving backboard comprises a substrate and a driving circuit layer on the first surface of the substrate, and the light-emitting functional layer comprises a plurality of light-emitting units distributed in an array. The driving circuit layer comprises a first conductive structure, the first conductive structure comprises a plurality of first signal lines and a plurality of second signal lines, the first signal lines extend in the first direction, the second signal lines extend in the second direction, the first direction intersects with the second direction, the first signal lines are electrically connected with the second signal lines, and the second signal lines are electrically connected with the first conductive structure. The first conductive structure is at least located in the display area and is used for providing a negative power supply voltage for the plurality of light-emitting units. According to the embodiment of the invention, the problem of high power consumption of the display panel can be solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and particularly to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] Display devices have a wide range of application scenarios in life, such as electronic devices like mobile phones and tablet computers. A display panel is an important component of a display device.

[0003] In related technologies, a display panel includes a stacked driving backplane and a light-emitting functional layer. The display panel includes a display area and a peripheral area, and the peripheral area surrounds the display area. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array. The driving backplane includes signal lines located in the peripheral area and surrounding the display area, and the signal lines supply a negative power supply voltage to the plurality of light-emitting units. This display panel has a problem of relatively high power consumption. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which can reduce the power consumption of the display panel. The technical solutions are as follows:

[0005] On the one hand, a display panel is provided. The display panel includes a display area and a peripheral area, and the peripheral area surrounds the display area. The display panel includes a stacked driving backplane and a light-emitting functional layer. The driving backplane includes a substrate and a driving circuit layer on a first surface of the substrate. The light-emitting functional layer includes a plurality of light-emitting units distributed in an array. The driving circuit layer includes a first conductive structure. The first conductive structure includes a plurality of first signal lines and a plurality of second signal lines. The plurality of first signal lines extend in a first direction, the plurality of second signal lines extend in a second direction, the first direction and the second direction intersect, the plurality of first signal lines and the plurality of second signal lines are electrically connected, and the first conductive structure is at least located in the display area and the first conductive structure is configured to supply a negative power supply voltage to the plurality of light-emitting units.

[0006] Optionally, the light-emitting functional layer further includes a pixel definition layer. The pixel definition layer includes a plurality of openings distributed in an array. The plurality of light-emitting units correspond to the plurality of openings one by one, and at least a part of the light-emitting unit is located in the corresponding opening. A positive projection of each first signal line on the first surface passes through a geometric center of a positive projection of at least one of the openings on the first surface, and different first signal lines pass through different openings.

[0007] Optionally, the plurality of first signal lines and the plurality of second signal lines are located in different layers, and the first signal lines and the second signal lines are electrically connected through vias; or, the plurality of first signal lines and the plurality of second signal lines are located in the same layer.

[0008] Optionally, the driving circuit layer further includes a second conductive structure and a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected to the plurality of light-emitting units in a one-to-one correspondence; the second conductive structure includes a plurality of third signal lines and a plurality of fourth signal lines, the plurality of third signal lines extend in a first direction, the plurality of fourth signal lines extend in a second direction, the plurality of third signal lines and the plurality of fourth signal lines are electrically connected, the second conductive structure is at least located in the display area, and the second conductive structure is configured to provide a positive power supply voltage to the plurality of pixel driving circuits.

[0009] Optionally, the plurality of openings include a plurality of first openings arranged in an array, the plurality of first openings are divided into a plurality of first opening groups arranged along the second direction, each first opening group includes a plurality of first openings arranged at intervals along the first direction, and the positive projections of the plurality of first openings in each first opening group on the first surface partially overlap with the positive projections of a pair of the third signal lines on the first surface; the positive projections of two third signal lines in a pair of the third signal lines on the first surface are located on both sides of a first connection line and are symmetric about the first connection line, and the first connection line is a connection line of the geometric centers of the positive projections of the plurality of first openings in the first opening group whose positive projections on the first surface partially overlap with the positive projections of a pair of the third signal lines on the first surface.

[0010] Optionally, the distance between the positive projection of the first opening on the first surface and the positive projection of the second signal line closest to the first opening on the first surface is greater than or equal to 3 μm.

[0011] Optionally, the second conductive structure further includes a plurality of connection portions, the plurality of connection portions are divided into a plurality of connection portion groups arranged along the second direction, each connection portion group includes a plurality of connection portions arranged at intervals along the first direction, and the plurality of connection portions in each connection portion group are respectively connected to two third signal lines in a pair of the third signal lines; the positive projection of the first opening on the first surface is located within the positive projection of a connection portion and a pair of the third signal lines connected by the connection portion on the first surface.

[0012] Optionally, the plurality of openings further includes a plurality of second openings arranged in an array, and the plurality of second openings are divided into a plurality of second opening groups arranged along the second direction. Each second opening group includes a plurality of second openings arranged at intervals along the first direction; the fourth signal line includes a main body and a plurality of protruding portions. The main body extends along the second direction, and one end of the plurality of protruding portions is connected to the main body, and the plurality of protruding portions extend along the first direction; the plurality of protruding portions arranged along the second direction are divided into a plurality of protruding portion groups, and each protruding portion group includes two adjacent protruding portions. The orthographic projection of the protruding portion group on the first surface partially coincides with the orthographic projection of one of the second openings on the first surface. The orthographic projections of the two protruding portions in the protruding portion group on the first surface are located on both sides of the geometric center of the orthographic projection of the corresponding second opening on the first surface in the second direction and are symmetric about the geometric center of the orthographic projection of the corresponding second opening on the first surface.

[0013] Optionally, the first signal line and the second signal line are on different layers, the third signal line and the first signal line are on the same layer, and the fourth signal line and the second signal line are on the same layer; or, the first signal line and the second signal line are on the same layer, the third signal line is located on one side of the first signal line close to the light-emitting unit, the plurality of fourth signal lines include a plurality of first portions and a plurality of second portions, the extending directions of the plurality of first portions and the plurality of second portions are the same and are arranged alternately in the second direction y, the first portion of each fourth signal line is on the same layer as the first signal line, and the second portion of each fourth signal line is on the same layer as the third signal line.

[0014] Optionally, the driving circuit layer includes a plurality of data lines extending along the first direction; the orthographic projections of the plurality of second openings in each second opening group on the first surface partially coincide with the orthographic projections of a pair of data lines on the first surface; the orthographic projections of the two data lines in a pair of data lines on the first surface are located on both sides of the geometric center of the orthographic projection of the second opening in the corresponding second opening group on the first surface in the second direction and are symmetric about the geometric center of the orthographic projection of the second opening in the corresponding second opening group on the first surface.

[0015] Optionally, the plurality of data lines and the third signal line are on the same layer.

[0016] Optionally, the light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence on the driving backplane. The plurality of second electrodes are connected into an integral structure, and the first conductive structure is electrically connected to the plurality of second electrodes through at least one first via, and the at least one first via is located in the peripheral area.

[0017] Optionally, the plurality of light-emitting units include a plurality of first light-emitting units, a plurality of second light-emitting units, and a plurality of third light-emitting units, and the lights emitted by the first light-emitting units, the second light-emitting units, and the third light-emitting units have different colors.

[0018] On the other hand, a method for manufacturing a display panel is provided. The method includes: providing a driving backplane, where the driving backplane includes a substrate and a driving circuit layer on a first surface of the substrate; manufacturing a light-emitting functional layer on the driving backplane, where the light-emitting functional layer includes a plurality of light-emitting units distributed in an array; wherein, the display panel includes a display area and a peripheral area, the peripheral area surrounds the display area, the driving circuit layer includes a first conductive structure, the first conductive structure includes a plurality of first signal lines and a plurality of second signal lines, the plurality of first signal lines extend along a first direction, the plurality of second signal lines extend along a second direction, the first direction and the second direction intersect, the plurality of first signal lines and the plurality of second signal lines are electrically connected, and the first conductive structure is at least located in the display area and the first conductive structure is configured to provide a negative power supply voltage to the plurality of light-emitting units.

[0019] In yet another aspect, a display device is further provided. The display device includes a power supply circuit and any one of the foregoing display panels, and the power supply circuit supplies power to the display panel.

[0020] The beneficial effects brought by the technical solution provided by the present disclosure at least include: by designing the signal lines for providing a negative power supply voltage to the plurality of light-emitting units as a first conductive structure, the first conductive structure includes a plurality of first signal lines and a plurality of second signal lines that are electrically connected, thereby reducing resistance and lowering the power consumption of the display panel. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 is a schematic plan view of a display panel in the related art;

[0023] Figure 2 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure;

[0024] Figure 3 is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0025] Figure 4It is a schematic plan view of a light-emitting unit and a first conductive structure provided by an embodiment of the present disclosure;

[0026] Figure 5 It is a schematic cross-sectional view of a driving circuit layer provided by an embodiment of the present disclosure;

[0027] Figure 6 It is a schematic distribution view of a plurality of openings in a pixel definition layer provided by an embodiment of the present disclosure;

[0028] Figure 7 It is a schematic plan view of a third source-drain layer and a schematic plan view of a second source-drain layer provided by an embodiment of the present disclosure;

[0029] Figure 8 It is a schematic plan view of another display panel provided by an embodiment of the present disclosure;

[0030] Figure 9 It is a schematic plan view of a third source-drain layer and a schematic plan view of a second source-drain layer provided by an embodiment of the present disclosure;

[0031] Figure 10 It is a schematic flow chart of a manufacturing method of a display panel provided by an embodiment of the present disclosure.

[0032] Legend description:

[0033] A, display area; B, peripheral area; x, first direction; y, second direction

[0034] 10, driving backplane; 11, substrate; 11a, first surface; 12, driving circuit layer

[0035] 121, first conductive structure; 1211, first signal line; 1212, second signal line

[0036] 122, second conductive structure; 1221, third signal line; 1222, fourth signal line

[0037] 12211, connecting portion; 122110, connecting portion group; 12221, main body; 12222, extending portion; 122220, extending portion group

[0038] 123, data line; 1201, first source-drain layer; 1202, second source-drain layer; 1203, third source-drain layer; 1204, light-shielding layer; 1205, buffer layer; 1206, first active layer; 1207, first gate insulating layer; 1208, first gate layer; 1209, first insulating layer; 1240, second gate layer; 1241, second gate insulating layer; 1242, second active layer; 1243, third gate insulating layer; 1244, third gate layer; 1245, interlayer dielectric layer; 1246, passivation layer; 1247, first planarization layer; 1248, second planarization layer

[0039] 20. Light-emitting functional layer 200, light-emitting unit

[0040] 21. First electrode 22. Light-emitting layer 23. Second electrode

[0041] 24. Pixel definition layer 240. Opening 241. First opening 2410. First opening group 242. Second opening 2420. Second opening group 243. Third opening

[0042] 30. FPC 40. Encapsulation layer 51. First via hole 52. Second via hole 53. Third via hole 54. Fourth via hole 55. Fifth via hole 56. Sixth via hole Detailed implementation manners

[0043] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe in detail the embodiments of the present application with reference to the accompanying drawings.

[0044] The terms used in the embodiments of the present disclosure are only for explaining the embodiments of the present disclosure, rather than aiming to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", "third", and similar terms used in the specification and claims of the present patent application do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. The terms such as "comprising" or "including" mean that the elements or objects appearing before "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The orientation terms mentioned in the present disclosure, for example, "top", "bottom", "upper", "lower", "left", or "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the orientation terms used are for better and clearer illustration and understanding of the embodiments of the present disclosure, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the embodiments of the present disclosure.

[0045] In the related art, a display panel includes a stacked driving backplane and a light-emitting functional layer. The driving backplane includes a substrate and a driving circuit layer on the first surface of the substrate, and the light-emitting functional layer includes a plurality of light-emitting units distributed in an array. Figure 1 It is a schematic plan view of a display panel in the related art. As Figure 1As shown, the display panel includes a display area A' and a peripheral area B'. The peripheral area B' surrounds the display area A'. The driving circuit layer includes a signal line 120' located in the peripheral area B' and surrounding the display area A'. The signal line 120' is used to provide a negative power supply voltage (also referred to as a VSS signal) to a plurality of light-emitting units, for example, providing a negative power supply voltage to the plurality of light-emitting units through an FPC (Flexible Printed Circuit Board) 30'. However, due to the relatively large resistance of the signal line 120', that is, the resistance between the cathode of the light-emitting unit and the external structure (such as the control circuit board) is too large, the power consumption of the display panel is relatively large.

[0046] Figure 2 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present disclosure. As Figure 2 shown, the display panel includes a stacked driving backplane 10 and a light-emitting functional layer 20. The driving backplane 10 includes a substrate 11 and a driving circuit layer 12 on a first surface 11a of the substrate 11.

[0047] Figure 3 is a schematic plan structure diagram of a display panel provided by an embodiment of the present disclosure. As Figure 3 shown, the display panel includes a display area A and a peripheral area B. The peripheral area B surrounds the display area A. The light-emitting functional layer 20 includes a plurality of light-emitting units 200 distributed in an array. The plurality of light-emitting units 200 are located in the display area A. The driving circuit layer 12 is used to control the plurality of light-emitting units 200 to emit light, thereby displaying an image.

[0048] The driving circuit layer 12 includes a first conductive structure 121. The first conductive structure 121 includes a plurality of first signal lines 1211 and a plurality of second signal lines 1212. The plurality of first signal lines 1211 extend along a first direction x, and the plurality of second signal lines 1212 extend along a second direction y. The first direction x and the second direction y intersect to form a Figure 3 shown mesh structure. The plurality of first signal lines 1211 and the plurality of second signal lines 1212 are electrically connected. The first conductive structure 121 is at least located in the display area A and the first conductive structure 121 is used to provide a negative power supply voltage to the plurality of light-emitting units 200.

[0049] By designing the signal line that provides a negative power supply voltage for multiple light-emitting units 200 as the first conductive structure 121, the first conductive structure 121 includes a plurality of first signal lines 1211 and a plurality of second signal lines 1212 that are electrically connected, which is equivalent to increasing the cross-sectional area of the signal line that provides the negative power supply voltage, or is equivalent to connecting a plurality of first signal lines and a plurality of second signal lines in parallel, so that the resistance of the first conductive structure 121 is smaller than that of the signal line in the related art, that is, the resistance between the light-emitting unit and the outside (such as a control circuit board) is reduced, preventing excessive energy such as heat energy from being lost on the signal line, thereby reducing the power consumption of the display panel.

[0050] Exemplarily, as Figure 3 shown, the display panel further includes an FPC 30, and the FPC 30 is electrically connected to the first conductive structure 121 for an external device (such as a control circuit board) to input a negative power supply voltage to the first conductive structure 121 through the FPC. Optionally, the first conductive structure is located in the display area A and the peripheral area B, and is electrically connected to the pads located in the peripheral area B, and the FPC is electrically connected to the pads located in the peripheral area B.

[0051] Optionally, as Figure 3 shown, the first conductive structure 121 is electrically connected to a plurality of second electrodes 23 through at least one first via 51, and at least one first via 51 is located in the peripheral area B. A plurality of light-emitting units 200 are electrically connected to the first conductive structure 121 through at least one first via 51, so as to facilitate the first conductive structure 121 to provide a negative power supply voltage for the plurality of light-emitting units. Optionally, as Figure 3 shown, the first conductive structure 121 further includes an annular signal line, and the annular signal line is located in the peripheral area B and surrounds the display area A, and the annular signal line is electrically connected to a plurality of first signal lines 1211 and a plurality of second signal lines 1212, and the annular signal line is connected to the first via 51. It should be noted that Figure 3 the position of the first via 51 in Figure 3 is only an example, and the first via 51 can also be located at other positions in the peripheral area B, such as in

[0052] the shown embodiment, the first via 51 can also be located on the left side of the display area A and in the peripheral area B. Optionally, the annular signal line and the first signal line 1211 are located on the same layer or different layers.

[0053] Exemplarily, as Figure 2As shown, the light-emitting unit includes a first electrode 21, a light-emitting layer 22, and a second electrode 23 that are sequentially stacked on the first surface 11a.

[0054] Optionally, the first electrode 21 is an anode, the second electrode 23 is a cathode, and the second electrode 23 is electrically connected to the first conductive structure 121. Optionally, a plurality of second electrodes 23 are connected into an integrated structure to simplify the manufacturing process. Optionally, a plurality of second electrodes 23 are connected into an integrated structure and the integrated structure is located in the display area A and the peripheral area B, and the orthographic projection of a plurality of first vias 51 on the first surface 11a is located within the orthographic projection of the integrated structure on the first surface 11a.

[0055] Optionally, a plurality of light-emitting units 200 include a plurality of first light-emitting units, a plurality of second light-emitting units, and a plurality of third light-emitting units. The colors of the light emitted by the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, realizing a color display function. For example, the color of the light emitted by the first light-emitting unit is green (G), the color of the light emitted by the second light-emitting unit is blue (B), and the color of the light emitted by the third light-emitting unit is red (R). The embodiments of the present disclosure do not limit the colors of the light emitted by the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit.

[0056] Exemplarily, the second electrode 23 can be made of a transparent conductive material, such as ITO (Indium tin oxide).

[0057] Exemplarily, the light-emitting layer 22 can include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), an electron blocking layer (EBL), and a light-emitting material layer. The colors of the light emitted by the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are determined by the light-emitting material layer.

[0058] Exemplarily, the first electrode layer 21 is made of a metal material such as a magnesium-silver alloy; or made of a transparent conductive material, such as ITO.

[0059] As Figure 2As shown, the light-emitting functional layer further includes a pixel definition layer 24. The pixel definition layer 24 includes a plurality of openings 240 distributed in an array. The plurality of light-emitting units 200 correspond to the plurality of openings 240 one by one, and at least a part of the light-emitting unit 200 is located in the corresponding opening 240. Here, at least a part of the light-emitting unit 200 being located in the corresponding opening 240 means that a part of the first electrode 21 of the light-emitting unit and the light-emitting layer 22 are located in the opening 240, another part of the first electrode 21 is located outside the opening 240 and on the side of the pixel definition layer 24 close to the substrate 11, and the second electrode 23 is not located in the opening 240, so as to facilitate the formation of an integral structure over the entire surface. In other possible embodiments, the second electrode 23 of the light-emitting unit 200 is entirely located in the opening 240, and the plurality of second electrodes 23 are electrically connected through, for example, strip-shaped connection electrodes to form a mesh-like integral structure.

[0060] Optionally, the orthographic projection of the opening 240 on the first surface 11a is located within the orthographic projection of the first electrode 21 of the corresponding light-emitting unit 200 on the first surface 11a.

[0061] Optionally, the shape of the orthographic projection of the opening 240 on the first surface 11a can be circular, or a figure approximately circular (such as an ellipse or other centrosymmetric figure), or can be square, etc., and the embodiments of the present disclosure do not limit this.

[0062] Exemplarily, the manufacturing material of the pixel definition layer 24 includes one or more of polyimide, polyphthalimide, polyamide, silicon oxide, silicon nitride, etc.

[0063] Exemplarily, as Figure 2 shown, the display panel further includes a packaging layer 40 for protecting the display panel. Optionally, the manufacturing material of the packaging layer 40 is silicon nitride, silicon oxide or silicon oxynitride material.

[0064] Optionally, the display panel further includes a color filter layer, and the color filter layer is located on the side of the packaging layer away from the substrate 11. The color filter layer includes a plurality of color resist blocks distributed in an array.

[0065] Optionally, the display panel further includes a touch layer, a touch insulation layer and a touch protection layer sequentially stacked on the first surface 11a, and the touch layer is located on the side of the color filter layer away from the substrate 11. Among them, the touch layer can be a self-capacitive touch structure or a mutual-capacitive touch structure, and the present disclosure does not limit this. Optionally, the manufacturing material of the touch layer is one or more of metal materials such as copper and aluminum. The manufacturing material of the touch insulation layer can be silicon oxide, silicon nitride or silicon oxynitride. The manufacturing material of the touch protection layer is a thermally curable or photocurable organic material such as acrylate and epoxy resin. Optionally, the touch layer can also be located on the side of the color filter layer close to the substrate 11.

[0066] It should be noted that for a display panel without a touch function, there is no need to provide the foregoing touch layer, touch insulation layer, and touch protection layer.

[0067] Figure 4 is a schematic plan view of a light-emitting unit and a first conductive structure provided by an embodiment of the present disclosure. Combining Figure 2 and Figure 4 , the orthographic projection of each first signal line 1211 on the first surface 11a passes through the geometric center O1 of the orthographic projection of at least one opening 240 on the first surface 11a, and different first signal lines 1211 pass through different openings 240. The first signal line 1211 is arranged to pass through the geometric center O1 of the opening 240, so that the opening 240 is symmetric about the first signal line 1211, and the part of the first electrode 21 of the light-emitting unit 200 located in the opening 240 and in contact with the light-emitting layer 22 has good flat symmetry, thereby effectively improving color shift and enhancing the display effect.

[0068] In one embodiment, a first signal line 1211 is provided below each opening 240, and the orthographic projection of the first signal line 1211 on the first surface 11a passes through the geometric center O1 of the orthographic projection of the opening 240 on the first surface 11a.

[0069] In another embodiment, a first signal line 1211 is provided below a part of the openings 240. For example, Figure 4 as shown, the first direction x is the column direction of a plurality of openings 240, and the second direction y is the row direction of a plurality of openings 240. There is a case where a first signal line 1211 is provided below one column of openings 240, while no first signal line 1211 is provided below another column of openings 240, and the orthographic projection of the first signal line 1211 on the first surface 11a passes through the geometric center O1 of the orthographic projection of the opening 240 on the first surface 11a, and no first signal line 1211 is provided below another part of the openings 240. Optionally, there is one column of openings, or multiple columns of openings, between two adjacent first signal lines 1211.

[0070] The relationship between flat symmetry and improvement of color shift will be described below. When viewing the image displayed on the display panel, referring again to Figure 2, assume that the line connecting the first position C and the center of the display panel is perpendicular to the display panel, and taking this line as the reference line, the line connecting the second position D and the center of the display panel forms a first angle with the reference line, and the line connecting the third position E and the center of the display panel forms a second angle with the reference line. The first position C, the second position D, and the third position E are on a straight line and this straight line is parallel to the display panel. If the part of the first electrode 21 located within the opening 240 and in contact with the light-emitting layer 22 is symmetrically flat with respect to the geometric center O1 of the opening, then the colors seen by the human eye when viewing the display panel at the second position D and at the third position E are the same; if the part of the first electrode 21 located within the opening 240 and in contact with the light-emitting layer 22 is asymmetrically flat with respect to the geometric center O1 of the opening, then the colors seen by the human eye when viewing the display panel at the second position D and at the third position E are different, that is, there is a color shift. Therefore, if there is good flat symmetry within the opening 240, the color shift can be effectively improved, so that the colors seen by the human eye when viewing the display panel at the second position and the third position are the same, improving the display effect.

[0071] In a possible implementation manner, multiple first signal lines and multiple second signal lines are located in different layers, and the first signal lines and the second signal lines are electrically connected through vias.

[0072] Exemplarily, the driving circuit layer 12 includes a first source-drain layer 1201, a second source-drain layer 1202, and a third source-drain layer 1203 that are sequentially stacked on the first surface 11a. Multiple first signal lines 1211 are located in the third source-drain layer 1203, multiple second signal lines 1212 are located in the second source-drain layer 1202, and the first signal lines 1211 and the second signal lines 1212 are electrically connected through vias. By respectively arranging multiple first signal lines 1211 and multiple second signal lines 1212 in the third source-drain layer 1203 and the second source-drain layer 1202, a mesh-shaped first conductive structure 121 is formed. In other possible embodiments, it may also be that the first signal lines 1211 are located in the second source-drain layer 1202 and the second signal lines 1212 are located in the third source-drain layer 1203.

[0073] Figure 5 It is a schematic cross-sectional structure diagram of a driving circuit layer provided by an embodiment of the present disclosure. As Figure 5As shown, the driving circuit layer 12 includes a light-shielding layer 1204, a buffer layer 1205, a first active layer 1206, a first gate insulating layer 1207, a first gate layer 1208, a first insulating layer 1209, a second gate layer 1240, a second gate insulating layer 1241, a second active layer 1242, a third gate insulating layer 1243, a third gate layer 1244, an interlayer dielectric layer 1245, a first source-drain layer 1201, a passivation layer 1246, a second source-drain layer 1202, a first planarization layer 1247, a third source-drain layer 1203, and a second planarization layer 1248, which are sequentially stacked on the first surface 11a of the substrate 11.

[0074] Optionally, the first source-drain layer, the second source-drain layer 1202, and the third source-drain layer 1203 are single-layer metal layers made of, for example, molybdenum or aluminum; or they are formed by stacking multiple metal layers, such as a stacked molybdenum layer, aluminum layer, and molybdenum layer, or a stacked titanium layer, aluminum layer, and titanium layer, etc.

[0075] Exemplarily, the substrate 11 can be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, other transparent rigid substrates, or other transparent flexible substrates, which can be a single-layer or multi-layer structure. Taking the multi-layer structure as an example, the substrate 11 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer, which are sequentially stacked from bottom to top. The two protective layers are used to protect the PI layer and prevent damage to the PI layer during subsequent processes. A buffer layer is also covered on the second protective layer, which can block water oxygen and alkaline ions.

[0076] Exemplarily, the material for making the light-shielding layer 1204 can be a metal material, including but not limited to materials such as molybdenum, aluminum, titanium, and copper. The light-shielding layer 1204 can reduce the light received by the TFT and can also conduct electricity. The light-shielding layer 1204 can also be called a BSM (bottom shield metal) layer.

[0077] Exemplarily, the first active layer 1206 is made of low-temperature polycrystalline silicon material, and the second active layer 1242 is made of a metal oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide). The driving backplane including both the first active layer 1206 and the second active layer 1242 is also called an LTPO (Low Temperature Polycrystalline Oxide) driving backplane.

[0078] Exemplarily, the materials for fabricating the first gate insulating layer 1207, the first insulating layer 1209, the second gate insulating layer 1241, the third gate insulating layer 1243, the interlayer dielectric layer 1245, the second insulating layer, and the passivation layer 1246 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0079] Exemplarily, the materials for fabricating the first gate layer 1208, the second gate layer 1240, and the third gate layer 1244 are metal materials, such as one or more of molybdenum, copper, and aluminum.

[0080] Exemplarily, the first planarization layer 1247 and the second planarization layer 1248 are made of an organic insulating material, such as resin.

[0081] In other possible embodiments, the driving backplane may not be an LTPO driving backplane, but an LTPS (Low Temperature Poly-Silicon) driving backplane. For the LTPS backplane, the driving circuit layer may include a buffer layer 1205, a first gate layer 1208, a first gate insulating layer 1207, a first active layer 1206, a second gate insulating layer 1241, a second gate layer 1240, an interlayer dielectric layer 1245, a first source-drain layer 1201, a passivation layer 1246, a second source-drain layer 1202, and a first planarization layer 1248 that are sequentially stacked on the first surface 11a. Among them, the first active layer 1206 is made of a low-temperature poly-silicon material.

[0082] Optionally, when the driving backplane is an LTPS driving backplane, the first signal line 1211 is located in the second source-drain layer 1202, and the second signal line 1212 is located in the first source-drain layer 1201; or, the first signal line 1211 is located in the first source-drain layer 1201, and the second signal line 1212 is located in the second source-drain layer 1202.

[0083] Exemplarily, the driving circuit layer 12 further includes a plurality of pixel driving circuits. The plurality of pixel driving circuits are connected to the plurality of light-emitting units 200 in a one-to-one correspondence. Each pixel driving circuit includes at least two TFTs (Thin Film Transistors). According to the number of TFTs and the number of capacitors included in each pixel driving circuit, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Each pixel driving circuit is used to control the light-emitting unit 200 connected thereto to emit light.

[0084] Optionally, the driving circuit layer 12 further includes a second conductive structure 122. The second conductive structure 122 includes a plurality of third signal lines 1221 and a plurality of fourth signal lines 1222. The plurality of third signal lines 1221 extend along the first direction x, and the plurality of fourth signal lines 1222 extend along the second direction y. The plurality of third signal lines 1221 and the plurality of fourth signal lines 1222 are electrically connected. The second conductive structure 122 is at least located in the display area A, and the second conductive structure 122 is used to provide a positive power supply voltage (also referred to as a VDD signal) to a plurality of pixel driving circuits. The second conductive structure 122 is the above-mentioned power supply line. Since the second conductive structure 122 is in a mesh shape and can be relatively evenly distributed in the display area A, the signal difference of the positive power supply voltage received by different pixel driving circuits can be made smaller, which is beneficial to improving the display uniformity.

[0085] Figure 6 is a schematic diagram of the distribution of a plurality of openings in a pixel definition layer provided by an embodiment of the present disclosure. As Figure 6 shown, the plurality of openings 240 include a first opening 241, a second opening 242, and a third opening 243. At least a part of the first light-emitting unit is located in the first opening 241, at least a part of the second light-emitting unit is located in the second opening 242, and at least a part of the third light-emitting unit is located in the third opening 243. The light-emitting units located in the first opening 241, the second opening 242, and the third opening 243 are the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit respectively. Optionally, the colors of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are green (G), blue (B), and red (R) respectively. In order to more clearly show the distribution of the first opening 241, the second opening 242, and the third opening 243, the first opening 241 where the first light-emitting unit is located, the second opening 242 where the second light-emitting unit is located, and the third opening 243 where the third light-emitting unit is located are respectively represented by Figure 6 R, G, and B in.

[0086] Optionally, as Figure 6 shown, a pixel includes two first light-emitting units, one second light-emitting unit, and one third light-emitting unit, that is, one pixel corresponds to an opening group p. An opening group p includes two first openings 241, one second opening 242, and one third opening 243. The distribution of the plurality of opening groups p is as Figure 6 shown. The plurality of opening groups p are arranged in an array, the row direction is the second direction y, and the column direction is the first direction x. For two adjacent rows of opening groups p, the second row of opening groups p can be obtained by first translating the first row of opening groups p along the first direction x and then translating along the second direction y. In each opening group p, the connection lines of the geometric centers of the four openings 240 form a rhombus. The two first openings 241 are distributed along the first direction x, and one second opening 242 and one first opening 241 are distributed along the second direction y.

[0087] In other possible embodiments, an opening group p may also include a first opening 241, a second opening 242, and a third opening 243 arranged in one direction, that is, a pixel may also include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit arranged in one direction. The embodiments of the present disclosure do not limit the types and numbers of light-emitting units included in a pixel.

[0088] Exemplarily, as Figure 6 shown, among the multiple openings 240, the multiple first openings 241 are distributed in an array. The multiple first openings 241 are divided into multiple first opening groups 2410 arranged along the second direction y. Each first opening group 2410 includes multiple first openings 241 arranged at intervals along the first direction x. Combining Figure 4 and Figure 6 , the orthographic projections of the multiple first openings 241 in each first opening group 2410 on the first surface 11a partially coincide with the orthographic projections of a pair of third signal lines 1221 on the first surface 11a. The orthographic projections of the two third signal lines 1221 in a pair of third signal lines 1221 on the first surface 11a are symmetric about the first connection line L. The first connection line L is the connection line of the geometric center O1 of the orthographic projections of the multiple first openings 241 in the first opening group 2410 whose orthographic projections on the first surface 11a partially coincide with the orthographic projections of the pair of third signal lines 1221 on the first surface 11a. That is, there is a first opening group 2410. The connection line of the geometric center O1 of the orthographic projections of the multiple first openings 241 in this first opening group 2410 on the first surface 11a is L. There is a pair of third signal lines 1221 above this first opening group 2410. The orthographic projections of this pair of third signal lines 1221 on the first surface 11a are symmetric about the connection line L. This design facilitates improving the good flat symmetry of the part of the first electrode 21 in contact with the light-emitting layer 22 in the first light-emitting unit located above the third signal line 1221, thereby effectively improving color deviation and enhancing the display effect.

[0089] Exemplarily, referring again to Figure 4 , the distance a between the orthographic projection of the first opening 241 on the first surface 11a and the orthographic projection of the second signal line 1212 closest to the first opening 241 on the first surface 11a is greater than or equal to 3 μm. Since the size of the first electrode 21 is larger than the size of the first opening 241, that is, the orthographic projection of the first opening 241 on the first surface 11a is located within the orthographic projection of the first electrode 21 on the first surface 11a, therefore as Figure 4 shown, if the distance a between the first opening 241 and the second signal line 1212 is too small, it may cause the first electrode 21 ( Figure 4The area near the second signal line 1212 (not shown in the figure) is relatively uneven. Even if the first signal line 1211 is located outside the first opening 241, this unevenness will affect the part of the first electrode 21 located inside the first opening 241, thereby affecting the flat symmetry of the part of the first electrode 21 located inside the first opening 241, which is not conducive to improving color shift and affects the display effect.

[0090] Exemplarily, the insulating layer between the third source-drain layer 1203 and the anode layer has a third via 53, and the insulating layer between the second source-drain layer 1202 and the third source-drain layer 1203 has a fourth via 54. Referring again to Figure 4 , Figure 4 FIG. exemplarily shows the projection relationship between a first electrode 21 and the opening 240, and the projection relationships between the third via 53 and the fourth via 54 and the first electrode 21. The shown first electrode 21 is located above a third opening 243. Optionally, the first electrode 21 has a strip-shaped connecting portion for connecting to the TFT in the pixel driving circuit. This connecting portion can first be connected to the pattern in the third source-drain layer through the third via 53, and then be connected to the pattern in the second source-drain layer through the fourth via 54. Through the transfer of the patterns in the third source-drain layer and the second source-drain layer, the connection to the TFT in the pixel driving circuit is achieved. Therefore, the third signal line 1221 needs to be set as a broken line instead of a straight line to avoid the third via 53 and the fourth via 54.

[0091] Exemplarily, as Figure 6 shown, the plurality of second openings 242 are divided into a plurality of second opening groups 2420 arranged along the second direction y, and each second opening group 2420 includes a plurality of second openings 242 arranged at intervals along the first direction x.

[0092] Figure 7 FIG. is a schematic plan view of a third source-drain layer and a schematic plan view of a second source-drain layer provided by an embodiment of the present disclosure. As Figure 7As shown in part (b), the fourth signal line 1222 includes a main body 12221 and a plurality of protruding portions 12222. The main body 12221 extends along the second direction y, and one end of each of the plurality of protruding portions 12222 is connected to the main body 12221. The plurality of protruding portions 12222 extend along the first direction x. The plurality of protruding portions 12222 arranged along the second direction y are divided into a plurality of protruding portion groups 122220. Each protruding portion group 122220 includes two adjacent protruding portions 12222. The orthographic projection of the protruding portion group 122220 on the first surface 11a partially coincides with the orthographic projection of a second opening 242 on the first surface 11a. The orthographic projections of the two protruding portions 12222 within the protruding portion group 122220 on the first surface 11a are located on both sides of the geometric center O1 of the orthographic projection of the corresponding second opening 242 on the first surface 11a in the second direction y and are symmetric about the geometric center O1 of the orthographic projection of the corresponding second opening 242 on the first surface 11a.

[0093] Here, the protruding portion 12222 has the function of electrically connecting other structures in the display panel. In the related art, the protruding portion 12222 is relatively short. For example, the orthographic projection of the protruding portion 12222 on the first surface 11a is located in the upper half of the orthographic projection of the second opening 242 on the first surface 11a, which is not conducive to the symmetric flatness of the first electrode 21 of the light-emitting unit located within the second opening 242, resulting in a color shift problem in the display panel. In contrast, in the embodiments of the present disclosure, by extending the length of the protruding portion 12222, the symmetric flatness of the first electrode 21 of the light-emitting unit located within the second opening 242 is improved, the color shift problem is improved, and the display effect is enhanced.

[0094] Exemplarily, the insulating layer between the second source-drain layer 1202 and the third source-drain layer 1203 has a fifth via 55, and the insulating layer between the first source-drain layer 1201 and the second source-drain layer 1202 has a sixth via 56. Referring again to Figure 4 , Figure 4 exemplarily shows the projection positions of a third via 53 and a fourth via 54 in Figure 4 . The third signal line 1221 can be electrically connected to the protruding portion 12222 through the fifth via 55 first, and then the protruding portion 12222 is electrically connected to the pattern in the first source-drain layer 1201 through the sixth via 56. The pattern in the first source-drain layer 1201 is electrically connected to the source electrode of a thin-film transistor in the pixel driving circuit, thereby realizing the introduction of the positive power supply voltage on the third signal line 1221 into the pixel driving circuit.

[0095] Exemplarily, the first signal line 1211 and the second signal line 1212 are on different layers. As shown in part (a) of Figure 4 and Figure 7 , the third signal line 1221 and the first signal line 1211 are on the same layer. As shown in part (a) ofFigure 4 and Figure 7 As shown in part (b) of Figure 7 , the fourth signal line 1222 is on the same layer as the second signal line 1212. Since the third signal line 1221 and the first signal line 1211 extend in the same direction, and the fourth signal line 1222 and the second signal line 1212 extend in the same direction, the first signal line 1211 and the third signal line 1221 can be fabricated on the same layer, and the second signal line 1212 and the fourth signal line 1222 can be fabricated on the same layer, saving the process.

[0096] An exemplary description of the structure of the data line is given below. Referring again to Figure 4 , the driving circuit layer 12 includes a plurality of data lines 123 extending along the first direction x. The positive projections of the plurality of second openings 242 in each second opening group 2420 on the first surface 11a partially coincide with the positive projections of a pair of data lines 123 on the first surface 11a. The positive projections of the two data lines 123 in a pair of data lines 123 on the first surface 11a are located on both sides of the geometric center O1 of the positive projection of the second opening 242 in the corresponding second opening group 2420 on the first surface 11a in the second direction y and are symmetric about the geometric center O1 of the positive projection of the second opening 242 in the corresponding second opening group 2420 on the first surface 11a, thereby improving the symmetric flatness of the first electrode 21 of the light-emitting unit located in the second opening 242, improving the color shift problem, and enhancing the display effect.

[0097] Exemplarily, the plurality of data lines 123 are on the same layer as the third signal line 1221. Since the data lines 123 and the third signal line 1221 extend in the same direction, they can be fabricated on the same layer, saving the process. Exemplarily, the data lines 123, the third signal line 1221, and the first signal line 1211 are all located in the third source-drain layer.

[0098] Figure 8 is a schematic plan view of another display panel provided by an embodiment of the present disclosure. Compared with the embodiment shown in Figure 4 , as shown in Figure 8 , Figure 8 In the embodiment shown, the plurality of first signal lines 1211 and the plurality of second signal lines 1212 of the first conductive structure 121 are located on the same layer. Since the electrical signals transmitted by the first signal line and the second signal line are the same, they can be arranged on the same layer to save the process. Exemplarily, the plurality of first signal lines 1211 and the plurality of second signal lines 1212 are both located in the aforementioned second source-drain layer 1202.

[0099] Exemplarily, Figure 8The illustrated embodiments also include multiple data lines 123, and the extending direction of the data lines 123 is the first direction x. Since the extending direction of the data lines 123 intersects with the extending direction of the second signal line 1212, the data lines 123 and the second signal line 1212 are fabricated in different layers. Optionally, the data lines 123 are located in the aforementioned third source-drain layer 1203.

[0100] Exemplarily, Figure 8 In the illustrated second conductive structure 122, the extending direction of the third signal line 1221 is the same as that of the data lines 123. Therefore, the third signal line 1221 can be fabricated on the same layer as the data lines 123, for example, both are located in the aforementioned third source-drain layer 1203. At the same time, since the fourth signal line 1222 transmits the same electrical signal as the third signal line 1221 but needs to avoid the data lines 123, a part of the fourth signal line 1222 can be disposed in the aforementioned third source-drain layer 1203, that is, on a different layer from the first signal line 1211, and another part of the fourth signal line 1222 can be disposed in the aforementioned second source-drain layer, that is, on the same layer as the first signal line 1211.

[0101] Figure 9 is a schematic plan view of a third source-drain layer and a schematic plan view of a second source-drain layer provided by an embodiment of the present disclosure. As Figure 9 shown in parts (a) and (b) thereof, each fourth signal line 1222 includes a plurality of first parts 1222a and a plurality of second parts 1222b. The extending directions of the plurality of first parts 1222a and the plurality of second parts 1222b are the same and are alternately arranged in the second direction y for transmitting an electrical signal of a positive power supply voltage in the second direction y, but the first part 1222a and the second part 1222b are located in different layers.

[0102] As Figure 9 shown in part (b) thereof, the first signal line 1211 and the second signal line 1212 are on the same layer. Among the fourth signal lines 1222, the first part 1222a is on the same layer as the first signal line 1211. The third signal line 1221 is not on the same layer as the first signal line 1211. As Figure 9 shown in part (a) thereof, the third signal line 1221 is located on the side of the first signal line 1211 close to the light-emitting unit 20.

[0103] As Figure 9 shown in part (a) thereof, the second part 1222b of each fourth signal line 1222 is on the same layer as the third signal line 1221. As Figure 9 shown in part (b) thereof, the first part 1222a of each fourth signal line is on the same layer as the first signal line.

[0104] The first conductive structure 121 is disposed on the same layer, a part of the second conductive structure 122 is disposed on the same layer as the first conductive structure 121, and another part of the second conductive structure 122 is disposed on another layer, and a first conductive structure 121 having a mesh structure and a second conductive structure 122 having a mesh structure can also be formed. Among them, in the second conductive structure 122, a part 1222a of the fourth signal line 1222 is connected to a second part 1222b of the fourth signal line 1222 through a second via 52. The orthographic projection of the second via 52 on the first surface 11a is located within the overlapping portion of the orthographic projection of the first part 1222a on the first surface 11a and the orthographic projection of the second part 1222b on the first surface 11a.

[0105] Exemplarily, as Figure 8 and Figure 9 shown, the second conductive structure 122 further includes a plurality of connection portions 12211. The plurality of connection portions 12211 are divided into a plurality of connection portion groups 122110 arranged along the second direction. Each connection portion group 122110 includes a plurality of connection portions 12211 arranged at intervals along the first direction x. The plurality of connection portions 12211 in each connection portion group 122110 are respectively connected to two third signal lines 1221 in a pair of third signal lines 1221. The orthographic projection of the first opening 241 on the first surface 11a is located within the orthographic projection of a connection portion 12211 and a pair of third signal lines 1221 connected by the connection portion 12211 on the first surface 11a. By providing the connection portions 12211, the symmetric flatness of the first electrode 21 of the light-emitting unit located in the second opening 242 can be further improved, the color shift problem can be improved, and the display effect can be enhanced.

[0106] Optionally, the plurality of connection portions 12211 correspond to the plurality of first openings 241 one by one, that is, there is a connection portion 12211 below each first opening 241. Alternatively, there is a connection portion 12221 below a part of the first openings 241, and there is no connection portion 12221 below another part of the first openings 241.

[0107] Figure 10 is a schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. As Figure 10 shown, the method includes:

[0108] In step S1, a driving backplane is provided. The driving backplane includes a substrate and a driving circuit layer on a first surface of the substrate.

[0109] In step S2, a light-emitting functional layer is fabricated on the driving backplane. The light-emitting functional layer includes a plurality of light-emitting units arranged in an array.

[0110] Among them, the display panel includes a display area and a peripheral area. The peripheral area surrounds the display area. The driving circuit layer includes a first conductive structure. The first conductive structure includes a plurality of first signal lines and a plurality of second signal lines. The plurality of first signal lines extend in a first direction, and the plurality of second signal lines extend in a second direction. The first direction and the second direction intersect. The plurality of first signal lines and the plurality of second signal lines are electrically connected. The first conductive structure is at least located in the display area and the first conductive structure is used to provide a negative power supply voltage to a plurality of light-emitting units.

[0111] Next, taking Figure 4 the structure shown as an example, step S2 will be exemplarily described. Exemplarily, this step S2 may include:

[0112] The first step: Deposit a light-shielding metal layer on the substrate, and then obtain a photoresist structure through processes such as photoresist coating, exposure, and development. Use this photoresist structure as a mask to etch the light-shielding metal layer to obtain a light-shielding layer.

[0113] The second step: Form a buffer layer on the light-shielding pattern layer. For example, form a buffer layer on the light-shielding pattern layer by deposition. Then, form a first active layer on the buffer layer. For example, first deposit and form an initial first active layer on the buffer layer, and perform patterning on the initial first active layer to obtain the first active layer.

[0114] The third step: Sequentially form an initial first gate insulating layer and an initial first gate layer on the first active layer by, for example, deposition. The initial first gate insulating layer covers the first active layer. Perform patterning on the initial first gate layer to obtain the first gate layer.

[0115] The fourth step: Sequentially form an initial first insulating layer and an initial second gate layer on the first gate layer by, for example, deposition. Perform patterning on the initial second gate layer to obtain the second gate layer.

[0116] The fifth step: Sequentially form an initial second gate insulating layer and an initial second active layer on the second gate layer by, for example, deposition. Perform patterning on the initial second active layer to obtain the second active layer.

[0117] The sixth step: Sequentially form an initial third gate insulating layer and an initial third gate layer on the second active layer by, for example, deposition. The initial third gate insulating layer covers the second active layer. Perform patterning on the initial third gate layer to obtain the third gate layer.

[0118] Step 7: An initial interlayer dielectric layer is formed on the third gate layer, for example, by deposition. Through a series of processes such as photoresist coating, exposure, etching, and stripping, a plurality of vias exposing the light-shielding layer are formed, and at the same time, the first gate insulating layer is obtained from the initial first gate insulating layer; then, through a series of processes such as photoresist coating, exposure, etching, and stripping, a plurality of vias exposing the first active layer are formed, and at the same time, the first insulating layer is obtained from the initial first insulating layer, the second gate insulating layer is obtained from the initial second gate insulating layer, and the interlayer dielectric layer is obtained at the same time.

[0119] Step 8: In the vias exposing the light-shielding layer and the first active layer obtained by etching in Step 7, a first source / drain layer is formed by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping.

[0120] Step 9: An initial passivation layer is thus formed on the first source / drain layer, for example, by deposition. A second source / drain layer is formed on the initial passivation layer by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping, where the second source / drain layer includes a plurality of second signal lines and a plurality of fourth signal lines. An initial first planarization layer is thus formed on the second source / drain layer. Through a series of processes such as photoresist coating, exposure, etching, and stripping, a plurality of vias exposing the second active layer are formed, and at the same time, the third gate insulating layer is obtained from the initial third gate insulating layer, and the passivation layer is obtained from the initial passivation layer.

[0121] Step 10: In the vias exposing the second active layer obtained by etching in Step 9, a third source / drain layer is formed by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping, where the third source / drain layer includes a plurality of first signal lines and a plurality of third signal lines.

[0122] Step 11: A second planarization layer is formed on the third source / drain layer, for example, by deposition.

[0123] For the materials of each layer, refer to the foregoing embodiments and will not be elaborated here.

[0124] Optionally, the patterning process includes processes such as photoresist coating, exposure, development, etching, and stripping.

[0125] The embodiments of the present disclosure further provide a display device, which includes a power supply circuit and any one of the foregoing display panels, and the power supply circuit supplies power to the display panel.

[0126] Exemplarily, the display device further includes a control circuit board, and the control circuit board inputs a negative power supply voltage and a positive power supply voltage to the first conductive structure and the second conductive structure respectively through the FPC in the display panel.

[0127] Exemplarily, the display device provided by the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0128] The display device has the same effect as the foregoing display panel, which will not be elaborated herein.

[0129] The foregoing are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a peripheral area, the peripheral area surrounds the display area, and the display panel includes a stacked driving backplane (10) and a light-emitting functional layer (20); The driving backplane (10) includes a substrate (11) and a driving circuit layer (12) on a first surface (11a) of the substrate (11), and the light-emitting functional layer (20) includes a plurality of light-emitting units (200) distributed in an array; The driving circuit layer (12) includes a first conductive structure (121), the first conductive structure (121) includes a plurality of first signal lines (1211) and a plurality of second signal lines (1212), the plurality of first signal lines (1211) extend in a first direction, the plurality of second signal lines (1212) extend in a second direction, the first direction and the second direction intersect, the plurality of first signal lines (1211) and the plurality of second signal lines (1212) are electrically connected, the first conductive structure (121) is at least located in the display area and the first conductive structure (121) is configured to provide a negative power supply voltage to the plurality of light-emitting units (200).

2. The display panel according to claim 1, wherein The light-emitting functional layer (20) further includes a pixel definition layer (24), the pixel definition layer (24) includes a plurality of openings (240) distributed in an array, the plurality of light-emitting units (200) correspond to the plurality of openings (240) one by one, and at least a part of the light-emitting unit (200) is located in the corresponding opening (240); The orthogonal projection of each first signal line (1211) on the first surface (11a) passes through the geometric center of the orthogonal projection of at least one of the openings (240) on the first surface (11a), and the openings (240) passed by different first signal lines (1211) are different.

3. The display panel according to claim 2, characterized in that, The plurality of first signal lines (1211) and the plurality of second signal lines (1212) are located in different layers, and the first signal lines (1211) and the second signal lines (1212) are electrically connected through vias; or, The plurality of first signal lines (1211) and the plurality of second signal lines (1212) are located in the same layer.

4. The display panel according to claim 3, wherein The driving circuit layer (12) further includes a second conductive structure (122) and a plurality of pixel driving circuits, and the plurality of pixel driving circuits are connected to the plurality of light-emitting units (200) one by one; The second conductive structure (122) includes a plurality of third signal lines (1221) and a plurality of fourth signal lines (1222), the plurality of third signal lines (1221) extend in a first direction, the plurality of fourth signal lines (1222) extend in a second direction, the plurality of third signal lines (1221) and the plurality of fourth signal lines (1222) are electrically connected, the second conductive structure (122) is at least located in the display area and the second conductive structure (122) is configured to provide a positive power supply voltage to the plurality of pixel driving circuits.

5. The display panel according to claim 4, characterized in that, The plurality of openings (240) include a plurality of first openings (241) distributed in an array. The plurality of first openings (241) are divided into a plurality of first opening groups (2410) arranged along the second direction. Each first opening group (2410) includes a plurality of first openings (241) arranged at intervals along the first direction. The orthographic projections of the plurality of first openings (241) in each first opening group (2410) on the first surface (11a) partially overlap with the orthographic projections of a pair of the third signal lines (1221) on the first surface (11a). The orthographic projections of the two third signal lines (1221) in a pair of the third signal lines (1221) on the first surface (11a) are located on both sides of a first connection line and are symmetric about the first connection line. The first connection line is the connection line of the geometric centers of the orthographic projections of the plurality of first openings (241) in the first opening group (2410) whose orthographic projections on the first surface (11a) partially overlap with the orthographic projections of a pair of the third signal lines (1221) on the first surface (11a).

6. The display panel according to claim 5, wherein The distance between the orthographic projection of the first opening (241) on the first surface (11a) and the orthographic projection of the second signal line (1212) closest to the first opening (241) on the first surface (11a) is greater than or equal to 3 μm.

7. The display panel according to claim 5, wherein The second conductive structure (122) further includes a plurality of connection part groups (12211). The plurality of connection part groups (12211) are divided into a plurality of connection part groups (122110) arranged along the second direction. Each connection part group (122110) includes a plurality of connection part groups (12211) arranged at intervals along the first direction. The plurality of connection part groups (12211) in each connection part group (122110) are respectively connected to the two third signal lines (1221) in a pair of the third signal lines (1221). The orthographic projection of the first opening (241) on the first surface (11a) is located within the orthographic projection of a connection part group (12211) and the pair of third signal lines (1221) connected by the connection part group (12211) on the first surface (11a).

8. The display panel according to claim 7, wherein The plurality of openings (240) further include a plurality of second openings (242) distributed in an array. The plurality of second openings (242) are divided into a plurality of second opening groups (2420) arranged along the second direction. Each second opening group (2420) includes a plurality of second openings (242) arranged at intervals along the first direction. The fourth signal line (1222) includes a main body (12221) and a plurality of protruding parts (12222). The main body (12221) extends along the second direction. One end of the plurality of protruding parts (12222) is connected to the main body (12221). The plurality of protruding parts (12222) extend along the first direction. A plurality of protruding portions (12222) arranged in a second direction are divided into a plurality of groups of protruding portions (122220), each group of protruding portions (122220) includes two adjacent protruding portions (12222), and the orthographic projection of the group of protruding portions (122220) on the first surface (11a) partially coincides with the orthographic projection of one of the second openings (242) on the first surface (11a). The orthographic projections of the two protruding portions (12222) within the group of protruding portions (122220) on the first surface (11a) are located on both sides of the geometric center of the orthographic projection of the corresponding second opening (242) on the first surface (11a) in the second direction and are symmetric about the geometric center of the orthographic projection of the corresponding second opening (242) on the first surface (11a).

9. The display panel according to any one of claims 4 to 8, characterized in that, The first signal line (1211) and the second signal line (1212) are on different layers, the third signal line (1221) is on the same layer as the first signal line (1211), and the fourth signal line (1222) is on the same layer as the second signal line (1212); or, The first signal line (1211) and the second signal line (1212) are on the same layer, the third signal line (1221) is located on the side of the first signal line (1211) closer to the light-emitting unit (200). The plurality of fourth signal lines (1222) include a plurality of first portions and a plurality of second portions. The extending directions of the plurality of first portions and the plurality of second portions are the same and are alternately arranged in the second direction y. The first portion of each fourth signal line (1222) is on the same layer as the first signal line (1211), and the second portion of each fourth signal line (1222) is on the same layer as the third signal line (1221).

10. The display panel according to claim 8, characterized in that, The driving circuit layer (12) includes a plurality of data lines (123) extending in a first direction; The orthographic projections of the plurality of second openings (242) in each second opening group (2420) on the first surface (11a) partially coincide with the orthographic projections of a pair of data lines (123) on the first surface (11a); The orthographic projections of the two data lines (123) in a pair of data lines (123) on the first surface (11a) are located on both sides of the geometric center of the orthographic projection of the second opening (242) in the corresponding second opening group (2420) on the first surface (11a) in the second direction and are symmetric about the geometric center of the orthographic projection of the second opening (242) in the corresponding second opening group (2420) on the first surface (11a).

11. The display panel according to claim 10, characterized in that, The plurality of data lines (123) are on the same layer as the third signal line (1221).

12. The display panel according to any one of claims 1 to 2, claims 4 to 8, and claims 10 to 11, characterized in that, The light-emitting unit (200) includes a first electrode (21), a light-emitting layer (22), and a second electrode (23) that are sequentially stacked on the driving backplane (10). A plurality of the second electrodes (23) are connected into an integrated structure. The first conductive structure (121) is electrically connected to the plurality of second electrodes (23) through at least one first via (51), and the at least one first via (51) is located in the peripheral area.

13. The display panel according to any one of claims 1 to 2, claims 4 to 8, and claims 10 to 11, characterized in that, The plurality of light-emitting units (200) includes a plurality of first light-emitting units, a plurality of second light-emitting units, and a plurality of third light-emitting units, and the lights emitted by the first light-emitting units, the second light-emitting units, and the third light-emitting units have different colors.

14. A method for manufacturing a display panel, characterized in that, The method includes: providing a driving backplane, the driving backplane including a substrate and a driving circuit layer on a first surface of the substrate; fabricating a light-emitting functional layer on the driving backplane, the light-emitting functional layer including a plurality of light-emitting units distributed in an array; Wherein, the display panel includes a display area and a peripheral area, the peripheral area surrounds the display area, the driving circuit layer includes a first conductive structure, the first conductive structure includes a plurality of first signal lines and a plurality of second signal lines, the plurality of first signal lines extend in a first direction, the plurality of second signal lines extend in a second direction, the first direction and the second direction intersect, the plurality of first signal lines and the plurality of second signal lines are electrically connected, and the first conductive structure is at least located in the display area and the first conductive structure is configured to provide a negative power supply voltage to the plurality of light-emitting units.

15. A display device, characterized in that, The display device includes a power supply circuit and the display panel according to any one of claims 1 to 13, and the power supply circuit supplies power to the display panel.

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