Image display algorithm and image display processing device

Abstract

The invention provides an image display algorithm and an image display processing device, and the algorithm comprises the steps: carrying out the rotation of a to-be-displayed image after partitioning, and obtaining a rotated image; correcting the rotated image to obtain a corrected image; and performing Demura compensation on the corrected image to obtain a target display image. According to the invention, small-angle image rotation and compensation under various precisions are realized by using fewer logic gates in an assembly line mode, real-time processing of high-speed and large-throughput data volume can be carried out, and the final display effect of the whole micro light-emitting diode chip is ensured.

Description

Technical Field

[0001] The present invention relates to the field of image display, and more particularly, to an image display algorithm and an image display processing device. Background Art

[0002] During the manufacturing process of the optical engine (hereinafter referred to as the optical engine) for color combination of the three-color panels in color display, a certain degree of misalignment will inevitably occur. Taking the color map displayed by the waveguide as an example, it can be clearly observed that there is misalignment between the red and blue pixels. In order to reduce this phenomenon, it is usually necessary to perform a small-angle rotation process on the image.

[0003] Traditional image rotation generally uses the cordic algorithm, which requires a certain amount of multiplication operations during implementation. This leads to problems of high implementation complexity and a large number of logic gates occupied when implemented in a circuit.

[0004] In summary, there is an urgent need to provide a new image display algorithm and an image display processing device to effectively simplify the implementation complexity of the circuit. Summary of the Invention

[0005] In view of some or all of the problems in the prior art, the task of the present invention is to provide an image display algorithm, including

[0006] Rotating the to-be-displayed image after being segmented to obtain a rotated image;

[0007] Correcting the rotated image to obtain a corrected image;

[0008] Performing Demura compensation on the corrected image to obtain a target display image.

[0009] In some embodiments, before rotating the to-be-displayed image after being segmented to obtain a rotated image, it further includes: segmenting the to-be-displayed image according to the parameters of the to-be-displayed image; wherein, the parameters of the to-be-displayed image include the resolution of the to-be-displayed image and a preset rotation angle.

[0010] In some embodiments, rotating the to-be-displayed image after being segmented includes: rotating the to-be-displayed image after being segmented according to a preset rotation angle.

[0011] In some embodiments, the preset rotation angle includes a clockwise preset rotation angle and / or a counterclockwise preset rotation angle.

[0012] In some embodiments, rotating the to-be-displayed image after being segmented according to a preset angle to obtain a rotated image includes:

[0013] Determine the pixel offset value of each pixel in the rotated image in response to each pixel coordinate and the preset rotation angle in the to-be-displayed image after chunking;

[0014] Determine the mapping coordinates of each pixel in the rotated image according to each pixel offset value, each pixel coordinate in the to-be-displayed image after chunking, and the overall offset value of the to-be-displayed image after chunking, so as to form the rotated image.

[0015] In some embodiments, the step of rotating the to-be-displayed image after chunking by a preset angle to obtain a rotated image further includes:

[0016] Blank pixel points generated during the rotation of the to-be-displayed image after chunking by a preset angle;

[0017] Determine a plurality of neighborhood coordinates of the blank pixel point coordinates in response to the blank pixel point coordinates;

[0018] Determine the pixel value of the blank pixel point according to the pixel mean value of the plurality of neighborhood coordinates, so as to form the mapping coordinates and corresponding pixel values of the pixels in the rotated image.

[0019] In some embodiments, the step of correcting the rotated image to obtain a corrected image includes:

[0020] Determine the pixel value of each pixel mapping coordinate in the corrected image according to the pixel value of each pixel mapping coordinate and a preset correction look-up table, so as to form the corrected image;

[0021] Wherein, the pixel value of the pixel mapping coordinate in the preset correction look-up table corresponds to the pixel value of the pixel mapping coordinate in the corrected image.

[0022] In some embodiments, the pixel value of the pixel mapping coordinate is calculated according to a preset correction formula to obtain the pixel value of the pixel mapping coordinate in the corrected image, thereby forming the preset correction look-up table.

[0023] In some embodiments, the preset correction formula is O = C * I γ , where O represents the output image, C represents a constant, I represents the input image, and γ represents the gamma value.

[0024] In some embodiments, the step of performing Demura compensation on the corrected image to obtain a target display image includes

[0025] The step of performing Demura compensation on the corrected image to obtain a target display image includes

[0026] Determine the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and the preset data remapping coefficient;

[0027] Determine the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, the compensation coefficient, and the pixel correction coefficient precision type, so as to form the target display image.

[0028] In some embodiments, the pixel correction coefficient precision type includes single-pixel correction coefficient precision and multi-pixel correction coefficient precision.

[0029] Another task of the present invention is to provide an image display processing device for executing the image display algorithm, including

[0030] A rotation unit for rotating the to-be-displayed image after block division to obtain a rotated image;

[0031] A correction unit for correcting the rotated image to obtain a corrected image;

[0032] A compensation unit for performing Demura compensation on the corrected image to obtain a target display image.

[0033] In some embodiments, the image display processing device further includes:

[0034] It further includes a remapping module that determines the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and the preset data remapping coefficient; the remapping module includes a first multiplier, a first shift register, a second multiplier, a first adder, and a random access memory,

[0035] Wherein, the output end of the second multiplier is connected to an input end of the first adder; the output end of the first adder is connected to the input end of the random access memory;

[0036] The output end of the first multiplier is connected to the input end of the first shift register.

[0037] In some embodiments, the random access memory uses a display look-up table.

[0038] In some embodiments, the image display processing device further includes a Demura compensation module that determines the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, the compensation coefficient, and the pixel correction coefficient precision type, so as to form the target display image; the Demura compensation module includes a third multiplier and a second shift register;

[0039] The input terminals of the third multiplier are respectively connected to the output terminal of the random access memory and the output terminal of the first shift register;

[0040] The output terminal of the third multiplier is connected to the input terminal of the second shift register.

[0041] The technical solution provided by the present invention has the following beneficial effects:

[0042] 1. The present invention innovatively proposes a method for rotating small-angle images based on image block look-up table mapping. This method significantly simplifies the implementation complexity. In the ASIC (Application Specific Integrated Circuit) environment, only a small number of logic gates are required to achieve the same function as the traditional method. At the same time, the pipeline processing method is adopted to meet the real-time processing requirements of high-frame-rate image data streams.

[0043] 2. The present invention uses the Demura algorithm to correct the pixels of the display panel by storing calibration parameters in the SRAM (Static Random Access Memory) inside the display panel. The present invention not only supports multi-precision calibration at the pixel level of a single display panel, but also can achieve high-precision coefficient calibration under the condition of poor uniformity. With less logic gate occupancy, it meets the calibration requirements in various scenarios and also takes into account the processing requirements of high-frame-rate real-time image data streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described below in conjunction with the specific embodiments with reference to the drawings.

[0045] Figure 1 A schematic flowchart of an image display algorithm according to an embodiment of the present invention is shown;

[0046] Figure 2 A schematic flowchart of an image display algorithm according to an embodiment of the present invention is shown;

[0047] Figure 3 Shown Figure 1 A flowchart of another embodiment of the circuit verification method shown;

[0048] Figure 4 Shown Figure 1 A flowchart of another embodiment of the circuit verification method shown;

[0049] Figure 5 Shown Figure 1 A flowchart of another embodiment of the circuit verification method shown;

[0050] Figure 6 A schematic diagram of small-angle image rotation according to an embodiment of the present invention is shown;

[0051] Figure 7Schematic diagram showing small-angle image rotation according to another embodiment of the present invention;

[0052] Figure 8 Schematic diagram showing the positions of 4 neighboring pixels according to an embodiment of the present invention;

[0053] Figure 9 Show Figure 1 Flowchart of another embodiment of the circuit verification method shown;

[0054] Figure 10 Schematic diagram showing the calibration process according to an embodiment of the present invention;

[0055] Figure 11 Show Figure 1 Flowchart of another embodiment of the circuit verification method shown;

[0056] Figure 12 Block diagram showing a Demura unit according to an embodiment of the present invention;

[0057] Figure 13 Circuit schematic diagram showing a Demura unit according to an embodiment of the present invention;

[0058] Figure 14 Schematic diagram showing the storage of single-pixel calibration coefficients according to an embodiment of the present invention;

[0059] Figure 15 Schematic diagram showing the storage of multi-pixel calibration coefficients according to an embodiment of the present invention;

[0060] Figure 16 Schematic block diagram showing an image display processing device according to an embodiment of the present invention;

[0061] Figure 17 Schematic block diagram showing an image display processing device according to an embodiment of the present invention;

[0062] Figure 18 Show Figure 16 Flowchart of another embodiment of the image display processing device shown;

[0063] Figure 19 Show Figure 16 Flowchart of another embodiment of the image display processing device shown;

[0064] Figure 20 Cross-sectional schematic diagram showing a micro light-emitting diode structure according to an embodiment of the present invention;

[0065] Figure 21 Cross-sectional schematic diagram showing a micro light-emitting diode structure according to another embodiment of the present invention. Detailed implementation manners

[0066] It should be noted that the components in the respective drawings may be exaggerated for illustrative purposes and not necessarily to scale correctly. In the respective drawings, the same or functionally identical components are provided with the same reference numerals.

[0067] In the present invention, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the presence of an intermediate between the two. In addition, "arranged on or above" only represents the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0068] In the present invention, the respective embodiments are merely intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0069] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0070] In the present invention, the term "connected" can refer to both direct connection between the two and indirect connection between the two through an intermediate element.

[0071] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teaching of the present invention.

[0072] It should also be noted here that in some embodiments, for the sake of clarity and simplicity, only a part of the components or assemblies may be shown, but those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario needs. Additionally, unless otherwise stated, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or the scope of recording of this application.

[0073] It should also be noted here that within the scope of the present invention, the terms "same", "equal", "equals", etc. do not mean that the two values are absolutely equal, but allow for a certain reasonable error, that is to say, the terms also cover "substantially the same", "substantially equal", "substantially equals". By analogy, in the present invention, the terms indicating direction such as "perpendicular to", "parallel to", etc. also cover the meanings of "substantially perpendicular to", "substantially parallel to".

[0074] The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention.

[0075] The present invention provides an image display algorithm and an image display processing device. By means of image block look-up table and offset calculation, a small-angle image rotation algorithm is realized, effectively solving the problem of misalignment of RGB pixels in the optical engine. In addition, on the basis of single-pixel demura correction at the single display panel level, for the case of poor uniformity, multi-pixel high-precision correction is introduced, and the application requirements in various scenarios are met with fewer logic gate resources.

[0076] In some embodiments, Figure 1 The flowchart of an image display algorithm 100 according to an embodiment of the present invention is shown. The image display algorithm of the present invention realizes a small-angle image rotation algorithm in the way of image block look-up table (rotation) and offset calculation (rotation), and solves the problem of misalignment of RGB pixels in the optical engine. At the same time, on the basis of single-pixel demura correction at the single Panel level, multi-pixel high-precision correction in the case of poor uniformity is introduced, and the usage requirements in various scenarios are realized with fewer logic gates.

[0077] As Figure 1 shown, the image display algorithm

[0078] In step 110, the to-be-displayed image after being divided into blocks is rotated to obtain the rotated image.

[0079] Figure 2 The flowchart of an image display algorithm 200 according to an embodiment of the present invention is shown. Figure 2 The difference between the shown image display algorithm 200 and Figure 1 is that the image display algorithm 200 further includes step 140. After receiving the to-be-displayed image, according to the parameters of the to-be-displayed image, the to-be-displayed image is divided into blocks, where the parameters of the to-be-displayed image may include the resolution and the preset rotation angle of the to-be-displayed image.

[0080] Figure 3 Shown Figure 1Flowchart of a more detailed embodiment of the circuit verification method 100 shown. In some embodiments, in step 110, the to-be-displayed image after being segmented is rotated to obtain the rotated image, which includes: in step 1101, the to-be-displayed image after being segmented is rotated according to a preset rotation angle, and the preset rotation angle includes a clockwise preset rotation angle and / or a counterclockwise preset rotation angle. In the manufacturing process of the optical engine, it is difficult to avoid physical deviations in the panel. Such deviations will cause misalignment problems in the optical engine. Taking the waveguide display color map as a typical example, it can be significantly observed that there is a misalignment between red and blue pixels. To effectively alleviate this phenomenon, it is usually necessary to perform a small-angle rotation operation on the image. Adding the rotation function aims to specifically solve the physical deviations in the panel during the optical engine manufacturing process. The rotation direction can be determined to be clockwise or counterclockwise according to the actual manufacturing deviation of the optical engine, and since the rotation angle is extremely small, it only causes an offset of 1 to 2 pixels in the physical sense.

[0081] In some embodiments, the to-be-displayed image can be one image or multiple images, and the content of the to-be-displayed image can be selected according to actual needs and is not limited herein.

[0082] In the above embodiments, when there are multiple to-be-displayed images, when the first to-be-displayed image completes step 110 and enters step 120, step 110 can process the next to-be-displayed image.

[0083] Figure 6 Schematic diagram showing small-angle image segmentation and rotation according to an embodiment of the present invention. As Figure 6 shown, the to-be-displayed image 200 is divided into 9 blocks 201-209. Each block is offset by a certain number of pixels in the up-down or left-right direction according to the rotation angle. The rotated image of each block is the image 300 on the right. At this time, the image 300 has completed a full rotation. During the image rotation process, some blank pixel points will be generated, as shown by the rectangular blocks 301 to 304 in the image 300. When the video data stream passes through the pixels in the neighborhood of these blank pixel points, the pixel values at the current position will be recorded and saved, and then the blank pixel values are generated by linear interpolation. For example, the mean value of the four neighboring pixel points can be taken as the value of the blank pixel point. Figure 6 The rotation shown is the case of clockwise rotation by one pixel, generating four blank pixels 301 to 304, and the corresponding number of interpolation points is 4. In other embodiments of the present invention, the image rotation can be counterclockwise rotation by 1 pixel, clockwise rotation by 2 pixels, counterclockwise rotation by 2 pixels, clockwise rotation by N pixels, or counterclockwise rotation by N pixels, where N is an integer greater than or equal to 2.

[0084] Figure 7Schematic diagram showing small - angle image block division and rotation according to another embodiment of the present invention. Figure 7 The rotation shown is a clockwise rotation by one pixel, resulting in 24 blank pixels, and the corresponding number of interpolation points is 24.

[0085] In some embodiments, when the resolution of the input image of the micro - light - emitting diode is 380 * 500, in a specific rotation mode, for example, clockwise rotation by 1 pixel, counter - clockwise rotation by 1 pixel, clockwise rotation by 2 pixels, or counter - clockwise rotation by 2 pixels, the separation coordinates between blocks are fixed values. The coordinates of the interpolation points are also fixed values. Taking the rotation by 1 pixel as an example, the horizontal separation coordinates of the input image are X1, X2, X3, X4, and the vertical separation coordinates are Y1, Y2, Y3, Y4. The coordinates of the interpolation points when rotating clockwise by 1 pixel are (A11, B11), (A22, B22), (A33, B33), (A44, B44), and the coordinates of the interpolation points when rotating counter - clockwise by 1 pixel are (C11, D11), (C22, D22), (C33, D33), (C44, D44).

[0086] In some embodiments, the block division is determined according to the rotation angle and image size in the algorithm. Under different parameters (rotation angle, image width and height), the whole image will be divided into different numbers of blocks. By dividing the image into blocks and translating each block image as a whole, the calculation required by the original complex rotation algorithm is avoided, and the hardware operation resource overhead is reduced.

[0087] Figure 4 Shows Figure 1 Flowchart of a more detailed embodiment of the circuit verification method 100 shown. In some embodiments, as Figure 4 shown, step 1101 further includes: step 1101 - 1, in response to each pixel coordinate and the preset rotation angle in the to - be - displayed image after block division, determining the coordinate offset value of each pixel in the rotated image; step 1101 - 2, according to the coordinate offset value of each pixel, each pixel coordinate in the to - be - displayed image after block division, and the overall offset value of the coordinates of the to - be - displayed image after block division, determining the mapping coordinates of each pixel in the rotated image, thereby forming the rotated image.

[0088] According to the X and Y coordinate addresses of the input image (denoted as the coordinate addresses of Xi and Yi), find the block it belongs to. The vertical nodes of the block are stored in the NR (node row) register, and its value range is 0, 1, 2. The horizontal nodes are stored in the NC (node col) register, and its value range is also 0, 1, 2. Next, calculate the horizontal and vertical offset pixel values after rotation according to the block where the input image coordinates are located. If it is rotated clockwise by 1 pixel, when NR is 0, 1, 2, the corresponding vertical pixel offsets are -1, 0, 1 pixels respectively. If it is rotated counterclockwise by 1 pixel, when NR is 0, 1, 2, the corresponding vertical pixel offsets are 1, 0, -1 pixels respectively. The corresponding offset pixel values are stored in the Y_SF_PIX register. Similarly, when rotated clockwise by 1 pixel, when NC is 0, 1, 2, the corresponding horizontal pixel offsets are -1, 0, 1 pixels respectively. If it is rotated counterclockwise by 1 pixel, when NC is 0, 1, 2, the corresponding horizontal pixel offsets are 1, 0, -1 pixels respectively. The corresponding offset pixel values are stored in the X_SF_PIX register. The coordinate Xi of the input pixel plus the horizontal offset X_SF_PIX after rotation and the horizontal offset X_OFFSET of the overall image is the horizontal coordinate of the pixel after the output calculation mapping, denoted as Xr; the coordinate Yi of the input pixel plus the vertical offset Y_SF_PIX after rotation and the horizontal offset Y_OFFSET of the overall image is the vertical coordinate of the pixel after the output calculation mapping, denoted as Yr, as shown in the following formula:

[0089] Xr = Xi + X_SF_PIX + X_OFFSET

[0090] Yr = Yi + Y_SF_PIX + Y_OFFSET

[0091] Among them, the value ranges of X_OFFSET and Y_OFFSET are different for different models of display panels. For example, they can be in the range of 0 - 20.

[0092] Figure 5 Show Figure 1 The flowchart of a more detailed embodiment of the circuit verification method 100 shown. In some embodiments, as Figure 5 shown, step 1101 further includes: step 1101-3, blank pixel points are generated during the rotation of the to-be-displayed image after being divided into blocks according to a preset angle; step 1101-4, in response to the coordinates of the blank pixel points, determine multiple neighborhood coordinates of the coordinates of the blank pixel points; step 1101-5, and determine the pixel value of the blank pixel points according to the pixel average value of the multiple neighborhood coordinates, so as to form the mapping coordinates and corresponding pixel values of the pixels in the rotated image.

[0093] When rotating a pixel clockwise, when the input pixel coordinates (xi and yi) match the 4 neighboring pixel coordinates of the following coordinates ((A11, B11), (A22, B22), (A33, B33), (A44, B44)) respectively, the pixel values are recorded in 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers; when rotating a pixel counterclockwise, when the input pixel coordinates match the 4 neighboring pixel coordinates of the following coordinates "(C11, D11), (C22, D22), (C33, D33), (C44, D44)" respectively, the pixel values are also recorded in 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers. Figure 8 The schematic diagram shows the positions of 4 neighboring pixels according to an embodiment of the present invention.

[0094] In some embodiments, data processing is performed in a pipelined manner. After rotation, the pixel coordinates and pixel data are continuously output to the next-level correction (Gamma) / compensation (Demura) module. At the end of the current frame, the pixel grayscale of the interpolation point is calculated by averaging the data in the 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers that have been recorded, and is output to the next-level module. The formula for calculating the pixel grayscale of the interpolation point is as follows: ipix_data_value = (ipix_node_t + ipix_node_b + ipix_node_l + ipix_node_r) / 4.

[0095] Return Figure 1 , at step 120, the rotated image is corrected to obtain the corrected image.

[0096] Figure 9 Show Figure 1 The flowchart of a more detailed embodiment of the circuit verification method 100 shown. In some embodiments, as Figure 9 shown, step 120 further includes: step 1201, determining the pixel value of each pixel mapping coordinate in the corrected image according to the pixel value of each pixel mapping coordinate and a preset correction look-up table, so as to form the corrected image, where the pixel value of the pixel mapping coordinate in the preset correction look-up table corresponds to the pixel value of the pixel mapping coordinate in the corrected image.

[0097] In some embodiments, the pixel value of the pixel mapping coordinate is calculated according to a preset correction formula to obtain the pixel value of the pixel mapping coordinate in the corrected image, forming a preset correction look-up table. The preset correction formula is O = C*I γ, where O represents the output image, C represents a constant, I represents the input image, and γ represents the gamma value. When the value of γ is less than 1, the dark details of the image can be enhanced; when the value of γ is greater than 1, the bright details of the image can be enhanced.

[0098] In some embodiments, the above image correction can be referred to as Gamma Correction, also known as gamma non-linearity or gamma encoding. It is a method for non-linearly editing the tone of an image and is used for non-linear operations or inverse operations on the luminance of light or the tristimulus values in a film or imaging system. Since the human eye's perception of the display screen brightness is not proportional to the physical power but is a power function relationship, and the exponent of the power function is the correction value (Gamma value), Gamma correction is required considering the proportion of the bright and dark parts of the Panel.

[0099] Figure 10 A schematic diagram showing the correction process according to an embodiment of the present invention. In some embodiments, multiple preset correction look-up tables can be stored to meet the usage requirements in different scenarios. For example, 8 preset correction look-up tables can be stored, and each correction look-up table has a correction value of 256 * 10 bits. The pixel data Dr output from the rotation module serves as the input address of the preset correction look-up table, and the corresponding 10-bit data is retrieved and denoted as Dg. The pixel data Dr includes the pixel data corresponding to the rotated pixel coordinates (Xr, Yr) and the pixel data corresponding to the interpolated pixels.

[0100] Return Figure 1 , in step 130, Demura compensation is performed on the corrected image to obtain the target display image.

[0101] Figure 11 Show Figure 1 A flowchart showing a more detailed embodiment of the circuit verification method 100 shown. In some embodiments, as Figure 11 shown, step 130 further includes: step 1301, determining the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and the preset data remapping coefficient; step 1302, determining the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, the compensation coefficient, and the pixel correction coefficient precision type, thereby forming the target display image.

[0102] Figure 12 A block diagram showing the Demura unit according to an embodiment of the present invention. Figure 13 A circuit schematic diagram showing the Demura unit according to an embodiment of the present invention. In the embodiment of the present invention, it can be through Figure 12 and Figure 13The Demura cells perform Demura compensation on the corrected image. As Figure 12 and Figure 13 shown, the Demura compensation module includes a remapping module 610 and a Demura compensation module 620. The remapping module 610 includes a first multiplier 701, a first shift register SFR0 702, a second multiplier 703, a first adder 704, and a random access memory 705. The Demura compensation module 620 includes a third multiplier 706 and a second shift register SFR1707. In some embodiments, the random access memory 705 may be a lookup table LUT (lookup table).

[0103] The mapped coordinate Xr, Yr addresses of each pixel in the rotated image are passed through the second multiplier 703 and the first adder 704 to calculate the byte address Ar. The calculation formula is:

[0104] Ar = Yr * Xmax + Xr

[0105] where Xr is the horizontal coordinate of the pixel in the rotated image, Yr is the vertical coordinate of the pixel in the rotated image, and Xmax is the maximum number of display pixels in the horizontal direction of the display panel.

[0106] Specifically, the second multiplier 703 multiplies the vertical coordinate Yr of the pixel in the rotated image by the maximum number of display pixels Xmax in the horizontal direction of the display panel, and the first adder 704 adds the product output by the second multiplier 703 to the horizontal coordinate Xr of the pixel in the rotated image to obtain the byte address Ar.

[0107] The corrected pixel data Dg is multiplied by the remapping coefficient Cr through the first multiplier 701 and stored in the first shift register SFR0 702, and then the shift register is shifted to the right. According to the required precision of the data to be retained, high-order data is obtained as the remapped data Dm. For example, the 10-bit corrected pixel data Dg is multiplied by the 11-bit remapping coefficient Cr through the first multiplier 701 and stored in the first shift register SFR0 702, and then the shift register is shifted to the right by 11 bits to obtain the high 10-bit data as the remapped data Dm. The calculation formula is:

[0108] SFR0 = Dg * Cr

[0109] Dm = SFR0 >> 11.

[0110] The remapped data Dm can dynamically adjust the overall brightness of the image and weaken the pixel grayscale in the highlighted area of the image.

[0111] The byte address Ar is input to the input terminal of the look-up table LUT 705, and the LUT 705 addresses to obtain the compensation (Demura) coefficient Cd. In some embodiments, the Demura coefficient Cd can be 8 bits or 16 bits.

[0112] The third multiplier 706 multiplies the remapped data Dm by the demura coefficient (Cd), and stores the product in the second shift register SFR1 707. Then, according to the input demura type, the calculation method is selected, the second shift register SFR1 707 is right-shifted by the demura fractional precision number of bits Fb, and the final result data is rounded to obtain the demura data Do, which is used as the target display image. The demura data Do can be 10 bits. The formula for this calculation is as follows:

[0113] SFR1 = Dm * Cd

[0114] D0 = SFR1 >> Fb.

[0115] In some embodiments, the demura pixel correction coefficient precision type can include single-pixel correction coefficient precision and multi-pixel correction coefficient precision. Figure 14 Shows a schematic diagram of the storage of single-pixel correction coefficients according to an embodiment of the present invention. As Figure 14 shown, each pixel corresponds to 1 8-bit correction coefficient, which can correspond to three precisions: 1. 3 bits of integer and 5 bits of decimal; 2. 2 bits of integer and 6 bits of decimal; 3. 1 bit of integer and 7 bits of decimal. The demura fractional precision number of bits Fb corresponding to the three precisions are 5 bits, 6 bits, and 7 bits respectively. Figure 15 Shows a schematic diagram of the storage of multi-pixel correction coefficients according to an embodiment of the present invention. As Figure 15 shown, every 2 pixels correspond to 1 16-bit correction coefficient, which can correspond to one precision: 4 bits of integer and 12 bits of decimal. The demura fractional precision number of bits Fb corresponding to the multi-pixel correction coefficient precision is 12 bits. Figure 16 Shows a schematic block diagram of the image display processing device 1000 according to an embodiment of the present invention. This image display processing device can be integrated on a micro light-emitting diode chip, with a power consumption of 8.75 uw, and the delay of the entire algorithm for processing data is only 7 clock cycles, meeting the requirements of real-time processing. For example, the image display processing device can be implemented by an application-specific integrated circuit.

[0116] As Figure 16As shown, the image display processing device includes a rotation unit 1010, a correction unit 1020, and a compensation unit 1030. The rotation unit 1010 is used to rotate the to-be-displayed image after block division to obtain a rotated image. The correction unit 1020 is used to correct the rotated image to obtain a corrected image. The compensation unit 1030 is used to perform Demura compensation on the corrected image to obtain a target display image.

[0117] The image display processing device proposed by the present invention realizes small-angle image rotation and Demura correction with multiple precisions in a pipelined manner with fewer logic gates on a micro light-emitting diode chip, can perform real-time processing of high-speed large-throughput data volume, and ensures the final display effect of the entire micro light-emitting diode chip.

[0118] Figure 17 The schematic block diagram of an image display processing device 2000 according to an embodiment of the present invention is shown. Figure 17 The shown image display processing device 2000 is different from Figure 16 in that: the image display processing device 2000 further includes a block division unit 1040, which is used to perform block division on the to-be-displayed image according to the parameters of the to-be-displayed image. The parameters of the to-be-displayed image include the resolution of the to-be-displayed image and a preset rotation angle.

[0119] The rotation unit 1010, the correction unit 1020, the compensation unit 1030, and the block division unit 1040 will be described in detail below in combination with specific embodiments.

[0120] In some embodiments, the rotation unit 1010 is used to rotate the to-be-displayed image after block division according to a preset rotation angle.

[0121] In some embodiments, the preset rotation angle includes a clockwise preset rotation angle and / or a counterclockwise preset rotation angle.

[0122] During the manufacturing process of the optical engine, it is difficult to avoid physical deviations in the panel. Such deviations will cause misalignment problems in the optical engine. Taking the waveguide display color map as a typical example, it can be significantly observed that there is a misalignment between red and blue pixels. To effectively alleviate this phenomenon, it is usually necessary to perform a small-angle rotation operation on the image. Adding a rotation function aims to specifically solve the physical deviations in the panel during the manufacturing process of the optical engine. The rotation direction can be determined to be clockwise or counterclockwise according to the actual manufacturing deviation of the optical engine, and since the rotation angle is extremely small, it only causes an offset of 1 to 2 pixels in the physical sense.

[0123] In some embodiments, refer to Figure 6 and Figure 7, the chunking unit 1040 divides the image 200 to be displayed into nine chunks 201-209. The rotation unit 1010 offsets each chunk by a certain number of pixels in the up-down or left-right direction according to the rotation angle. The rotated image of each chunk is the image 300 on the right. At this time, the image 300 has completed a full rotation. During the image rotation process, some blank pixel points will be generated, as shown by the rectangular blocks 301 to 304 in the image 300. When the video data stream passes through the pixels in the neighborhood of these blank pixel points, the pixel value at the current position will be recorded and saved, and then the blank pixel value is generated by linear interpolation. For example, the average value of the four neighboring pixel points can be taken as the value of the blank pixel point. Figure 6 The rotation shown is the case of clockwise rotation by one pixel, generating four blank pixels 301 to 304, and the number of corresponding interpolation points is 4. In other embodiments of the present invention, the image rotation can be counterclockwise rotation by 1 pixel, clockwise rotation by 2 pixels, counterclockwise rotation by 2 pixels, clockwise rotation by N pixels or counterclockwise rotation by N pixels, where N is an integer greater than or equal to 2. Figure 7 The rotation shown is the case of clockwise rotation by one pixel, generating 24 blank pixels, and the number of corresponding interpolation points is 24.

[0124] In some embodiments, when the resolution of the input image of the micro light-emitting diode is 380*500, in a specific rotation mode, for example, clockwise rotation by 1 pixel, counterclockwise rotation by 1 pixel, clockwise rotation by 2 pixels or counterclockwise rotation by 2 pixels, the separation coordinates between chunks are fixed values. The coordinates of the interpolation points are also fixed values. Taking the rotation by 1 pixel as an example, the horizontal separation coordinates of the input image are X1, X2, X3, X4, and the vertical separation coordinates are Y1, Y2, Y3, Y4. The coordinates of the interpolation points when rotating clockwise by 1 pixel are (A11, B11), (A22, B22), (A33, B33), (A44, B44), and the coordinates of the interpolation points when rotating counterclockwise by 1 pixel are (C11, D11), (C22, D22), (C33, D33), (C44, D44).

[0125] In some embodiments, chunking is determined according to the rotation angle and image size in the algorithm. Under different parameters (rotation angle, image width and height), the whole image will be divided into different numbers of blocks. By chunking and translating the whole block image, the calculation required by the original complex rotation algorithm is avoided, and the operation resource overhead of the hardware is reduced. Figure 18 Shown Figure 16 The flowchart of a more detailed embodiment of the image display processing device 1000 shown. In some embodiments, such as Figure 18As shown, the rotation unit 1010 includes: a first determination module 1011, configured to determine the offset value of each pixel in the rotated image in response to each pixel coordinate and a preset rotation angle in the to-be-displayed image after block division; a second determination module 1012, configured to determine the mapping coordinate of each pixel in the rotated image according to the offset value of each pixel, each pixel coordinate in the to-be-displayed image after block division, and the overall offset value of the to-be-displayed image after block division, so as to form the rotated image.

[0126] In some embodiments, the first determination module 1011 finds the block where it is located according to the X and Y coordinate addresses of the input image (denoted as the coordinate addresses of Xi and Yi). The longitudinal nodes of the block where it is located are stored in the NR (node row) register, and its value range is 0, 1, 2. The transverse nodes are stored in the NC (node col) register, and its value range is also 0, 1, 2. Next, the first determination module 1011 calculates the rotated horizontal and vertical offset pixel values according to the block where the input image coordinates are located. If it is rotated clockwise by 1 pixel, when NR is 0, 1, 2, the corresponding vertical pixel offsets are -1, 0, 1 pixel respectively. If it is rotated counterclockwise by 1 pixel, when NR is 0, 1, 2, the corresponding vertical pixel offsets are 1, 0, -1 pixel respectively. The corresponding offset pixel values are stored in the Y_SF_PIX register. Similarly, when rotated clockwise by 1 pixel, when NC is 0, 1, 2, the corresponding horizontal pixel offsets are -1, 0, 1 pixel respectively. If it is rotated counterclockwise by 1 pixel, when NC is 0, 1, 2, the corresponding horizontal pixel offsets are 1, 0, -1 pixel respectively. The corresponding offset pixel values are stored in the X_SF_PIX register. The second determination module 1012 adds the coordinate Xi of the input pixel to the rotated horizontal offset X_SF_PIX and the horizontal offset X_OFFSET of the whole image, and outputs the calculated mapped pixel horizontal coordinate, denoted as Xr; the second determination module 1012 adds the coordinate Yi of the input pixel to the rotated vertical offset Y_SF_PIX and the horizontal offset Y_OFFSET of the whole image, and outputs the calculated mapped pixel vertical coordinate, denoted as Yr, as shown in the following formula:

[0127] Xr = Xi + X_SF_PIX + X_OFFSET

[0128] Yr = Yi + Y_SF_PIX + Y_OFFSET

[0129] Where the value ranges of X_OFFSET and Y_OFFSET are different for different models of display panels. For example, they can be in the range of 0 - 20.

[0130] Figure 19 shown Figure 16The flowchart of a more detailed embodiment of the image display processing apparatus 1000 shown. In some embodiments, as Figure 19 shown, in some embodiments, the rotation unit 1010 further includes: a third determination module 1013, configured to, when blank pixel points are generated during rotation of the to-be-displayed image after block division according to a preset angle, determine a plurality of neighborhood coordinates of the blank pixel point coordinates in response to the blank pixel point coordinates; and a fourth determination module 1014, configured to determine the pixel value of the blank pixel point according to the pixel mean value of the plurality of neighborhood coordinates, so as to form the mapping coordinates and corresponding pixel values of the pixels in the rotated image.

[0131] When rotating one pixel clockwise, when the input pixel coordinates (xi and yi) match the 4 neighborhood pixel coordinates of the following coordinates ((A11, B11), (A22, B22), (A33, B33), (A44, B44)) respectively, the third determination module 1013 records the pixel value in 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers; when rotating one pixel counterclockwise, when the input pixel coordinates match the 4 neighborhood pixel coordinates of the following coordinates "(C11, D11), (C22, D22), (C33, D33), (C44, D44)" respectively, the third determination module 1013 also records the pixel value in 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers. Figure 8 The schematic diagram of the positions of 4 neighborhood pixels according to an embodiment of the present invention is shown.

[0132] In some embodiments, data processing is performed in a pipeline manner. After rotation, the pixel coordinates and pixel data are continuously output to the next-stage correction (Gamma) / compensation (Demura) module. At the end of the current frame, the fourth determination module 1014 calculates the pixel gray level of the interpolation point by averaging the data in the 4 groups of ipix_node_t, ipix_node_b, ipix_node_l, and ipix_node_r registers that have been recorded, and outputs it to the next-stage module. The calculation formula for the pixel gray level of the interpolation point is as follows:

[0133] ipix_data_value = (ipix_node_t + ipix_node_b + ipix_node_l + ipix_node_r) / 4.

[0134] In some embodiments, the correction unit 1020 determines the pixel value of each pixel mapping coordinate in the corrected image according to the pixel value of each pixel mapping coordinate and a preset correction look-up table, so as to form the corrected image; wherein, the pixel value of the pixel mapping coordinate in the preset correction look-up table corresponds to the pixel value of the pixel mapping coordinate in the corrected image.

[0135] In some embodiments, the pixel value of the pixel mapping coordinate is calculated according to a preset correction formula to obtain the pixel value of the pixel mapping coordinate in the corrected image, thereby forming a preset correction look-up table. The preset correction formula is O = C * I γ , where O represents the output image, C represents a constant, I represents the input image, and γ represents the gamma value. When the value of γ is less than 1, the dark details of the image can be enhanced; when the value of γ is greater than 1, the bright details of the image can be enhanced.

[0136] The specific correction process of the correction unit 1020 can be referred to Figure 10 , and for the sake of simplifying this specification, it will not be elaborated herein.

[0137] In some embodiments, the compensation unit 1030 is similar to the compensation unit shown in Figure 12 and Figure 13 above, and includes a remapping module 610 and a Demura compensation module 620. The remapping module 610 is configured to determine the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and a preset data remapping coefficient. The Demura compensation module 620 is configured to determine the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, a preset compensation coefficient, and the pixel correction coefficient accuracy type, so as to form the target display image. For the sake of simplifying this specification, the specific modules and circuits of the compensation unit will not be described repeatedly.

[0138] In an embodiment of the present invention, the micro light-emitting diode chip includes a micro light-emitting diode array. The micro light-emitting diode array may include a single-layer micro light-emitting diode structure formed in an array form, such as Figure 20 and 21 shown.

[0139] Figure 20 FIG. shows a cross-sectional schematic diagram of a micro light-emitting diode structure according to an embodiment of the present invention. As Figure 20 shown, the micro light-emitting diode structure includes a pixel driving backplane 110, a lower electrode layer 120, a conductive layer 130, a light-emitting mesa 140, an upper electrode layer 150, a passivation layer 160, and a microlens 170.

[0140] For convenience, "up" is used to indicate away from the pixel driving backplane 110, "down" indicates towards the pixel driving backplane 110, and other directional terms such as top, bottom, above, below, directly below, beneath, etc. are interpreted accordingly.

[0141] A micro light-emitting diode is a basic element that constitutes a micro light-emitting diode pixel. Each micro light-emitting diode pixel may include one or more micro light-emitting diode structures. A plurality of micro light-emitting diode pixels are arranged in an array to form a micro light-emitting diode display screen or a micro light-emitting diode chip. For example, each pixel in a color micro light-emitting diode chip may include a plurality of micro light-emitting diode structures of different colors, while each pixel in a monochromatic micro light-emitting diode chip may include only one color of micro light-emitting diode structure.

[0142] In an embodiment of the present invention, the size of each micro light-emitting diode chip does not exceed 1 centimeter, preferably does not exceed 20 micrometers. The micro light-emitting diode structures are formed in an array in the micro light-emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. In some embodiments, the pitch of the micro light-emitting diode array, that is, the minimum center-to-center distance between micro light-emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0143] In some embodiments, the pixel driving backplane 110 may employ an integrated circuit chip. The pixel driving backplane 110 includes a substrate, a driving circuit, and contact pads 111. Each micro light-emitting diode corresponds to a contact pad 111, and the contact pad 111 is electrically connected to the lower electrode layer 120. Each driving circuit is a pixel driver. In certain cases, the driving circuit is a thin-film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the pixel driving backplane 110 is a Si substrate. In another embodiment, the substrate of the pixel driving backplane 110 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. The pixel driving backplane 110 is used to control the lighting and extinguishing of the micro light-emitting diodes in each pixel. In one embodiment, the material of the contact pad 111 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0144] In some embodiments of the present invention, the pixel driving backplane can be electrically connected to each micro - light - emitting diode in the micro - light - emitting diode array through separate metal interconnections. In some embodiments, each micro - light - emitting diode can be individually electrically controlled by the pixel driving backplane. In some embodiments, the pixel driving backplane can be electrically connected to the electrodes of the micro - light - emitting diode chips through metal interconnections. In some embodiments, a dielectric layer can be formed in the gaps between the micro - light - emitting diodes. In some embodiments, the dielectric layer can also be formed in the gaps between the interconnections.

[0145] In one embodiment, the lower electrode layer 120 can be a metal - bonding composite layer. The light - emitting mesa 140 of the micro - light - emitting diode can be bonded to the surface of the pixel driving backplane 110 through the metal - bonding composite layer 120, and the bonding can be completed by means such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In one embodiment, the metal - bonding composite layer 120 can be disposed on the pixel driving backplane 110. In another embodiment, the metal - bonding composite layer 120 grows on the pixel driving backplane 110. In one embodiment, the thickness of the metal - bonding composite layer 120 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the metal - bonding composite layer 120 is 0.3 μm. In some embodiments, the material of the metal - bonding composite layer 120 is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The metal - bonding composite layer 120 can include an ohmic - contact layer and a metal - bonding layer. In some cases, the metal - bonding composite layer 120 includes two metal layers. One of the two metal layers is deposited on a layer above the metal - bonding layer in the LED. The corresponding bonding metal layer is deposited on the pixel driving backplane 110. For example, the metal - bonding composite layer 120 can be an Au - Au bond, an Au - Sn bond, an Au - In bond, a Ti - Ti bond, a Cu - Cu bond, or a combination of the above. For example, if an Au - Au bond is selected, each of the two Au layers requires a Cr layer as an adhesion layer and a Pt layer as an anti - diffusion layer. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located on the top and bottom of the two bonded Au layers. In some embodiments, when the thicknesses of the two Au layers are substantially the same, at high pressure and high temperature, the Au on the two layers diffuses into each other to bond the two layers together.

[0146] In some embodiments, the metal - bonding composite layer 120 can also be used as a reflector to reflect the light emitted from the light - emitting mesa 140 above.

[0147] In some embodiments, the conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 to form an electrical connection between the light-emitting mesa 140 and the metal bonding composite layer 120. In some embodiments, the conductive layer 130 may be a conductive transparent layer that is transparent to the light emitted by the light-emitting mesa 140 to improve conductivity and light transmittance. In some embodiments, the upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the upper electrode layer 150 is electrically connected to a current spreading structure or a top electrode (not shown).

[0148] In one embodiment, the conductive layer 130, the upper electrode layer 150, and their connection components may be one or more combinations of, such as, graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0149] The light-emitting mesa 140 includes a first-type epitaxial layer 141, a second-type epitaxial layer 143, and a light-emitting layer 142 therebetween. The first-type epitaxial layer 141 is electrically connected to the conductive layer 130. The second-type epitaxial layer 143 is electrically connected to the upper electrode layer 150. In some embodiments, the light-emitting mesa of each micro light-emitting diode in the micro light-emitting diode array can be a micron-level light-emitting mesa. In the three-layer structure, the first-type epitaxial layer 141 is closest to the driving backplane 110; the light-emitting layer 142 is located above the first-type epitaxial layer and is farther from the driving backplane 110; the second-type epitaxial layer 143 is located above the light-emitting layer 142 and is the farthest from the driving backplane 110. In some embodiments, the light-emitting layer 142 is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer 141 is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type epitaxial layer 141 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer 141 can include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer from top to bottom; in addition, an ohmic contact layer can be formed below the window layer. In some embodiments, the second-type epitaxial layer 143 is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer 143 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer 143 can include, but is not limited to, a confinement layer and a waveguide layer from top to bottom; in addition, in some embodiments, an ohmic contact layer can be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0150] In some embodiments, the first type of epitaxial layer 141 is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer 143 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer 143 can be a material layer of the second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first type of epitaxial layer 141 can be a material layer of the first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 142 includes a multi-quantum well layer and an electron blocking layer. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 142 further includes an electron blocking layer, and the electron blocking layer is disposed on the first side of the light-emitting layer. The first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer 141 can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer 143 is an N-type GaN layer or an N-type AlGaN layer.

[0151] In some embodiments, the light-emitting layer 142 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9, and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0152] In some embodiments, one of the first type of epitaxial layer 141 and the second type of epitaxial layer 143 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3 . The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times that of y. The thickness of the N-type spacer layer is from 50 nm to 75 nm, for example, 65 nm.

[0153] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is from 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is from 10 nm to 30 nm, for example, 20 nm.

[0154] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times that of y. In some embodiments, the thickness of the P-type spacer layer is from 50 nm to 70 nm, for example, 65 nm.

[0155] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, such as 30 nm.

[0156] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, such as x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, such as 20 nm.

[0157] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0158] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. Additionally, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0159] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0160] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first type epitaxial layer 141, and the electrode polarity of the upper electrode layer 150 is determined by the second type epitaxial layer 143. The electrode polarity of the conductive layer 130 is opposite to that of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 is an electrode with a polarity opposite to that of the conductive layer 130, such as an N electrode or a cathode electrode, and vice versa.

[0161] In one embodiment, the light-emitting mesa 140 may be a platform with a trapezoidal cross-section, and the bottom lateral dimension of the light-emitting mesa is greater than the top lateral dimension. There is an inclination angle between the sidewall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and the inclination angle is less than or equal to 90°. In one embodiment, the range of the inclination angle of the sidewall of the light-emitting mesa is: 45° to 90°. In one embodiment, the bottom lateral dimension of the light-emitting mesa exceeds 2 microns. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns. In one embodiment, the lateral dimension of the metal bonding composite layer is greater than the bottom lateral dimension of the light-emitting mesa.

[0162] In some embodiments, the light-emitting mesa 140 may emit red light, blue light, green light or light of any other color.

[0163] In some embodiments, the passivation layer 160 coats the sides of the metal bonding composite layer 120, the conductive layer 130, and the light-emitting mesa 140. In some embodiments of the present invention, the passivation layer 160 may also cover a part of the side of the upper electrode layer 150, and a part of the top surface of the upper electrode layer 150 is exposed to form an electrical connection with the top electrode. In other embodiments of the present invention, the passivation layer 160 does not cover the top surface and the side of the upper electrode layer 150, so that the upper electrode layers 150 of adjacent LED structures can be connected to each other to form a common cathode or anode. In some embodiments of the present invention, the passivation layer 160 coats the sides of the metal bonding composite layer 120, the conductive layer 130, the first-type epitaxial layer 141, the light-emitting layer 142, and a part of the side of the second-type epitaxial layer 143.

[0164] In one embodiment, the material of the passivation layer is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0165] In one embodiment, the insulating medium 180 fills the gap between the light-emitting mesas 140. The insulating medium 180 is transparent to the light emitted by the light-emitting mesas 140.

[0166] In some embodiments, the insulating dielectric 180 is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass, or any combination thereof. In some embodiments, the plastic material includes polymers such as SU-8, PermiNex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or an adhesive Micro Resist BCL-1200, or any combination thereof. In some embodiments, the insulating dielectric 180 can facilitate the light emitted from the LED structure to pass through.

[0167] In some embodiments, the microlens 170 is formed on top of the light-emitting mesa 140. The lateral dimension of the bottom of the microlens 170 can be greater than the lateral dimension of the micro light-emitting diode light-emitting region. In some embodiments, the lateral dimension of the bottom of the microlens 102 can be equal to the lateral dimension of the micro light-emitting diode light-emitting region.

[0168] In some embodiments, one microlens 170 can cover a plurality of lensless micro light-emitting diodes. A plurality of microlenses constitute a microlens array. The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used for converging and / or collimating light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the light-emitting mesa of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. In one embodiment, the typical shape of the bottom cross-section of each microlens includes a circle, a square, a rectangle, and a hexagon. The microlenses in the microlens array of the display panel can be the same or different in terms of shape, curvature, optical power, size, base, spacing, etc.

[0169] In some embodiments, the shape of the microlens 170 can be a curved hemispherical shape or a regular hemispherical shape. In some embodiments, the height of the microlens 170 is not greater than 2 microns. In some embodiments, the height of the microlens 170 is not greater than 1 micron. In some embodiments, the height of the microlens 170 is not greater than 0.5 micron. In some embodiments, the width of the microlens 170 is not greater than 4 microns. In some embodiments, the width of the microlens 170 is not greater than 3 microns. In some embodiments, the width of the microlens 170 is not greater than 2 microns. In some embodiments, the width of the microlens 170 is not greater than 1 micron. In some embodiments, the ratio of the width to the height of the microlens 170 is greater than 1.5.

[0170] In some embodiments, the microlens 170 can be made of various materials that are transparent to light of each wavelength emitted by the micro light-emitting diode. Exemplary transparent materials for the microlens 170 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 170 is made of a photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro light-emitting diode by chemical vapor deposition (CVD) technology.

[0171] Figure 21 A cross-sectional schematic diagram of a micro light-emitting diode structure according to another embodiment of the present invention is shown. As Figure 21 shown, the micro light-emitting diode structure includes a pixel driving backplane 210, a lower electrode layer 220, a conductive layer 230, a light-emitting mesa 240, an upper electrode layer 250, a passivation layer 260, a microlens 270, an insulating dielectric 280, and a reflective layer 290.

[0172] The light-emitting mesa 240 includes a first-type epitaxial layer 241, a second-type epitaxial layer 243, and a light-emitting layer 242 located therebetween. The first-type epitaxial layer 241 is electrically connected to the conductive layer 230. The second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250. Figure 21 The light-emitting mesa 240 shown is different from Figure 20 the light-emitting mesa 140 shown in that: the cross-sectional shape of the light-emitting mesa 240 is an inverted trapezoid. The lateral dimension at the bottom of the light-emitting mesa is smaller than the lateral dimension at the top. There is an inclined angle between the sidewall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and the inclined angle is greater than or equal to 90°. In one embodiment, the range of the inclined angle of the sidewall of the light-emitting mesa is: 90° to 135°.

[0173] In some embodiments, the passivation layer 260 coats the side surfaces of the conductive layer 230 and the light-emitting mesa 240. In some embodiments of the present invention, the tops of the second-type epitaxial layers 243 of adjacent light-emitting mesas 240 are connected to each other, and the passivation layer 260 covers the bottom surface of the connected portion of the second-type epitaxial layers 243. At least a portion of the bottom surface of the light-emitting mesa 240 is not covered by the passivation layer 260, and the conductive layer 230 is located on the bottom surface of the light-emitting mesa 240 and forms an electrical connection therewith. The material of the passivation layer 260 is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0174] In some embodiments, the reflective layer 290 is formed on the surfaces of the passivation layer 260 and the conductive layer 230 that are away from the light-emitting mesa 240.

[0175] In some embodiments, the reflective layer 290 may be a metal layer with a high reflectivity, which includes one or more metals, such as Pt, Rh, Al, Au, and Ag, a stacked DBR layer including a TiO2 / SiO2 layer, or any other layer with total reflection characteristics, including a multi-layer omnidirectional reflector (ODR), or a combination thereof.

[0176] In some embodiments, the reflective layer 290 may be one or more reflective coatings. The one or more reflective coatings can reflect the light emitted from the light-emitting region, thereby enhancing the brightness and light-emitting efficiency of the micro-LED panel or display. For example, the light emitted from the light-emitting region can reach the one or more reflective coatings and can be reflected upward by the one or more reflective coatings.

[0177] Since the reflective layer can be made of a conductive material, there is a gap 291 between the reflective layers of adjacent micro-mesa structures, thus avoiding short circuits between adjacent light-emitting mesas.

[0178] In one embodiment, the insulating medium 280 fills the gap between the light-emitting mesas 240. The insulating medium 280 is transparent to the light emitted by the light-emitting mesas 240. The material of the insulating medium 280 is similar to that of the insulating medium 180, and for the sake of simplicity of this specification, it will not be repeated here.

[0179] In some embodiments, the light-emitting mesa 240 of the micro light-emitting diode can be bonded to the surface of the pixel driving backplane 210 through a hybrid bonding process. For example, in the hybrid bonding process, an oxide bonding layer is deposited on the bottom of the light-emitting mesa structure; a corresponding oxide bonding layer is deposited on the substrate 110. Then, vias can be formed in the oxide bonding layer and filled with metal to form the lower electrode layer 220. A CMP process can be performed on the surface of the lower electrode layer 220 such that the surface of the lower electrode layer 220 is flush with the surface of the oxide bonding layer. Then, the light-emitting mesa 240 is bonded to the substrate 210 under high pressure and high temperature. In some embodiments, the lower electrode layer 220 is electrically connected between the contact 211 on the substrate 210 and the light-emitting mesa 240 above the lower electrode layer 220, acting as a P electrode.

[0180] In one embodiment, the upper electrode layer 250 is formed on the top surface of the light-emitting mesa 240, and the second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250. The material of the upper electrode layer 250 is similar to that of the upper electrode layer 150, and will not be repeated here for the sake of simplicity of this specification. In some embodiments, the microlens 270 is formed on the top of the light-emitting mesa 240. The material of the microlens 270 is similar to that of the microlens 170, and will not be repeated here for the sake of simplicity of this specification.

[0181] In the embodiments of the present invention, the micro light-emitting diodes introduced above or other similar micro light-emitting diodes constitute micro light-emitting diode pixels, and a plurality of micro light-emitting diode pixels are arranged in an array to form a micro light-emitting diode display chip.

[0182] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, variations, and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. An image display algorithm, characterized in that: It includes: Rotating the to-be-displayed image after block division to obtain a rotated image; Correcting the rotated image to obtain a corrected image; Performing Demura compensation on the corrected image to obtain a target display image.

2. The image display algorithm according to claim 1, characterized in that: Before rotating the to-be-displayed image after block division to obtain a rotated image, it further includes: According to the parameters of the to-be-displayed image, performing block division on the to-be-displayed image; Wherein, the parameters of the to-be-displayed image include the resolution and a preset rotation angle of the to-be-displayed image.

3. The image display algorithm according to claim 1, characterized in that: Rotating the to-be-displayed image after block division includes: Rotating the to-be-displayed image after block division according to a preset rotation angle.

4. The image display algorithm according to claim 3, characterized in that: The preset rotation angle includes a clockwise preset rotation angle and / or a counterclockwise preset rotation angle.

5. The image display algorithm according to claim 3, characterized in that: Rotating the to-be-displayed image after block division according to a preset angle to obtain a rotated image includes: Responding to each pixel coordinate and the preset rotation angle in the to-be-displayed image after block division, and determining the pixel offset value of each pixel in the rotated image; According to each pixel offset value, each pixel coordinate in the to-be-displayed image after block division, and the overall offset value of the to-be-displayed image after block division, determining the mapping coordinate of each pixel in the rotated image, thereby forming the rotated image.

6. The image display algorithm according to claim 5, characterized in that: Rotating the to-be-displayed image after block division according to a preset angle to obtain a rotated image further includes: Blank pixel points generated during the rotation of the to-be-displayed image after block division according to a preset angle; Responding to the blank pixel point coordinates, and determining multiple neighborhood coordinates of the blank pixel point coordinates; According to the pixel mean values of multiple neighborhood coordinates, determining the pixel value of the blank pixel point, thereby forming the mapping coordinates and corresponding pixel values of the pixels in the rotated image.

7. The image display algorithm according to claim 5, characterized in that: Correcting the rotated image to obtain a corrected image includes: According to the pixel value of each pixel mapping coordinate and a preset correction look-up table, determining the pixel value of each pixel mapping coordinate in the corrected image, thereby forming the corrected image; Wherein, the pixel value of the pixel mapping coordinate in the preset correction look-up table corresponds to the pixel value of the pixel mapping coordinate in the corrected image.

8. The image display algorithm according to claim 7, characterized in that: The pixel value of the pixel mapping coordinate is calculated according to a preset correction formula to obtain the pixel value of the pixel mapping coordinate in the corrected image, thereby forming the preset correction look-up table.

9. The image display algorithm according to claim 8, characterized in that: The preset correction formula is O = C * I γ , where O represents the output image, C represents a constant, I represents the input image, and γ represents the gamma value.

10. An image display algorithm according to claim 8, wherein: Performing Demura compensation on the corrected image to obtain a target display image, including Determining the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and a preset data remapping coefficient; Determining the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, a compensation coefficient, and a pixel correction coefficient accuracy type, thereby forming the target display image.

11. An image display algorithm according to claim 10, wherein: The pixel correction coefficient accuracy type includes a single-pixel correction coefficient accuracy and a multi-pixel correction coefficient accuracy.

12. An image display processing device executes the method according to claim 1, wherein It includes: A rotation unit that rotates the to-be-displayed image after being segmented to obtain a rotated image; A correction unit that corrects the rotated image to obtain a corrected image; A compensation unit that performs Demura compensation on the corrected image to obtain a target display image.

13. An image display processing device according to claim 12, wherein: The image display processing device uses an application-specific integrated circuit.

14. An image display processing device according to claim 12, wherein: It further includes a remapping module that determines the pixel value of each pixel remapping coordinate according to the pixel value of each pixel mapping coordinate in the corrected image and a preset data remapping coefficient; the remapping module includes a first multiplier, a first shift register, a second multiplier, a first adder, and a random access memory, wherein, the output end of the second multiplier is connected to an input end of the first adder; the output end of the first adder is connected to the input end of the random access memory; The output end of the first multiplier is connected to the input end of the first shift register.

15. An image display processing device according to claim 14, wherein: The random access memory uses a display look-up table.

16. An image display processing device according to claim 15, wherein: It further includes a Demura compensation module that determines the pixel value of each pixel coordinate in the target display image according to the pixel value of each pixel remapping coordinate, a compensation coefficient, and a pixel correction coefficient accuracy type, thereby forming the target display image; The Demura compensation module includes a third multiplier and a second shift register; The input ends of the third multiplier are respectively connected to the output end of the random access memory and the output end of the first shift register; The output end of the third multiplier is connected to the input end of the second shift register.

Images