Memory allocation method and device and storage medium

Abstract

The invention discloses a memory allocation method and device and a storage medium, and relates to the field of computers. Performing hierarchical division on the memory nodes based on access performance of the memory nodes, constructing an affinity group in combination with an access relationship between the computing nodes and the memory nodes, and incorporating local memory nodes and extended memory nodes into a memory allocation range; meanwhile, weight factors reflecting the relative access capability of the memory nodes are distributed to the memory nodes in the affinity group, so that the memory can be distributed in a weighted mode according to performance differences. The memory resource allocation does not simply depend on a physical topology and a local priority strategy, but comprehensively considers the bandwidth and delay difference of the heterogeneous memory, thereby avoiding the problems of excessive consumption of high-performance memory nodes and idle low-performance nodes; the problems of performance bottleneck and resource allocation imbalance caused by the fact that related technical strategies cannot deal with heterogeneous memory differences are solved, and the effects of balancing and efficiently utilizing the memory and improving the overall performance and resource utilization rate of the system are achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory allocation method, device, and storage medium. Background Art

[0002] In modern computer systems, multiple processor cores often need to share system memory resources. To improve memory access efficiency and system scalability, mainstream servers widely adopt the NUMA (Non-Uniform Memory Access) architecture. In this architecture, the system is divided into multiple memory nodes. Each memory node typically includes a set of processor cores, a shared cache, and directly connected local memory. Processors accessing local memory within their memory node experience lower latency and higher bandwidth, while accessing remote memory on other memory nodes incurs higher latency and lower bandwidth. This difference in access performance means that memory allocation strategies can significantly impact system performance.

[0003] With the development of heterogeneous memory technologies, such as PMem (Persistent Memory) and extended memory based on the CXL (Compute Express Link) protocol, they are gradually being introduced into modern systems. These new memory media are typically accessed through dedicated controllers and abstracted as independent memory nodes. Due to their significant differences in performance characteristics from related technology, DRAM (Dynamic Random-Access Memory), such as higher latency and lower bandwidth, the access performance differences between memory nodes in the system are further amplified, leading to more complex memory access behavior during program execution.

[0004] In this context, related technologies employ a local-first memory allocation strategy, prioritizing memory allocation to the local memory node of the processor where the process resides. This can easily lead to excessive resource consumption on high-performance nodes, while leaving low-performance nodes idle, resulting in an imbalance in overall resource allocation. Furthermore, related technical strategies often divide memory nodes based on physical topology, failing to fully identify and distinguish performance differences between memory media.

[0005] Therefore, in a heterogeneous memory architecture, there is an urgent need for an optimization strategy that can perceive the performance differences of different types of memory nodes and perform memory allocation to improve resource utilization and overall system performance. Summary of the Invention

[0006] The present application provides a memory allocation method, device and storage medium to at least solve the problem that the related technology cannot cope with the performance bottleneck and resource allocation imbalance caused by the differences in heterogeneous memory, thereby achieving the effect of balanced and efficient memory utilization and improving the overall performance and resource utilization of the system.

[0007] The present application provides a memory allocation method, which is applied to a computing system including multiple computing nodes and multiple memory nodes. The memory allocation method includes: determining the memory hierarchy of the memory node, wherein the memory hierarchy represents the access performance of the memory node; constructing an affinity group corresponding to the computing node based on the access relationship between the computing node and the memory node, wherein the affinity group includes the local memory node of the computing node and at least one extended memory node; assigning a weight factor to each memory node in the affinity group, wherein the weight factor represents the relative access capability of the memory node; and allocating memory resources within the affinity group according to the weight factor based on the affinity group corresponding to the computing node where the process currently applying for memory is located and the weight factor corresponding to each memory node in the affinity group.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned memory allocation methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned memory allocation methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory allocation methods when executed by a processor.

[0011] Through this application, memory nodes are divided into layers based on their access performance, and affinity groups are constructed based on the access relationship between computing nodes and memory nodes, so that local memory nodes and extended memory nodes are included in the memory allocation range; at the same time, each memory node in the affinity group is assigned a weight factor that reflects its relative access capability, so that memory allocation can be weighted according to performance differences. The memory resource allocation of this application no longer simply relies on physical topology and local priority strategies, but comprehensively considers the bandwidth and latency differences of heterogeneous memory, avoiding the problems of excessive consumption of high-performance memory nodes and idle low-performance nodes, and solving the problem that related technical strategies cannot cope with the performance bottlenecks and resource allocation imbalances caused by heterogeneous memory differences, achieving the effect of balanced and efficient use of memory and improving the overall performance and resource utilization of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A flowchart of a memory allocation method provided in an embodiment of the present application; Figure 2 An architectural diagram of a computing system provided in an embodiment of the present application; Figure 3 A flowchart of calculating a weight factor provided in an embodiment of the present application; Figure 4 An architectural diagram for allocating memory according to weight factors provided in an embodiment of the present application; Figure 5 A schematic diagram of an electronic device provided in an embodiment of the present application; Figure 6 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0015] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0016] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0017] like Figure 1 , an embodiment of the present application provides a memory allocation method, which is applied to a computing system including multiple computing nodes and multiple memory nodes, and the memory allocation method includes: S11: Determine the memory level of the memory node. The memory level represents the access performance of the memory node.

[0018] Specifically, this step is used to hierarchically identify each memory node in the system to reflect differences in access performance. Modern computing systems may contain multiple types of memory media, such as DRAM, PMem, and extended memory accessed via high-speed interconnect protocols like CXL. These memories exhibit significant differences in access latency, bandwidth, and capacity, necessitating a unified, abstract approach to categorize memory node performance into different levels.

[0019] This memory hierarchy doesn't rely on direct mapping to the physical topology. Instead, it categorizes memory nodes based on access performance, using characteristics like bandwidth and latency, and assigns them corresponding access performance levels. Each memory node is assigned a specific tier, representing its relative position in the system's access efficiency. This access performance tiering serves as the basis for subsequent resource scheduling and affinity analysis, supporting more precise resource matching and differentiated memory management.

[0020] S12: Construct an affinity group corresponding to the computing node according to the access relationship between the computing node and the memory node, where the affinity group includes the local memory node of the computing node and at least one extended memory node.

[0021] Specifically, this step constructs an affinity group corresponding to each compute node. This affinity group reflects the set of memory nodes that the compute node tends to access during actual operation. The construction principle is to comprehensively consider the access relationship between the compute node and different memory nodes, especially key performance indicators such as access latency and data transmission efficiency. Because the overhead of each compute node accessing local memory and remote memory in the NUMA architecture is significantly different, and the introduction of heterogeneous memory further expands this difference, relying solely on physical connection relationships or fixed strategies cannot achieve efficient memory resource management. By identifying the local memory nodes of the compute node during the system initialization phase and further selecting non-local memory nodes with better access paths to them from all memory nodes to form a more reasonable affinity group, the available memory resource space can be expanded while maintaining performance predictability.

[0022] like Figure 2, including two compute nodes, the first compute node and the second compute node. The first affinity group corresponding to the first compute node includes the first memory node (the first local memory node) and the third memory node (the first compute fast link node). Similarly, the second affinity group corresponding to the second compute node includes the second memory node (the second local memory node) and the fourth memory node (the second compute fast link node). The two local memory nodes are in the same memory hierarchy (e.g., the first hierarchy), and the two compute fast link nodes are in the same memory hierarchy (e.g., the second hierarchy). The compute fast link nodes are the extended memory nodes described above. As can be seen, each affinity group not only includes local memory nodes directly connected to the compute node with the lowest access overhead, but also includes other extended memory nodes (e.g., compute fast link nodes) with acceptable performance. This affinity group construction overcomes the limitations of related technologies that rely solely on local nodes for memory allocation, enabling a more optimal trade-off between performance and capacity in the use of memory resources. This strategy is particularly suitable for resource-intensive applications. While maintaining the lowest possible access latency, it improves the schedulability and utilization of overall memory capacity, laying the foundation for subsequent allocation strategies that incorporate weighting factors.

[0023] S13: Assign a weight factor to each memory node in the affinity group, where the weight factor represents the relative access capability of the memory node.

[0024] Specifically, this step assigns a suitable weight factor to each memory node in the affinity group corresponding to each computing node, in order to quantify the proportion of memory allocation that each memory node should bear in the overall resource scheduling. Since the memory nodes in the affinity group may come from different memory levels, there are significant differences in access bandwidth, response delay, etc., so these nodes cannot be simply treated as equivalent. By introducing weight factors, the performance differences between memory nodes can be reflected in a unified quantitative standard, so that subsequent memory allocation can be proportionally adjusted according to the access capabilities of each node, achieving more reasonable resource sharing.

[0025] This weighting factor essentially reflects the relative access capabilities of memory nodes. Specifically, in scenarios where multiple nodes participate in allocation, which nodes should shoulder more memory allocation tasks, and which nodes, due to lower performance, should be used less frequently. This mechanism prevents excessive load from being concentrated on a single high-performance node, leading to resource exhaustion and bottlenecks, while also appropriately activating the potential of suboptimal nodes, expanding the overall system's available memory boundaries. By dynamically introducing and utilizing weighting factors, the system improves allocation flexibility and operational efficiency in heterogeneous memory environments without sacrificing critical path performance, effectively supporting high-concurrency, high-load memory management requirements.

[0026] S14: Allocate memory resources within the affinity group according to the affinity group corresponding to the computing node where the process currently requesting memory is located and the weight factors corresponding to the memory nodes in the affinity group.

[0027] Specifically, when a memory request actually occurs, this step dynamically distributes memory resources proportionally across multiple memory nodes based on the process's current compute node, the node's corresponding affinity group, and the weight factors of each memory node. This process no longer relies on the static strategies of proximity priority or round-robin allocation used in related operating systems. Instead, it introduces a weighted-driven mechanism tied to access performance, allowing the allocation process to comprehensively consider the access efficiency of each memory node and the current system load, achieving more detailed and intelligent memory scheduling.

[0028] Through a weighted allocation strategy based on affinity groups, each memory page allocation reflects awareness of differences in access performance: nodes with higher access efficiency take on more memory allocation tasks, while nodes with relatively lower performance participate less frequently. This mechanism effectively expands the range of schedulable memory resources while ensuring primary path performance, avoiding problems such as resource exhaustion or inefficient waiting caused by performance imbalances. This approach also offers excellent scalability and adaptability, enabling a unified scheduling framework in systems with coexisting different types of memory media. It is a critical foundational capability for memory management in future heterogeneous computing environments.

[0029] In an exemplary embodiment, an affinity group corresponding to the computing node is constructed based on the access relationship between the computing node and the memory node, including: adding the local memory node directly connected to the computing node to the affinity group; from each different memory level, selecting a memory node with the smallest access distance to the computing node as the corresponding extended memory node, and adding it to the affinity group.

[0030] In a heterogeneous memory architecture, there may be complex access paths and significant performance differences between compute nodes and multiple memory nodes. The related technology NUMA architecture emphasizes that compute nodes give priority to accessing the local memory to which they are connected to obtain the lowest latency and highest bandwidth. However, with the introduction of heterogeneous memory types, such as CXL memory, PMem, etc., the capacity of a single type of local memory is often difficult to meet the running requirements of all tasks. To this end, it is necessary to build an affinity group that includes local memory nodes and other accessible extended memory nodes to achieve effective expansion and allocation of resources. However, simply incorporating all accessible remote nodes into the group can easily lead to an imbalance in access efficiency. Therefore, a balance must be struck between expanding resources and access performance.

[0031] In this embodiment, affinity groups are constructed using an optimization strategy based on hierarchical sampling. First, local memory nodes directly connected to the compute nodes are included in the group to ensure basic performance requirements. Then, for each different memory hierarchy, a memory node with the shortest access distance to the current compute node is selected from that hierarchy and added to the affinity group as the representative node of that hierarchy. This approach avoids including multiple remote nodes in the same hierarchy in the affinity group, reducing unnecessary cross-node accesses and management overhead while maintaining a representative sampling of the performance characteristics of that hierarchy.

[0032] Access distances are determined based on system-provided topology information, such as the System Locality Information Table (SLIT) in the Advanced Configuration and Power Interface (ACPI) or data provided by a predefined path in the Linux kernel. These distance values typically reflect the physical distance of the inter-node communication link and the cross-bridge latency. Therefore, selecting the extended memory node with the shortest access distance maximizes the availability and responsiveness of extended resources, improving overall access balance and performance controllability within the affinity group.

[0033] This affinity group construction mechanism is not only applicable to scheduling between related technical DRAM and remote DRAM, but also effectively supports cross-media layered awareness. For example, in a system consisting of local DRAM, PMem, and CXL extended memory, affinity groups constructed in this way can accurately cover multiple performance tiers while avoiding access path uncertainty and resource selection redundancy. This lays the foundation for a clearly structured and well-performing resource collection for subsequent weight allocation and hierarchical memory scheduling strategies.

[0034] In an exemplary embodiment, a weight factor is assigned to each memory node in an affinity group, including: performing a bandwidth test on each memory node in the affinity group to obtain a corresponding test time; calculating a relative access capability ratio of each memory node based on a ratio between the test times; and determining a weight factor corresponding to each memory node based on the relative access capability ratio.

[0035] In a heterogeneous memory environment, different memory nodes may have different physical media characteristics and connection methods, resulting in significant differences in their access bandwidth and latency. It is difficult to accurately quantify these differences based solely on static hardware descriptions or topology information. Therefore, in this embodiment, bandwidth testing during actual runtime is used to perceive and characterize the access capabilities of each memory node in the affinity group. This testing method can more closely reflect the load behavior in the actual operating environment, comprehensively considering multiple factors such as hardware characteristics, topology layout, kernel scheduling, and cache system, thereby more accurately reflecting the actual access performance of each memory node.

[0036] Specifically, bandwidth testing simulates typical memory access behavior by performing simple, repetitive computational operations (such as array multiplication) on a fixed-size data structure bound to a specific memory node within a compute node. During this process, the actual time required to complete the operation is measured, which serves as an inverse indicator of the memory node's bandwidth capability. Shorter test times indicate higher memory access bandwidth for that memory node; conversely, longer test times indicate lower access performance. This approach avoids bias caused by purely theoretical estimates, making the setting of weighting factors more data-driven and adaptable.

[0037] After obtaining the test time for each memory node, we further calculate the relative access capability ratio by comparing these test times. This ratio reflects the bandwidth performance of each node relative to other nodes. For example, if the test time for node A is twice that of node B, then node B's access capability can be considered twice that of node A.

[0038] In an exemplary embodiment, the weight factor corresponding to each memory node is determined based on the relative access capability ratio, including: normalizing the relative access capability ratio so that all ratios are scaled relative to a preset reference value; multiplying the normalized ratio by a preset integer multiple to generate a weight factor in integer form.

[0039] In this embodiment, in order to enable each memory node to participate in memory resource allocation according to its actual access capability within the affinity group, it is necessary to convert the access capability differences obtained from the test into a set of weight factors that can be used for calculation and scheduling. Since the original relative access capability ratios may be decimals and have large differences in range and precision, it is not convenient to use them directly in the system scheduling logic. Therefore, these ratios need to be normalized first. The core idea of normalization is to use a certain benchmark value (for example, the node with the weakest access capability has a ratio of 1) as a reference, and express the access capability of all other nodes as a ratio relative to the benchmark node, ensuring that the relative strength relationship between different nodes is preserved, while building a unified scale.

[0040] After the normalization process is completed, the ratio obtained is usually still a floating-point number, which is not convenient for direct use in integer operations and storage in the system kernel data structure. Therefore, in order to improve computing efficiency and simplify the scheduling process, an integer processing step is further introduced. The specific method is to multiply the normalized ratio by a preset integer multiple (such as 10, 100, etc.) to expand the scale of the value and discard the decimal part, thereby generating an integer weight factor. For example, if the normalized ratio of a node is 5.2, multiplying it by 10 gives 52, which is the final integer weight factor of the node. The choice of this multiple depends on the system accuracy requirements. Its essential purpose is to achieve integerization while retaining the ratio difference.

[0041] This integer weighting factor facilitates proportional execution of the memory allocation algorithm within the system kernel while also providing flexibility and adjustability. The larger the weight of each memory node, the greater its access capability. It will be selected more frequently during subsequent memory allocations and will take on more memory page allocation tasks. Nodes with lower weights participate less frequently, effectively avoiding performance bottlenecks. This approach not only enables the system to dynamically adapt to bandwidth differences between different memory media, but also allows for more refined resource control and performance tuning in complex load and multi-tasking scenarios.

[0042] This integerized weight model, constructed based on access capability ratios, eliminates the need for real-time bandwidth measurement or complex computations when performing page allocation. Instead, page allocation can be performed directly through a table lookup to obtain the weight value for each node, enabling rapid allocation decisions and achieving a good balance between performance and efficiency. This makes this strategy particularly suitable for modern computing platforms that deploy heterogeneous memory devices such as DRAM, PMem, and CXL. It can significantly improve overall memory utilization and task scheduling responsiveness, while avoiding issues such as resource redundancy and imbalanced allocation.

[0043] In an exemplary embodiment, the weight factor corresponding to each memory node is determined based on the relative access capability ratio, including: normalizing the relative access capability ratio so that all ratios are scaled relative to a preset reference value; multiplying the normalized ratio by a preset integer multiple to generate a weight factor in integer form.

[0044] In this embodiment, in the process of determining the weight factor corresponding to each memory node based on the relative access capability ratio, a method combining normalization and integer processing is adopted to achieve quantitative expression of performance differences and meet the operating system's requirements for data format and processing efficiency in actual scheduling.

[0045] First, the relative access capability ratio is normalized to eliminate the dimensional inconsistency problem caused by physical property differences or different absolute values of measurements between different memory nodes. Normalization usually takes the memory node with the weakest access capability as the reference benchmark, setting its access capability ratio to 1, and the other nodes are scaled up proportionally based on this node. For example, if a node has an access speed twice that of the benchmark node, its normalized ratio is 2. In this way, the access capability can be converted into a set of ratios under a unified scale without changing the relative performance order between the nodes, making these ratios more suitable for subsequent weight conversion.

[0046] Secondly, to meet the system scheduling requirement for integer weights, the normalized ratio is multiplied by a preset integer multiple (such as 10 or 100) to preserve the fractional information, and the result is converted to an integer. The essential purpose of this conversion is to approximate the ratio difference with an integer, thereby improving kernel scheduling processing efficiency and data structure compatibility. For example, a node with a normalized ratio of 5.2 will receive a weight factor of 52 after multiplying by 10, while another node with ratios of 1.2, 1.0, and 5.0 will receive a weight factor of 12, 10, and 50, respectively. Subsequent memory allocation can be used to allocate resources according to the ratio of 52:12:10:50.

[0047] In summary, this process maintains the proportional relationship between performance differences between nodes through normalization and achieves data format conversion usable in system scheduling through integer scaling. This ensures that the weight factor setting is both mathematically rigorous and practical for engineering implementation. This approach is particularly critical in heterogeneous memory systems, as it can be used to accurately express the access capabilities of various memory nodes, such as DRAM, PMem, and CXL, providing quantitative support for memory allocation strategies.

[0048] In an exemplary embodiment, a bandwidth test is performed on each memory node in an affinity group to obtain a corresponding test time, including: allocating a test array bound to a target memory node in a computing node; performing a preset multiplication operation on each element in the test array, and counting the test time required to perform the multiplication operation; and setting the length of the test array to be greater than twice the cache capacity of a processor corresponding to the computing node.

[0049] In modern computing systems, processors are typically equipped with multiple levels of cache to accelerate access to memory data. However, when performing memory bandwidth testing, if the test data is swallowed by the cache, it cannot accurately reflect the actual access performance of the underlying memory nodes. This is especially true when performing cross-node memory access testing in a NUMA architecture, which is more susceptible to cache interference. Therefore, in this embodiment, a design is adopted to avoid cache interference. Specifically, by carefully setting the length of the test array to be significantly larger than the processor's cache capacity, this ensures that most data accesses will directly hit the memory nodes rather than being hit by the processor cache, thereby effectively reducing cache interference on the test results.

[0050] More specifically, the test allocates a memory array in the compute node, forcibly binding the physical address of the array to the target memory node through system interfaces or commands (such as binding a memory policy). This ensures that memory operations actually occur on the node under test, avoiding memory drift or data migration issues caused by system scheduling uncertainty. Furthermore, the test uses a simple, branch-free multiplication operation. This operation not only has low computational overhead and a stable execution path, but is also primarily driven by memory read speed, highlighting the bandwidth bottleneck of the underlying memory.

[0051] During execution, the test program performs a multiplication instruction on each element in the array, for example, multiplying each element by a constant and accumulating or discarding the results. This operation design avoids complex data dependencies and ensures that each operation reads the corresponding data from the actual physical memory, making the overall test time more fully reflect the access efficiency of the target memory node. Furthermore, all array elements are initialized to the same value to maintain balanced operations and prevent the optimizer from introducing interference that eliminates calculations.

[0052] Because the length of the test array is set to far exceed twice the processor cache capacity, this means that even if some data may be briefly cached during the initial test, most subsequent accesses will not hit the cache and must fall back to the memory access path. This ensures that the total test time is not shortened by cache hits and can truly and stably reflect the raw bandwidth performance of the target memory node. Ultimately, the test times of multiple nodes will be used to form a basis for comparing access capabilities, supporting the subsequent calculation of relative access capability ratios and weighting factors.

[0053] In an exemplary embodiment, determining the memory level of each memory node includes: dividing the memory nodes according to at least one indicator of bandwidth, access latency, capacity and storage medium cost corresponding to each memory node to obtain multiple memory levels representing different access performance characteristics.

[0054] In this embodiment, in order to rationally organize the heterogeneous memory resources distributed across multiple memory nodes in the system and provide a performance basis for subsequent affinity group construction and weight allocation, it is first necessary to hierarchically classify each memory node and clarify its performance level in the overall memory architecture. The core of this hierarchical process is the access performance indicators reflected by each memory node, including but not limited to parameters such as bandwidth, access latency, capacity, and storage media cost. These parameters essentially reflect the service capabilities, access response speed, and resource scheduling priority of the memory node.

[0055] For example, bandwidth represents the amount of data that can be transmitted per unit time and is a key indicator of a node's concurrent access capabilities. Access latency reflects the time from request issuance to data return and is the primary metric for measuring node response speed. Capacity, on the other hand, relates to the maximum amount of data a node can carry, determining its applicable scenarios and scheduling boundaries. Cost factors reflect the investment and efficiency of media implementation and are used to comprehensively consider the balance between performance and cost in multi-media hybrid systems. In actual operation, the system can quantify and aggregate these indicators through a preset weighting model or a multi-metric scoring mechanism, dividing the memory hierarchy into several representative access performance characteristics.

[0056] For example, memory nodes constructed with DRAM typically have high bandwidth, low latency, and medium capacity, and therefore can be classified as the first tier with higher performance. However, nodes constructed with CXL extended memory typically exhibit lower bandwidth and higher latency due to their access paths involving heterogeneous interfaces and longer data links, and are therefore classified as the second tier. Figure 2 Similarly, other media such as PMem (persistent memory) can be mapped to different memory hierarchies based on their access characteristics. This hierarchical classification can be achieved by automatically identifying the memory type and hardware characteristics corresponding to each NUMA node by analyzing ACPI tables, device tree information, or firmware descriptions.

[0057] The establishment of this memory hierarchy not only serves as a structural abstraction but also provides a clear reference framework for subsequent memory affinity group division, bandwidth testing and comparison, weight calculation, and dynamic scheduling. This hierarchical approach allows for a more organized understanding and organization of heterogeneous memory resources, enabling the introduction of logical performance tiers without disrupting the physical topology. This approach is suitable for both static resource configuration and future dynamic expansion of heterogeneous resource access, and is widely applicable to next-generation computing platforms equipped with hybrid memory.

[0058] like Figure 3In a specific embodiment, the process of determining the weight factor includes: S21: after the system is started, all memory nodes and their corresponding memory levels are identified; S22: bandwidth test is performed on each memory node, and the test time is recorded; S23: the reciprocal ratio of the test time of each memory node is calculated to obtain the relative access capability ratio; S24: the relative access capability ratio is normalized and multiplied by a preset integer multiple to generate a weight factor in integer form; S25: the calculated weight factor is stored in the kernel data structure for use in memory allocation.

[0059] In an exemplary embodiment, based on the affinity group corresponding to the computing node where the process currently applying for memory is located, and the weight factors corresponding to each memory node in the affinity group, memory resources are allocated within the affinity group according to the weight factors, including: when a memory application request from a process is received, determining the number of memory pages requested by the process and determining the computing node where the process is located; obtaining the affinity group corresponding to the computing node, and reading the weight factors corresponding to each memory node in the affinity group; calling memory pages proportional to the number of memory pages in each memory node in the affinity group according to the weight factors of each memory node, and allocating the memory pages to the process.

[0060] In modern heterogeneous memory systems, memory resources are distributed across multiple memory nodes with varying performance and access characteristics. Rationally and efficiently allocating memory resources is crucial for ensuring overall system performance and responsiveness. To address this need, this embodiment proposes a memory allocation mechanism based on affinity groups and their weighting factors. This mechanism dynamically adjusts the allocation ratio of memory pages based on the current compute node and affinity group structure of the process, maximizing resource utilization and optimizing access performance.

[0061] When receiving a memory request from a process, the first thing to do is to determine the size of the request, specifically the number of memory pages required. The compute node on which the process is currently running should also be determined, as this node determines the efficiency and bandwidth performance of its access to local and extended memory nodes. This localization allows us to establish a set of memory nodes with relatively high priority and matching performance for the process, known as an affinity group. This group includes local high-performance memory and several extended remote memory nodes, covering the process's primary memory access paths.

[0062] The weight factors of each memory node within the affinity group are then queried. These weight factors reflect the relative access capabilities and bandwidth resources of each memory node. The weight factors are designed to allocate more memory to nodes with stronger access capabilities, while allocating less memory to nodes with weaker capabilities, thereby avoiding resource bottlenecks and performance degradation. By reading the weight factors, the resource ratio structure within the affinity group is determined, which serves as a guide for memory allocation.

[0063] like Figure 4 Finally, physical memory is allocated cyclically based on the weight factors of each node within the affinity group (for example, the weight factors of the first and third memory nodes in the first affinity group are 52:12, and the weight factors of the fourth and second memory nodes in the second affinity group are 10:50). The corresponding proportion of memory pages in each memory node is calculated and allocated, and these memory pages are allocated to the requesting process. Specifically, for a process on the second compute node, if the weight factors of the two memory nodes in the second affinity group are 1:5, then for every six memory pages allocated, the fourth memory node receives one memory page and the second memory node receives five. This weighted allocation method enables dynamic and precise resource control, fully utilizing local high-performance memory resources while rationally utilizing expanded memory, balancing performance and capacity requirements, and avoiding resource exhaustion or performance bottlenecks caused by over-reliance on a single node. This mechanism is suitable for diverse heterogeneous memory environments and effectively improves overall system memory access efficiency and application performance.

[0064] In an exemplary embodiment, according to the weight factor of each memory node, memory pages proportional to the number of memory pages are called in each memory node in the affinity group, and the memory pages are allocated to the process, including: setting a counter for controlling memory allocation in the structure of the process; initializing the count value of the counter to the weight factor value of the currently selected memory node; decrementing the count value of the counter each time a memory page is allocated to the process; when the count value of the counter decrements to zero, switching to the next memory node in the affinity group, and re-entering the step of initializing the count value of the counter to the weight factor value of the currently selected memory node.

[0065] To implement weight-based proportional memory allocation, this embodiment introduces a dedicated counter in the process's data structure to control memory allocation counting. The core design of this counter uses the weight factor as the initial count value, accurately reflecting the memory allocation proportion that the current memory node should assume within the affinity group. This counting mechanism allows memory allocation requests to be distributed gradually and orderly to different memory nodes within the affinity group according to their weighted proportions.

[0066] Specifically, when a process first requests memory, the first memory node in the affinity group is selected based on the affinity group of the compute node where the process is located, and the weight factor corresponding to this node is assigned to a counter in the process structure. At this point, the counter value indicates how many memory pages remain to be allocated from this memory node. As the process continues to request memory allocations, the counter value decreases with each allocated memory page, indicating that the memory share allocated from this memory node is gradually consumed. When the counter decreases to zero, it means that the weight share of this memory node has been allocated. This means that the next memory node in the affinity group is switched and the counter is reinitialized to the weight factor of this node to continue the next round of memory allocation tasks.

[0067] This cyclical pattern of counter decrement and node rotation enables even memory allocation proportional to weight factors. For example, if the weight factor of the fourth memory node is 1 and the weight factor of the second memory node is 5, the system will first allocate one memory page from the fourth memory node, then switch to the second memory node to allocate five consecutive memory pages, then return to the fourth memory node, and repeat this cycle. This mechanism ensures that high-weight nodes occupy a larger share of memory resource scheduling while avoiding resource exhaustion or performance bottlenecks caused by continuous single-node allocation.

[0068] This simple and efficient design not only ensures fair and flexible scheduling, but also facilitates implementation and maintenance within the operating system kernel. The counter decrement and node switching logic ensure that the proportional significance of the weight factor is accurately reflected in actual memory page allocation, significantly improving the rationality of resource allocation and overall performance in heterogeneous memory systems.

[0069] In an exemplary embodiment, it also includes: providing an interface for configuring the affinity group corresponding to the computing node, the interface allows the user to specify or modify the set of memory nodes that are members of the affinity group of a computing node to dynamically adjust the ownership of memory resources; providing an interface for adjusting the weight factors of each memory node in the affinity group, the interface supports the user to manually set or modify the weight value of each memory node to flexibly control the allocation ratio of memory resources within the affinity group; supporting the definition of a new memory allocation strategy through the system call interface, the strategy is based on the affinity group and its weight factor, to achieve proportional interleaving allocation of hierarchical memory resources by processes or virtual memory areas, thereby adapting to the performance optimization requirements of different application scenarios.

[0070] To enhance the flexibility and adaptability of the system's memory allocation policy, particularly in heterogeneous memory and multi-node environments, this embodiment provides a set of user-mode configuration interfaces that allow users to dynamically adjust affinity group membership and weight factors based on specific application requirements and the operating environment. Through these interfaces, users can independently define and optimize the mapping between compute nodes and their associated memory nodes, enabling more refined and efficient memory resource management.

[0071] First, an interface is provided for configuring the affinity group corresponding to the compute node. This interface allows users to explicitly specify the set of memory nodes in the affinity group corresponding to a compute node, or to modify the members of an existing affinity group. This allows the system to no longer rely entirely on static hardware topology or default policies, but instead supports flexible adjustment of the ownership of memory nodes based on runtime load conditions, application characteristics, or performance monitoring results. For example, users can add a high-performance memory node to the affinity group of multiple compute nodes to achieve resource sharing, or replace remote nodes with more suitable extension nodes to optimize access latency and bandwidth utilization.

[0072] Secondly, an interface is provided for adjusting the weight factor of each memory node within an affinity group. The weight factor is a key control parameter in the memory allocation policy, determining the resource allocation ratio of each memory node within the affinity group. Through this interface, users can manually adjust the weight value based on actual performance requirements and the operating status of the memory nodes, raising or lowering the allocation priority of certain memory nodes. This weight adjustment capability enables the system to more effectively schedule resources based on the performance differences between heterogeneous memory media (such as DRAM, CXL, PMem, etc.), avoid performance bottlenecks, and fully utilize various memory resources.

[0073] Finally, to enable processes or VMAs (Virtual Memory Areas) to flexibly utilize the aforementioned affinity groups and weighting mechanism, a new memory allocation strategy has been introduced. Users can use system call interfaces (such as mbind() or set_mempolicy()) to bind processes or VMAs to a hierarchical interleaved allocation strategy based on affinity groups and weighting factors. This strategy ensures proportional memory allocation across different memory tiers, maintaining memory access locality while achieving bandwidth and capacity load balancing. This significantly improves the system's support for diverse application scenarios and overall performance.

[0074] In summary, this embodiment prioritizes local or low-latency memory nodes during memory allocation by constructing NUMA affinity groups that match the performance characteristics of the memory hierarchy. This significantly reduces the frequency of compute nodes accessing remote or high-latency memory nodes, thereby reducing cross-node access latency and improving overall system memory access performance. Static weight initialization based on the bandwidth ratio of memory nodes in the affinity group, combined with a weight-factor-driven memory interleaving allocation strategy, aligns the memory resource allocation ratio with the actual access capabilities of each memory node, optimizing resource utilization in heterogeneous memory systems and avoiding memory resource waste and performance bottlenecks caused by node performance differences. A sysfs interface exposed in user mode allows users to manually configure affinity group membership for compute nodes and adjust the weight factors of each memory node. This supports flexible customization of memory allocation strategies for different application scenarios (such as high-performance computing and artificial intelligence training), enhancing the system's adaptability to diverse needs. Lightweight memory bandwidth testing is performed as a system service during system initialization, eliminating the need for external tools. This enables bandwidth measurement and weight generation for heterogeneous memory media (including non-volatile memory and high-bandwidth memory), ensuring the solution's compatibility and broad applicability.

[0075] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0076] like Figure 5 An embodiment of the present application further provides an electronic device, comprising a memory 101 and a processor 102, wherein the memory 101 stores a computer program, and the processor 102 is configured to run the computer program to execute the steps in any one of the above-mentioned memory allocation method embodiments.

[0077] like Figure 6 An embodiment of the present application further provides a computer-readable storage medium 201, in which a computer program 202 is stored, wherein the computer program 202 is configured to execute the steps of any of the above-mentioned memory allocation method embodiments when running.

[0078] In an exemplary embodiment, the computer-readable storage medium 201 may include, but is not limited to, various media that can store the computer program 202, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0079] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned memory allocation method embodiments are implemented.

[0080] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned memory allocation method embodiments are implemented.

[0081] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] The above is a detailed introduction to a memory allocation method, device, and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory allocation method, characterized in that: Applied to a computing system including multiple computing nodes and multiple memory nodes, the memory allocation method includes: Determining a memory level of the memory node, where the memory level represents access performance of the memory node; Building an affinity group corresponding to the computing node according to the access relationship between the computing node and the memory node, the affinity group including a local memory node and at least one extended memory node of the computing node; Assigning a weight factor to each memory node in the affinity group, wherein the weight factor represents a relative access capability of the memory node; According to the affinity group corresponding to the computing node where the process currently applying for memory is located and the weight factors corresponding to the memory nodes in the affinity group, memory resources are allocated within the affinity group according to the weight factors.

2. The memory allocation method according to claim 1, wherein: Building an affinity group corresponding to the computing node according to the access relationship between the computing node and the memory node, including: Adding a local memory node directly connected to the computing node to the affinity group; From each different memory level, a memory node with the smallest access distance to the computing node is selected as the corresponding extended memory node, and the node is added to the affinity group.

3. The memory allocation method according to claim 1, wherein: Assign a weight factor to each memory node in the affinity group, including: Performing a bandwidth test on each memory node in the affinity group to obtain a corresponding test time; Calculating the relative access capability ratio of each memory node according to the ratio between the test times; A weight factor corresponding to each of the memory nodes is determined according to the relative access capability ratio.

4. The memory allocation method according to claim 3, wherein: Performing a bandwidth test on each memory node in the affinity group to obtain a corresponding test time includes: In the computing node, allocating a test array bound to a target memory node; Performing a preset multiplication operation on each element in the test array, and counting the test time required to perform the multiplication operation; The length of the test array is set to be greater than twice the cache capacity of the processor corresponding to the computing node.

5. The memory allocation method according to claim 3, wherein: Determining a weight factor corresponding to each of the memory nodes according to the relative access capability ratio includes: Normalizing the relative access capability ratios so that all ratios are scaled relative to a preset reference value; The normalized ratio is multiplied by a preset integer multiple to generate an integer weight factor.

6. The memory allocation method according to claim 1, wherein: Determining a memory level of the memory node includes: The memory nodes are divided according to at least one indicator of bandwidth, access latency, capacity and storage medium cost corresponding to each memory node to obtain multiple memory levels representing different access performance characteristics.

7. The memory allocation method according to any one of claims 1 to 6, characterized in that: According to the affinity group corresponding to the computing node where the process currently requesting memory is located and the weight factors corresponding to the memory nodes in the affinity group, memory resources are allocated within the affinity group according to the weight factors, including: When receiving a memory request from a process, determining the number of memory pages requested by the process and determining the computing node where the process is located; Obtaining the affinity group corresponding to the computing node, and reading the weight factor corresponding to each of the memory nodes in the affinity group; According to the weight factor of each memory node, memory pages proportional to the number of memory pages are called in each memory node in the affinity group, and the memory pages are allocated to the process.

8. The memory allocation method according to claim 7, wherein: The method further comprises: calling memory pages proportional to the number of memory pages in each memory node in the affinity group according to the weight factor of each memory node, and allocating the memory pages to the process, including: Setting a counter for controlling memory allocation in a structure of the process; Initializing the count value of the counter to the weight factor value of the currently selected memory node; After each memory page is allocated to the process, the count value of the counter is decremented; When the count value of the counter decreases to zero, switching to the next memory node in the affinity group and re-entering the step of initializing the count value of the counter to the weight factor value of the currently selected memory node.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the memory allocation method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory allocation method according to any one of claims 1 to 8.

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