Charge pump device for mode multiplexing in CDR

Abstract

The invention relates to the technical field of communication systems, in particular to a charge pump device for mode multiplexing in a CDR, which is judged by a phase frequency detector (PFD), charges UP or discharges DN for a loop filter (LPF), and comprises a current source current mirror module, a current source current mirror module and a mode multiplexing module, the current source and current mirror module comprises a CDR positive current source, a CDR negative current source, a PLL positive current source, a PLL negative current source, an operational amplifier module and a switch module, the CDR positive current source, the CDR negative current source, the PLL positive current source and the PLL negative current source are arranged in a mirror image mode, the switch module comprises a plurality of sets of switches TG and a logic control module, and the logic control module comprises a PLL-mode finite state machine FSM and a CDR-mode finite state machine FSM. The mode multiplexing charge pump device is used for a PLL mode multiplexing charge pump circuit and a CDR mode multiplexing charge pump circuit in a CDR, can rapidly switch between the two modes, keeps high stability, low mismatch and low power consumption at the same time, and reduces the arrangement of operational amplifiers and charge discharge switches, thereby reducing the circuit area.

Description

Technical Field

[0001] The present invention relates to the technical field of communication systems, and in particular to a charge pump device for mode multiplexing in a CDR. Background Art

[0002] In high-speed communication systems, clock and data recovery (CDR) circuits are critical modules for ensuring correct data reception. CDR circuits typically operate in two modes: PLL mode and CDR mode. PLL mode is used for frequency locking and is primarily employed during system startup or when signal quality is poor to ensure the clock signal frequency is consistent with the frequency of the incoming data stream. CDR mode, on the other hand, is used for phase locking and is enabled when signal quality is good. It performs phase detection and adjustment on the received data to accurately lock the clock phase, thereby improving the stability and reliability of data transmission.

[0003] like Figure 1 As shown, conventional CDR circuits typically require separate charge pump circuits to support both modes, increasing circuit complexity and area. To reduce circuit area and power consumption, multiplexing charge pump circuits has become an attractive solution. However, existing multiplexing schemes suffer from poor stability, slow response, and large mismatch during mode switching, which compromises CDR circuit performance. Therefore, designing a device that can reuse charge pump circuits to simultaneously meet the requirements of both PLL and CDR modes has become a pressing issue. Summary of the Invention

[0004] In order to solve the problems of poor stability, slow response speed, large mismatch, etc. in the existing multiplexing scheme, the present invention provides a charge pump device for mode multiplexing in CDR, which meets the charge pump circuit that multiplexes the PLL mode and CDR mode in CDR and can quickly switch between the two modes while maintaining high stability, low mismatch, low power consumption and reducing circuit area.

[0005] The present invention provides a charge pump device for mode multiplexing in a CDR. The charge pump device charges UP or discharges DN to a loop filter LPF according to a phase frequency detector (PFD). The charge pump device includes a current source / current mirror module for providing a stable current output. The current source / current mirror module includes a CDR positive current source and a CDR negative current source and a PLL positive current source and a PLL negative current source arranged in a mirrored manner. An operational amplifier module is used to amplify and process signals. A switch module is used to control a signal path. The switch module includes a plurality of switch groups TG. A logic control module is used to control the switch state of the switch module. The logic control module includes a finite state machine (FSM) for PLL mode and a finite state machine (FSM) for CDR mode. When the frequency or phase is slower than the reference clock, the PLL FSM controls switch TG to open, allowing the CDR positive current source and the PLL positive current source to charge the loop filter (LPF). When the frequency or phase is faster than the reference clock, the CDR FSM controls switch TG to open, allowing the CDR negative current source and the PLL negative current source to discharge the loop filter (LPF). When the frequency or phase is roughly consistent with the reference clock, switch TG closes. Reusing the same circuit saves circuit area, and the FSM's sophisticated logic management ensures that the PLL and CDR modes operate independently, significantly improving the stability and performance of the entire phase-locked loop system.

[0006] Furthermore, the switch module includes four groups of switches TG, each consisting of two parallel transmission gates. The inputs of the transmission gates are connected to the outputs of the current source and current mirror modules, and the outputs of the transmission gates are connected to the output IOUT of the loop filter LPF. By using multiple groups of switches TG to separate the CDR module and the PLL module, current paths can be flexibly selected, improving the circuit's flexibility and scalability.

[0007] Furthermore, the transmission gate is composed of complementary PMOS and NMOS transistors, forming two gate control terminals with opposite connections. Both gate control terminals are connected to a finite state machine (FSM). The FSM dynamically adjusts the selection of the switch module based on the input signal, achieving adaptive regulation of the circuit.

[0008] Furthermore, the four groups of switches TG are divided into switch No. 1, switch No. 2, switch No. 3, and switch No. 4 according to the current path. The four gate control terminals of switch No. 1 are respectively connected to UP_PLL_1, UPB_PLL_4, UP_CDR_1, and UPB_CDR_4; the four gate control terminals of switch No. 2 are respectively connected to UPB_CDR_3, UP_CDR_2, UPB_PLL_3, and UP_PLL_2; the four gate control terminals of switch No. 3 are respectively connected to DNB_CDR_7, DN_CDR_6, DNB_PLL_7, and DN_PLL_6; and the four gate control terminals of switch No. 4 are respectively connected to DN_PLL_5, DNB_PLL_8, DN_CDR_5, and DNB_CDR_8.

[0009] Furthermore, when the frequency or phase is slower than the reference clock, UP_PLL_2 and UP_CDR_2 of switch #2 are high, and the corresponding UPB_PLL_3 and UPB_CDR_3 are low, turning switch #2 on. DN_PLL_6 and DN_CDR_6 of switch #3 are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, turning switch #3 off. UP_PLL_1 and UP_CDR_1 of switch #1 are high, and the corresponding UPB_PLL_4 and UPB_CDR_4 are low, turning switch #1 off. DN_PLL_5 and DN_CDR_5 of switch #4 are low, and the corresponding DNB_PLL_8 and DNB_CDR_8 are high, turning switch #4 on. Switches #2 and #4 are on, charging the LPF.

[0010] Furthermore, when the frequency or phase is faster than the reference clock, UP_PLL_2 and UP_CDR_2 of switch #2 are low, and the corresponding UPB_PLL_3 and UPB_CDR_3 are high, turning switch #2 off. DN_PLL_6 and DN_CDR_6 of switch #3 are high, and the corresponding DNB_PLL_7 and DNB_CDR_7 are low, turning switch #3 on. UP_PLL_1 and UP_CDR_1 of switch #1 are low, and the corresponding UPB_PLL_4 and UPB_CDR_4 are high, turning switch #1 on. DN_PLL_5 and DN_CDR_5 of switch #4 are high, and the corresponding DNB_PLL_8 and DNB_CDR_8 are low, turning switch #4 off. Switches #1 and #3 are turned on, discharging the LPF.

[0011] Furthermore, when the frequency or phase is substantially consistent with the reference clock, the PLL mode is locked. UP_PLL_2 and UP_CDR_2 of switch #2 are low, and the corresponding UPB_PLL_3 and UPB_CDR_3 are high, turning switch #2 off. DN_PLL_6 and DN_CDR_6 of switch #3 are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, turning switch #3 off. UP_PLL_1 and UP_CDR_1 of switch #1 are low, and the corresponding UPB_PLL_4 and UPB_CDR_4 are high, turning switch #1 on. DN_PLL_5 and DN_CDR_5 of switch #4 are low, and the corresponding DNB_PLL_8 and DNB_CDR_8 are high, turning switch #4 on. Neither the upper nor the lower switches are turned on, preventing the LPF from charging or discharging, thereby maintaining the VCO frequency.

[0012] Furthermore, in CDR mode, UP_PLL_2 of switch #2 is low, and the corresponding UPB_PLL_3 is high. DN_PLL_6 of switch #3 is low, and the corresponding DNB_PLL_7 is high. UPB_PLL_4 of switch #1 is low, and the corresponding UP_PLL_1 is high. DN_PLL_5 of switch #4 is high, and the corresponding DNB_PLL_8 is low. PLL-related switches remain closed, without affecting CDR-related switches.

[0013] The beneficial effects of the present invention are: The present invention provides a charge pump device for mode multiplexing in a CDR. By reusing the same circuit to save circuit area, a finite state machine (FSM) is used to logically control the on and off of a switch TG, effectively avoiding conflicts between the PLL mode and the CDR mode. The device can quickly switch between the two modes while maintaining high stability, low mismatch, and low power consumption, thereby meeting the high charge pump performance requirements of the CDR system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts. Figure 1 This is a schematic diagram of a traditional charge pump used in CDR; Figure 2 is a schematic diagram of embodiment 1; Figure 3 This is a schematic diagram of the on-off state switch of the charging state in the first embodiment; Figure 4 This is a schematic diagram of the on-off switch in the discharge state of Example 1; Figure 5 1 is a schematic diagram of the switch on and off after the PLL mode is locked in the first embodiment; Figure 6 Schematic diagram of the switch on and off in the CDR mode of the first embodiment; Figure 7 is a schematic diagram of embodiment 2; DETAILED DESCRIPTION

[0015] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0016] In the charge pump traditionally used in clock data recovery (CDR) circuits, two operational amplifiers and charge discharge switches are required to avoid the problem of charge sharing due to the two-way current control, which increases the area and power consumption. Among them, the operational amplifier often occupies a large part of the area due to the problem of input and output dynamic range. In order to reuse some circuits and operational amplifiers to effectively reduce the area of the charge pump, a charge pump device for mode multiplexing in CDR is designed. After judgment by the phase frequency detector (PFD), the loop filter LPF is charged UP or discharged DN to achieve frequency control of the VCO to track the input reference clock frequency and phase. Figure 2 As shown, the charge pump device includes a current source and current mirror module, an operational amplifier module, a switch module and a logic control module. The current source and current mirror module includes a CDR positive current source and a CDR negative current source and a PLL positive current source and a PLL negative current source in a mirrored arrangement, which are used to provide a stable current output. The operational amplifier module is an operational amplifier, which is used to amplify and process signals. The switch module includes several groups of switches TG, which are used to control the signal path. The logic control module includes a finite state machine FSM in PLL mode and a finite state machine FSM in CDR mode, which are used to control the switching state of the switch module.

[0017] When the frequency or phase is slower than the reference clock, the finite state machine FSM of the PLL mode controls the switch TG to turn on, so that the CDR positive current source and the PLL positive current source charge the loop filter LPF UP; when the frequency or phase is faster than the reference clock, the finite state machine FSM of the CDR mode controls the switch TG to turn on, so that the CDR negative current source and the PLL negative current source discharge the loop filter LPF DN.

[0018] The switch module includes four groups of switches (TG), each consisting of two parallel transmission gates. The inputs of the transmission gates are connected to the outputs of the current source / current mirror modules, and the outputs of the transmission gates are connected to the output terminal (IOUT) of the loop filter (LPF). The transmission gates are composed of complementary PMOS and NMOS transistors, forming two oppositely connected gate control terminals, both of which are connected to the finite state machine (FSM).

[0019] Specifically, the four groups of switches TG are divided into switch No. 1, switch No. 2, switch No. 3 and switch No. 4 according to the current path. The four gate control terminals of switch No. 1 are respectively connected to UP_PLL_1, UPB_PLL_4, UP_CDR_1 and UPB_CDR_4; the four gate control terminals of switch No. 2 are respectively connected to UPB_CDR_3, UP_CDR_2, UPB_PLL_3 and UP_PLL_2; the four gate control terminals of switch No. 3 are respectively connected to DNB_CDR_7, DN_CDR_6, DNB_PLL_7 and DN_PLL_6; and the four gate control terminals of switch No. 4 are respectively connected to DN_PLL_5, DNB_PLL_8, DN_CDR_5 and DNB_CDR_8.

[0020] In phase-locked loop (PLL) mode, to ensure sufficient ICP current for frequency tracking and lock, the logic control module's finite state machine (FSM) sequentially controls the PLL current switches (UP_PLL_1, UP_PLL_2, UPB_PLL_3, UPB_PLL_4, DN_PLL_5, DN_PLL_6, DNB_PLL_7, and DNB_PLL_8). This enables high-current charging and discharging, thus locking the PLL's frequency. After frequency lock, when switching to clock data recovery (CDR) mode, the logic control module's finite state machine (FSM) disables the PLL current switch enable, allowing the phase loop to track and lock the phase using only the low current of the CDR current source. In high-speed processes, the high leakage of LVT-type MOSFETs can cause significant current-charge mismatch when switching to CDR mode. Isolation through the switch module effectively reduces the mismatch caused by the large leakage of the PLL MOSFETs. The added logic control module (FSM finite state machine) can effectively realize the control of enabling, powering off and mode switching, and can ensure its logical function.

[0021] like Figure 3As shown, when the frequency or phase is slower than the reference clock, the LPF is charged, UP_PLL_2 and UP_CDR_2 of the second switch are high, the corresponding UPB_PLL_3 and UPB_CDR_3 are low, and the second switch is turned on; DN_PLL_6 and DN_CDR_6 of the third switch are low, the corresponding DNB_PLL_7 and DNB_CDR_7 are high, and the third switch is turned off; UP_PLL_1 and UP_CDR_1 of the first switch are high, the corresponding UPB_PLL_4 and UPB_CDR_4 are low, and the first switch is turned off; DN_PLL_5 and DN_CDR_5 of the fourth switch are low, the corresponding DNB_PLL_8 and DNB_CDR_8 are high, and the fourth switch is turned on, so that the CDR positive current source CDR_P_Current Source and the PLL positive current source PLL_P_CurrentSource charge the loop filter LPF. At this time, the current of the two current sources added together is large enough, and the charge pump ICP increases the current injected into the LPF, thereby increasing the LPF charge and raising the control voltage of the VCO. The loop can track the reference clock.

[0022] like Figure 4 As shown, when the frequency or phase is faster than the reference clock, the LPF is discharged, UP_PLL_2 and UP_CDR_2 of the second switch are low, the corresponding UPB_PLL_3 and UPB_CDR_3 are high, and the second switch is disconnected; DN_PLL_6 and DN_CDR_6 of the third switch are high, the corresponding DNB_PLL_7 and DNB_CDR_7 are low, and the third switch is turned on; UP_PLL_1 and UP_CDR_1 of the first switch are low, the corresponding UPB_PLL_4 and UPB_CDR_4 are high, and the first switch is turned on; DN_PLL_5 and DN_CDR_5 of the fourth switch are high, the corresponding DNB_PLL_8 and DNB_CDR_8 are low, and the fourth switch is disconnected, so that the CDR negative current source CDR_N_Current Source and PLL negative current source PLL_N_CurrentSource draw power to the LPF. ICP draws more current from the LPF, which reduces the charge on the LPF and lowers the control voltage of the VCO, allowing the loop to track the reference clock.

[0023] like Figure 5As shown in the figure, when the frequency or phase is basically consistent with the reference clock, the PLL mode is locked, UP_PLL_2 and UP_CDR_2 of the second switch are low, and the corresponding UPB_PLL_3 and UPB_CDR_3 are high, and the second switch is disconnected; DN_PLL_6 and DN_CDR_6 of the third switch are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, and the third switch is disconnected; UP_PLL_1 and UP_CDR_1 of the first switch are low, and the corresponding UPB_PLL_4 and UPB_CDR_4 are high, and the first switch is turned on; DN_PLL_5 and DN_CDR_5 of the fourth switch are low, and the corresponding DNB_PLL_8 and DNB_CDR_8 are high, and the fourth switch is turned on. Neither the upper nor the lower switches are turned on, and no charging or discharging operation is caused on the LPF. The phase-locked loop enters a locked state to maintain the frequency of the VCO, and the system is in a stable working mode.

[0024] like Figure 6 As shown, entering CDR mode, UP_PLL_2 and UP_CDR_2 of switch No. 2 are low, and the corresponding UPB_PLL_3 and UPB_CDR_3 are high, and switch No. 2 is disconnected; DN_PLL_6 and DN_CDR_6 of switch No. 3 are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, and switch No. 3 is disconnected; UP_PLL_1 and UP_CDR_1 of switch No. 1 are high, and the corresponding UPB_PLL_4 and UPB_CDR_4 are low, and switch No. 1 is disconnected; DN_PLL_5 and DN_CDR_5 of switch No. 4 are high, and the corresponding DNB_PLL_8 and DNB_CDR_8 are low, and switch No. 4 is turned on.

[0025] Reusing the same circuit saves circuit area and avoids conflicts between PLL and CDR modes. (CDR mode must prevent the high current of the PLL_Current Source from affecting loop stability, so it cannot operate in response to the UP and DN signals, requiring an FSM for logic control.) The main purpose of this sequence is to ensure that after LOCK (PLL mode lock), the control signal LOCKN ensures that the FSM controlling the PLL mode charge pump switches always keeps the PLL-related switches in the charge pump closed, without affecting the CDR-related switches. This ensures that the PLL and CDR modes do not interfere with each other when operating independently, greatly improving the stability and performance of the entire phase-locked loop system.

[0026] After the PLL is turned off, UP_CDR_2 is high, controlling the ICP to inject LPF charge and raise the VCO control voltage; UP_CDR_1 is high, controlling the left switch to close, DN_CDR_6 is high, controlling the ICP to extract LPF charge and lower the VCO control voltage; DN_CDR_5 is high, controlling the left switch to open, maintaining the voltage drop of the upper and lower current sources to avoid inaccurate current of the current source.

[0027] like Figure 7 As shown, the difference between Example 2 and Example 1 is that the PLL mode switch tube is connected in series to the UP and DN switch sources. Since the PLL mode current switch is loaded at the UP and DN switch sources, the logic control module and some switch tubes can be further saved, the logic is simpler, and the area can be further reduced.

[0028] The above description is only illustrative of the present invention and not restrictive. Those skilled in the art will understand that many modifications, changes or equivalents may be made without departing from the spirit and scope defined by the appended claims, but all of them will fall within the scope of protection of the present invention.

Claims

1. A charge pump device for mode multiplexing in a CDR, which charges a loop filter (LPF) with a current (UP) or discharges a current (DN) with a current (DN) as determined by a phase frequency detector (PFD), characterized in that: The charge pump device includes A current source and current mirror module is used to provide a stable current output. The current source and current mirror module includes a CDR positive current source and a CDR negative current source and a PLL positive current source and a PLL negative current source in a mirrored arrangement. Op amp module, used to amplify and process signals, A switch module is used to control the signal path, the switch module includes several groups of switches TG, and A logic control module, used to control the switching state of the switch module, wherein the logic control module includes a finite state machine FSM in the PLL mode and a finite state machine FSM in the CDR mode; When the frequency or phase is slower than the reference clock, the finite state machine FSM of the PLL mode controls the switch TG to turn on, so that the CDR positive current source and the PLL positive current source charge the loop filter LPF UP; when the frequency or phase is faster than the reference clock, the finite state machine FSM of the CDR mode controls the switch TG to turn on, so that the CDR negative current source and the PLL negative current source discharge the loop filter LPF DN; when the frequency or phase is basically consistent with the reference clock, the switch TG is closed.

2. The charge pump device for mode multiplexing in CDR according to claim 1, characterized in that: The switch module includes four groups of switches TG, each group of switches TG consists of two parallel transmission gates, the input end of the transmission gate is connected to the output end of the current source current mirror module, and the output end of the transmission gate is connected to the output end IOUT of the loop filter LPF.

3. The charge pump device for mode multiplexing in CDR according to claim 2, characterized in that: The transmission gate is composed of a complementary PMOS transistor and an NMOS transistor, forming two gate control terminals with opposite connection relationships, and both of the gate control terminals are connected to a finite state machine FSM.

4. The charge pump device for mode multiplexing in CDR according to claim 3, characterized in that: The four groups of switches TG are divided into switch No. 1, switch No. 2, switch No. 3, and switch No. 4 according to the current path. The four gate control terminals of switch No. 1 are respectively connected to UP_PLL_1, UPB_PLL_4, UP_CDR_1, and UPB_CDR_4. The four gate control terminals of switch No. 2 are respectively connected to UPB_CDR_3, UP_CDR_2, UPB_PLL_3, and UP_PLL_2. The four gate control terminals of switch No. 3 are respectively connected to DNB_CDR_7, DN_CDR_6, DNB_PLL_7, and DN_PLL_6. The four gate control terminals of switch No. 4 are respectively connected to DN_PLL_5, DNB_PLL_8, DN_CDR_5, and DNB_CDR_8.

5. The charge pump device for mode multiplexing in CDR according to claim 4, characterized in that: When the frequency or phase is slower than the reference clock, UP_PLL_2 and UP_CDR_2 of switch No. 2 are high, and the corresponding UPB_PLL_3 and UPB_CDR_3 are low, and switch No. 2 is turned on; DN_PLL_6 and DN_CDR_6 of switch No. 3 are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, and switch No. 3 is turned off; UP_PLL_1 and UP_CDR_1 of switch No. 1 are high, and the corresponding UPB_PLL_4 and UPB_CDR_4 are low, and switch No. 1 is turned off; DN_PLL_5 and DN_CDR_5 of switch No. 4 are low, and the corresponding DNB_PLL_8 and DNB_CDR_8 are high, and switch No. 4 is turned on.

6. The charge pump device for mode multiplexing in CDR according to claim 4, characterized in that: When the frequency or phase is faster than the reference clock, UP_PLL_2 and UP_CDR_2 of switch No. 2 are low, the corresponding UPB_PLL_3 and UPB_CDR_3 are high, and switch No. 2 is disconnected; DN_PLL_6 and DN_CDR_6 of switch No. 3 are high, the corresponding DNB_PLL_7 and DNB_CDR_7 are low, and switch No. 3 is turned on; UP_PLL_1 and UP_CDR_1 of switch No. 1 are low, the corresponding UPB_PLL_4 and UPB_CDR_4 are high, and switch No. 1 is turned on; DN_PLL_5 and DN_CDR_5 of switch No. 4 are high, the corresponding DNB_PLL_8 and DNB_CDR_8 are low, and switch No. 4 is disconnected.

7. The charge pump device for mode multiplexing in CDR according to claim 4, characterized in that: When the frequency or phase is basically consistent with the reference clock, UP_PLL_2 and UP_CDR_2 of switch No. 2 are low, and the corresponding UPB_PLL_3 and UPB_CDR_3 are high, and switch No. 2 is disconnected; DN_PLL_6 and DN_CDR_6 of switch No. 3 are low, and the corresponding DNB_PLL_7 and DNB_CDR_7 are high, and switch No. 3 is disconnected; UP_PLL_1 and UP_CDR_1 of switch No. 1 are low, and the corresponding UPB_PLL_4 and UPB_CDR_4 are high, and switch No. 1 is turned on; DN_PLL_5 and DN_CDR_5 of switch No. 4 are low, and the corresponding DNB_PLL_8 and DNB_CDR_8 are high, and switch No. 4 is turned on.

8. The charge pump device for mode multiplexing in CDR according to claim 4, characterized in that: Entering CDR mode, UP_PLL_2 of switch No. 2 is low, and the corresponding UPB_PLL_3 is high; DN_PLL_6 of switch No. 3 is low, and the corresponding DNB_PLL_7 is high; UPB_PLL_4 of switch No. 1 is low, and the corresponding UP_PLL_1 is high; DN_PLL_5 of switch No. 4 is high, and the corresponding DNB_PLL_8 is low.

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