Memory test system and method, board card and server

Abstract

The invention discloses a memory test system and method, a board card and a server. The memory test system comprises an out-of-band management unit and a target chip, the out-of-band management unit sends a pressure test instruction to the target chip through the preset communication interface, the pressure test instruction comprises dynamically adjusted test strength parameters, and the pressure test instruction is generated based on a preset instruction set; the target chip performs calibration verification on the target memory in response to the pressure test instruction; after the calibration verification is passed, a test load is applied to the target memory according to the test strength parameter, and a cyclic pressure test is executed; the target chip collects test data generated in the pressure test process and transmits the test data back to the out-of-band management unit through the preset communication interface, and the out-of-band management unit generates structured test data according to the test data. Compared with the prior art, the situation that normal services are interrupted due to testing in a traditional testing method can be avoided, and the availability and stability of the system in the testing process are guaranteed.

Description

Technical Field

[0001] The present disclosure relates to the technical field of servers, and in particular to a system and method for memory testing, a board, and a server. Background Art

[0002] Field-Programmable Gate Array (FPGA) testing often relies on external testing equipment. This approach is not only cumbersome to operate, requiring the device to be separated from the operating environment, disrupting normal business operations, but also increases testing costs and time due to the complexity of device connection and configuration. Existing software simulation testing and self-testing are convenient, but they suffer from timing distortion and cannot accurately reflect the true performance and reliability of memory. FPGA memory testing technology in related technologies has significant deficiencies in test triggering, process control, and result feedback, making it difficult to meet the current high-performance, high-reliability, and intelligent operation and maintenance requirements of servers. Summary of the Invention

[0003] The present disclosure provides a system and method for memory testing, a board, and a server, the main purpose of which is to solve the problem in related technologies that FPGA memory testing requires interruption of normal business operations.

[0004] According to a first aspect of the present disclosure, a memory testing system is provided, comprising: an out-of-band management unit, a target chip, the target chip being connected to a target memory on which a stress test is to be performed;

[0005] The out-of-band management unit sends a stress test instruction to the target chip through a preset communication interface, where the stress test instruction includes a dynamically adjusted test intensity parameter and is generated based on a preset instruction set;

[0006] The target chip performs calibration verification on the target memory in response to the stress test instruction; after the calibration verification passes, a test load is applied to the target memory according to the test intensity parameter and a cyclic stress test is performed;

[0007] The target chip collects the test data generated during the stress test and transmits it back to the out-of-band management unit through a preset communication interface. The out-of-band management unit generates structured test data based on the test data.

[0008] Optionally, the target chip includes: a stress test module and a status register;

[0009] The stress test module monitors the value changes of the status register;

[0010] After the value of the status register changes to the preset startup value, the stress test module performs a stress test on the target memory.

[0011] Optionally, the stress test module generates a test load corresponding to each memory channel according to the test intensity parameter, applies the test load to the target memory of different channels respectively, and performs a cyclic stress test;

[0012] The stress test module performs data integrity verification during the test and generates test data for each memory channel based on the verification results of each channel.

[0013] The stress test module writes the test data into the status register, wherein each status bit segment of the status register maps to a different memory channel for recording the test data of the corresponding channel.

[0014] Optionally, the out-of-band management unit sends a stress test instruction to modify the value of the status register.

[0015] Optionally, the cyclic stress test includes at least one of a sequential read / write mode, a random read / write mode, and a checkerboard mode.

[0016] Optionally, the out-of-band management unit sends an immediate status query instruction or a log acquisition instruction to the target chip through a preset communication interface to obtain test data, wherein the immediate status query instruction and the log acquisition instruction are generated based on a preset instruction set.

[0017] According to a second aspect of the present disclosure, a memory testing method is provided, comprising:

[0018] Integrate a memory stress test program into the target chip and trigger the start of the test program by detecting the value change of the status register;

[0019] Perform cyclic read and write operations on the target memory and apply continuous pressure load to the target memory, while simultaneously performing data integrity verification;

[0020] The test process is monitored at multiple levels through the baseboard management controller, which collects test status data in real time and generates structured test data.

[0021] Optionally, before the target chip performs a stress test on the memory of the target chip and simultaneously performs a data integrity check, the method further includes:

[0022] The memory of the target chip is calibrated and verified, and after passing the verification, the memory of the target chip is stress tested.

[0023] According to a third aspect of the present disclosure, a board is provided, comprising: the memory testing system described in the first aspect.

[0024] According to a fourth aspect of the present disclosure, a server is provided, comprising the board card described in the third aspect.

[0025] The present disclosure provides a memory testing system and method, board, and server. Compared to related technologies, the present disclosure utilizes an out-of-band management unit to interact with the target chip via a preset communication interface. Out-of-band management is a management method independent of the service data channel. The out-of-band management unit sends stress test instructions to the target chip, and the target chip's execution of the memory stress test does not interfere with the normal operation of the FPGA. Because the preset communication interface and out-of-band management mechanism separate the test operation from the service data transmission, this avoids the interruption of normal service due to testing in traditional testing methods, ensuring the availability and stability of the system during the test process. The out-of-band management unit sends stress test instructions to the target chip via the preset communication interface, and the stress test instructions are generated based on a preset instruction set. This overcomes the limitation of traditional test triggers that rely on physical interface operations. The preset communication interface can be a network interface, etc., allowing remote control and automated operation. The out-of-band management unit can automatically generate and send stress test instructions based on preset rules or remote instructions, realizing remote automated test triggering. In large-scale data center environments, this eliminates the need for on-site manual operation, greatly improving testing flexibility and efficiency, and meeting the requirements of modern server operation and maintenance intelligence and automation. Through a pre-set communication interface, test data is promptly transmitted from the target chip to the out-of-band management unit, reducing delays in test result feedback. The out-of-band management unit then processes the test data to generate structured test data. This structured data, clearly formatted and categorized, contains multi-dimensional information on memory performance, such as read and write error rates and response time. This enables operations and maintenance personnel to quickly and accurately obtain memory status information, identify problems promptly, and conduct troubleshooting and repairs, eliminating the difficulties in fault location and extended repair times caused by a lack of structured data. Dynamically adjustable test intensity parameters allow the system to flexibly adjust the test load intensity based on different testing requirements and memory characteristics. Cyclic stress testing ensures continuous testing and simulates long-term high-load memory operation. By applying continuous stress, memory stability and reliability can be more comprehensively tested, identifying potential faults that might not be revealed through conventional, short-term testing. This helps identify memory problems early, improving system stability and reliability.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0028] Figure 1 A schematic structural diagram of a memory testing system provided by an embodiment of the present disclosure;

[0029] Figure 2 A schematic structural diagram of another memory testing system provided by an embodiment of the present disclosure;

[0030] Figure 3 A flowchart of a memory testing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0032] The following describes the memory testing system and method, board, and server according to the embodiments of the present disclosure with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic diagram of the structure of a memory test system provided by an embodiment of the present disclosure. The system includes: an out-of-band management unit 11, a target chip 12, and the target chip 12 is connected to a target memory 13 that needs to perform stress testing.

[0034] The out-of-band management unit 11 sends a stress test instruction to the target chip 12 through a preset communication interface. The stress test instruction includes a dynamically adjusted test intensity parameter, and the stress test instruction is generated based on a preset instruction set.

[0035] In the disclosed embodiment, the memory testing system primarily consists of an out-of-band management unit 11 and a target chip 12. The target chip 12 establishes a connection with the target memory 13 to be stress-tested. These components collaborate to achieve efficient and accurate memory testing. As one of the control cores of the entire testing system, the out-of-band management unit 11 possesses important command-issuing and data-processing capabilities. It utilizes a pre-set communication interface to enable stable and reliable communication with the target chip 12. This communication interface, designed based on a specific communication protocol, ensures accurate and efficient information transmission. The stress test instructions sent by the out-of-band management unit 11 are of great significance. These instructions are generated based on a pre-set instruction set that encompasses a variety of standardized instruction formats and parameter configuration rules, ensuring the standardization and compatibility of the instructions. Crucially, the stress test instructions include dynamically adjustable test intensity parameters. These parameters can be flexibly set based on the different characteristics of the target memory 13, the specific requirements of the application scenario, and the varying test objectives, providing a high degree of flexibility and targetedness for the subsequent testing process.

[0036] The target chip 12 performs calibration verification on the target memory 13 in response to the stress test instruction; after the calibration verification passes, a test load is applied to the target memory 13 according to the test intensity parameter and a cyclic stress test is performed.

[0037] In an embodiment of the present disclosure, after receiving the stress test instruction sent by the out-of-band management unit 11, the target chip 12 immediately responds and starts the test process. First, it performs a calibration verification operation on the target memory 13. This calibration verification process is based on a specific calibration algorithm and verification mechanism. By detecting and adjusting the various parameters of the target memory 13, it ensures that it is in the best test state, laying the foundation for subsequent accurate stress testing. Only after the calibration verification is passed, the target chip 12 will apply the corresponding test load to the target memory 13 based on the test intensity parameters. The test load is dynamically generated according to the test intensity parameters, and can simulate different degrees of working pressure, and truly reflect the performance of the target memory 13 in various actual scenarios. Subsequently, the target chip 12 performs a cyclic stress test on the target memory 13, and through multiple cyclic tests, comprehensively and in-depth detects the stability and reliability of the target memory 13.

[0038] The target chip 12 collects the test data generated during the stress test and transmits it back to the out-of-band management unit 11 through a preset communication interface. The out-of-band management unit 11 generates structured test data based on the test data.

[0039] In an embodiment of the present disclosure, during the cyclic stress test, the target chip 12 is responsible for the important task of collecting test data. It uses an internally integrated data acquisition module to monitor and collect various types of data generated during the stress test in real time. These data cover a variety of performance indicators of the target memory 13 at different test stages. After completing the data acquisition, the target chip 12 transmits the collected test data back to the out-of-band management unit 11 with the help of a preset communication interface. After receiving the test data, the out-of-band management unit 11 uses specific data processing algorithms and structured generation rules to perform in-depth processing on these data and finally generates structured test data. This structured test data is presented in a clear and standardized format, which is convenient for intuitively displaying the various performance indicators and test results of the target memory 13, and provides strong support for subsequent analysis and decision-making.

[0040] From a technical perspective, the design architecture and workflow of this memory testing system effectively overcome many of the drawbacks of traditional testing technologies. Through the collaborative work of the out-of-band management unit 11 and the target chip 12, the test process is separated from business operations, avoiding interference with normal business operations. Based on a design based on a preset communication interface and instruction set, it eliminates reliance on physical interface operations and makes remote automated testing possible. The real-time data collection and feedback mechanism, as well as the generation of structured test data, effectively resolve the issues of delayed test result feedback and lack of data structure. Dynamic adjustment of test intensity parameters and cyclic stress testing ensures continuous and effective stress testing of the target memory 13, comprehensively improving the accuracy, reliability, and efficiency of memory testing.

[0041] The present disclosure provides a memory testing system that utilizes an out-of-band management unit to interact with a target chip via a preset communication interface. Out-of-band management is a management method independent of the service data channel. The out-of-band management unit sends stress test instructions to the target chip, and the target chip's execution of the memory stress test does not interfere with the normal operation of the FPGA. Because the preset communication interface and out-of-band management mechanism make the test operation and service data transmission independent of each other, this avoids the interruption of normal service due to testing in traditional testing methods, thereby ensuring the availability and stability of the system during the testing process. The out-of-band management unit sends stress test instructions to the target chip via the preset communication interface, and the stress test instructions are generated based on a preset instruction set. This breaks away from the limitation of traditional test triggers that rely on physical interface operations. The preset communication interface can be a network interface, etc., allowing remote control and automated operation. The out-of-band management unit can automatically generate and send stress test instructions based on preset rules or remote instructions, realizing remote automated test triggering. In large-scale data center environments, no manual on-site operation is required, greatly improving the flexibility and efficiency of testing and meeting the requirements of intelligent and automated modern server operation and maintenance. Through a pre-set communication interface, test data is promptly transmitted from the target chip to the out-of-band management unit, reducing delays in test result feedback. The out-of-band management unit then processes the test data to generate structured test data. This structured data, clearly formatted and categorized, contains multi-dimensional information on memory performance, such as read and write error rates and response time. This enables operations and maintenance personnel to quickly and accurately obtain memory status information, identify problems promptly, and conduct troubleshooting and repairs, eliminating the difficulties in fault location and extended repair times caused by a lack of structured data. Dynamically adjustable test intensity parameters allow the system to flexibly adjust the test load intensity based on different testing requirements and memory characteristics. Cyclic stress testing ensures continuous testing and simulates long-term high-load memory operation. By applying continuous stress, memory stability and reliability can be more comprehensively tested, identifying potential faults that might not be revealed through conventional, short-term testing. This helps identify memory problems early, improving system stability and reliability.

[0042] Furthermore, in a possible implementation of this embodiment, as Figure 2 As shown, the target chip 12 includes: a stress test module 121 and a status register 122; the stress test module 121 monitors the value change of the status register 122; after the value change of the status register 122 reaches a preset start value, the stress test module 121 performs a stress test on the target memory 13.

[0043] Specifically, the target chip 12 integrates a stress test module 121 and a status register 122 with clear functions and mutual cooperation. The status register 122 serves as a key identification storage unit for the system's operating status and records various system status information in a specific binary code format. It is connected to the data bus and control bus inside the target chip 12 to ensure efficient data interaction with other functional modules. The stress test module 121 is the core component responsible for performing memory stress testing tasks. It establishes a close connection with the status register 122 through a specific monitoring circuit to achieve real-time monitoring of changes in the value of the status register 122. This monitoring mechanism is based on hardware logic design. When the value of one or more bits in the status register 122 changes, the stress test module 121 can quickly capture this signal.

[0044] When the value of status register 122 reaches a preset activation value, this change triggers the logic circuit within stress test module 121, causing it to enter an operational state. This preset activation value is a specific binary-coded value pre-set based on system design and test requirements. It serves as the trigger condition for the start of the stress test, ensuring the accuracy and controllability of the test startup.

[0045] The stress testing module 121 performs a comprehensive stress test on the target memory 13 based on the technical solutions of the present invention. Its testing process follows a rigorous set of logic. The stress testing module 121 calibrates and verifies the target memory 13, similar to system initialization, to ensure that the target memory 13 begins subsequent testing in a stable and testable state. This calibration and verification process includes testing and adjusting the memory's electrical characteristics and timing parameters to ensure the accuracy of the test environment.

[0046] After the calibration verification is passed, the stress test module 121 will apply a test load to the target memory 13 according to the preset test strategy and the test strength parameters obtained from the out-of-band management unit 11. There are various ways to apply the test load, such as through memory filling operations, filling the memory space according to a fixed pattern or random data to simulate the load of the memory in actual use; continuously performing high-frequency read and write operations, covering sequential access, random access, and data reversal operations to verify the data integrity and access stability of the memory unit. In this process, the stress test module 121 will also use methods such as CRC verification and data comparison to detect in real time whether data corruption or loss occurs during the reading and writing process. In some embodiments, the target chip 12 is an FPGA.

[0047] Furthermore, in a possible implementation of this embodiment, the stress testing module 121 generates a test load corresponding to each memory channel according to the test intensity parameter, applies the test load to the target memory 13 of different channels respectively and performs a cyclic stress test; the stress testing module 121 synchronously implements data integrity verification during the test process, and generates test data corresponding to each memory channel according to the verification results of each channel; the stress testing module 121 writes the test data into the status register 122, wherein each status bit segment of the status register 122 maps a different memory channel respectively, for recording the test data of the corresponding channel.

[0048] Specifically, the stress testing module 121 receives and analyzes test intensity parameters, which are sent by the out-of-band management unit 11 based on system requirements and memory characteristics. Based on these parameters, the stress testing module 121 uses its internal load generation logic to generate corresponding test loads for different channels of the target memory 13. For example, for channels with high read and write speed requirements, the stress testing module 121 increases the frequency and data volume of read and write operations to simulate high-load usage scenarios. For channels with stringent data stability requirements, more complex data patterns and verification algorithms are used for testing. After generating the test loads, the stress testing module 121 applies these loads to the target memory 13 in different channels and initiates a cyclic stress testing process. During this process, it continuously performs read and write operations on the memory channels. To ensure the reliability of the test results, the stress testing module 121 performs data integrity verification during the test. It uses various verification methods, such as a CRC checksum algorithm to verify read and write data. It also combines data comparison technology to compare data written to the memory with data read out to detect errors during data transmission and storage.

[0049] After completing a round of verification, the stress test module 121 will generate test data corresponding to each memory channel based on the verification results of each channel. These test data contain rich information, such as the number of read and write times of the channel, the number of errors, the data transmission rate, etc. By analyzing these data, the performance status of each memory channel can be accurately evaluated. Subsequently, the stress test module 121 writes these test data into the status register 122. The status register 122 is designed as a special structure, and its various status bit segments map different memory channels respectively. This mapping relationship enables the status register 122 to accurately record the test data of the corresponding channel. For example, some bits of the status register 122 are specifically used to record the error count of a certain channel, and other bits are used to record information such as the number of read and write operations of the channel.

[0050] Furthermore, in a possible implementation of this embodiment, the out-of-band management unit 11 sends a stress test instruction to modify the value of the status register 122 .

[0051] Specifically, the out-of-band management unit 11 generates a stress test instruction containing specific control information based on a preset instruction set. The instruction set follows the standardized communication protocol specification to ensure the standardization and compatibility of the instruction format so that the target chip 12 can accurately identify and parse it. The stress test instruction not only contains the basic control signal for starting the test, but also integrates rich test parameter information. These parameters are dynamically configured according to the type, performance indicators and specific test requirements of the target memory 13. The out-of-band management unit 11 sends the stress test instruction to the target chip 12 with the help of a preset communication interface. This preset communication interface adopts a specific electrical interface standard and communication protocol, such as a high-speed serial communication protocol, to ensure the accuracy and efficiency of the instruction during transmission and reduce signal interference and transmission delay.

[0052] After receiving the stress test instruction, the target chip 12 decodes the instruction through its internal instruction parsing circuit. The instruction parsing circuit extracts the control information and parameter data from the instruction according to the rules of the preset instruction set. The control information that modifies the value of the status register 122 is accurately identified and extracted.

[0053] Status register 122, a key component within target chip 12 for storing system status and test parameters, is connected to the instruction parsing circuit. When the instruction parsing circuit extracts information to modify the value of status register 122, it transmits the corresponding data signal to status register 122. Status register 122 updates its internally stored value based on the received data signal.

[0054] Different bit segments of the status register 122 are assigned specific meanings, which are used to control the test process of the target chip 12 and record the test status. For example, certain bit segments are used to identify whether the test is started, the configuration information of the test intensity parameters, and the test result status of each memory channel. The stress test instruction sent by the out-of-band management unit 11 achieves precise control of the test process of the target chip 12 by modifying the values of these bit segments. For example, by modifying the start flag bit, changing its value from the initial "0" to "1", the stress test module 121 is triggered to start testing the target memory 13; at the same time, the test intensity parameter bit segment is modified, and the corresponding value is set to a parameter value that meets the test requirements, providing a basis for the stress test module 121 to generate a suitable test load.

[0055] Furthermore, in a possible implementation of this embodiment, the cyclic stress test includes at least one of a sequential read / write mode, a random read / write mode, and a checkerboard mode.

[0056] Specifically, in the sequential read and write mode, the stress test module 121 performs continuous data write and read operations on the target memory 13 according to a specific address sequence. For example, predetermined data is written to each address unit in sequence according to the memory address from low to high, and after writing is completed, the read operation is performed according to the same address sequence. During the writing and reading process, the stress test module 121 controls the data writing and reading speed, data volume and other parameters according to the system preset rules. This mode is mainly used to detect the accuracy and stability of data transmission during sequential memory access, as well as the correctness of memory address mapping. Through the test of the sequential read and write mode, it can be found whether there are errors in the memory caused by continuous address access, such as address access errors caused by address line failures, and problems such as disordered order during data transmission.

[0057] The random read and write mode breaks the rules of sequential access. The stress test module 121 randomly generates a series of memory addresses and performs data write and read operations on these random addresses. The generation of random addresses is based on a specific random number generation algorithm to ensure the randomness and uniformity of address distribution. When performing random read and write, the written and read data will also be verified, such as using CRC verification or data comparison to detect data integrity. This mode simulates the random access scenario of memory in actual applications, and can effectively detect the random access performance of memory, and discover problems such as random address access conflicts, data loss or errors that may exist in memory. Since the random read and write mode has high requirements on the access randomness of the memory controller and storage unit, it can dig deeper into potential failure points of memory.

[0058] The checkerboard mode is a special test mode in which the stress test module 121 writes different data patterns in the memory according to a specific checkerboard pattern. Typically, different data values are written to adjacent memory address units to form a checkerboard-like distribution. For example, "0x00" is written to the odd address unit and "0xFF" is written to the even address unit. Then, these address units are read and the read data is compared to see if it is consistent with the written data. This mode can focus on detecting the interference between adjacent storage units in the memory, as well as the memory's ability to handle different data patterns. Because in actual applications, the data of adjacent storage units may affect each other, the checkerboard mode can effectively detect such potential interference problems, such as adjacent unit data errors caused by capacitive coupling.

[0059] Furthermore, in a possible implementation of this embodiment, the out-of-band management unit 11 sends an immediate status query instruction or a log acquisition instruction to the target chip 12 through a preset communication interface to obtain test data, wherein the immediate status query instruction and the log acquisition instruction are generated based on a preset instruction set.

[0060] Specifically, as one of the control cores of the test system, the out-of-band management unit 11 needs to understand the test progress and status information of the target memory 13 in real time during the test process, as well as obtain detailed test data for subsequent analysis. To this end, it generates instant status query instructions or log acquisition instructions based on a preset instruction set. The preset instruction set is a set of standardized and normalized instruction rules that clearly defines the format and encoding method of the instructions, as well as the meaning and range of the parameters carried by the instructions, ensuring the accuracy and consistency of the instructions transmitted between the out-of-band management unit 11 and the target chip 12.

[0061] After generating the instruction, the out-of-band management unit 11 sends the instruction to the target chip 12 through a preset communication interface. The preset communication interface is a specially designed communication channel that transmits data based on a specific communication protocol, such as a high-speed, reliable serial communication protocol, to ensure that the instruction reaches the target chip 12 quickly and accurately while effectively avoiding interference and errors during the data transmission process.

[0062] After receiving the instruction, the target chip 12's internal instruction parsing circuit will parse the real-time status query instruction or log acquisition instruction according to the preset instruction set. If the instruction received is a real-time status query instruction, the instruction parsing circuit will recognize that the function of the instruction is to query the real-time status information of the current test, and then extract the corresponding data from the relevant registers and storage units. This data may include information such as the current working status of the stress test module 121, the test progress of each memory channel, whether an error has occurred, and the type of error. This real-time status data is usually stored in the status register or a specific cache area inside the target chip 12 and is closely related to the memory test process.

[0063] If a log acquisition instruction is received, the instruction parsing circuit will start the log generation and transmission process. During the stress test, the target chip 12 will continuously record detailed test-related data, such as the number of read and write times of each memory channel, the timestamp of each read and write operation, the data transmission rate, the time and location of the error, and other information, and store it in the internal memory according to a specific log format. After receiving the log acquisition instruction, the target chip 12 will organize and package the stored test log data and transmit it back to the out-of-band management unit 11 through the preset communication interface.

[0064] Figure 3 A flowchart of a memory testing method provided in an embodiment of the present disclosure.

[0065] like Figure 3 As shown, the method comprises the following steps:

[0066] Step 201: Integrate a memory stress test program into the target chip, and trigger the start of the test program by detecting the value change of the status register.

[0067] Specifically, a memory stress test program is integrated into the target chip during its design and construction. This program, written based on specific algorithms and logic, performs a comprehensive stress test on the target memory. The target chip contains a status register, a key storage unit for system status information, recording various system status indicators in binary format. The status register is tightly connected to the target chip's data and control buses, ensuring efficient data exchange with other functional modules.

[0068] The triggering conditions for starting the memory stress test program rely on monitoring changes in the status register value. During the system initialization phase, the status register is assigned a specific initial value. When an external control signal or a specific event occurs within the system, the status register value changes accordingly. The memory stress test program monitors the status register value changes in real time through a hardware logic monitoring circuit. Once the status register value change reaches the preset trigger threshold, it is determined that the test program startup conditions have been met. At this point, the hardware logic monitoring circuit sends a start signal to the memory stress test program, triggering the test program to start. This triggering mechanism based on status register value changes ensures the accuracy and controllability of the test program startup, avoids the test program from starting inadvertently, and provides a reliable prerequisite for subsequent testing processes.

[0069] Step 202 : cyclically read and write operations are performed on the target memory, a continuous pressure load is applied to the target memory, and data integrity verification is performed simultaneously.

[0070] Specifically, in terms of cyclic read and write operations, the test program operates on the target memory according to a pre-set read and write mode. The read and write modes include sequential read and write and random read and write. In the sequential read and write mode, the test program writes and reads data to the memory cells in sequence according to the order of the memory addresses. For example, starting from the starting address of the memory, a specific data pattern, such as all "0" or all "1", is written to each memory cell one by one in the order of increasing address values, and then the data is read in the same address sequence, and the read data is compared with the written data to detect the accuracy of data transmission. The random read and write mode generates a series of random memory addresses through a random number generation algorithm, and performs data write and read operations on these random addresses to simulate the random access scenario of memory in actual applications to detect the random access performance and data processing capabilities of the memory.

[0071] To more realistically simulate the target memory's actual operating environment, the test program applies a continuous stress load to the target memory. This process writes large amounts of data to the target memory, placing it under high load. The amount and speed of data writes are set based on the target memory's specifications and test requirements, aiming to achieve a level close to or exceeding its normal operating load, thereby testing the memory's stability and reliability.

[0072] Data integrity checks are performed simultaneously during cyclic read and write operations and the application of a continuous stress load. The test program uses various verification methods to ensure data accuracy, such as the CRC (Cyclic Redundancy Check) algorithm and data comparison technology. The CRC algorithm generates a checksum by performing specific mathematical operations on the written and read data. When the data is read, the checksum is recalculated and compared with the checksum used when writing. If the two do not match, an error has occurred during data transmission or storage. Data comparison technology compares the data written to memory with the data read bit by bit to directly detect any changes. This simultaneous data integrity verification mechanism can promptly detect errors that occur during memory read and write operations, ensuring the reliability of test results.

[0073] Step 203: Perform multi-level monitoring of the test process through the baseboard management controller, collect test status data in real time, and generate structured test data.

[0074] Specifically, the BMC monitors the test process at multiple levels and dimensions. At the hardware level, the BMC monitors physical parameters such as the target chip's operating voltage and temperature to ensure it operates within normal operating conditions and avoid inaccurate test results due to hardware anomalies. At the test process level, the BMC tracks the execution progress of the memory stress test program in real time, including information such as the number of read and write cycles, the stress load applied, and the results of data integrity checks. The BMC collects this test status data in real time and, using specific data processing algorithms and structured generation rules, converts the collected raw data into structured test data. Structured test data is presented in a clear and standardized format, facilitating subsequent analysis and processing. For example, test information such as timestamps, memory addresses, read and write operation types, and data verification results are organized according to a specific logical structure to form easy-to-understand and easy-to-analyze data tables or documents. This structured data processing approach makes test data management and analysis more efficient, providing strong support for subsequent fault diagnosis and performance optimization.

[0075] The present disclosure provides a memory testing method that utilizes an out-of-band management unit to interact with a target chip via a preset communication interface. Out-of-band management is a management method independent of the service data channel. The out-of-band management unit sends stress test instructions to the target chip, and the target chip's execution of the memory stress test does not interfere with the normal operation of the FPGA. Because the preset communication interface and out-of-band management mechanism make the test operation and service data transmission independent of each other, this avoids the interruption of normal service due to testing in traditional testing methods, thereby ensuring the availability and stability of the system during the test process. The out-of-band management unit sends stress test instructions to the target chip via the preset communication interface, and the stress test instructions are generated based on a preset instruction set. This breaks away from the limitation of traditional test triggers that rely on physical interface operations. The preset communication interface can be a network interface, etc., allowing remote control and automated operation. The out-of-band management unit can automatically generate and send stress test instructions based on preset rules or remote instructions, realizing remote automated test triggering. In large-scale data center environments, no manual on-site operation is required, greatly improving the flexibility and efficiency of testing and meeting the requirements of intelligent and automated modern server operation and maintenance. Through a pre-set communication interface, test data is promptly transmitted from the target chip to the out-of-band management unit, reducing delays in test result feedback. The out-of-band management unit then processes the test data to generate structured test data. This structured data, clearly formatted and categorized, contains multi-dimensional information on memory performance, such as read and write error rates and response time. This enables operations and maintenance personnel to quickly and accurately obtain memory status information, identify problems promptly, and conduct troubleshooting and repairs, eliminating the difficulties in fault location and extended repair times caused by a lack of structured data. Dynamically adjustable test intensity parameters allow the system to flexibly adjust the test load intensity based on different testing requirements and memory characteristics. Cyclic stress testing ensures continuous testing and simulates long-term high-load memory operation. By applying continuous stress, memory stability and reliability can be more comprehensively tested, identifying potential faults that might not be revealed through conventional, short-term testing. This helps identify memory problems early, improving system stability and reliability.

[0076] Furthermore, in a possible implementation of this embodiment, before the target chip performs stress testing on the target chip's memory and simultaneously performs data integrity verification, the method also includes: calibrating and verifying the target chip's memory, and stress testing the target chip's memory after the verification passes.

[0077] Specifically, calibration and verification of the target chip's memory is performed based on a specific calibration algorithm and verification process. During the calibration phase, the first task is to initialize the memory's physical layer (PHY). This process involves configuring various physical circuits and signal links within the memory chip, such as adjusting the clock signal's frequency and phase and setting the voltage threshold for data transmission, to ensure the memory hardware environment is stable and suitable for testing. After PHY initialization, clock training is performed. Because memory read and write operations require extremely high clock signal stability and accuracy, clock training optimizes clock signal quality to meet the requirements of high-speed memory read and write operations and reduces data transmission errors caused by clock skew. Data eye diagram calibration is also a crucial component of calibration and verification. The data eye diagram provides a visual representation of data signal quality. By calibrating the data eye diagram, parameters such as signal amplitude, rising and falling edges can be adjusted to ensure a clearer and more stable data signal, improving data transmission reliability.

[0078] After completing the calibration steps, the verification phase begins. This process primarily involves sending specific test data patterns and analyzing the data returned by the memory to determine if the memory is functioning properly. For example, a series of known data combinations are written to the memory, then read back the data and compare the read results with the original written data to ensure consistency. If the data matches perfectly and all calibration parameters are within reasonable ranges, the calibration verification is considered successful.

[0079] It should be noted that the embodiments of the present disclosure may include multiple steps. For the convenience of description, these steps are numbered, but these numbers do not limit the execution time slots or execution order between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not limit this.

[0080] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] The above is a detailed introduction to the system and method, board and server for memory testing provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory testing system, characterized in that: The system includes: an out-of-band management unit and a target chip, wherein the target chip is connected to a target memory that needs to perform a stress test; The out-of-band management unit sends a stress test instruction to the target chip through a preset communication interface, wherein the stress test instruction includes a dynamically adjusted test intensity parameter and is generated based on a preset instruction set; The target chip performs calibration verification on the target memory in response to the stress test instruction; after the calibration verification passes, applies a test load to the target memory according to the test intensity parameter and performs a cyclic stress test; The target chip collects test data generated during the stress test and transmits the data back to the out-of-band management unit through the preset communication interface. The out-of-band management unit generates structured test data based on the test data.

2. The memory testing system according to claim 1, wherein: The target chip includes: a stress test module and a status register; The stress test module monitors the value change of the status register; After the value of the status register changes to a preset startup value, the stress test module performs a stress test on the target memory.

3. The memory testing system according to claim 2, wherein: The stress test module generates a test load corresponding to each memory channel according to the test intensity parameter, applies the test load to the target memory of different channels respectively, and performs a cyclic stress test; The stress test module synchronously performs data integrity verification during the test process and generates test data corresponding to each memory channel according to the verification results of each channel; The stress test module writes the test data into a status register, wherein each status bit segment of the status register is mapped to a different memory channel for recording the test data of the corresponding channel.

4. The memory testing system according to claim 2, wherein: The out-of-band management unit sends the stress test instruction to modify the value of the status register.

5. The memory testing system according to claim 1, wherein: The cyclic stress test includes at least one of a sequential read / write mode, a random read / write mode, and a checkerboard mode.

6. The memory testing system according to claim 1, wherein: The out-of-band management unit sends an immediate status query instruction or a log acquisition instruction to the target chip through the preset communication interface to acquire the test data, wherein the immediate status query instruction and the log acquisition instruction are generated based on the preset instruction set.

7. A memory testing method, characterized in that: The method is applied to the memory test system according to any one of claims 1 to 6, and the method includes: Integrate a memory stress test program into the target chip and trigger the start of the test program by detecting the value change of the status register; Performing cyclic read and write operations on the target memory and applying a continuous stress load to the target memory, and simultaneously performing a data integrity check; The test process is monitored at multiple levels through the baseboard management controller, which collects test status data in real time and generates structured test data.

8. The memory testing method according to claim 7, characterized in that: Before the target chip performs a stress test on the memory of the target chip and simultaneously performs a data integrity check, the method further includes: Calibration verification is performed on the memory of the target chip, and after verification passes, stress testing is performed on the memory of the target chip.

9. A board, characterized in that: The board includes: a memory testing system according to any one of claims 1 to 6.

10. A server, characterized in that: The server comprises the board according to claim 9.

Images