Method for preventing PCIe switch internal link state from being recognized abnormally by OS

Abstract

The invention discloses a method for preventing a PCIe switch internal link state from being recognized to be abnormal by an OS, and relates to the field of link state recognition anomalies, a high-risk link is recognized by obtaining a historical data set, configuration processing and algorithm optimization are carried out, an injection verification mirror image is obtained, and accurate link training control analysis is carried out based on the injection verification mirror image, so that the reliability of the PCIe switch internal link state is improved. Carrying out intelligent topology mapping management on the final link stability score to obtain an optimized topology; carrying out anomaly detection and hierarchical response control on the optimized topology to obtain a response action set; and carrying out repair or degradation processing on the link based on the response action set. And finally, the link state and the topological structure are updated according to the processing result to obtain a repair result and the updated topological structure, so that the high-risk link can be identified, the OS link state can be accurately judged, the system availability is improved, the misjudgment risk is reduced, and a dynamic degradation and active repair mechanism based on the actual risk levels (high, medium and low stability) of the link is provided.

Description

Technical Field

[0001] The present invention relates to the field of link status abnormality recognition, and in particular to a method for preventing an OS from recognizing abnormalities in a PCIe switch internal link status. Background Art

[0002] In data centers and computing devices, PCIe switch chips are responsible for high-speed interconnection. However, existing technical solutions have obvious shortcomings when dealing with abnormal PCIe link status:

[0003] Existing anomaly identification methods rely on the OS to directly access and manage the PCIe configuration space. When the internal link of a PCIe switch becomes temporarily unstable due to environmental fluctuations (such as temperature and noise) or hardware compatibility issues, the OS driver layer directly perceives the register state anomaly (such as training failure or rate negotiation degradation). This often causes the OS to misidentify the link as "faulty" or "device lost," leading to unnecessary device resets, driver reloads, and even system blue screens and crashes, severely impacting system availability and increasing the risk of misjudgment.

[0004] At the same time, existing methods often respond to link anomalies in a simplistic manner. They either downgrade the entire link to its lowest speed (e.g., GEN1), significantly sacrificing performance, or simply disable the link, rendering the device unavailable. These methods lack a dynamic downgrade and proactive repair mechanism based on the link's actual risk level (high, medium, or low stability), failing to meet current demands for PCIe switch chips.

[0005] In order to solve the above-mentioned defects, a technical solution is now provided. Summary of the Invention

[0006] In order to solve the technical problems raised by the above background technology, the present invention is proposed. An embodiment of the present invention provides a method for preventing the internal link status of a PCIe switch from being abnormally recognized by the OS.

[0007] The object of the present invention can be achieved by the following technical solution: A method for preventing the internal link status of a PCIe switch from being abnormally recognized by the OS, comprising the following steps:

[0008] Step S100: Identify high-risk links by acquiring historical data sets, perform configuration processing, and optimize algorithms to obtain an injection verification image;

[0009] Step S200: performing precise link training control analysis based on the injected verification image to obtain a final link stability score;

[0010] Step S300: performing intelligent topology mapping management on the final link stability score to obtain an optimized topology;

[0011] Step S400: performing anomaly detection and hierarchical response control on the optimized topology to obtain a response action set;

[0012] Step S500: Repair or degrade the link based on the response action set, and finally update the link state and topology structure according to the processing result to obtain a repair result and an updated topology structure.

[0013] Furthermore, the injection verification image is analyzed as follows:

[0014] The capability registers of all links in the high-risk link set are forcibly configured to the GEN1 configuration mask to obtain the capability registers. The control registers of all links in the high-risk link set are forcibly configured to the forced training configuration to obtain the control registers. Based on the forced configuration of the capability registers and control registers, a sequential quadratic programming algorithm is used to solve the optimization function for the actual negotiated rate. The bit error rate limit of the chip's built-in BIST circuit is ensured to meet the reliability threshold to obtain the optimal configuration vector.

[0015] The basic firmware image is loaded from the read-only storage area preset at the factory of the chip. The security chip generates a signature key based on the P-256 elliptic curve. Based on the basic firmware image, signature key and optimal configuration vector, the injection function is used to execute the operations of writing the configuration to the PCIe space, generating the ECDSA signature key and writing it into the verification area to obtain the injection verification image.

[0016] Furthermore, the high-risk link set is analyzed as follows:

[0017] The operating system name is read from the device system information and converted into a numerical code based on preset mapping rules to obtain the operating system type code. The CPU manufacturer and main accelerator type are extracted from the device hardware information and a unique hardware combination code is generated based on preset combination rules. The operating temperature is read in real time through the sensor of the PCIe switch chip, and the temperature interval code is obtained by dividing the temperature into intervals according to the discretization rules and assigning codes to each interval. The number of historical exceptions is counted based on the unique device ID from the PCIe link layer error records in the device exception log database.

[0018] Based on the operating system type code, unique hardware combination code, temperature range code and historical anomaly count, an anomaly probability prediction model is created and weighted linear combination and logical function conversion are performed to obtain a set of high-risk links.

[0019] Furthermore, the final link stability score is analyzed as follows:

[0020] An oscilloscope is used to measure the difference between the high and low levels of the signal to obtain the signal swing. During the link training phase, the transmitter and receiver exchange TS ordered sets and negotiate and analyze them to obtain the pre-emphasis level. The signal swing, pre-emphasis level, and TS sequence interval adjustment are integrated according to the protocol specification to obtain a structured training parameter package.

[0021] The operating system risk factor, hardware performance level, and hardware performance level are extracted from the secure boot record to obtain the environmental adjustment parameters. The weights of each parameter in the structured training parameter package are dynamically calculated based on the environmental adjustment parameters to obtain the initial stability score. The initial stability score is constrained by boundary constraints to obtain the final link stability score.

[0022] Furthermore, the TS sequence interval adjustment amount is analyzed as follows:

[0023] The signed SBR image and ECDSA signature key are digitally verified and unsealed through hardware call functions to obtain the valid register values.

[0024] Normalize the effective register values according to the maximum configuration range to obtain the configuration adjustment vector. Count the proportion of bit error rates less than the bit error rate reliability threshold in n times to obtain the link stability.

[0025] Enable the power management unit and set the sampling mode to every microsecond to collect voltage signals and calculate deviations to obtain power supply noise. Activate the phase-locked loop and clock jitter analysis functions. The phase-locked loop monitors the clock signal and obtains the clock offset through the phase difference statistical algorithm.

[0026] A state transition probability model is constructed based on the configuration adjustment vector, link stability, power supply noise, and clock offset. This model is linearly combined and processed with an activation function to obtain the state transition probability.

[0027] Based on the state transition probability, the probability of traversing the state pairs is calculated, and a matrix is constructed to obtain the state transition matrix;

[0028] Extract the specific state transition probability based on the state transition matrix to obtain the target state probability;

[0029] The target state probability is adjusted proportionally and integrally through the adaptive training controller formula to obtain the TS sequence interval adjustment amount.

[0030] Furthermore, the optimized topology analysis is as follows:

[0031] Perform visibility decisions based on the final link stability scores to obtain a complete topology map;

[0032] Based on the visibility flag in the topology mapping table, a shadow register mapping table is obtained through a dual register mapping function;

[0033] The dynamic topology filter obtains the shadow register mapping table and performs three levels of hardware-level operations to obtain the optimized topology structure.

[0034] Furthermore, the response action set is analyzed as follows:

[0035] Based on the optimized topology, different data collection strategies are implemented for different links. The frequency deviation risk quantification model based on link stability classification is used to obtain the abnormality score of each link.

[0036] Perform link-level operations on the abnormal score values of each link to obtain the response action set of each link.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] 1. The present invention obtains historical data sets to identify high-risk links, performs configuration processing and algorithm optimization, and obtains an injection verification image. Based on the injection verification image, precise link training control analysis is performed to obtain a final link stability score. The final link stability score is then intelligently mapped and managed to obtain an optimized topology. Anomaly detection and hierarchical response control are then performed on the optimized topology to obtain a response action set. When the internal links of the PCIe Switch become temporarily unstable due to environmental fluctuations (such as temperature and noise) or hardware compatibility issues, the OS can identify the high-risk links and accurately determine the OS link status, thereby improving system availability and reducing the risk of misjudgment.

[0039] 2. The present invention repairs or downgrades the link based on the response action set, and finally updates the link status and topology structure according to the processing results to obtain the repair result and updated topology structure. It also has a dynamic degradation and active repair mechanism based on the actual risk level of the link (high, medium, and low stability). It can meet the current demand for PCIe Switch chips, ensure system compatibility, and maximize hardware performance, allowing the device to run smoothly. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. The following drawings are not intentionally scaled to the actual size, and the focus is on illustrating the main purpose of the present invention.

[0041] Figure 1 is a flow chart of the method of the present invention;

[0042] Figure 2 This is a flow chart of step S300 of the present invention. DETAILED DESCRIPTION

[0043] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts also fall within the scope of protection of the present invention.

[0044] like Figure 1 As shown, a method for preventing the OS from identifying abnormal link status within a PCIe switch includes the following steps:

[0045] Step S100: Identify high-risk links by acquiring historical data sets, perform configuration processing, and optimize algorithms to obtain an injection verification image;

[0046] Step S200: performing precise link training control analysis based on the injected verification image to obtain a final link stability score;

[0047] Step S300: performing intelligent topology mapping management on the final link stability score to obtain an optimized topology;

[0048] Step S400: performing anomaly detection and hierarchical response control on the optimized topology to obtain a response action set;

[0049] Step S500: Repair or degrade the link based on the response action set, and finally update the link state and topology structure according to the processing result to obtain a repair result and an updated topology structure.

[0050] Specifically, step S100 is analyzed as follows:

[0051] The operating system name is read from the device system information and converted into a numerical code based on the preset mapping rules to obtain the operating system type code. The CPU manufacturer and main accelerator type in the device hardware information are extracted and a unique hardware combination code is generated according to the preset combination rules. The operating temperature is read in real time through the sensor of the PCIe switch chip, and the temperature interval code is obtained by dividing the temperature interval into intervals according to the discretization rules and assigning codes to each interval. The PCIe link layer error records in the device abnormality log database are used to count the number of historical abnormalities according to the device's unique ID. The operating system type code, unique hardware combination code, temperature interval code, and historical abnormality count are marked as a historical data set.

[0052] Based on the operating system type code, unique hardware combination code, temperature range code, and historical anomaly count, an anomaly probability prediction model is created and weighted linear combination and logic function conversion are performed to obtain a set of high-risk links;

[0053] Specifically, the system reads the operating system name, such as Windows, Linux, or VMware, from the device system information and converts it into a numerical code according to a preset mapping rule: Windows corresponds to code 1, Linux corresponds to code 2, and VMware corresponds to code 3. This code reflects the differences in driver compatibility between different operating systems with the PCIe link. The system also extracts the CPU manufacturer (such as Intel or AMD) and main accelerator type (such as NVIDIA GPU or AMD GPU) from the device hardware information and generates a unique numerical code according to a preset combination rule. For example, the combination of NVIDIA GPU and Intel CPU corresponds to code 101, and the combination of NVIDIA GPU and AMD CPU corresponds to code 102. This code reflects the impact of this hardware combination on PCIe link bandwidth and stability. The operating temperature is read in real time by the PCIe switch chip's sensor and divided into intervals according to a discretization rule: code 0 is assigned for temperatures below 40°C, code 1 is assigned for temperatures between 40°C and 60°C, and code 2 is assigned for temperatures above 60°C. This code quantifies the risk of high temperature-related link signal degradation. The PCIe link layer error records (such as link training failure or CRC check error) that occurred in the past 12 months are filtered from the device anomaly log database. The total number of anomalies is counted by the device unique ID. This value is used to predict the probability of future link anomalies based on the historical failure frequency. The anomaly probability prediction model includes: Among them, P a represents the probability of link anomaly, OS, HW, ΔT, and Em represent the operating system type code, unique hardware combination code, temperature range code, and historical anomaly count. α, β, χ, and δ represent weight coefficients. A calculated result threshold > 0.75 is defined as high risk, and the high-risk link set is obtained.

[0054] The capability registers of all links in the high-risk link set are forcibly configured to the GEN1 configuration mask to obtain the capability registers. The control registers of all links in the high-risk link set are forcibly configured to the forced training configuration to obtain the control registers. Based on the forced configuration of the capability registers and control registers, a sequential quadratic programming algorithm is used to solve the optimization function for the actual negotiated rate. The bit error rate limit of the chip's built-in BIST circuit is ensured to meet the reliability threshold to obtain the optimal configuration vector.

[0055] Specifically, the formulas involved above are:

[0056]

[0057] subject to

[0058] LinkCapReg=GEN1_MASK

[0059] LinkCtrlReg=TRAINING_FORCE_GEN1

[0060] BER(Rc)<10 -12

[0061] Among them, minimize means to make the subsequent objective function value reach the minimum variable value, L risk Represents a set of high-risk links. ID represents a link identifier, distinguishing between different links within a PCIe switch, such as iDP0 and iUP1, following specific naming conventions. iDP generally represents an internal downlink port, and iUP represents an internal uplink port. These identifiers enable the location and management of PCIe links. Link status monitoring and parameter optimization (such as register configuration adjustments for links in the high-risk link set) accurately identify the corresponding links, ensuring accurate link management and optimization in the PCIe system. Rc represents the actual negotiated rate, output in real time by the PCIe LTSSM (Link Training and State Machine), reflecting the actual transmission rate level of the link. GEN5 represents the target rate defined in the PCIe 5.0 specification. LinkCapReg represents the capability register. GEN1_MASK represents the GEN1 configuration mask, which is used to force link training to start at 2.5 GT / s according to the PCIe specification. LinkCtrlReg represents the control register. TRAINING_FORCE_GEN1 represents the forced training configuration, which controls the PCIe link training process according to a specific GEN1 mode. to represents the constraint condition, BER represents the bit error rate, which is obtained through the built-in BIST (built-in self-test) circuit of the chip. This circuit detects the data during the link transmission at a sampling frequency of every millisecond, calculates the proportion of erroneous data, and obtains the bit error rate value. -12 Indicates the bit error rate reliability threshold. It is obtained by using the capability register configuration (LinkCapReg), the control register configuration (LinkCtrlReg), and the bit error rate threshold (BER_Threshold) through the sequential quadratic programming algorithm to obtain the optimal configuration vector for optimizing PCIe link-related configurations.

[0062] The basic firmware image is loaded from the read-only storage area preset at the factory on the chip. The security chip generates a signature key based on the P-256 elliptic curve. Based on the basic firmware image, signature key, and optimal configuration vector, the injection function writes the configuration to the PCIe space, generates the ECDSA signature key, and writes it into the verification area to obtain the injection verification image.

[0063] Specifically, the above formula: SBR′=f inje (SBRbase ,R cf , K ecds ), where SBR′ represents the injection verification image, SBR base Represents the basic firmware image, which is preset by the chip when it leaves the factory and is generally stored in the read-only storage area of the chip. During the device startup loading phase, it can be directly read from the read-only storage area as the basis for subsequent security injection operations. cf represents the optimal configuration vector, K ecds Represents the signature key, provided by the security chip and generated based on the P-256 elliptic curve, f inje It represents the injection function. Based on the optimal configuration vector, it accurately writes the configuration information such as the link capability register and control register into the corresponding address space of the PCIe bus (0x0C, 0x10, etc.), completes the hardware configuration initialization, and calls the ECDSA signature key provided by the security chip to generate a digital signature for the basic firmware image and configuration data.

[0064] Specifically, step S200 is analyzed as follows:

[0065] The signed SBR image and ECDSA signature key are digitally verified and unsealed through hardware call functions to obtain the effective register values. act =f load (SBR′,K ecds ), where Config act Indicates the effective register value, f load Represents the secure loading function, which uses the ECDSA signature key to verify the authenticity of the ECDSA signature of the signed SBR image. From the verified image, it extracts and activates the optimal configuration vector. The hardware automatically overwrites the control register and capability register with the unsealed parameters to obtain the effective register values.

[0066] Normalize the effective register values according to the maximum configuration range to obtain a configuration adjustment vector. Specifically, obtain the currently effective link capability register value LinkCapReg and link control register value LinkCtrlReg from the hardware, find the maximum values that can be set for the link capability register and the maximum value that can be set for the link control register, divide the effective values of the link capability register and the link control register by their respective maximum values, and combine them to obtain the configuration adjustment vector.

[0067] Count the proportion of bit error rates less than the bit error rate reliability threshold in n times to obtain the link stability;

[0068] Enable the power management unit and set the sampling mode to every microsecond to collect voltage signals and calculate deviations to obtain power supply noise. Activate the phase-locked loop and clock jitter analysis functions. The phase-locked loop monitors the clock signal and obtains the clock offset through the phase difference statistical algorithm.

[0069] Specifically, turn on the power management unit (PMU), set the sampling mode every microsecond in the PMU, collect power supply voltage signal data, and calculate the deviation between the collected voltage data and the reference value to obtain power supply noise; activate the phase-locked loop (PLL) and clock jitter analysis function, the PLL continuously monitors the input and output clock signals, the clock jitter analysis module synchronously collects the edge, phase and other information of the clock signal, and calculates the offset of the clock signal through the phase difference statistical algorithm to obtain the clock offset and link stability. I represents the indicator function, which takes 1 if the condition is met and 0 if it is not met. i is the statistical number of times;

[0070] The state transition probability model is constructed by linear combination and activation function processing of the configuration adjustment vector, link stability, power supply noise and clock offset to obtain the state transition probability. Specifically, P tra =σ(C cfg (ω1×V noi +ω2×T ske +ω3×H stab )+b), where P tra represents the state transition probability, C cfg represents the configuration adjustment vector, T ske Indicates clock skew, V noi represents power supply noise, ω1, ω2, ω3 represent weight coefficients, b represents bias, and σ represents activation function, such as Sigmoid;

[0071] Based on the state transition probability, the probabilities of state pairs are calculated and a matrix is constructed to obtain the state transition matrix. Specifically, all states of the PCIe LTSSM are identified (for example, five states). For each pair of "current state → next state" combinations, the link is in the current state, the effective configuration and real-time monitoring data are input, and the model is used to calculate the probability of transitioning from the current state to the next state. These probability values are then filled in the corresponding positions. Finally, a matrix that can fully describe the transition rules of the state machine is obtained, where the sum of the probabilities of each row in the matrix is 1, resulting in the state transition matrix.

[0072] Based on the state transition matrix, the specific state transition probability is extracted to obtain the target state probability. The specific specific state represents Configuration.Link. Configuration.Link is a specific state in the PCIe link training process. It represents the stage where the link completes preliminary negotiation and enters the stage of configuring link-related parameters. It is an important boundary state for the link to transition from the initial state to the normal data transmission state.

[0073] The target state probability is adjusted proportionally and integrally through the adaptive training controller formula to obtain the TS sequence interval adjustment amount. The specific adaptive training controller formula is:

[0074] Δt TS Indicates the TS sequence interval adjustment amount, dynamically controls the TS1 / TS2 sending interval, Kp represents the proportional gain, P Start represents the target state probability, Ki represents the integral gain, τ is the integral variable,

[0075] An oscilloscope is used to measure the difference between the high and low levels of the signal to obtain the signal swing. During the link training phase, the pre-emphasis level is determined through analysis of the TS1 / TS2 ordered set exchanged between the transmitter and receiver. The signal swing, pre-emphasis level, and TS sequence interval adjustment amount are integrated according to the protocol specification to obtain a structured training parameter package.

[0076] Specifically, an oscilloscope is used to measure the difference between the high and low levels of the signal to obtain the signal swing. During the link training phase, the transceiver exchanges TS1 / TS2 ordered sets for negotiation, and a signal analyzer is used to analyze the high-frequency components to determine the pre-emphasis level. The signal swing, pre-emphasis level, and TS sequence interval adjustment amount are configured in a configuration table based on the mapping relationship between register addresses and parameter values according to the PCIe protocol specification, thereby obtaining a structured training parameter package containing the signal swing, pre-emphasis level, and TS sequence interval adjustment amount.

[0077] Extract the operating system risk factor, hardware performance level, and hardware performance level from the secure boot record to obtain the environment adjustment parameters. Dynamically calculate the parameter weights of the structured training parameter package based on the environment adjustment parameters to obtain the initial stability score. Constrain the initial stability score through boundary constraints to obtain the final link stability score.

[0078] Specifically, the operating system risk coefficient (corresponding to the historical abnormality probability of the operating system), hardware performance level (according to the chip specification classification, the energy efficiency ratio is in the range of KY1, KY2, KY3 and KY4, corresponding to level 1 (basic level), level 2 (mainstream level), level 3 (high performance level) and level 4 (flagship level)) and current temperature code (0 is low temperature, 1 is normal temperature, 2 is high temperature, the temperature classification level determination interval is XT1, XT2 and XT3, corresponding to low temperature, medium temperature and high temperature respectively) are extracted from the secure boot record (SBR) as environmental parameters, and structured training is dynamically calculated based on the environmental parameters. The weight coefficients of each parameter in the parameter package, where the weight of the time series interval is obtained by dividing the historical anomaly probability by 10, the weight of the signal amplitude is directly mapped through the hardware level, and the weight coefficients of levels 1-4 correspond to a1, a2, a3 and a4 respectively. The weight of the pre-emphasis is directly mapped through temperature encoding, and 0-2 encoding corresponds to b1, b2 and b3. The actual value of the training parameter is multiplied by the corresponding weight, and the basic offset is added to obtain the initial stability score. Finally, the initial stability score is ranged from 0 to 100 points through boundary constraints. The specific boundary constraints are full marks for more than 100 points and zero points for less than 0 points.

[0079] like Figure 1 Specifically, step S300 is analyzed as follows:

[0080] Perform visibility decisions based on the final link stability scores to obtain a complete topology map;

[0081] Based on the visibility flag in the topology mapping table, a shadow register mapping table is obtained through a dual register mapping function;

[0082] The dynamic topology filter obtains the shadow register mapping table and performs three hardware-level operations to obtain the optimized topology structure;

[0083] Specifically, the visibility flag is determined according to the final link stability score. Specifically, when the final link stability score is lower than 50 points, it is determined to be a low stability link, and the corresponding flag value is 0. It needs to be completely hidden to avoid misidentification by the operating system. When the final link stability score is between 50 and 75 points, it is determined to be a medium stability link, and the corresponding flag value is 1. It needs to be modified to a PCIe bridge device and fixedly report the GEN3 rate. When the final link stability score is higher than 75 points, it is determined to be a high stability link, and the corresponding flag value is 2, allowing the reporting of the actual negotiated rate. The switch hardware obtains the physical addresses of the internal downlink ports (iDP) and uplink ports (iUP). Each port pair (such as iDP0-iUP0) is uniquely identified by a code. The port code is bound to the visibility flag to create a "port pair-flag value" triplet data structure (for example, {iDP0, iUP0, 1}). After obtaining all virtual links within the chip, all triplets are collected to form a complete topology mapping table. The dual register mapping function is as follows: for links marked as high stability, the actual values of the physical registers (such as the link status register and capability register) are directly read to reflect physical characteristics such as the GEN5 rate. For medium stability links, the predefined GEN3 rate mask value (0x0008) is written to the shadow register. For low stability links, the invalid flag value (0xFFFF) is set. The shadow register values of various links are obtained. All links are traversed to obtain the shadow register mapping table, which reflects the shadow register value corresponding to each link.

[0084] Specifically, the third-level hardware-level operation is to modify the device ID and manufacturer ID of the PCIe configuration space to 0xFFFF when an invalid identification value (0xFFFF) is detected, so that the operating system can completely ignore the device during detection. When the value is the GEN3 mask (0x0008), the device header type is adjusted to PCIe bridge (0x01), and the category code is set to bridge device (0x0604), so that the operating system can identify it as a general bridge device. When the value is a valid physical register value, the _DSM control method is injected into the ACPI table, which can return the actual rate value stored in the shadow register to obtain the optimized PCIe topology structure.

[0085] Specifically, step S400 is analyzed as follows:

[0086] Based on the optimized topology, different data collection strategies are implemented for different links. The frequency deviation risk quantification model based on link stability classification is used to obtain the abnormality score of each link.

[0087] Specifically, different data collection strategies are as follows: for highly stable links, the LTSSM status register (0x1A) and rate negotiation register (0x12) are scanned once within a certain period of time (every 5 seconds); for medium stable links, the bit error rate counter (0x28) and training state machine register (0x30) are monitored every 500 milliseconds within a certain period of time (every 500 milliseconds); for low stable links, the parameter data of the voltage sensor, temperature sensor, bit error rate counter and eye diagram monitoring register are collected within a certain period of time (every 10 milliseconds), with special attention paid to low stable links; the frequency deviation risk quantification model for link stability classification means that when a highly stable link detects an illegal state (such as Detect.Quiet of 0x01), it is marked as a Class A anomaly, and the actual number of Class A anomalies (such as detecting the Detect.Quiet state) per unit time is calculated. If the actual occurrence frequency exceeds the set threshold of c1 times per hour, the score increases by (actual frequency - c1) / c2. If the BER of a medium-stable link exceeds the bit error rate reliability threshold or the training state stagnates for more than 30 seconds, it is marked as a Class B anomaly. If the actual frequency of Class B anomalies exceeds the preset benchmark d1 times per minute, the score increases by (actual frequency - d1) × d2. For low-stability links, the voltage deviation rate, temperature deviation rate, BER deviation rate, and eye diagram degradation rate are calculated and compared with the set thresholds. If the actual frequency of two or more indicators exceeding the set thresholds simultaneously exceeds the set critical value f1 times per second, the score increases by (actual frequency - f1) × f2. The initial score of each link is set to g to obtain the anomaly score, where c1, c2, d1, d2, f1, and f2 are set values.

[0088] Perform link-level operations on the abnormal score values of each link to obtain the response action set of each link;

[0089] Specifically, when the anomaly score of each link is greater than the set threshold JK1, a dynamic downgrade operation is performed accordingly, downgrading the link to GEN3 mode or converting the GEN3 mode link to a hidden state. At the same time, the operating system is prevented from dangerously writing to the link configuration space. When the anomaly score of each link is equal to the set threshold JK1, the link is forced to retrain to restore stability. If it is lower than the set threshold JK1, only logs are recorded and no action is taken. The response action set of each link is obtained;

[0090] Specifically, step S500 is analyzed as follows:

[0091] Repair or degrade the link based on the response action set, and finally update the link status and topology structure according to the processing results to obtain the repair result and updated topology structure;

[0092] Specifically, the response actions of each link are concentrated on the dynamic degradation operation. If the link is originally in GEN5 mode, the capability register (0x0C) is modified to the GEN3 rate mask value 0x0008, the control register retraining flag is turned on, and it is updated and adjusted to a medium stability link. If the link is originally in GEN3 mode, the write capability register is modified to the invalid identification value 0xFFFF, the control register link disable bit is started, and it is updated and adjusted to a low stability link. The configuration space locking mechanism prevents OS writing. The response actions of each link are concentrated on the forced retraining operation. The medium stability link loads the preset from address 200 of the secure boot image. For the GEN3 parameter package, the high-stability link activates the adjustment of the downstream port (iDP) pre-emphasis level 4 and the upstream port (iUP) equalization level 3, and uses the reference clock to start strict timing verification. If the link state machine register shows the normal working L0 state, the eye diagram monitoring value is greater than the set threshold bj1, and the error detector bit error rate is less than the set value kl1, if all the above three indicators are met, it is marked as a successful repair, the link stability mark is updated and the success status is recorded. In other cases, the storage area restores the original register configuration and maintains the original stability link to obtain the repair result and the updated topology structure, and the result is success or success.

[0093] Specifically, information such as the operating system, hardware combination, temperature, and historical anomaly counts is collected and integrated into a historical data set. An anomaly probability model is then constructed to calculate the link anomaly probability, and links exceeding the threshold are designated as high-risk. The capability registers and control registers of high-risk links are forcibly configured, and an optimal configuration vector is obtained through algorithmic optimization. The chip's basic firmware image is then loaded, combined with the signature key generated by the security chip, and an injection function is used to ultimately obtain the injection verification image. After the verification image is injected, the effective register value is first verified and unsealed, and then normalized into a configuration adjustment vector. Link stability, power supply noise, and clock offset are simultaneously calculated. A model is constructed to obtain a state transition matrix. Key state probabilities are extracted and adjusted to obtain the TS sequence interval adjustment value. Parameters such as signal swing are then integrated to generate a training parameter package, and the final stability score is calculated based on environmental parameters. Finally, the links are classified into high, medium, and low stability according to the scores. By changing the device ID, manufacturer ID, or disguising it as a bridge device, a topology mapping table and a shadow register table are generated to optimize the PCIe topology structure, avoid the system from misidentifying the link status, and prevent the operating system from misjudging normal links as faulty devices, reducing problems such as blue screens and freezes. For example, after a low-stability link is directly hidden, the system will not read its status at all, and naturally there will be no error report; a medium-stability link is disguised as a bridge device, which can not only ensure basic communication, but also will not be misjudged as a hardware failure by the system due to abnormal rate display; a high-stability link maintains the actual rate without affecting high-speed transmission performance. At the same time, links with different stabilities have special processing strategies, which not only ensure system compatibility but also maximize hardware performance, allowing the device to run smoothly.

[0094] The above is an illustration of the present invention and should not be considered as limiting thereof. Although several exemplary embodiments of the present invention have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined by the claims. It should be understood that the above is an illustration of the present invention and should not be considered as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present invention is defined by the claims and their equivalents.

Claims

1. A method for preventing the abnormal recognition of the internal link status of a PCIe switch by the OS, characterized in that: The following steps are involved: Step S100: Identify high-risk links by acquiring historical data sets, perform configuration processing, and optimize algorithms to obtain an injection verification image; Step S200: performing precise link training control analysis based on the injected verification image to obtain a final link stability score; Step S300: performing intelligent topology mapping management on the final link stability score to obtain an optimized topology; Step S400: performing anomaly detection and hierarchical response control on the optimized topology to obtain a response action set; Step S500: Repair or degrade the link based on the response action set, and finally update the link state and topology structure according to the processing result to obtain a repair result and an updated topology structure.

2. The method for preventing the PCIe switch internal link status from being abnormally identified by the OS according to claim 1, characterized in that: The injection verification image analysis is as follows: The capability registers of all links in the high-risk link set are forcibly configured to the GEN1 configuration mask to obtain the capability registers. The control registers of all links in the high-risk link set are forcibly configured to the forced training configuration to obtain the control registers. Based on the forced configuration of the capability registers and control registers, a sequential quadratic programming algorithm is used to solve the optimization function for the actual negotiated rate. The bit error rate limit of the chip's built-in BIST circuit is ensured to meet the reliability threshold to obtain the optimal configuration vector. The basic firmware image is loaded from the read-only storage area preset at the factory of the chip. The security chip generates a signature key based on the P-256 elliptic curve. Based on the basic firmware image, signature key and optimal configuration vector, the injection function is used to execute the operations of writing the configuration to the PCIe space, generating the ECDSA signature key and writing it into the verification area to obtain the injection verification image.

3. The method for preventing the PCIe switch internal link status from being abnormally recognized by the OS according to claim 2, characterized in that: The high-risk link set is analyzed as follows: The operating system name is read from the device system information and converted into a numerical code based on a preset mapping rule to obtain the operating system type code. The CPU manufacturer and main accelerator type in the device hardware information are extracted and a unique hardware combination code is generated according to the preset combination rule. The operating temperature is read in real time through the sensor of the PCIe switch chip, divided into intervals according to the discretization rule and assigned codes respectively to obtain the temperature interval code. From the PCIe link layer error records in the device exception log database, count the number of historical exceptions by device unique ID; Based on the operating system type code, unique hardware combination code, temperature range code and historical anomaly count, an anomaly probability prediction model is created and weighted linear combination and logical function conversion are performed to obtain a set of high-risk links.

4. The method for preventing the PCIe switch internal link status from being abnormally identified by the OS according to claim 1, characterized in that: The final link stability score analysis is as follows: An oscilloscope is used to measure the difference between the high and low levels of the signal to obtain the signal swing. During the link training phase, the transmitter and receiver exchange TS ordered sets and negotiate and analyze them to obtain the pre-emphasis level. The signal swing, pre-emphasis level, and TS sequence interval adjustment are integrated according to the protocol specification to obtain a structured training parameter package. The operating system risk factor, hardware performance level, and hardware performance level are extracted from the secure boot record to obtain the environmental adjustment parameters. The weights of each parameter in the structured training parameter package are dynamically calculated based on the environmental adjustment parameters to obtain the initial stability score. The initial stability score is constrained by boundary constraints to obtain the final link stability score.

5. The method for preventing the PCIe switch internal link status from being abnormally identified by the OS according to claim 4, characterized in that: The TS sequence interval adjustment amount is analyzed as follows: The signed SBR image and ECDSA signature key are digitally verified and unsealed through hardware call functions to obtain the valid register values. Normalize the effective register values according to the maximum configuration range to obtain the configuration adjustment vector. Count the proportion of bit error rates less than the bit error rate reliability threshold in n times to obtain the link stability. Turn on the power management unit and set the sampling mode to every microsecond to collect voltage signals and calculate deviations to obtain power supply noise; Activate the phase-locked loop and clock jitter analysis functions. The phase-locked loop monitors the clock signal and obtains the clock offset through the phase difference statistical algorithm. A state transition probability model is constructed based on the configuration adjustment vector, link stability, power supply noise, and clock offset. This model is linearly combined and processed with an activation function to obtain the state transition probability. Based on the state transition probability, the probability of traversing the state pairs is calculated, and a matrix is constructed to obtain the state transition matrix; Extract the specific state transition probability based on the state transition matrix to obtain the target state probability; The target state probability is adjusted proportionally and integrally through the adaptive training controller formula to obtain the TS sequence interval adjustment amount.

6. The method for preventing the abnormality of the internal link status of a PCIe switch from being recognized by the OS according to claim 1, characterized in that: The optimized topology analysis is as follows: Perform visibility decisions based on the final link stability scores to obtain a complete topology map; Based on the visibility flag in the topology mapping table, a shadow register mapping table is obtained through a dual register mapping function; The dynamic topology filter obtains the shadow register mapping table and performs three levels of hardware-level operations to obtain the optimized topology structure.

7. The method for preventing the PCIe switch internal link status from being abnormally identified by the OS according to claim 1, characterized in that: The response action set is analyzed as follows: Based on the optimized topology structure, different data collection strategies are implemented for different links. The frequency deviation risk quantification model of link stability classification is used to obtain the anomaly score value of each link. Link-level operations are performed on the anomaly score value of each link to obtain the response action set of each link.

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