Calculation module, wafer level processor and wafer level computer

Abstract

The invention provides a calculation module, a wafer level processor and a wafer level computer, the calculation module comprises a plurality of calculation nodes arranged in a preset arrangement mode, and each calculation node comprises a control unit and a plurality of quantum calculation units. The control unit is electrically connected with each quantum computing unit, the control unit is used for deploying computing tasks of each quantum computing unit, and the quantum computing units carry out quantum computing and information storage. The wafer-level processor comprises a plurality of calculation modules, and the wafer-level processor is arranged in a dilution refrigerator to form the wafer-level computer. According to the calculation module, the wafer-level processor and the wafer-level computer provided by the embodiment of the invention, the integration density is improved through a wafer-level integration technology, so that the calculation power of a system is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a computing module, a wafer-level processor, and a wafer-level computer. Background Art

[0002] Superconducting quantum chips exploit the unique physical properties of quantum bits (qubits) at low temperatures, such as entanglement and superposition, to enable quantum computing. This significantly increases the speed of computation for specific scientific problems and is expected to play a significant role in scientific research, finance, artificial intelligence, cryptography, and other fields.

[0003] In recent years, artificial intelligence (AI) and quantum computing, two cutting-edge technological fields, have shown a trend of convergence. This trend stems from the current mismatch between the computing power requirements of AI and the capabilities of computer hardware. Consequently, practitioners hope to overcome this computing power shortage by leveraging quantum computing's exponential superiority over classical computing for specific problems. According to OpenAI data, the computing power required for AI development has been growing exponentially since 2012, doubling on average every three to four months, and increasing by over 300,000 times from 2012 to 2018. However, the scale and integration of current quantum computing chips remain relatively small, failing to meet the demands of commercial AI applications. Superconducting quantum computing is one of the most promising new high-computing computing architectures, but the most advanced superconducting quantum processors are still limited to conventional single-chip sizes and only a few thousand bits. Therefore, how to scale up the computing power of wafer-scale processors has become a critical and pressing issue in this field. Summary of the Invention

[0004] In response to the problems in the prior art, embodiments of the present invention provide a wafer-level computer, a computing module, a wafer-level processor, and a wafer-level computer, which can at least partially solve the problems in the prior art.

[0005] In a first aspect, the present invention provides a computing module, comprising a plurality of computing nodes, each computing node comprising a control unit and a plurality of quantum computing units, wherein:

[0006] The control unit is electrically connected to each quantum computing unit, and the control unit is used to allocate computing tasks of each quantum computing unit;

[0007] The plurality of computing nodes are arranged in a preset arrangement, and the control units of the plurality of computing nodes communicate through a wiring layer.

[0008] Furthermore, each quantum computing unit includes a quantum computing core particle and a superconducting memory core particle, the quantum computing core particle is electrically connected to the superconducting memory core particle, the superconducting memory core particle and the quantum computing core particle are vertically stacked, or the quantum computing core particle and the superconducting memory core particle are arranged in parallel.

[0009] Furthermore, the control unit includes a complementary metal oxide semiconductor control chip and a memory chip arranged on the complementary metal oxide semiconductor control chip, the complementary metal oxide semiconductor control chip and the memory chip are vertically stacked, or the complementary metal oxide semiconductor control chip and the memory chip are arranged in parallel.

[0010] Furthermore, the computing module provided by an embodiment of the present invention also includes multiple optical engines, each optical engine is electrically connected to a computing node located at the edge of the multiple computing nodes, and the optical engine is used to convert external optical signals into electrical signals and transmit them to the connected computing nodes, or convert electrical signals from the connected computing nodes into optical signals for output.

[0011] In a second aspect, the present invention provides a wafer-level processor, comprising a plurality of computing modules, a wafer-level interconnect substrate, a measurement and control substrate, and a wafer-level backside power supply substrate according to any one of the above embodiments, wherein:

[0012] The multiple computing modules are arranged on a wafer-level interconnection substrate, the wafer-level interconnection substrate is arranged on the wafer-level back power supply substrate, and the wafer-level back power supply substrate is arranged on the back power supply electrical interconnection layer; the measurement and control substrate is arranged on the top of the multiple computing modules, and is used to transmit measurement and control signals for the multiple computing modules, and the measurement and control signal electrical interconnection layer is arranged on the measurement and control substrate, and is used to deploy the measurement and control circuits of the multiple computing modules; the wafer-level back power supply substrate and the back power supply electrical interconnection layer are used to provide power to the multiple computing modules in the vertical direction.

[0013] Furthermore, a plurality of first conductive vias are provided in the wafer-level interconnect substrate, and a plurality of second conductive vias are provided in the wafer-level back power supply substrate. Each computing module is connected to at least one first conductive via, each first conductive via is electrically connected to at least one second conductive via through a solder ball, and each second conductive via is electrically connected to the back power supply electrical interconnection layer.

[0014] Furthermore, a plurality of first thermal via structures are provided in the wafer-level interconnect substrate, and a plurality of second thermal via structures are provided in the wafer-level back power supply substrate, and the first thermal via structures are low-temperature bonded to the corresponding second thermal via structures; wherein the low-temperature bonding temperature is lower than a preset temperature.

[0015] Furthermore, a plurality of coaxial conductive through-holes are provided in the measurement and control substrate, each coaxial conductive through-hole corresponds to at least one quantum bit included in the computing module, and each coaxial conductive through-hole is coupled to the corresponding quantum bit.

[0016] Furthermore, the multiple computing modules are arranged in an array.

[0017] Furthermore, the various computing modules communicate with each other via optical waveguides.

[0018] Furthermore, the wafer-level processor provided by the embodiment of the present invention further includes a coaxial line and / or an optical fiber, one end of the coaxial line is electrically connected to the wafer-level interconnect substrate, and the optical fiber is connected to the optical engine of the computing module.

[0019] In a third aspect, the present invention provides a wafer-level computer, comprising the wafer-level processor according to any one of the above embodiments, a first cold plate, and a second cold plate, wherein:

[0020] The wafer-level processor is disposed between the first cold plate and the second cold plate, and is in contact with the first cold plate and the second cold plate respectively.

[0021] Furthermore, a first heat dissipation layer is provided between the wafer-level processor and the first cold plate, and / or a second heat dissipation layer is provided between the wafer-level processor and the second cold plate.

[0022] Furthermore, the wafer-level computer provided by an embodiment of the present invention also includes a microfluidic power pump and a microfluidic loop, and the microfluidic loop is arranged on the lower surface of the wafer-level back power supply substrate of the wafer-level processor and / or the upper surface of the measurement and control substrate of the wafer-level processor.

[0023] The computing module, wafer-level processor, and wafer-level computer provided by the embodiments of the present invention include a plurality of computing nodes, each of which includes a control unit and a plurality of quantum computing units. The control unit is electrically connected to each quantum computing unit and is used to allocate computing tasks for each quantum computing unit. The plurality of computing nodes are arranged in a preset arrangement, and the control units of the plurality of computing nodes communicate via a wiring layer. The control unit is electrically connected to each quantum computing unit, and the quantum computing units are measured and controlled via a measurement and control substrate. The computing module, wafer-level processor, and wafer-level computer provided by the embodiments of the present invention improve integration density through wafer-level integration technology, thereby facilitating improved system computing power. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0025] Figure 1A It is a schematic diagram of the top view of the computing module provided by the first embodiment of the present invention.

[0026] Figure 1B It is a schematic cross-sectional structural diagram of a computing module provided in the first embodiment of the present invention.

[0027] Figure 1C It is a partially enlarged structural diagram of the calculation module provided by the first embodiment of the present invention.

[0028] Figure 2 2 is a schematic structural diagram of a wafer-level processor provided by the second embodiment of the present invention.

[0029] Figure 3 It is a schematic diagram of the planar arrangement structure of the computing modules in the wafer-level processor provided by the third embodiment of the present invention.

[0030] Figure 4 4 is a schematic diagram of the structure of a wafer-level computer provided by the fourth embodiment of the present invention.

[0031] Figure 5 4 is a schematic structural diagram of a wafer-level computer provided by the fifth embodiment of the present invention.

[0032] Figure 6 2 is a schematic diagram of the structure of a wafer-level computer provided by the sixth embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments in this application can be combined with each other in any way. The acquisition, storage, use, processing, etc. of data in the technical solutions in this application comply with the relevant provisions of laws and regulations.

[0034] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0035] To address the problem that existing superconducting quantum processors are still limited to conventional single-chip sizes and thousands of bits, making them incapable of large-scale integration, this application proposes to realize a wafer-level quantum computing platform through mask splicing technology and three-dimensional integration technology. Complementary metal oxide semiconductor control core particles are used as the core to build computing nodes for on-chip integration, which is conducive to wafer-level integration of processors and improves processor computing power. The scope of wafer level in this application is not limited to circular wafers, but can also be extended to square panels. The panels can be made of glass or other substrate materials that can be used for large areas and low losses.

[0036] Figure 1A is a schematic diagram of a top view of the computing module provided by the first embodiment of the present invention, Figure 1B is a schematic cross-sectional structural diagram of a computing module provided in the first embodiment of the present invention, Figure 1B yes Figure 1A The cross-sectional view of AA in the figure, Figure 1C is a partially enlarged structural diagram of a calculation module provided by the first embodiment of the present invention, Figure 1C for Figure 1A The enlarged picture of point B is as follows: Figure 1A 、 Figure 1B and Figure 1C As shown, the computing module 100 provided in the embodiment of the present invention includes multiple computing nodes 1, each computing node 1 includes a control unit 1-1 and multiple quantum computing units 1-2, wherein:

[0037] The control unit 1-1 is electrically connected to each quantum computing unit 1-2, and the control unit 1-1 is used to allocate computing tasks of each quantum computing unit 1-2;

[0038] The plurality of computing nodes 1 are arranged in a preset arrangement, and the control units 1 - 1 of the plurality of computing nodes 1 communicate with each other through a wiring layer.

[0039] Specifically, the control unit 1-1 may include a complementary metal oxide semiconductor (CMOS) control core and a memory core. The CMOS control core may include a circulator, a parametric amplifier circuit, a high-frequency oscillator, a phase-locked loop (PLL), an analog-to-digital converter (ADC), a quantum random number generator (QNRG), a qubit readout circuit, and a multi-gated pulse circuit structure. The configuration is based on actual needs and is not limited in the embodiment of the present invention. The memory core is used to store instructions, data, and radio frequency pulse waveforms of the CMOS control core. The memory core may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FeRAM), a phase change random access memory (PCRAM), etc. The configuration is based on actual needs and is not limited in the embodiment of the present invention.

[0040] Control unit 1-1 is electrically connected to each quantum computing unit 1-2. Control unit 1-1 is used to coordinate the computing tasks of each quantum computing unit 1-2. Quantum computing unit 1-2 may include a quantum computing core and a superconducting memory core. The quantum computing core has independent quantum computing functions. The superconducting memory core is electrically connected to the quantum computing core to store and read quantum data.

[0041] The multiple computing nodes 1 are arranged in a predetermined arrangement, such as an array or linear arrangement. The predetermined arrangement is determined based on actual needs and is not limited in this embodiment. The control units 1-1 of the multiple computing nodes 1 communicate via a wiring layer. The wiring layer includes a connection network composed of single or multiple layers of electrical interconnects and insulating layers.

[0042] The total number of computing nodes 1 is set based on actual needs and is not limited in this embodiment of the present invention. The total number of computing nodes 1 can be set to a number that exceeds the actual computing requirements, i.e., to introduce a redundant design. When a computing node fails, sufficient computing nodes are still available to operate, thereby improving the flexibility and reliability of the system.

[0043] This application adopts a new architecture in which the control unit 1-1 and the quantum computing unit 1-2 are directly integrated on-chip, which can effectively solve the problem of highly discrete and highly complex long-distance interconnection between the logic control module and the quantum processor in the traditional architecture, and has significant advantages in noise reduction, fidelity and scalability.

[0044] For example, Figure 1A 、 Figure 1B and Figure 1C As shown, the computing node 1 inside the computing module 100 includes 1 control unit 1-1 and 4 quantum computing units 1-2; the computing node 1 at the edge of the computing module 100 (excluding the four corners) may include 1 control unit 1-1 and 3 quantum computing units 1-2; the computing node 1 at the four corners of the computing module 100 may include 1 control unit 1-1 and 2 quantum computing units 1-2.

[0045] A computing module provided by an embodiment of the present invention includes multiple computing nodes, each computing node includes a control unit and multiple quantum computing units, the control unit is electrically connected to each quantum computing unit, and the control unit is used to allocate computing tasks for each quantum computing unit; the multiple computing nodes are arranged in a preset arrangement, the control units of the multiple computing nodes communicate through a wiring layer, and the computing nodes are constructed with the control unit as the core for on-chip integration, thereby improving the integration level and thereby facilitating improving the system computing power.

[0046] like Figure 1A 、 Figure 1B and Figure 1C As shown, on the basis of the above embodiments, further, the quantum computing unit 1-2 includes a quantum computing core particle 1-2-1 and a superconducting memory core particle 1-2-2, the quantum computing core particle 1-2-1 is electrically connected to the superconducting memory core particle 1-2-2, the superconducting memory core particle 1-2-2 and the quantum computing core particle 1-2-1 are vertically stacked, or the quantum computing core particle 1-2-1 and the superconducting memory core particle 1-2-2 are arranged in parallel.

[0047] Specifically, the quantum computing core particle 1-2-1 is used to realize the quantum computing function. The quantum computing core particle 1-2-1 can use quantum bits of charge, phase, flux, Transmon and other types, which can be selected according to actual needs and are not limited in the embodiment of the present invention.

[0048] The superconducting memory core 1-2-2 is electrically connected to the quantum computing core 1-2-1 to implement the storage and reading of quantum data. The superconducting memory core 1-2-2 can employ a Josephson junction (JJ), a magnetic JJ (MJJ), or other structures, depending on practical needs and not limited by the present embodiment. Other structures may also be employed, such as a superconductor-insulator-ferromagnet-superconductor (SIFS) MJJ or a quantized Abrikosov vortex (QAV) MJJ.

[0049] The quantum computing core 1-2-1 and the superconducting memory core 1-2-2 can be arranged in parallel, or the superconducting memory core 1-2-2 can be arranged on the quantum computing core 1-2-1 to form a vertical stacking structure. The quantum computing core 1-2-1 is electrically connected to the control unit 1-1.

[0050] like Figure 1A 、 Figure 1B and Figure 1C As shown, based on the above embodiments, the control unit 1-1 further includes a CMOS control chip 1-1-1 and a superconducting memory chip 1-1-2 arranged on the CMOS control chip 1-1-1, and the CMOS control chip 1-1-1 is electrically connected to the superconducting memory chip 1-1-2.

[0051] Specifically, CMOS control core 1-1-1 is used to coordinate computing tasks of multiple quantum computing units 1-2 in computing node 1. CMOS control core 1-1-1 may include circuit structures such as a circulator, a parametric amplifier circuit, a high-frequency oscillator, a phase-locked loop, an analog-to-digital converter, a quantum random number generator, a qubit readout, and multiple gated pulses, and is configured based on actual needs and is not limited in this embodiment of the present invention.

[0052] The superconducting memory core 1-1-2 is used to store the instructions, data, and radio frequency pulse waveforms of the CMOS control core. The superconducting memory core 1-1-2 can be SRAM, DRAM, RRAM, MRAM, FeRAM, PCRAM, etc., and is selected according to actual needs and is not limited in this embodiment of the present invention.

[0053] like Figure 1A and Figure 1B On the basis of the above embodiments, the computing module 100 further includes multiple optical engines 2, each optical engine 2 is electrically connected to a computing node 1 located at the edge of the multiple computing nodes 1, and the optical engine 2 is used to convert external optical signals into electrical signals and transmit them to the connected computing nodes 1, and convert electrical signals from multiple computing nodes 1 into optical signals for output.

[0054] Specifically, a wafer-level processor may include multiple computing modules 100, which are integrated to communicate with each other. Each computing module 100 communicates with each other via its own multiple optical engines 2 and optical waveguides connected to the optical engines 2. Each optical engine 2 is electrically connected to one of the multiple computing nodes 1 located at the edge. Optical communication between computing modules 100 is achieved through the optical engines 2 of each computing module 100, improving communication efficiency and reducing signal loss.

[0055] The computing module 100 is provided with an optical engine 2 for electro-optical signal conversion, so as to fully utilize the advantages of optical signals such as low loss in long-distance transmission, high transmission efficiency, high transmission quality, strong anti-interference ability and large transmission capacity, and perform wafer-level high-quality communication between each computing module 100.

[0056] The optical engine 2 can adopt a monolithic optical engine, or a combination of a photonic integrated chip (PIC) and an electronic integrated chip (EIC). The monolithic optical engine integrates the functions of both the PIC and the EIC. The monolithic optical engine can achieve electrical communication through wire bonding and optical communication through optical fibers and optical couplers; or it can achieve electrical communication through conductive through-holes provided in the adapter board by bump bonding to the adapter board, and achieve optical communication through optical through-holes, optical couplers and optical waveguides provided in the adapter board. When the optical engine 2 includes a separate PIC and EIC, the PIC can be bonded to the EIC through bump bonding, or the EIC can be bonded to the PIC through bump bonding. The PIC and EIC can also be stacked in a non-direct contact manner through an adapter board. The specific structure of the optical engine 2 is selected according to actual needs and is not limited in the embodiment of the present invention.

[0057] In the traditional superconducting quantum processor architecture, the quantum processor and the control circuit are separated in space, and each quantum bit requires a matching measurement and control circuit running in a room temperature environment (about 300K) to realize operations such as controlling the quantum bit and reading the quantum information. However, there is a long-distance electrical connection link between the classical measurement and control circuit at room temperature and the quantum processor at extremely low temperature, and a large number of noise reduction components and heat sink components need to be installed on the link, resulting in a very complex structure of the entire signal link and a very high manufacturing cost. As the number of quantum bits continues to grow, the number of lines, complexity and hardware cost required for this measurement and control system will rise rapidly. Therefore, the present application proposes a wafer-level processor that moves the power supply network down to the bottom of the computing wafer, so as to leave sufficient wiring resources in the top space of the computing module for the measurement and control signals required by the quantum bits.

[0058] Figure 2FIG. 1 is a schematic diagram of the structure of a wafer-level processor provided by a second embodiment of the present invention. Figure 2 As shown, the wafer-level processor provided by the embodiment of the present invention includes multiple computing modules 201, a wafer-level back power supply substrate 202, a measurement and control substrate 203 and a wafer-level interconnect substrate 204, wherein:

[0059] Multiple computing modules 201 are arranged on a wafer-level interconnection substrate 204, which is arranged on a wafer-level back power supply substrate 202, which is arranged on a back power supply electrical interconnection layer 205; a measurement and control substrate 203 is arranged on top of the multiple computing modules 201, and is used to transmit measurement and control signals for each computing module 201; a measurement and control signal electrical interconnection layer 206 is arranged on the measurement and control substrate 203, and is used to deploy measurement and control circuits of the multiple computing modules 201; the wafer-level back power supply substrate 202 and the back power supply electrical interconnection layer 205 are used to provide power to the multiple computing modules 201 in the vertical direction.

[0060] Specifically, in the current mature technology, power and signals are usually wired on the front side of the integrated circuit chip, which results in the power supply network occupying a portion of the wiring space required for the signal network. For quantum processors, such problems are more serious for wafer-level chips because, on the one hand, each quantum bit requires a separate measurement and control path, and the space resources for signal wiring are already very tight; on the other hand, the power supply network often uses thicker power lines to alleviate the IRdrop problem, which may lead to wiring congestion and impose more serious limitations on system performance. This application proposes to move the power supply network down to the bottom of the wafer-level interconnect substrate 204, and power the computing module 201 from the back through the wafer-level back power supply substrate 202 and the back power supply electrical interconnect layer 205 to ensure that there are sufficient wiring resources for the measurement and control signals on the front.

[0061] Each computing module 201 can be bonded to a wafer-level interconnect substrate 204 via micro-bump bonding or hybrid bonding. The wafer-level interconnect substrate 204 can be bonded to the wafer-level back power substrate 202 via solder balls 207. Solder balls 207 can be superconducting single-element solder balls or superconducting alloy solder balls. The choice is made based on practical needs and is not limited in this embodiment of the present invention. The first surface of the wafer-level back power substrate 202 faces the wafer-level interconnect substrate 204, and the second surface of the wafer-level back power substrate 202 contacts the back power electrical interconnect layer 205. A first conductive via 204-1 can be provided in the wafer-level interconnect substrate 204, and a second conductive via 202-1 can be provided in the wafer-level back power substrate 202. The first conductive via 204-1 and the second conductive via 202-1 are connected via solder balls 207. The back power electrical interconnect layer 205 supplies power to the computing module 201 via the first conductive via 204-1 and the second conductive via 202-1. The backside power supply interconnect layer 205 can be connected to a power line 214, allowing for an external power source or ground connection. The wafer-level interconnect substrate 204 and the wafer-level backside power supply substrate 202 can be manufactured from a single wafer. The wafer can be 4-inch, 6-inch, 8-inch, or 12-inch, depending on actual needs and is not limited in this embodiment.

[0062] The measurement and control substrate 203 can be bonded to multiple computing modules 201 via multiple bump bonding pairs 212. The first surface of the measurement and control substrate 203 faces the multiple computing modules 201, and the second surface of the measurement and control substrate 203 contacts the measurement and control signal electrical interconnect layer 206, which includes measurement and control circuits corresponding to each qubit in the computing module 201. The measurement and control signal electrical interconnect layer 206 can receive external measurement and control signals via measurement and control transmission lines 213. Coaxial conductive vias are provided within the measurement and control substrate 203, corresponding to the measurement and control ports of the qubits and enabling transmission of control signals through capacitive coupling. The bypass capacitors connected to the Josephson junctions can also adopt a coaxial configuration to achieve higher-quality capacitive coupling with the coaxial conductive vias. The measurement and control substrate 203 can be wafer-level or core-level, corresponding one-to-one with a computing module, or corresponding to multiple computing modules. Each bump bonding pair 212 can include an upper bump 212-1 and a lower bump 212-2. The upper bump 212-1 and the lower bump 212-2 are bonded to form a bump bonding pair 212. The upper bump 212-1 is made on the lower surface of the measurement and control substrate 203, and the lower bump 212-2 is made on the upper surface of the computing module 201.

[0063] Each computing module 201 can communicate optically via optical waveguides. These waveguides can include embedded waveguides, slab waveguides, circular waveguides, ridge waveguides, and the like, and are selected based on practical needs and are not limited in this embodiment. The optical waveguides that enable optical communication between computing modules 201 can form an interconnected optical waveguide network.

[0064] The wafer-level processor provided by an embodiment of the present invention includes multiple computing modules, a wafer-level interconnect substrate, a measurement and control substrate, and a wafer-level back power supply substrate. The multiple computing modules are arranged on the wafer-level interconnect substrate, the wafer-level interconnect substrate is arranged on the wafer-level back power supply substrate, and the wafer-level back power supply substrate is arranged on the back power supply electrical interconnection layer; the measurement and control substrate is arranged on top of the multiple computing modules and is used to transmit measurement and control signals to the multiple computing modules. The measurement and control signal electrical interconnection layer is arranged on the measurement and control substrate and is used to deploy the measurement and control circuits of the multiple computing modules; the wafer-level back power supply substrate and the back power supply electrical interconnection layer are used to supply power to the multiple computing modules in the vertical direction. By providing separate wafer-level back power supply substrates and measurement and control substrates, power supply and measurement and control signals are routed separately, avoiding the problem of wiring congestion and ensuring sufficient routing space for measurement and control signals. In addition, by comprehensively considering the hardware requirements for power supply and measurement and control, a wafer-level three-dimensional integrated architecture is constructed, which can provide computing power far exceeding that of a single-chip quantum processor, thereby improving the data processing capability of the quantum processor.

[0065] like Figure 2 As shown, on the basis of the above embodiments, further, a plurality of first conductive vias 204-1 are set in the wafer-level interconnect substrate 204, and a plurality of second conductive vias 202-1 are set in the wafer-level back power supply substrate 202, each computing module 201 is connected to at least one first conductive via 204-1, each first conductive via 204-1 is electrically connected to at least one second conductive via 202-1 through a solder ball 207, and each second conductive via 202-1 is electrically connected to the back power supply electrical interconnection layer 205.

[0066] Specifically, a through hole is formed in the wafer-level interconnect substrate 204 and filled with conductive material to produce a first conductive through hole 204-1; a through hole is formed in the wafer-level back power supply substrate 202 and filled with conductive material to produce a second conductive through hole 202-1. The first conductive through hole 204-1 and the second conductive through hole 202-1 are used to connect different circuit layers or wafers to achieve mechanical support and the transmission of signals and power. The wafer-level interconnect substrate 204 and the wafer-level back power supply substrate 202 are bonded via solder balls 207. There are multiple solder balls 207, and each computing module 201 corresponds to at least one solder ball 207. Each computing module 201 is electrically connected to the back power supply electrical interconnect layer 205 through the first conductive through hole 204-1, the second conductive through hole 202-1, and the corresponding solder ball 207, thereby achieving power supply for each computing module 201.

[0067] like Figure 2As shown, based on the above embodiments, multiple first thermal via structures 204-2 are further provided in the wafer-level interconnect substrate 204, and multiple second thermal via structures 202-2 are provided in the wafer-level back power substrate 202. The first thermal via structures 204-2 correspond to the second thermal via structures 202-2 one by one, and the first thermal via structures 204-2 and the corresponding second thermal via structures 202-2 are low-temperature bonded. The first thermal via structures 204-2 and the second thermal via structures 202-2 can be filled with a high thermal conductivity material such as diamond or indium. The temperature of the low-temperature bonding is lower than a preset temperature.

[0068] Multiple second thermal via structures 202-2 are fabricated in the wafer-level back power substrate 202, with the material filling height appropriately higher than the upper surface of the wafer-level back power substrate 202. Multiple first thermal via structures 204-2 are fabricated in the wafer-level interconnect substrate 204, with the material filling height appropriately higher than the lower surface of the wafer-level interconnect substrate 204. The first thermal via structures 204-2 correspond one-to-one with the second thermal via structures 202-2. That is, where a second thermal via structure 202-2 is located on the wafer-level back power substrate 202, a first thermal via structure 204-2 is located at the corresponding location on the wafer-level interconnect substrate 204. The second thermal via structures 202-2 and the corresponding first thermal via structures 204-2 are bonded together at a predetermined temperature. The second thermal via structures 202-2 are used to improve the local thermal conductivity of the wafer-level back power substrate 202, while the first thermal via structures 204-2 are used to improve the local thermal conductivity of the wafer-level interconnect substrate 204.

[0069] Among them, nanoparticles can be selected as an intermediate layer for low-temperature bonding. Nanoparticles can be selected from high thermal conductivity materials such as gold and silver. The nanoparticle intermediate layer can be prepared by physical vapor deposition or pulsed laser deposition and then low-temperature bonding can be implemented. The metal nanoparticles prepared by physical vapor deposition or pulsed laser deposition are loosely dispersed, have a large surface area, have high surface energy and activity, and help to reduce the bonding temperature. The temperature of low-temperature bonding is lower than the preset temperature, and the preset temperature is set according to actual needs, and the embodiment of the present invention does not limit it. For example, the preset temperature is the melting point of the indium bump, 156.51°C.

[0070] Each first thermal via structure 204-2 and the corresponding second thermal via structure 202-2 provide micron-scale localized heat dissipation channels for the hotspots of each computing module 201, helping to improve the heat dissipation efficiency of the quantum processor. This selective localized heat dissipation structure also avoids the high mechanical stress that may be caused by the growth of thermally conductive materials (such as diamond) on the entire surface of the wafer.

[0071] On the basis of the above embodiments, further, in order to ensure the parallelism between the computing module 201 and the wafer-level back power supply substrate 202, the sum of the thicknesses of the first conductive via 204-1, the solder ball 207 and the second conductive via 202-1 is equal to the sum of the thicknesses of the first thermal via structure 204-2, the second thermal via structure 202-2 and the intermediate layer for low-temperature bonding of the second thermal via structure 202-2 and the first thermal via structure 204-2.

[0072] like Figure 2 As shown, based on the above embodiments, further, a plurality of coaxial conductive through-holes 203-1 are provided in the measurement and control substrate 203, each coaxial conductive through-hole 203-1 is coupled with a corresponding quantum bit, and the quantum computing unit of each computing module 201 includes at least one quantum bit.

[0073] Specifically, the quantum bits included in the quantum computing unit of each computing module 201 can be designed in a coaxial configuration, and the bypass capacitors connected to the Josephson junctions can also be coaxially configured. The quantum bits and the corresponding coaxial conductive vias 203-1 form a controllable capacitive coupling structure, ensuring that off-chip signals can effectively and individually access each quantum bit of each computing node 1 of each computing module 201, thereby achieving low crosstalk and high-density measurement and control. The distance between the quantum bits and the corresponding coaxial conductive vias 203-1 can be ensured by highly parallel flip-chip bonding bump bonding pairs 212 and / or by providing hard spacers between the computing module 201 and the measurement and control substrate 203.

[0074] Figure 3 FIG. 1 is a schematic diagram of a planar arrangement structure of a computing module in a wafer-level processor provided by a third embodiment of the present invention. Figure 3 As shown, based on the above embodiments, multiple computing modules 201 are further arranged in an array. Each computing module 201 optically communicates with each other via connected optical waveguides 208. The optical waveguides 208 connecting each computing module 201 form an optical waveguide interconnection network. Multiple computing modules 201 can be arranged in an array on a wafer.

[0075] The communication between the wafer-level processor and the outside world can be achieved through the input / output (I / O) module 209 . The I / O module 209 can communicate with the outside world through optical fibers and / or coaxial cables.

[0076] like Figure 2 and Figure 3 As shown, based on the above embodiments, further, each computing module 201 can perform optical communication through an optical waveguide 208. Planar optical waveguides can be selected from buried waveguides, slab waveguides, circular waveguides, ridge waveguides, etc., and are selected according to actual needs, and are not limited in the embodiments of the present invention.

[0077] The internal scale of the computing node is small, and the loss caused by the electrical interconnection is acceptable. However, the communication between computing modules involves wafer-level centimeter or even decimeter-scale wiring. The signal transmission delay of the electrical interconnection may become the main factor affecting the operating speed of the integrated system. Therefore, this application introduces an optical waveguide interconnection network for communication between computing modules, which can achieve better communication bandwidth, energy consumption and delay. Accordingly, an optical engine is provided at the edge of the computing node for the conversion of optical signals into electrical signals, so as to make full use of the advantages of optical signals such as low loss over long distances, high transmission efficiency, high transmission quality, strong anti-interference ability and large transmission capacity, which helps to improve the communication efficiency between computing modules.

[0078] like Figure 2 As shown, based on the above embodiments, the wafer-level processor provided by the embodiment of the present invention further includes a coaxial line 211 and / or an optical fiber 210. One end of the coaxial line 211 is electrically connected to the wafer-level interconnect substrate 204, and the optical fiber 210 is connected to the optical engine of the computing module 201. The coaxial line 211 is used to realize the electrical signal connection between the wafer-level processor and the outside world. The optical fiber 210 is used to realize the optical signal connection between the wafer-level processor and the outside world.

[0079] The optical fiber 210 may be connected to the optical engine of the computing module 201 .

[0080] To facilitate the installation of the coaxial cable 211 and power cable 214, holes are not drilled in the measurement and control substrate 203 and the measurement and control signal electrical interconnection layer 206. Since the wafer-level back power supply substrate 202 and wafer-level interconnection substrate 204 can be wafer-level, and the multiple computing modules 201, measurement and control substrate 203, and measurement and control signal electrical interconnection layer 206 stacked thereon can be core-level, there is room for pre-reserved solder pads or interfaces, allowing the coaxial cable 211 and power cable 214 to be directly soldered or plugged in. Furthermore, the coaxial cable 211 and power cable 214 can be assembled separately after all bonding processes are completed in the wafer-level processor.

[0081] Inside the ultra-low-temperature, high-vacuum dilution refrigerator, which operates at a high vacuum, convective heat transfer is significantly suppressed. According to the Stefan-Boltzmann law, an object's radiation capacity is proportional to the fourth power of its temperature. This also significantly suppresses radiative heat transfer at extremely low temperatures. Therefore, quantum computers require an effective heat conduction mechanism to dissipate heat from wafer-level processors.

[0082] Figure 4 FIG. 4 is a schematic diagram of the structure of a wafer-level computer provided by a fourth embodiment of the present invention. Figure 4 As shown, the wafer-level computer provided by an embodiment of the present invention includes the wafer-level processor 401, the first cold plate 402 and the second cold plate 403 according to any of the above embodiments, wherein:

[0083] The wafer-level processor 401 is disposed between the first cold plate 402 and the second cold plate 403 and is in contact with the first cold plate 402 and the second cold plate 403. The wafer-level processor 401 dissipates heat through heat conduction between the first cold plate 402 and the second cold plate 403.

[0084] The specific structure of the wafer-level processor 401 is described above and will not be repeated here.

[0085] Figure 5 FIG. 1 is a schematic diagram of the structure of a wafer-level computer provided by a fifth embodiment of the present invention. Figure 5 As shown, based on the above embodiments, a first heat dissipation layer 404 is further provided between the wafer-level processor 401 and the first cold plate 402 , and / or a second heat dissipation layer 405 is provided between the wafer-level processor 401 and the second cold plate 403 .

[0086] The first heat sink layer 404 can include a low-temperature bonding layer 404-1, a diamond heat sink 404-2, and a thermal interface material 404-3. The diamond heat sink 404-2 can be secured to the wafer-level processor 401 via the low-temperature bonding layer 404-1. The diamond heat sink 404-2 contacts the first cold plate 402 via the thermal interface material 404-3. The thermal interface material 404-3 effectively fills the gap between the diamond heat sink 404-2 and the first cold plate 402, reducing contact thermal resistance and improving device heat dissipation performance. Diamond, with its excellent insulation and ultra-high thermal conductivity, is an ideal heat sink material. Thanks to its ultra-high thermal conductivity, heat generated by the wafer-level processor 401 is quickly transferred to the first cold plate 402, thereby enhancing the heat dissipation capability of the wafer-level processor 401. Diamond is extremely hard and difficult to machine. No special machining is required for a single piece of diamond sheet. The first heat sink layer 404 can consist of a single piece or multiple separate diamond heat sinks.

[0087] The second heat dissipation layer 405 can include a low-temperature bonding layer 405-1, a diamond heat sink 405-2, and a thermal interface material 405-3. The diamond heat sink 405-2 can be fixed to the wafer-level processor 401 via the low-temperature bonding layer 405-1, and the diamond heat sink 405-2 is in contact with the second cold plate 403 via the thermal interface material 405-3. The second heat dissipation layer 405 can have a structure similar to that of the first heat dissipation layer 404, and will not be described in detail here.

[0088] By sandwiching a heat dissipation layer consisting of a low-temperature bonding layer, a diamond heat sink, and a thermal interface material between the wafer-level processor and the first and second cold plates, a good thermal contact interface can be formed, thereby improving the heat dissipation efficiency of the wafer-level processor.

[0089] Figure 6 FIG. 1 is a schematic diagram of the structure of a wafer-level computer provided by a sixth embodiment of the present invention. Figure 6 As shown, on the basis of the above embodiments, further, the wafer-level computer provided by the embodiment of the present invention also includes a microfluidic power pump 406 and a microfluidic loop 407, and the microfluidic loop 407 is arranged on the lower surface of the wafer-level back power supply substrate 401-1 of the wafer-level processor 401 and / or the upper surface of the measurement and control substrate 401-2 of the wafer-level processor 401.

[0090] Microfluidics have advantages such as small physical size and high heat transfer efficiency. Microchannels or micropillars can be etched into a substrate, and then different substrates are bonded and sealed together through silicon-silicon bonding, silicon-metal bonding, or other bonding processes to form a microfluidic loop 407. Heat generated by the wafer-level processor 401 is removed by the forced flow of liquid coolant or two-phase coolant within the microfluidic loop 407. A microfluidic power pump 406 is used to drive the flow of coolant within the microfluidic loop 407. The microfluidic power pump 406 can be located on either the first cold plate 402 or the second cold plate 403.

[0091] The microfluidic power pump 406 forcibly drives the convection microfluidic loop 407, which serves as a global heat dissipation channel and can effectively solve the problem of poor heat dissipation caused by the large scale of the on-chip system, ensuring the rapid cooling of the quantum computing unit and the stability of the quantum state during service.

[0092] For example, Figure 6As shown, when a first heat sink layer 404 is provided between a wafer-level processor 401 and a first cold plate 402, and a second heat sink layer 405 is provided between the wafer-level processor 401 and a second cold plate 403, microfluidic loops 407 can be provided on the upper and lower surfaces of the wafer-level processor 401, respectively, to form a first microfluidic layer 407-1 and a second microfluidic layer 407-2. Diamond heat sink 404-2 is low-temperature bonded to the first microfluidic layer 407-1, forming a low-temperature bonding layer 404-1 between the diamond heat sink 404-2 and the first microfluidic layer 407-1. Thermal interface material 404-3 effectively fills the gap between the contact surface of the diamond heat sink 404-2 and the first cold plate 402, reducing contact thermal resistance and improving device heat dissipation performance. Similarly, diamond heat sink 405-2 is low-temperature bonded to second microchannel layer 407-2, forming a low-temperature bonding layer 405-1 between diamond heat sink 405-2 and second microchannel layer 407-2. Thermal interface material 405-3 effectively fills the gap between the contact surface between diamond heat sink 404-2 and first cold plate 402, reducing contact thermal resistance and improving device heat dissipation performance. Microchannel power pump 406 is disposed on first cold plate 402 to drive the forced flow of coolant in microchannel loop 407. The two layers of microchannels form a closed loop of forced flow through microchannel power pump 406, effectively dissipating heat rapidly and evenly on a wafer-scale and rapidly dissipating it through the diamond heat sinks of first and second heat dissipation layers 404 and 405.

[0093] The wafer-level computer provided by the embodiment of the present invention has the following advantages:

[0094] (1) This application proposes a wafer-level computing paradigm for quantum computing, and designs a multi-level architecture hierarchy of core-unit-node-module-wafer-level interconnection network-wafer-level interconnection substrate, wafer-level back power supply substrate-wafer-level processor-wafer-level computer, which can significantly improve computing power compared with the monolithic integration solution in the existing technology.

[0095] (2) In this application, the wafer-level computing platform in which each computing module communicates through an interconnected network composed of optical waveguides can achieve better communication bandwidth, energy consumption and latency.

[0096] (3) This application proposes to move the power supply network down to the bottom of the wafer-level interconnect substrate, and to power the computing nodes from the back through the wafer-level back power supply substrate to ensure that there are sufficient wiring resources for the measurement and control signals on the front.

[0097] (4) This application designs three heat exchange mechanisms: an off-chip heat dissipation channel of a low-temperature bonding layer + a diamond heat sink + a thermal interface material, an on-chip local heat dissipation channel of a thermal via, and a global heat dissipation channel of a microfluidic power pump circulation closed-circuit forced convection. These can effectively solve the problem of poor heat dissipation caused by the large scale of the on-chip system, and ensure the rapid cooling of the quantum computing unit and the stability of the quantum state.

[0098] The wafer-level computer provided by the embodiment of the present invention comprehensively considers the hardware requirements in terms of power supply, measurement and control, and heat dissipation, and constructs a wafer-level three-dimensional integrated architecture. The computing power it can provide far exceeds that of a quantum computer based on a single-chip quantum processor, and can provide massive computing power support for the rapid development of large AI models.

[0099] Throughout this specification, reference to terms such as "one embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0100] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A computing module, characterized in that: The system comprises a plurality of computing nodes, each of which comprises a control unit and a plurality of quantum computing units, wherein: The control unit is electrically connected to each quantum computing unit, and the control unit is used to allocate computing tasks of each quantum computing unit; The plurality of computing nodes are arranged in a preset arrangement, and the control units of the plurality of computing nodes communicate through a wiring layer.

2. The calculation module according to claim 1, characterized in that Each quantum computing unit includes a quantum computing core particle and a superconducting memory core particle, wherein the quantum computing core particle is electrically connected to the superconducting memory core particle, the superconducting memory core particle is vertically stacked with the quantum computing core particle, or the quantum computing core particle and the superconducting memory core particle are arranged in parallel.

3. The calculation module according to claim 1, characterized in that The control unit includes a complementary metal oxide semiconductor control chip and a memory chip arranged on the complementary metal oxide semiconductor control chip, the complementary metal oxide semiconductor control chip and the memory chip are vertically stacked, or the complementary metal oxide semiconductor control chip and the memory chip are arranged in parallel.

4. The computing module according to any one of claims 1 to 3, characterized in that: It also includes multiple optical engines, each of which is electrically connected to a computing node located at the edge of the multiple computing nodes. The optical engine is used to convert external optical signals into electrical signals and transmit them to the connected computing nodes, or convert electrical signals from the connected computing nodes into optical signals for output.

5. A wafer-level processor, characterized in that: The device comprises a plurality of computing modules, wafer-level interconnect substrates, measurement and control substrates, and wafer-level back power supply substrates according to any one of claims 1 to 4, wherein: Multiple computing modules are arranged on a wafer-level interconnection substrate, which is arranged on the wafer-level back power supply substrate, which is arranged on the back power supply electrical interconnection layer; the measurement and control substrate is arranged on the top of the multiple computing modules, and is used to transmit measurement and control signals for the multiple computing modules, and the measurement and control signal electrical interconnection layer is arranged on the measurement and control substrate, and is used to deploy the measurement and control circuits of the multiple computing modules; the wafer-level back power supply substrate and the back power supply electrical interconnection layer are used to provide power to the multiple computing modules in the vertical direction.

6. The wafer-level processor according to claim 5, wherein: A plurality of first conductive vias are provided in the wafer-level interconnect substrate, and a plurality of second conductive vias are provided in the wafer-level back power supply substrate. Each computing module is connected to at least one first conductive via, each first conductive via is electrically connected to at least one second conductive via through a solder ball, and each second conductive via is electrically connected to the back power supply electrical interconnection layer.

7. The wafer-level processor according to claim 5, wherein: A plurality of first thermal via structures are provided in the wafer-level interconnect substrate, and a plurality of second thermal via structures are provided in the wafer-level back power supply substrate. The first thermal via structures are low-temperature bonded to the corresponding second thermal via structures; wherein the temperature of the low-temperature bonding is lower than a preset temperature.

8. The wafer-level processor according to claim 5, wherein: A plurality of coaxial conductive through holes are provided in the measurement and control substrate, each coaxial conductive through hole corresponds to at least one quantum bit included in the calculation module, and each coaxial conductive through hole is coupled to the corresponding quantum bit.

9. The wafer-level processor according to claim 5, wherein: The multiple computing modules are arranged in an array.

10. The wafer-level processor according to claim 5, wherein: The various computing modules communicate with each other via optical waveguides.

11. The wafer-level processor according to claim 5, wherein: It also includes a coaxial line and / or an optical fiber, one end of the coaxial line is electrically connected to the wafer-level interconnect substrate, and the optical fiber is connected to the optical engine of the computing module.

12. A wafer-level computer, characterized in that: The wafer-level processor according to any one of claims 5 to 11, a first cold plate and a second cold plate, wherein: The wafer-level processor is disposed between the first cold plate and the second cold plate, and is in contact with the first cold plate and the second cold plate respectively.

13. The wafer-level computer according to claim 12, wherein: A first heat dissipation layer is provided between the wafer-level processor and the first cold plate, and / or a second heat dissipation layer is provided between the wafer-level processor and the second cold plate.

14. The wafer-level computer according to claim 12, wherein: It also includes a microfluidic power pump and a microfluidic loop, and the microfluidic loop is arranged on the lower surface of the wafer-level back power supply substrate of the wafer-level processor and / or the upper surface of the measurement and control substrate of the wafer-level processor.

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