Implementation method of multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception

Abstract

The present invention discloses a method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception, belonging to the field of computer systems and compilation technology. The method comprises the following steps: obtaining hardware feature data to form a hardware feature database; adopting a hierarchical and controllable IR exposure mechanism, and generating intrinsic function-related source code for specific hardware feature data based on the hierarchical intermediate representation and the hardware feature database, based on a three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set; using a general compiler to compile scalar-related source code and intrinsic function-related source code in user source code into an executable file or binary library, or using a general compiler to compile intrinsic function-related source code into an executable file or binary library. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception can quickly adapt to new chips and closely match the hardware, achieving efficient super-heterogeneous and super-parallel code generation.

Description

Technical Field

[0001] The present invention relates to the field of computer systems and compilation technology, and in particular to a method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception. Background Art

[0002] Existing traditional compilers (such as GCC / LLVM) and deep learning compilers (such as TVM / XLA) face the following problems in adapting to hardware chips:

[0003] The compiler lacks dedicated optimization for RISC-V open source chips and lacks support for the latest or upcoming Matrix-related extended instruction sets.

[0004] The RISC-V chip microarchitectures launched by various chip manufacturers are black-box compatible with the RISC-V open source instruction set. The internal microarchitecture implementation technologies of the chips are not unified, but are numerous and complex, each with its own characteristics. There is a lot of room for deep proprietary optimization. Traditional compilers and deep learning compilers find it difficult to deeply optimize the entire chip, including hardware acceleration such as VPU or MPU.

[0005] Manual tuning and optimization is inefficient, relies on expert experience, requires familiarity with chip microarchitecture and specialized assembly languages, is highly professional and costly, and cannot quickly adapt to new hardware features.

[0006] Traditional compilation strategies have difficulty dynamically perceiving hardware runtime status (such as cache hit rate and branch prediction), resulting in limitations in static optimization.

[0007] During compiler front-end optimization, the type and number of tensor computing units (SPU, VPU, or MPU) in the chip are unknown, nor is the hierarchical structure of the memory subsystem (cache, TCM, SRAM, DRAM, or HBM, etc.). Furthermore, the computing resources and memory resources cannot be integrated during parallel optimization. There is a lack of deep support for the emerging HBM and in-memory computing, resulting in a split between the computing subsystem and the memory subsystem.

[0008] The lack of a unified scheduling mechanism for multi-core heterogeneous hardware (SPU, VPU, or MPU) leads to low resource utilization and insufficient resource scheduling.

[0009] The lack of unified system-wide resources based on the concept of hyper-heterogeneous and hyper-parallelism, as well as the coordinated scheduling of synchronization and timing at the circuit module level, leads to the fragmentation of the computing subsystem, memory subsystem, external device subsystem and bus subsystem. Summary of the Invention

[0010] In order to overcome the defects of the existing technology, the present invention provides a multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception to solve the above problems.

[0011] The technical solution adopted by the present invention to solve the technical problem is: a method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception, comprising the following steps:

[0012] S1: Acquire hardware feature data and form a hardware feature database;

[0013] S2: A hierarchical and controllable IR exposure mechanism is adopted. Based on the hierarchical intermediate representation and hardware feature database, the source code related to the intrinsic function targeting specific hardware feature data is generated based on the three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set. The source code related to the intrinsic function includes the operator name and operator parameters.

[0014] S3: Use a general compiler to compile the scalar-related source code and the intrinsic function-related source code in the user source code into an executable file or a binary library, or use a general compiler to compile the intrinsic function-related source code into an executable file or a binary library.

[0015] In step S1, hardware feature data is acquired using a variety of AI learning methods, and the hardware feature data includes hardware micro-architecture features of a tensor computing unit, a memory subsystem, external devices, and bus devices.

[0016] Optionally, in step S1, the hardware feature data is obtained by using multiple AI learning methods, that is, multimodal learning is used to obtain the hardware feature data, and the multimodal learning includes static learning, dynamic analysis and neural network prediction;

[0017] The static learning is to use a large language model to parse various micro-architectures from the chip user manual as static feature data;

[0018] The dynamic analysis automatically generates various micro-benchmark codes for AI to test the performance fluctuation range of computing power, throughput, bandwidth, and latency of learning tensor computing units, memory subsystems, external devices, and bus devices as dynamic feature data;

[0019] The neural network prediction model outputs computing power, throughput, bandwidth, and latency under different business conditions, and then selects the combination with the highest computing power, maximum throughput, maximum bandwidth, and lowest latency as the comprehensive optimal solution, or selects one or more combinations of the highest computing power, maximum throughput, maximum bandwidth, and lowest latency as the local optimal solution, and uses the comprehensive optimal solution or the local optimal solution as the predictive feature data.

[0020] Specifically, in step S2, the hierarchical intermediate representation includes a high-level intermediate representation, a middle-level intermediate representation, and a low-level intermediate representation;

[0021] Determine the operator names supported by the VPU or MPU in the hardware chip through the high-level intermediate representation;

[0022] Determine the parameters corresponding to the operators in the high-level intermediate representation through the middle-level intermediate representation;

[0023] Through the underlying intermediate representation, operators, their corresponding parameters, and instruction scheduling of external devices and bus devices are formed into a unified underlying representation of the intrinsic function.

[0024] It is worth noting that, in step S2, the step of determining the operator name supported by the VPU or MPU in the hardware chip through the high-level intermediate representation includes:

[0025] For high-level language source code, based on the operator types supported by the VPU and MPU in the hardware feature data, first convert the matrix-capable scalar loops in the high-level language source code into matrix operators supported by the MPU, and then convert the vector-capable scalar loops in the remaining source code into vector operators supported by the VPU;

[0026] For AI training models, analyze the calculation graph contained in the file output by the AI ​​training model. Based on the operator types supported by the VPU and MPU in the hardware feature data, first convert the matrixable calculation links in the calculation graph into matrix operators, and then convert the vectorizable calculation links in the calculation graph into vector operators.

[0027] Preferably, in step S2, the step of determining the parameters corresponding to the operators in the high-level intermediate representation by using the middle-level intermediate representation includes:

[0028] Obtain the number and shape of each type of tensor computing unit in the chip, the memory subsystem hierarchy, and the size of each type of memory in the memory subsystem hierarchy through hardware feature data;

[0029] The matrixable scalar loop count or the total amount of data in the computation graph of the VPU or MPU-supported operator in the high-level intermediate representation is converted into blocks of parallel computation of the VPU or MPU-supported operator based on the number and shape of each type of tensor computation units as the operator block status, and the corresponding number of blocks is obtained.

[0030] Divide the size of each type of memory in the memory subsystem hierarchy into blocks according to the number of blocks of all computing units, so that each computing unit has corresponding exclusive memory space for parallel computing, and obtain the memory block situation;

[0031] The operator parameters including the operator block status, the number of blocks and the memory block status are formed.

[0032] Specifically, in step S2, according to the hardware feature data corresponding to the external devices and bus devices supporting scalar, vector or matrix operations, the operator names and operator parameters of the corresponding external devices and bus devices are obtained as instruction scheduling of the external devices and bus devices.

[0033] It is worth noting that, in step S2, the IR exposure mechanism is a graded progressive exposure strategy;

[0034] Regarding the IR exposure mechanism, the hardware information exposed by the high-level intermediate representation includes tensor computing units and the operator types actually supported by each type of computing unit;

[0035] The hardware information exposed by the middle-level intermediate representation includes the number and shape of each type of tensor computing unit, the memory subsystem hierarchy, and the size of each type of memory in the memory subsystem hierarchy;

[0036] The hardware information exposed by the underlying intermediate representation includes external devices and bus devices.

[0037] Optionally, in step S2, the three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set includes a scalar computing unit instruction set, a vector computing unit extended instruction set, and a matrix computing unit extended instruction set.

[0038] The beneficial effect of the present invention is that in the multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception, through the collaborative optimization of layered intermediate representation (IR) and RISC-V open source SOC chip, it can quickly adapt to new chips and closely fit the hardware to achieve efficient super-heterogeneous and super-parallel code generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a flowchart of a method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception in one embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a three-level universal computing architecture of a RISC-V open source chip in one embodiment of the present invention;

[0041] Figure 3 This is a flowchart of a detailed implementation method of a RISC-V hardware-aware multi-layer intermediate representation compiler commonly used for high-level language source code and AI training models in one embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following is a further description of specific embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is intended to facilitate understanding of the present invention and does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0043] First, the concepts and English abbreviations involved in this plan are explained as follows:

[0044] Tensor: A broad tensor refers to anything from 0 to n dimensions. Dimension 0 is a scalar, i.e., a single integer or floating-point value. Dimension 1 is a vector, i.e., a set of m integers or floating-point values, such as a one-dimensional array array[m]. Dimension 2 is a matrix, i.e., a set of m by n integers or floating-point values, such as a two-dimensional array array[n,m]. Dimensions 3 and above are three-dimensional arrays or arrays of three or more dimensions. A narrow tensor refers to an n-dimensional tensor (n>0), excluding scalars. This document refers to the narrow tensor when the term "tensor" is used without a broad definition. The shape of a tensor represents the number of elements in each dimension of the narrow tensor. Chunking involves breaking down the overall data required for computation within each high-level language scalar loop or computation graph into chunks that can be efficiently processed by the hardware processing units.

[0045] The SPU (Scalar Processing Unit) represents a scalar processing unit, including integer and floating-point scalar computing units. The VPU (Vector Processing Unit) represents a chip's vector processing unit, including integer and floating-point vector computing units. The MPU (Matrix Processing Unit) represents a chip's matrix processing unit, including integer and floating-point matrix computing units. The MPU, VPU, and SPU are all considered generalized tensor computing units; the MPU and VPU are considered narrow tensor computing units.

[0046] TCM (Tightly Coupled Memory) stands for tightly coupled memory.

[0047] HBM (High Bandwidth Memory) stands for high bandwidth memory.

[0048] TVM (Tensor Virtual Machine) is an open source machine learning compiler stack that optimizes and compiles deep learning models so that they can run efficiently on various hardware.

[0049] XLA (Accelerated Linear Algebra) stands for Accelerated Linear Algebra and is a deep learning compiler.

[0050] LLVM (Low Level Virtual Machine) provides compiler-related support and can perform compile-time optimization, link optimization, online compilation optimization, and code generation for programming languages.

[0051] like Figures 1 to 3 As shown, a compiler optimization strategy fusion method based on a multi-level IR architecture includes:

[0052] S1: Acquire hardware feature data and form a hardware feature database;

[0053] A variety of AI learning methods are used to obtain hardware feature data, including hardware microarchitecture features of tensor computing units, memory subsystems, external devices, and bus devices; the AI ​​learning method is used to reduce labor costs and increase work efficiency.

[0054] The method of using multiple AI learning methods to obtain hardware feature data is to use multimodal learning to obtain hardware feature data:

[0055] Static learning: Static learning involves using a large language model to parse various microarchitectures from chip user manuals as static feature data.

[0056] Dynamic analysis: AI automatically generates various micro-benchmark codes to test the performance fluctuation range of computing power, throughput, bandwidth, and latency of learning tensor computing units, memory subsystems, external devices, and bus devices as dynamic feature data;

[0057] Neural network prediction: The output results of static learning and dynamic analysis are combined and input into the neural network prediction model. The neural network prediction model outputs the computing power, throughput, bandwidth and latency under different business conditions, and then selects the combination with the highest computing power, maximum throughput, maximum bandwidth and lowest latency as the overall optimal solution, or selects one or more combinations of the highest computing power, maximum throughput, maximum bandwidth and lowest latency as the local optimal solution. It can be used to optimize the overall performance or to strengthen the special performance when special application requirements are met. The overall optimal solution or the local optimal solution is used as predictive feature data.

[0058] The hardware feature data represents the microarchitecture parameters of the target hardware and is saved in a specific format as a summary file of the Hardware Abstraction Layer (HAL). The hardware description forms a decision table during compiler pre-compilation and is triggered on demand during optimization. The summary file code is as follows:

[0059]

[0060] S2: Adopt a hierarchical and controllable IR exposure mechanism. Based on the hierarchical intermediate representation and hardware feature database, and based on the three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set, generate intrinsic function-related source code for specific hardware feature data; the intrinsic function-related source code includes the operator name and operator parameters.

[0061] Specifically, under the standard of heterogeneous multi-core RISC-V open source SOC chip architecture, we build Figure 2 The RISC-V open source chip instruction set and extended instruction set composed of the scalar computing unit, vector computing unit and matrix computing unit shown in the figure include the scalar computing unit instruction set (RISC-VR's I, M, F, D and other modules), the vector computing unit extended instruction set (RISC-V Vector module) and the matrix computing unit extended instruction set (RISC-V Matrix module). The three-level general computing power architecture covers all computing units in the host system such as traditional non-general computing power CPU, SIMD, GPU, TPU, APU or DPU. Among them, scalar is used to process control flow and branch logic, which is point operation; vector is used to accelerate parallel data calculation, which is line operation; matrix is ​​used for block calculation, which is surface operation;

[0062] Under the standards of the RISC-V open source chip architecture, we break the shackles of traditional non-general computing power and build a three-level general computing power architecture of "scalar base, vector acceleration, and matrix sprint".

[0063] RISC-V Matrix extensions are under development and no unified standard has been made public, so the content of this application has 1 to 3 years of forward-looking innovation.

[0064] In this proposal, only these three RISC-V extensions are considered to be the most promising candidates for developing a universal three-tier computing architecture for image processing, signal processing, and machine learning. These three standards are expected to unify hardware and software, eliminating the fragmented standards currently in place for CPUs, SIMDs, GPUs, NPUs, and TPUs.

[0065] For the hierarchical intermediate representation, it includes high-level intermediate representation, middle-level intermediate representation and low-level intermediate representation.

[0066] like Figure 3 As shown in the figure, the core of the high-level intermediate representation is to determine the operator names supported by the VPU or MPU in the hardware chip:

[0067] For high-level language source code, based on the operator types supported by the VPU and MPU in the hardware feature data, we first convert the matrix-capable scalar loops in the source code into matrix operators supported by the MPU. Then, we convert the vector-capable scalar loops in the remaining source code into vector operators supported by the VPU. This conversion results in a high-level intermediate representation consisting of the corresponding matrix and vector operators.

[0068] For AI training models (such as ONNX files), the computation graph contained in the file is analyzed. Based on the operator types supported by the VPU and MPU in the hardware feature data, the matrixable computational steps in the computational graph are first converted into matrix operators, and then the vectorable computational steps in the computational graph are converted into vector operators. The remaining computational steps that cannot be converted are converted into scalar loops described in a high-level language. This conversion results in a high-level intermediate representation consisting of the corresponding matrix and vector operators.

[0069] Before the conversion, hardware feature data will be considered. That is, whether the chip has VPU and MPU and the supported operator types will be considered based on the hardware feature data.

[0070] If there is an MPU and the corresponding MPU operator is supported, the part of the matrixable scalar loop or calculation graph link that conforms to the MPU operator type is converted into a matrix operator;

[0071] After performing the conversion that meets the above conditions, if there is a VPU and the corresponding VPU operator support, the operator type that meets the VPU support in the vectorizable scalar loop or calculation graph link is converted into a vector operator;

[0072] After the conversion that meets the above two conditions, the rest of the high-level language source code remains unchanged, and the computation graph can only be converted into a scalar loop; operator types that have vector and matrix computation units but are not actually supported are also handled according to the above conditions.

[0073] The core of the middle-level intermediate representation is the parameters of the operators in the high-level intermediate representation.

[0074] Obtain the number and shape of each type of tensor computing unit in the chip, the memory subsystem hierarchy, and the size of each type of memory in the memory subsystem hierarchy through hardware feature data;

[0075] Computing unit blocking: The number of matrixable scalar loops or the total amount of data in the computational graph of the hardware chip VPU or MPU-supported operators in the high-level intermediate representation is converted into blocks for parallel computing of the VPU or MPU-supported operators as operator blocking, based on the number and shape of each type of tensor computing units. The corresponding number of blocks is then obtained.

[0076] Memory partitioning: Divide the size of each type of memory in the memory subsystem hierarchy into blocks according to the number of blocks of all computing units, so that each computing unit has corresponding exclusive memory space for parallel computing, and obtain the memory partitioning situation;

[0077] The operator parameters including the operator block status, the number of blocks and the memory block status are formed.

[0078] The core of the underlying intermediate representation is to form a unified underlying representation of the intrinsic function by combining the operators and the corresponding parameters of the intermediate representation layer, as well as the instruction scheduling of external devices and bus devices.

[0079] The reason why intrinsic functions are used instead of the seemingly simple IR (intermediate representation) of traditional compilers such as GCC or LLVM is that, first, the compilation operation process before the IR of traditional compilers belongs to the front-end. The IR and front-end of traditional compilers do not contain any hardware information, and are only deeply coupled with the specific target hardware information in the back-end. Secondly, intrinsic functions are the C language form of hardware assembly instructions (or machine instructions), which are essentially specific hardware-specific instructions that are deeply bound to the target hardware information.

[0080] Based on the hardware feature data corresponding to external devices and bus devices that support scalar, vector, or matrix operations, high-level and middle-level intermediate representations are performed on these external devices and bus devices to obtain the corresponding operator names (such as bus operations and data consistency operation instructions) and operator parameters, which are used for instruction scheduling of external devices and bus devices. Combined with the operator names and operator parameters corresponding to the hardware chips, this system achieves hyper-heterogeneous hyper-parallelism, unified scheduling of synchronous parallel computing, and achieves system-wide parallel scheduling and data flow coordination. Ultimately, the underlying operator representation is formed in the form of intrisic functions.

[0081] The IR exposure mechanism in this solution is controllable using the hardware description language (HDL) and hierarchical intermediate representation (HIR). A hierarchical progressive exposure strategy is employed, allowing each IR level to access only necessary hardware information.

[0082] Regarding the IR exposure mechanism, the hardware information exposed by the high-level intermediate representation includes tensor computing units and the operator types actually supported by each type of computing unit;

[0083] The hardware information exposed by the middle-level intermediate representation includes the number and shape of each type of tensor computing unit, as well as the memory subsystem hierarchy and the size of each type of memory in the memory subsystem hierarchy;

[0084] The hardware information exposed by the underlying intermediate representation includes external devices and bus devices.

[0085] Step S2 breaks the conventional restriction of the compiler front end not using hardware information. The compiler front end injects hardware information at an early stage to make global optimization decisions and release deeper performance potential.

[0086] The front-end knows the hardware information in advance and can coordinate the allocation of computing tasks (such as allocating vector calculations to vector computing units and matrix calculation operations to matrix computing units). The parallelism of calculations at all levels (including in-memory calculations) supports the deep integration of heterogeneous parallel computing, rather than passive allocation on the back-end.

[0087] This solves traditional problems, such as front-end optimizations (such as loop unrolling and constant propagation) being conservative due to a lack of hardware details (such as cache size and SIMD tensor register width); and back-ends, while aware of hardware details, being constrained by the fixed IR structure (such as loop nesting order), preventing architectural refactoring. By knowing the hardware parameters in advance, the compilation front-end can directly generate hardware-friendly computation graphs or loop structure transformations and blocks (such as block division based on cache size and data layout adjustment based on tensor register width) during the IR construction phase.

[0088] To avoid conflicts in later optimization, if the front-end knows that the chip has a dedicated matrix calculation unit, it can avoid splitting matrix multiplication into vector operations and retain them as atomic operators for efficient mapping to hardware instructions.

[0089] Hardware constraints narrow the optimization search space in advance (for example, the loop block size only needs to be searched within the L1 cache capacity), improving the efficiency of automated tuning and accelerating similar tuning processes such as AutoTVM.

[0090] S3: Use a general compiler (LLVM, GCC, CLANG, etc.) to compile the scalar-related source code and the intrinsic function-related source code in the user source code into an executable file or binary library, or use a general compiler to compile the intrinsic function-related source code into an executable file or binary library.

[0091] like Figure 3 As shown, for high-level language source code, a general compiler is used to compile the scalar-related source code and intrinsic function-related source code in the user source code into an executable file or binary library; for the calculation graph output by the AI ​​training model, a general compiler is used to compile the intrinsic function-related source code into an executable file or binary library.

[0092] Specifically, assembly language, machine language and other similar methods that are equivalent to intrinsic functions are also within the scope of protection.

[0093] In the described multi-layer intermediate representation compiler implementation method based on RISC-V open source chip hardware perception, by co-optimizing the layered intermediate representation (IR) with the RISC-V open source SOC chip, it can quickly adapt to new chips and closely fit the hardware to achieve efficient super-heterogeneous and super-parallel code generation.

[0094] The compilation technology of this application can be used for AI acceleration hardware optimization of traditional compilation of high-level languages ​​​​(such as C / C++), and can also compile trained AI models (such as ONNX, etc.) into deployable executable files, integrating traditional compilers and deep learning compilers into a general compiler.

[0095] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It is apparent to those skilled in the art that various changes, modifications, substitutions, and variations to these embodiments may be made without departing from the principles and spirit of the present invention, and these changes and modifications still fall within the scope of protection of the present invention.

Claims

1. A method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception, characterized in that: The following steps are involved: S1: Acquire hardware feature data and form a hardware feature database; In step S1, hardware feature data is acquired using a variety of AI learning methods, wherein the hardware feature data includes hardware microarchitecture features of a tensor computing unit, a memory subsystem, external devices, and bus devices; S2: A hierarchical and controllable IR exposure mechanism is adopted. Based on the hierarchical intermediate representation and hardware feature database, the source code related to the intrinsic function targeting specific hardware feature data is generated based on the three-level general computing power architecture of the RISC-V open source chip instruction set and the extended instruction set. The source code related to the intrinsic function includes the operator name and operator parameters. The hierarchical intermediate representation includes the high-level intermediate representation, the middle-level intermediate representation, and the low-level intermediate representation. In step S2, the step of determining the operator name supported by the VPU or MPU in the hardware chip through the high-level intermediate representation includes: For high-level language source code, based on the operator types supported by the VPU and MPU in the hardware feature data, first convert the matrix-capable scalar loops in the high-level language source code into matrix operators supported by the MPU, and then convert the vector-capable scalar loops in the remaining source code into vector operators supported by the VPU; For AI training models, analyze the computation graph contained in the output file of the AI ​​training model. Based on the operator types supported by the VPU and MPU in the hardware feature data, first convert the matrix-capable computational steps in the computation graph into matrix operators, and then convert the vector-capable computational steps in the computation graph into vector operators. The IR exposure mechanism is a graded progressive exposure strategy; Regarding the IR exposure mechanism, the hardware information exposed by the high-level intermediate representation includes tensor computing units and the operator types actually supported by each type of computing unit; The hardware information exposed by the middle-level intermediate representation includes the number and shape of each type of tensor computing unit, the memory subsystem hierarchy, and the size of each type of memory in the memory subsystem hierarchy; The hardware information exposed by the bottom intermediate representation includes external devices and bus devices; S3: Use a general compiler to compile the scalar-related source code and the intrinsic function-related source code in the user source code into an executable file or a binary library, or use a general compiler to compile the intrinsic function-related source code into an executable file or a binary library.

2. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception according to claim 1 is characterized in that: In step S1, the hardware feature data is obtained by using multiple AI learning methods, that is, multimodal learning is used to obtain the hardware feature data, and the multimodal learning includes static learning, dynamic analysis and neural network prediction; The static learning is to use a large language model to parse various micro-architectures from the chip user manual as static feature data; The dynamic analysis automatically generates various micro-benchmark codes for AI to test the performance fluctuation range of computing power, throughput, bandwidth, and latency of learning tensor computing units, memory subsystems, external devices, and bus devices as dynamic feature data; Neural network prediction combines the output results of static learning and dynamic analysis and inputs them into the neural network prediction model. The neural network prediction model outputs computing power, throughput, bandwidth and latency under different business conditions, and then selects the combination with the highest computing power, maximum throughput, maximum bandwidth and lowest latency as the comprehensive optimal solution, or selects one or more combinations of the highest computing power, maximum throughput, maximum bandwidth and lowest latency as the local optimal solution, and uses the comprehensive optimal solution or the local optimal solution as the predictive feature data.

3. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception according to claim 1, characterized in that: In step S2, the operator name supported by the VPU or MPU in the hardware chip is determined through the high-level intermediate representation; Determine the parameters corresponding to the operators in the high-level intermediate representation through the middle-level intermediate representation; Through the underlying intermediate representation, operators, their corresponding parameters, and instruction scheduling of external devices and bus devices are formed into a unified underlying representation of the intrinsic function.

4. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception according to claim 1, characterized in that: In step S2, the step of determining the parameters corresponding to the operators in the high-level intermediate representation through the middle-level intermediate representation includes: Obtain the number and shape of each type of tensor computing unit in the chip, the memory subsystem hierarchy, and the size of each type of memory in the memory subsystem hierarchy through hardware feature data; The matrixable scalar loop count or the total amount of data in the computation graph of the VPU or MPU-supported operator in the high-level intermediate representation is converted into blocks of parallel computation of the VPU or MPU-supported operator based on the number and shape of each type of tensor computation units as the operator block status, and the corresponding number of blocks is obtained. Divide the size of each type of memory in the memory subsystem hierarchy into blocks according to the number of blocks of all computing units, so that each computing unit has corresponding exclusive memory space for parallel computing, and obtain the memory block situation; The operator parameters including the operator block status, the number of blocks and the memory block status are formed.

5. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception according to claim 1, characterized in that: In step S2, according to the hardware feature data corresponding to the external devices and bus devices supporting scalar, vector or matrix operations, the operator names and operator parameters of the corresponding external devices and bus devices are obtained as instruction scheduling of the external devices and bus devices.

6. The method for implementing a multi-layer intermediate representation compiler based on RISC-V open source chip hardware perception according to claim 1, characterized in that: In step S2, the three-level general computing power architecture of the RISC-V open source chip instruction set and extended instruction set includes a scalar computing unit instruction set, a vector computing unit extended instruction set, and a matrix computing unit extended instruction set.

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