Attack method for logic locking composite scheme
By building a fan-in cone to identify and remove anti-SAT attack blocks, the traditional solution key is restored using SAT attacks, which solves the high computing resources and training dataset dependence problems of the logically locked composite solution, and achieves efficient circuit function recovery.
Patent Information
- Application Number
- CN202510522517.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-08-26
AI Technical Summary
The existing attack methods of logic-locking composite schemes have the problem of high computing resource requirements, training data sets are required, and the original circuit function cannot be fully restored.
By building a fan-in cone, identifying and removing anti-SAT attack blocks, and resuming the keys of the traditional solution using SAT attacks, realizing accurate and efficient attacks on the logically locked composite solution.
A logic-locked composite solution attack with high success rate is realized, which can quickly restore the original circuit function, reduce the computing resource requirements and avoid dependence on the training data set.
Smart Images
Figure CN120542340A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of integrated circuit (IC) hardware security technology and relates to an attack method for a logic locking protection mechanism, and in particular to an attack method for a composite protection mechanism that integrates a traditional logic locking scheme with an anti-SAT attack scheme. Background Art
[0002] With the increasing complexity of integrated circuit design and the globalization of the supply chain, some aspects of IC design and manufacturing often need to be outsourced. This brings significant flexibility and cost-effectiveness to chip design. However, it also raises security risks. Therefore, how to ensure the security, integrity, and protection of intellectual property rights of integrated circuits from misappropriation has become a key issue in protecting modern chip design.
[0003] Logic locking is an effective chip security protection mechanism that introduces additional logic units, called "key gates," into the original hardware design to ensure that the circuit will work properly only when the correct key is input; otherwise, the circuit will produce incorrect outputs or fail to perform the intended function. Figure 2 (a) shows an original design gate-level netlist. Figure 2 (b) A logic exclusive OR gate (XOR) G5 is added to the original design netlist. When k = 0, the output O2 will not be affected. When k = 1, the output O2 may be flipped.
[0004] At the same time, attack methods targeting logic locks have also become a research area. Sensitization attacks, an early and representative attack method against logic locks, sensitize a single key bit to the output by selecting a specific input pattern. By observing the output of the original design circuit under this input pattern, the key value is obtained. Subsequently, enhanced logic lock protection mechanisms were proposed. These select specific key gate insertion locations to cause multiple key bits to interfere with each other in the sensitization path, effectively resisting sensitization attacks. Subsequently, SAT attacks were proposed. SAT attacks iteratively search for discriminative inputs, each of which can eliminate a large number of incorrect keys, allowing the correct key to be found quickly. To combat SAT attacks, representative anti-SAT attack schemes, AntiSAT and SARLock, have been proposed. These schemes effectively resist SAT attacks by reducing the number of keys eliminated by each discriminative input. However, their protection effectiveness is limited when used alone. Logic lock protection schemes prior to SAT attacks are known as traditional schemes. Current logic lock protection mechanisms combine traditional schemes with anti-SAT attack schemes into the original design circuit to enhance overall protection capabilities, known as composite schemes. Existing research has proposed attack methods against complex logic lock schemes. Shamsi K et al. proposed an attack method called AppSAT. AppSAT can quickly recover an approximately correct key. However, when this key is applied, certain input patterns still produce erroneous outputs. This is an approximate attack method and cannot fully restore the functionality of the original circuit design. Alaql A et al. proposed a combined attack strategy called SOMA. SOMA cleverly combines multiple existing attack methods, gradually optimizing the attack process and ultimately restoring the functionality of the locked circuit. SOMA involves multiple iterations and complex algorithms, requiring high computing resources. In addition, some attacks used in SOMA require a training dataset using the same locking technique as the target circuit. Without a suitable training dataset, the effectiveness of the attack can be greatly reduced.
[0005] Currently, attack methods targeting logic lockup schemes still have some significant limitations. First, some attack methods rely on approximate attack strategies and cannot fully restore the functionality of the original design circuit. Second, some methods require high computing resources and require training datasets generated using the same lockup technology as the target circuit, which may be difficult to obtain or construct in real applications.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention
[0007] The present invention provides an attack method for a logic-locked composite scheme, which is used to quickly and efficiently remove the anti-SAT blocks in the logic-locked composite scheme, reducing the protection effect of the composite scheme to that of a traditional scheme, and then using a SAT attack to recover the key of the traditional scheme, thereby restoring the function of the original circuit before the logic lock.
[0008] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.
[0009] According to a first aspect of the present invention, there is provided a method for attacking a logical locking composite scheme, the method comprising:
[0010] Step 1: Use FPGA synthesis tools to perform logic synthesis on the integrated circuit design file after logic locking to generate an FPGA netlist file consisting of LUTs;
[0011] Step 2: Flatten the FPGA netlist to eliminate the design hierarchy and obtain a flattened FPGA netlist.
[0012] Step 3: Build the fan-in cone for each LUT and multiplexer in the netlist file generated in step 2;
[0013] Step 4: Delete the sub-cone from the fan-in cone set;
[0014] Step 5: Calculate the number of LUTs with low flip rate in each fan-in cone and calculate their proportion to the total number of LUTs in the fan-in cone;
[0015] Step 6: Define a sorting metric based on the number and proportion of LUTs with low flip rates in the fan-in cone, sort the fan-in cones, and find the output signal of the SAT attack resistance block from the output signals of the top five fan-in cones with the highest metric.
[0016] Step 7: Force the predicted anti-SAT attack block output signal to zero, and use the SAT attack to recover the key used by the logic lock.
[0017] In some exemplary embodiments, in step 3, the structure of the fan-in cone is an n-ary tree, each node represents a LUT or MUX, and the output signal of the fan-in cone is determined by the LUT or MUX output of the root node; if the output signal of a LUT or MUX is connected to the input signal of a node in the previous layer, it is added as a node in this layer; a fan-in cone can be constructed by setting the fan-in level.
[0018] In some exemplary embodiments, the fan-in level is set to nine.
[0019] In some exemplary embodiments, in step 4, if the output signal of fan-in cone B is connected to the fan-in signal of a LUT in fan-in cone A, then fan-in cone B is a sub-cone of fan-in cone A.
[0020] In some exemplary embodiments, in step 5, if the proportion of '0' or '1' in the binary representation of the LUT after the initialization vector of the LUT is converted to binary is less than 1 / 8, then the LUT is determined to have a low flip rate.
[0021] In some exemplary embodiments, in step 6, the ranking index is defined as xy 4 , which is used to screen the fan-in cone with a large number and proportion of LUTs with low flip rate.
[0022] According to a second aspect of the present invention, a storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the attack method of the logical locking composite scheme described in the first aspect is implemented.
[0023] According to a third aspect of the present invention, a computer program product is provided, on which a computer program is stored. When the computer program is executed by a processor, the attack method of the logical locking composite scheme described in the first aspect is implemented.
[0024] According to a fourth aspect of the present invention, there is provided an electronic device, comprising:
[0025] processor; and
[0026] a memory for storing executable instructions of the processor;
[0027] The processor is configured to implement the attack method of the logic locking composite scheme described in the first aspect above when executing the executable instructions.
[0028] The embodiment of the present invention provides an attack method for a logic lock composite scheme, which uses the flipping behavior characteristics of the LUT to locate the control signal of the anti-SAT block. It also implements a removal attack against the logic lock composite scheme with a high attack success rate. Experiments are conducted on multiple logic lock composite schemes to prove the effectiveness of the proposed attack method.
[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0031] Figure 1 The present invention is an overall design flow chart of the method.
[0032] Figure 2 Schematic diagram of logic locking: (a) original design; (b) locking circuit with a key gate inserted.
[0033] Figure 3 Schematic diagram of the logical structure of the fan-in cone.
[0034] Figure 4 Define a graph for a subcone.
[0035] Figure 5 This is the LUT structure diagram.
[0036] Figure 6 Schematic diagram of the AntiSAT design structure: (a) The construction basis of the Anti-SAT block; (b) A feasible Anti-SAT block construction.
[0037] Figure 7 Graph of the algorithm for constructing the fan-in cone.
[0038] Figure 8 Diagram of the algorithm for predicting the output signal of the anti-SAT attack block. DETAILED DESCRIPTION
[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0040] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.
[0041] In response to the shortcomings and deficiencies of the existing technology, this example embodiment provides an accurate and efficient attack method against the logic-locked composite scheme. First, the anti-SAT attack scheme in the composite scheme is logically removed, and then the key of the traditional scheme in the composite scheme is restored to fully restore the functionality of the original circuit design.
[0042] refer to Figure 1 As shown, the following steps may be specifically included:
[0043] Step 1: First, use the FPGA synthesis tool to perform logic synthesis on the integrated circuit design file after logic locking, map the circuit to the FPGA process library, and thus generate an FPGA netlist file mainly composed of LUT (Look-up Table).
[0044] Specifically, the generated LUT-based FPGA netlist file mainly includes input signals, output signals, intermediate signals, LUTs, MUXs, input buffers (ibuf), and some assign statements.
[0045] In the subsequent steps, the generated FPGA netlist file will be analyzed in detail.
[0046] Step 2: Flatten the synthesized FPGA netlist to eliminate the design hierarchy and obtain a flattened FPGA netlist.
[0047] In the subsequent steps, the flattened FPGA netlist is represented by W.
[0048] Step 3: Build a fan-in cone for each LUT and multiplexer (MUX, Multiplexer) in the netlist file generated in step 2. The fan-in cone structure is as follows: Figure 3 shown.
[0049] Specifically, a fan-in cone is constructed for each LUT and MUX in W. First, the basic concept of fan-in cone is defined. Fan-in cone is a logic structure in which each element consists of a lookup table (LUT) or multiplexer (MUX). Its overall structure is similar to an n-ary tree, where each node represents a LUT or MUX, and the output signal of the fan-in cone is determined by the LUT or MUX output of the root node, such as Figure 3 shown.
[0050] After logic synthesis, some key inputs of traditional schemes may be connected to ibufs. The output signals of such ibufs are stored in keyWireList. If the input signals of a LUT contain key inputs or intersect with keyWireList, these LUTs are stored in LutsToFilter. When constructing the fan-in cone, these LUTs need to be excluded because they do not contribute to the identification of anti-SAT cones and may introduce interference in subsequent identification.
[0051] A fan-in cone is constructed for each LUT and MUX in W. The process includes the following: First, all LUT and MUX information in W is extracted, including its type, input signal, output signal, etc. Then, this data is processed. In the process of constructing the fan-in cone, the parent-child relationship between nodes is as follows: Figure 3 As shown in the figure, if the fan-out signal of LUT_B is connected to a fan-in signal of LUT_A, then LUT_B becomes a child node of LUT_A. The process of constructing a fan-in cone is similar to constructing an n-ary tree: nodes on the first level are children of the root node, nodes on the second level are children of nodes on the first level, and nodes on the nth level are children of nodes on the n-1th level. By setting the fan-in level, or the height of the tree, a complete fan-in cone can be constructed. The output signal of the fan-in cone is determined by the output signal of the root node.
[0052] The specific algorithm for constructing the fan-in cone is as follows: Figure 7 As shown in Figure 2. curLevel represents the node set of the current layer, and preLevel represents the node set of the previous layer. Lines 4-6 of Algorithm search for nodes in the current layer. Lines 7-16 of Algorithm iteratively update the current layer until no nodes in the current layer are in the set LutsToFilter. Lines 9-14 of Algorithm replace a node with its child nodes if it is in LutsToFilter. This eliminates the impact of LUTs with traditional key inputs on anti-SAT cone recognition.
[0053] In this embodiment, the fan-in level is represented by coneLevel. When coneLevel is set to a larger value, the time complexity of the algorithm will increase, and when coneLevel is set to a smaller value, the anti-SAT block may not be fully identified. Considering the efficiency and recognition ability comprehensively, coneLevel can be set to 9 in the specific implementation.
[0054] Step 4: After step 3, a fan-in cone set is obtained. The sub-cone is deleted from the fan-in cone set to avoid misjudgment caused by the output signal prediction of the anti-SAT attack block.
[0055] Specifically, after constructing all fan-in cones, a fan-in cone set (denoted by D) is obtained. If the output signal of fan-in cone B is connected to the input signal of a node of fan-in cone A, then fan-in cone B is called a sub-cone of fan-in cone A, such as Figure 4 Specifically, in the design of Anti-SAT, there are two AND trees based on point functions, and the sub-cone of the Anti-SAT cone also exhibits a low flip probability, which may cause misjudgment of the Anti-SAT cone, so the sub-cone needs to be deleted from D.
[0056] Step 5: Calculate the number of LUTs with low flip rate in each fan-in cone, denoted as x, and calculate their proportion in the total number of LUTs in the fan-in cone, denoted as y.
[0057] Specifically, a LUT with a low flip rate is defined. The structure of the LUT is as follows Figure 5 As shown, each LUT has an initialization vector (IV) that represents the truth table result of the LUT's input signal. The specific function is determined by the value of .INIT. For example, for a two-input LUT whose function is logical OR, the .INIT value is .INIT(4'b1110). Based on this, the standard for LUTs with a low flip rate is defined: if the proportion of '0' or '1' in the binary representation of a LUT after its .INIT value is converted to binary is less than 1 / 8, the LUT is considered to have a low flip rate. Calculate the number of LUTs with a low flip rate in each fan-in cone, denoted as x, and calculate the proportion of LUTs with a low flip rate in the total number of LUTs in the fan-in cone, denoted as y.
[0058] Step 6: Define the sorting index based on the number and proportion of LUTs with low flip rate in the fan-in cone. Sort all fan-in cones and select the output signals of the 5 fan-in cones with the highest index as the anti-SAT attack block (a structure of the anti-SAT attack block is as follows Figure 6 Each time a candidate signal is forced to be 0, a SAT attack is performed to determine whether the effect of the anti-SAT attack block is eliminated, thereby determining the output signal of the anti-SAT attack block.
[0059] Specifically, we define a prediction index and sort the fan-in cone set according to the prediction index. The goal is to identify fan-in cones with large x and y. Such fan-in cones indicate that the flip probability of their output signals is very low, which is consistent with the characteristics of the output signal of the anti-SAT attack block implemented based on the point function. Figure 6The design structure of a representative anti-SAT attack block is shown in the following figure. The output signal of the anti-SAT attack block is constant when the correct key is used. However, when the incorrect key is used, only one input pattern will cause the output to be opposite to the other patterns. Therefore, by identifying signals with a low probability of flipping, the output signal of the anti-SAT attack block can be effectively predicted.
[0060] In this embodiment, the prediction index set is xy 4 The purpose of setting this indicator is to defeat two types of misjudgments: one is that the x of the fan-in cone is large and the y is small. The other is that the x of the fan-in cone is small and the y is large.
[0061] Step 7: In the logic-locked design, force the predicted output signal value of the SAT-resistant block to zero. This eliminates the protection provided by the SAT-resistant block. The SAT attack can then be used to recover the key used for the logic lock.
[0062] Specifically, the prediction algorithm is Figure 8 As shown in the figure, by sorting the fan-in cone set D and determining the output signal of the SAT attack-resistant block (denoted by s) from the output signals of the five fan-in cones with the largest indices, and then forcing the signal s in V to 0, the anti-SAT attack scheme in the logic lock composite scheme is eliminated. Finally, the SAT attack is used to recover the key from V, obtaining the key K of the logic lock circuit.
[0063] The present exemplary embodiment is verified by simulation experiments below:
[0064] The verification environment is as follows:
[0065] This invention targets logic-locked integrated circuit design files, using Yosys as the synthesis tool. The ISCAS85 benchmarks were used for analysis. The experimental environment consisted of a computer equipped with a 3GHz eight-core Intel CPU and 16GB of RAM. The attack algorithm was implemented in Python. To demonstrate the effectiveness of the invention against logic-locked composite schemes, three composite schemes from the ISCAS85 benchmark were selected for verification, as described below:
[0066] AntiSAT+RND: randomly inserts XOR / XNOR key gates into the circuit and also inserts AntiSAT blocks to increase protection strength.
[0067] AntiSAT+SLL: Inserts XOR / XNOR key gates at specific locations to avoid variable key gates, and adds AntiSAT blocks at the same time.
[0068] SARLock+LogicCone: Inserts a MUX key gate into the logic cone, randomly selects incorrect MUX paths from the circuit to construct virtual functions, and adds a SARLock block.
[0069] Experimental verification results:
[0070] In the ISCAS85 benchmark, we added two different AntiSAT composite schemes. Within each composite scheme, four different key addition schemes were used in all benchmarks, except for c432 and c499, which had three. In each scheme, the key length of the AntiSAT blocks within the same circuit was the same, equal to the length of the benchmark's primary input signal. The difference lay in the key lengths of the traditional schemes, which were 32, 64, 128, and 256, respectively. For all benchmarks, the AntiSAT blocks employed security integration. Table 1 shows the attack results for AntiSAT+RLL, and Table 2 shows the attack results for AntiSAT+SLL. Similarly, a SARLock composite scheme was added to the ISCAS85 benchmarks. In this scheme, the key length of the SARLock blocks within the same circuit was equal to the benchmark's primary input length, while the key lengths of the traditional schemes were set to 32, 64, 128, and 256, respectively. Table 3 shows the attack results for SARLock+LogicCone.
[0071] For the ISCAS85 benchmarks, each composite scheme consists of 38 test benchmarks. In the AntiSAT+RLL scheme, our attack success rate was 37 / 38 (97.4%). In the AntiSAT+SLL scheme, the success rate reached 38 / 38 (100%). For SARLock+LogicCone, the success rate reached 38 / 38 (100%). Overall, we accurately identified the control signals of the anti-SAT attack block in 113 of the 114 test benchmarks, achieving an average success rate of 99.1%. Further analysis shows that for the Anti-SAT+RLL scheme, in 35 benchmarks, the output signal of the fan-in cone with the largest index value is the output signal of the anti-SAT attack block. For Anti-SAT+SLL, this occurred in 38 benchmarks, and for SARLock+LogicCone, this occurred in 37 circuits. Regarding execution time, the attack completed within 6 minutes for all test benchmarks, except for c6288. Further analysis shows that, except for c6288 and c3540, the attacks on the remaining test benchmarks were completed within 3 minutes.
[0072] After predicting the output signal of the SAT-resistant block, we disabled this signal in the benchmark (forcing it to 0). We then used the SAT tool to attack the removed test benchmark to recover the keys of the traditional scheme. Experimental results showed that, with the exception of c6288, the maximum number of iterations under the SAT attack for all test benchmarks was 103, and all traditional keys were successfully recovered within 23 minutes. Finally, we used the SAT tool to verify the correctness of the recovered traditional keys. Experimental results show that all recovered keys can achieve equivalent functionality to the original circuit in circuit applications.
[0073] Table 1 AntiSAT+RLL attack results
[0074]
[0075]
[0076] Table 2 AntiSAT+SLL attack results
[0077]
[0078] Table 3 SARLock+LogicCone attack results
[0079]
[0080] Other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the invention herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the claims.
[0081] It should be understood that the present invention is not limited to the exact construction described above and shown in the drawings and that various modifications and variations can be made without departing from the scope thereof, which is limited only by the appended claims.
Claims
1. An attack method against a logical lock compound scheme, characterized in that: The following steps are involved: Step 1: Use FPGA synthesis tools to perform logic synthesis on the integrated circuit design file after logic locking to generate an FPGA netlist file consisting of LUTs; Step 2: Flatten the FPGA netlist to eliminate the design hierarchy and obtain a flattened FPGA netlist. Step 3: Build the fan-in cone for each LUT and multiplexer in the netlist file generated in step 2; Step 4: Delete the sub-cone from the fan-in cone set; Step 5: Calculate the number of LUTs with low flip rate in each fan-in cone and calculate their proportion to the total number of LUTs in the fan-in cone; Step 6: Define a sorting metric based on the number and proportion of LUTs with low flip rates in the fan-in cone, sort the fan-in cones, and find the output signal of the SAT attack resistance block from the output signals of the top five fan-in cones with the highest metric. Step 7: Force the predicted anti-SAT attack block output signal to zero, and use the SAT attack to recover the key used by the logic lock.
2. The attack method of the logic lock composite scheme according to claim 1, characterized in that: In step 3, the structure of the fan-in cone is an n-ary tree, where each node represents a LUT or MUX. The output signal of the fan-in cone is determined by the LUT or MUX output of the root node. If the output signal of a LUT or MUX is connected to the input signal of a node in the previous layer, it is added as a node in this layer. A fan-in cone can be constructed by setting the fan-in level.
3. The attack method of the logic lock composite scheme according to claim 2, characterized in that: The fan-in level is set to 9.
4. The attack method of the logic lock compound scheme according to claim 1 is characterized in that: In step 4, if the output signal of fan-in cone B is connected to the fan-in signal of a certain LUT in fan-in cone A, then fan-in cone B is a sub-cone of fan-in cone A.
5. The attack method of the logic lock compound scheme according to claim 1 is characterized in that: In step 5, if the proportion of '0' or '1' in the binary representation of the LUT after the initialization vector of the LUT is converted into binary is less than 1 / 8, then the LUT is determined to be a LUT with a low flip rate.
6. The attack method of the logic lock compound scheme according to claim 1, characterized in that: In step 6, the sorting index is defined as xy 4 , which is used to screen the fan-in cone with a large number and proportion of LUTs with low flip rate.
7. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the attack method of the logic locking composite scheme according to any one of claims 1 to 6 is implemented.
8. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the attack method of the logic locking composite scheme according to any one of claims 1 to 6 is implemented.
9. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the attack method of the logic locking composite scheme according to any one of claims 1 to 6 by executing the executable instructions.