Asynchronous counter, ramp generator, analog-to-digital converter and image sensor
By optimizing the logic gate connection of odd and even-order flip-flops in asynchronous counters, the delay time of the clock input signal is reduced, the problem of output signal delay of the asynchronous counters under high-frequency clocks is solved, and the performance of the image sensor is improved.
Patent Information
- Application Number
- CN202510572538.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-06
- Publication Date
- 2025-08-26
AI Technical Summary
After the asynchronous counter of the existing SS ADC increases the clock signal frequency, the delay time of the output signal of the different bits of the asynchronous counter increases, resulting in an error in the output signal.
Multiple cascaded D flip-flops, odd and even flip-flops are connected through specific logic gates to optimize the generation process of clock input signals and reduce the delay time.
It effectively reduces the delay time of the output signal under different bits of the asynchronous counter, and improves the frame rate of the image sensor and the accuracy of the output signal.
Smart Images
Figure CN120546677A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of integrated circuits, and in particular relates to an asynchronous counter, a ramp generator, an analog-to-digital converter and an image sensor. Background Art
[0002] The SS ADC (Single Slope Digital-to-Analog Converter) is widely used in CMOS (Complementary Metal-Oxide-Semiconductor) image sensors due to its simple circuitry. Each pixel column requires only one comparator and counter, and all columns share a common ramp signal, resulting in good column consistency. However, existing SS ADCs have a significant drawback: slow quantization speed, which limits the expansion of CMOS image sensors towards higher resolutions or larger pixel arrays.
[0003] Considering that the slope of RAMP (ramp signal output by the ramp generator) is proportional to the frequency of the clock signal, the time required for image signal quantization can be reduced and the frame rate of the image output by the image sensor can be increased by increasing the frequency of the clock signal.
[0004] However, as the clock signal frequency increases, the delay between the output signals of the asynchronous counter within the ramp generator increases. When the maximum delay of the asynchronous counter's output signal exceeds half a clock cycle, the highest bit is sampled and output by the D latch only when the next clock edge triggers it, resulting in an erroneous output signal.
[0005] Therefore, an asynchronous counter is urgently needed to reduce the delay time of output signals at different bit positions to solve the above problems. Summary of the Invention
[0006] The present application proposes an asynchronous counter, a ramp generator, an analog-to-digital converter, and an image sensor, which are used to reduce the delay time of output signals of different bits in the asynchronous counter.
[0007] To achieve the above objectives, this application proposes the following technical solutions: In a first aspect of the present application, an asynchronous counter is provided, comprising: A plurality of cascaded D flip-flops, wherein the data input terminal of each D flip-flop is connected to the inverting output terminal, and the D flip-flops are divided into even-numbered stage flip-flops and odd-numbered stage flip-flops according to the cascade order; The clock input terminal and the inverting output terminal of each odd-numbered stage flip-flop are respectively connected to the first input terminal and the second input terminal of an OR logic gate, and the output terminal of the OR logic gate is connected to the clock input terminal of the next even-numbered stage flip-flop; The positive output terminal of each even-numbered stage trigger and the positive output terminal of the previous odd-numbered stage trigger are respectively connected to the first input terminal and the second input terminal of the NAND logic gate, and the clock input terminal of the previous odd-numbered stage trigger is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the third input terminal of the NAND logic gate, and the output terminal of the NAND logic gate is connected to the clock input terminal of the next odd-numbered stage trigger.
[0008] Optionally, the OR logic gate is formed by connecting the output end of the NOR logic gate to the input end of the inverter.
[0009] Optionally, the triggering mode of the clock input terminal in the D flip-flop is rising edge triggering.
[0010] Optionally, the clock input end of each D flip-flop is used to receive an inverted clock signal and a same-phase clock signal; wherein, the inverted clock signal is obtained by passing the clock input signal through a first-stage inverter; the same-phase signal received by the odd-numbered flip-flop is obtained by passing the clock input signal through two-stage inverters, and the same-phase clock signal received by the even-numbered flip-flop is consistent with the clock input signal.
[0011] Optionally, the clock input signal received by the even-numbered trigger is obtained by performing an OR logic operation on the inverted output signal output from the inverting output terminal of the previous odd-numbered trigger and the clock input signal input to the clock input terminal.
[0012] Optionally, the clock input signal received by the odd-level trigger is obtained by performing a NOT logic operation on the positive output signal provided by the positive output end of the previous even-level trigger, the positive output signal provided by the positive output end of the previous odd-level trigger, and the inverted clock signal; wherein, the inverted clock signal represents the clock input signal input to the clock input end of the previous odd-level trigger, which is obtained after passing through a first-level inverter; the external clock signal of the first-level trigger is directly provided by the external clock signal.
[0013] In a second aspect of the present application, a ramp generator is provided, comprising: an asynchronous counter, a thermometer code conversion device, a binary code conversion device, and a signal generation module as described in any one of the first aspects; Among them, the input end of the thermometer code conversion device is connected to the output end of the asynchronous counter, and a first digital signal is generated based on the minimum counting bit width; the input end of the binary code conversion device is connected to the output end of the asynchronous counter, and a second digital signal is generated based on the floating counting bit width; the input end of the signal generating module is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device, and a corresponding ramp voltage signal is generated based on the first digital signal and the second digital signal.
[0014] Optionally, the signal generating module includes: a reference current generating circuit, a current source unit and a compensation unit, Wherein: the input end of the current source unit is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device; the reference current generating circuit is connected to the input end of the current source unit, and is used to provide a reference current to the current source unit; the compensation unit is connected to the output end of the current source unit, and is used to balance the power supply ripple suppression ratio of the current source unit.
[0015] In a third aspect of the present application, an analog-to-digital converter is provided, comprising: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit comprising: a comparator, a column counter and a ramp generator as described in any one of the second aspects, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; and the input terminal of the column counter is connected to the output terminal of the comparator.
[0016] In a fourth aspect of the present application, an image sensor is provided, comprising: a pixel circuit, a digital logic circuit, and an analog-to-digital converter as described in the third aspect, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; and the digital logic circuit is used to configure a flip point, a ramp excitation signal, and a ramp initial value signal.
[0017] The beneficial effects of this application are as follows: The present application provides an asynchronous counter, comprising: a plurality of cascaded D flip-flops, wherein the data input terminal in each D flip-flop is connected to the inverting output terminal, and the D flip-flops are divided into even-numbered stage flip-flops and odd-numbered stage flip-flops according to the cascade order; the clock input terminal and the inverting output terminal of each odd-numbered stage flip-flop are respectively connected to the first input terminal and the second input terminal of an OR logic gate, and the output terminal of the OR logic gate is connected to the clock input terminal of the next even-numbered stage flip-flop; the positive output terminal of each even-numbered stage flip-flop and the positive output terminal of the previous odd-numbered stage flip-flop are respectively connected to the first input terminal and the second input terminal of a NAND logic gate, and the clock input terminal of the previous odd-numbered stage flip-flop is connected to the input terminal of an inverter, the output terminal of the inverter is connected to the third input terminal of the NAND logic gate, and the output terminal of the NAND logic gate is connected to the clock input terminal of the next odd-numbered stage flip-flop.
[0018] According to common knowledge in the art, the positive output signals of different D flip-flops are the output signals of corresponding bits in the asynchronous counter, and the output timing of the positive output signals of the D flip-flops is determined by the clock input signal.
[0019] Based on the logic gate setting between the odd-level trigger and the even-level trigger in the above-mentioned asynchronous counter, compared with the asynchronous counter scheme provided by the prior art, the present application changes the connection relationship between the NAND logic operation gate and the port in the previous odd-level trigger on the basis of ensuring the normal operation of the asynchronous counter, so that the clock input signal input to the next odd-level trigger is obtained by performing a NAND logic operation on the positive output signal of the even-level trigger, the positive output signal of the previous odd-level trigger, and the inverted clock input signal. The generation logic of the clock input signal in the next odd-level trigger is optimized, the delay time in the clock input signal generation process is reduced, and thus the delay time of the output signal at different bit positions is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 This is a structural diagram of a D flip-flop provided by this application; Figure 2 This is a schematic diagram of output signals of different bits in an asynchronous counter provided by this application; Figure 3 This is a schematic diagram of the structure of an asynchronous counter provided by this application; Figure 4 This is a schematic diagram of the structure of an asynchronous counter in the prior art provided by this application; Figure 5 This is a schematic diagram of signal waveforms in an asynchronous counter provided by this application; Figure 6 This is a schematic diagram of the structure of an odd-level trigger provided by this application; Figure 7 This is a schematic diagram of generating an inverted clock signal and an in-phase clock signal provided by the present application; Figure 8 This is a schematic diagram of the structure of an even-numbered trigger provided by this application; Figure 9 This is a schematic structural diagram of a ramp generator provided in this application. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.
[0022] During image sensor operation, increasing the clock frequency is often necessary to reduce the time required to quantize the image signal and improve the image sensor's frame rate. However, as the clock frequency increases, the output delay of the asynchronous counter within the ramp generator gradually increases. When the maximum delay between the asynchronous counter's outputs at different bit positions exceeds half a clock cycle, the high bit will not be sampled and output by the D latch until the next clock edge triggers it, resulting in output signal errors.
[0023] The asynchronous counter proposed in this application is composed of a D flip-flop. The structure of the D flip-flop is as follows: Figure 1 As shown, clk represents the clock input signal, and the port receiving the clk signal in the D flip-flop is the clock input terminal, which is used to receive the clock input signal; the D port represents the data input terminal of the D flip-flop; the Q port represents the positive output terminal of the D flip-flop, which is used to provide a positive output signal; the Q port represents the negative output terminal of the D flip-flop, which is used to provide a negative output signal, which is opposite to the positive output signal provided by the Q port.
[0024] For an n-bit asynchronous counter composed of D flip-flops, the waveform of its output signal is shown as follows Figure 2 As shown in the figure, the asynchronous counter's n-bit output q<1:n> is clocked by the synchronous clock signal clk. q<1:n> represents the n-bit counting signal of the asynchronous counter; qout<1:n> represents the n-bit counting signal after synchronization by the D latch; and n represents the total number of D flip-flops, i.e., the total number of bits of the asynchronous counter. Figure 2 It can be seen that the falling edge of q<1:n> must be between the falling edge and the rising edge of clk, and q <1> There is a certain hold time between the falling edge of clk, q <n>A certain amount of settling time must be left between the rising edge of clk to ensure that q<1:n> completes synchronization under n D flip-flops without bit errors. <1> With q <n>When the delay between them is longer than half a clock cycle, the nth bit will be sampled and outputted by the D latch only when the next clock edge is triggered, resulting in an error in the output signal of the asynchronous counter.
[0025] In order to reduce the delay time of output signals of different bits, the present application provides an asynchronous counter, such as Figure 3 As shown, the asynchronous counter includes: A plurality of cascaded D flip-flops, wherein the data input terminal in each D flip-flop is connected to the inverting output terminal, and the D flip-flops are divided into even-numbered stage flip-flops and odd-numbered stage flip-flops according to the cascade order.
[0026] The clock input terminal and the inverting output terminal of each odd-numbered stage flip-flop are respectively connected to the first input terminal and the second input terminal of an OR logic gate, and the output terminal of the OR logic gate is connected to the clock input terminal of the next even-numbered stage flip-flop; The positive output terminal of each even-numbered stage trigger and the positive output terminal of the previous odd-numbered stage trigger are respectively connected to the first input terminal and the second input terminal of the NAND logic gate, and the clock input terminal of the previous odd-numbered stage trigger is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the third input terminal of the NAND logic gate, and the output terminal of the NAND logic gate is connected to the clock input terminal of the next odd-numbered stage trigger.
[0027] According to common knowledge in the art, the positive output signals of different D flip-flops are the output signals of the corresponding bits in the asynchronous counter, and the output timing of the positive output signals of the D flip-flops is determined by the clock input signal.
[0028] Based on the setting of the logic operation gate between the odd-level trigger and the even-level trigger in the above-mentioned asynchronous counter, compared with the asynchronous counter scheme provided in the prior art, the present application changes the connection relationship between the NAND logic operation gate and the port in the previous odd-level trigger on the basis of ensuring the normal operation of the asynchronous counter, so that the clock input signal input to the next odd-level trigger is obtained by performing a NAND logic operation on the positive output signal of the even-level trigger, the positive output signal of the previous odd-level trigger, and the inverted clock input signal. The generation logic of the clock input signal in the next odd-level trigger is optimized, the delay time in the clock input signal generation process is reduced, and thus the delay time of the output signal at different bit positions is reduced.
[0029] like Figure 3 As shown, the specific structure of the asynchronous counter provided by this application is as follows: The clock input of the first-stage flip-flop is connected to the output of a NAND gate; the clock input signal clk is connected to the first input of the NAND gate after passing through an inverter, and the clock enable signal clk_en is connected to the second input of the above-mentioned NAND gate. When the clock enable signal clk_en takes effect, the D flip-flops that are not bypassed start working.
[0030] The digital input terminal D in each D flip-flop is connected to its inverting output terminal qb, thereby forming a divide-by-two frequency circuit for obtaining a positive output signal q with a frequency twice slower than the clock input signal clk.
[0031] The OR logic gate connected to the clock input and inverting output of the odd-numbered flip-flops is formed by connecting the output of the NOR logic gate to the input of an inverter. That is, the first input of the NOR gate is connected to the clock input of the odd-numbered flip-flop, the second input of the NOR gate is connected to the inverting output qb of the odd-numbered flip-flop, and the input of the NOT gate is connected to the output of the NOR gate.
[0032] From the perspective of signal transmission, the clock input signal of each odd-numbered flip-flop is ORed with its inverted output signal and then inverted, and then used as the clock input signal of the next even-numbered flip-flop. Taking the first-level flip-flop (bit1) as an example, the clock input signal clk_cnt <1> and the inverted output signal qb <1> After performing the NOR and NOT operations, it serves as the clock input signal clk_cnt of the second-stage trigger (bit2) <2> .
[0033] Each even-numbered stage flip-flop is connected to the next odd-numbered stage flip-flop via a NAND gate. The first input of the NAND gate is connected to the positive output of the even-numbered stage flip-flop; the second input of the NAND gate is connected to the positive output of the odd-numbered stage flip-flop immediately preceding the even-numbered stage flip-flop; and the third input of the NAND gate is connected to the output of an inverter, whose input is connected to the clock input of the odd-numbered stage flip-flop immediately preceding the even-numbered stage flip-flop.
[0034] From the perspective of signal transmission, the positive output signal of each even-numbered flip-flop is AND-NON-ed with the positive output signal of the previous odd-numbered flip-flop and the inverted clock signal (i.e., the clock signal after the clock input signal is inverted), and then used as the clock input signal of the next odd-numbered flip-flop of the even-numbered flip-flop. Taking the even-numbered flip-flop (bit2) as an example, its positive output signal q <2> The inverted clock signal clk_cntb of bit1 <1> and the positive output signal q <1> After performing the AND-NOT operation, it serves as the clock input signal clk_cnt for the next odd-numbered trigger (bit3) <2> .
[0035] The prior art also discloses an asynchronous counter composed of a D flip-flop, such as Figure 4 As shown, its internal structure is as follows: Each even-numbered stage flip-flop is cascaded with the previous odd-numbered stage flip-flop via a NOR gate and a NOT gate, the specific connection relationship of which is consistent with the solution of the present application. Each even-numbered stage flip-flop is cascaded with the next odd-numbered stage flip-flop via a NAND gate, wherein the first input of the NAND gate is connected to the input of the NOT gate connected to the clock input of the even-numbered stage flip-flop, the second input of the NAND gate is connected to the positive output of the even-numbered stage flip-flop, and the clock input of the next odd-numbered stage flip-flop is connected to the output of the NAND gate.
[0036] For the asynchronous counter solution, from the perspective of signal transmission, the positive output signal of each even-numbered flip-flop is ANDed with the signal after the clock input signal and the inverted output signal of the previous odd-numbered flip-flop are ORed and NOTed, and then used as the clock input signal of the next odd-numbered flip-flop. Taking the even-numbered flip-flop (bit2) as an example, its positive output signal q <2> and the clock input signal clk_cnt from the first stage trigger (bit1) <1> and inverted output signal qb <1> The signal after completing the OR operation is then ANDed and used as the clock input signal clk_cnt for the next odd-numbered trigger (bit3). <2> .
[0037] For the asynchronous counter disclosed in this application and the prior art, the positive output signal q of each D flip-flop <1> To q <n>The corresponding signals are at different bits in the asynchronous counter, and the output time of the positive output signal is determined by the input clock signal of the D flip-flop. Taking the odd-level flip-flop (bit3) as an example, its positive output signal q <3> As the signal of the 3rd bit, and q <3> The output time is determined by clk_cnt <3> Determined.
[0038] Compared with the above-mentioned prior art solutions, the clock input signal generation process of the even-numbered triggers is the same, but the clock input signal generation process of the odd-numbered triggers is different. <3> For example, in the asynchronous counter solution provided by this application, it uses q <1> 、clk_cntb <1> and q <2> The AND-NON logic is obtained. Among them, clk_cntb <1> The falling edge of clk_cnt determines <3> In this application, the trigger mode of the clock input terminal of the D flip-flop is rising edge trigger. Therefore, clk_cntb <1> The earlier the falling edge of clk_cnt comes, the <3> The earlier the rising edge, the <3> Compared to q <2> The smaller the delay time.
[0039] In the asynchronous counter solution disclosed in the prior art, clk_cnt <3> is through clk_cnt <1> and qb <1> Then add q after the logical OR <2> After doing the AND NOT logic, the clk_cnt <3> The rising edge of clk_cnt can be regarded as <1> It is obtained after passing through one level of NOR gate and one level of NAND gate.
[0040] Since the circuit structure complexity of the NOR gate is higher than that of the inverter, the delay of the same signal passing through the NOR gate is higher than that of the inverter. It can be seen that the asynchronous counter provided in this application has lower delay compared with the prior art.
[0041] like Figure 3 As shown, in this application solution, clk_cnt <3> By q <1> 、clk_cntb <1> and q <2> The AND-NON logic is obtained. And clk_cntb <1> By clk_cnt <1> After passing through the inverter, we get q <1> It is clk_cnt <1> Obtained by the first-level trigger, q <2> It is through clk_cnt <1> With qb <1> Get clk_cnt through the NOR gate and NOT gate <2> After passing through the D flip-flop, the signal is obtained. Since the delay of the signal passing through the D flip-flop is longer than the inverter, clk_cntb <1> Earlier than q <1> ,q <2> Input to the NAND gate, we can know clk_cntb <1> The falling edge of clk_cnt determines <3> The rising edge time of Figure 5 shown.
[0042] Similarly, in the existing asynchronous counter solution, clk_cnt <1> Also determines clk_cnt <3> Therefore, in the technical solution provided by this application, by adjusting the input terminals of the NAND gates between adjacent D flip-flops, the generation process of the clock input signal in the odd-numbered flip-flops is changed. In addition, considering the specific structure within the counter, the operation logic of the key signal (clock input signal) that determines the delay is optimized, thereby reducing the delay time in the clock input signal generation process, thereby achieving the purpose of reducing the delay time of the output signal at different bit positions.
[0043] The asynchronous counter solution provided in this application may also include N control units. The set and reset terminals of each D flip-flop are connected to the output terminal of the control unit, and the input terminals of the m control units are connected to the bypass control signal load. <m:1>The corresponding bit signal and the ramp initial value signal of the (nm) control unit are connected to the count assignment signal and the ramp initial value signal. Among them, when some or all of the m D flip-flops are bypassed, the bypass control signal load <m:1>The state value of the corresponding bit in the D flip-flop is assigned to "1"; when the m D flip-flops do not perform the bypass operation, the bypass control signal load <m:1>The state value of the corresponding bit in is set to be the same as the count assignment signal.
[0044] Each control unit consists of two NAND gates and a NOT gate. For m control units, inside each control unit, the input of a NAND gate is connected to the bypass control signal load <m:1>The corresponding bit signal and the ramp initial value signal; the input end of the NOT gate is connected to the ramp initial value signal; the input end of the other NAND gate is connected to the bypass control signal load <m:1>For the other (nm) control units, within each control unit, the input of a NAND gate is connected to the count assignment signal and the ramp initial value signal; the input of the NAND gate is connected to the ramp initial value signal; and the input of the second NAND gate is connected to the count assignment signal and the output signal of the first NAND gate.
[0045] Bypass control signal load <m:1>Configure the initial bit width of the asynchronous counter. The floating count bit width that the asynchronous counter can achieve is between (nm) and n. When the floating count bit width of the asynchronous counter is (nm), the bypass control signal load <m:1>The state value of each bit in the asynchronous counter is digital "1"; when the floating count bit width of the asynchronous counter is N, the bypass control signal load <m:1>The status value of each bit in is the same as the count assignment signal.
[0046] During the operation of the existing D flip-flop, the clock input signal (i.e., clk or CP) received at its clock input terminal is transmitted through a two-stage inverter structure to obtain CLKB and CLKBB, which are used to control the sampling and triggering of the D flip-flop. Figure 6 、 7 As shown in the figure, this type of D flip-flop is called a normal DFF; CLKB represents the inverted clock signal obtained by passing the external clock signal through one stage of inverters; CLKBB represents the in-phase clock signal obtained by passing the external clock signal through two stages of inverters. In this case, the delay time of CLKBB compared to the external clock signal CP includes the delay within the two inverters.
[0047] In the asynchronous counter provided in the present application, the clock input terminal of each D-type flip-flop is used to receive an inverted clock signal and a non-inverted clock signal. The inverted clock signal is obtained by passing the external clock signal through a first-stage inverter; the non-inverted clock signal received by the odd-numbered flip-flop is obtained by passing the external clock signal through two-stage inverters, and the non-inverted clock signal received by the even-numbered flip-flop is consistent with the external clock signal. That is, the clock signals of the odd-numbered flip-flops include CLKB and CLKBB, and the clock signals of the even-numbered flip-flops include CLKB and CP. Figure 8 Because the signal CP has two fewer inverter delays than CLKBB, the even-numbered flip-flop is also called a fast DFF.
[0048] Since the D flip-flop provided in this application is low-level sampling and high-level triggering, the time when the rising edge of its CP arrives determines the moment when the DFF outputs the signal. Taking the lower 2 bits as an example, the existing asynchronous counter is to set the qb of bit 1 to <1> The output is used as the CP clock of bit2, then q <2> Compared to q <1> There is a delay through DFF, which is approximately equivalent to the delay of 5 inverters. For a high-bit counter, the output delay of the traditional counter will continue to accumulate, and the highest bit q <n>With q <1> The difference is the delay of n-1 DFF levels. So at high frequencies, the output signal delay between the highest bit and the lowest bit in the asynchronous counter is greater than half a clock cycle, and the high bit output cannot beat at the same time as the low bit output under the synchronous clock.
[0049] Based on the above settings, in the asynchronous counter provided in this application, the trigger of the first bit is normal DFF, and the D trigger of the second bit is fast DFF. Similarly, the normal DFF and fast DFF are used alternately in the subsequent stage, reducing the output delay of the high bit and the low bit.
[0050] In addition, compared with the asynchronous counter structure of the full-fast DFF, the present application can reduce the probability of occurrence of contention-hazard, effectively avoid the adverse effects of spike pulses, and ensure the accuracy of the output results of the asynchronous counter.
[0051] Further, refer to Figure 3 The clock input signal received by the even-numbered trigger is obtained by performing an OR logic operation on the inverted output signal output from the inverting output terminal of the previous odd-numbered trigger and the clock input signal input to the clock input terminal.
[0052] The clock input signal received by the odd-numbered trigger is obtained by performing a NOT logic operation on the positive output signal provided by the positive output terminal of the previous even-numbered trigger, the positive output signal provided by the positive output terminal of the previous odd-numbered trigger, and the inverted clock signal; wherein, the inverted clock signal represents the clock input signal input to the clock input terminal of the previous odd-numbered trigger, which is obtained after passing through a first-level inverter; the external clock signal of the first-level trigger is directly provided by the external clock signal.
[0053] like Figure 9 As shown, this embodiment further provides a ramp generator, which includes: the asynchronous counter, thermometer code conversion device, binary code conversion device and signal generation module described in this embodiment. The input terminal of the thermometer code conversion device is connected to the output terminal of the asynchronous counter, and generates a first digital signal based on the minimum counting bit width.
[0054] The input terminal of the binary code conversion device is connected to the output terminal of the asynchronous counter, and generates a second digital signal based on the floating count bit width.
[0055] The input end of the signal generating module is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device, and generates a corresponding ramp voltage signal based on the first digital signal and the second digital signal.
[0056] Specifically, as an example, the signal generation module includes: a reference current generating circuit, a current source unit, and a compensation unit, wherein: the input end of the current source unit is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device; the reference current generating circuit is connected to the input end of the current source unit for providing a reference current to the current source unit; and the compensation unit is connected to the output end of the current source unit for balancing the power supply ripple rejection ratio of the current source unit. It should be noted that the signal generation module can also be configured using a field programmable logic gate array or an application-specific integrated circuit. As long as the configuration of the signal generation module can generate a corresponding ramp voltage signal based on the first digital signal and the second digital signal, any configuration of the signal generation module is applicable and is not limited to this embodiment.
[0057] This embodiment further provides an analog-to-digital converter, comprising: at least one column of analog-to-digital conversion units, each of which comprises: a comparator, a statistical device, and the ramp generator described in this embodiment. The comparator's non-inverting input is connected to the ramp generator's output, the statistical device's input is connected to the comparator's output, and the statistical device has a counting function.
[0058] This embodiment further provides an image sensor, comprising: a pixel circuit, a digital logic circuit, and the analog-to-digital converter described in this embodiment. The pixel circuit is connected to the inverting input terminal of the comparator, and the digital logic circuit is used to configure the flip point, the ramp excitation signal, and the ramp initial value signal.
[0059] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.< / n> < / n> < / n> < / n>
Claims
1. An asynchronous counter, characterized in that: include: A plurality of cascaded D flip-flops, wherein the data input terminal of each D flip-flop is connected to the inverting output terminal, and the D flip-flops are divided into even-numbered stage flip-flops and odd-numbered stage flip-flops according to the cascade order; The clock input terminal and the inverting output terminal of each odd-numbered stage flip-flop are respectively connected to the first input terminal and the second input terminal of an OR logic gate, and the output terminal of the OR logic gate is connected to the clock input terminal of the next even-numbered stage flip-flop; The positive output terminal of each even-numbered stage trigger and the positive output terminal of the previous odd-numbered stage trigger are respectively connected to the first input terminal and the second input terminal of the NAND logic gate, and the clock input terminal of the previous odd-numbered stage trigger is connected to the input terminal of the inverter, the output terminal of the inverter is connected to the third input terminal of the NAND logic gate, and the output terminal of the NAND logic gate is connected to the clock input terminal of the next odd-numbered stage trigger.
2. The asynchronous counter according to claim 1, wherein: The OR logic gate is formed by connecting the output terminal of the NOR logic gate to the input terminal of the inverter.
3. The asynchronous counter according to claim 1, wherein: The triggering mode of the clock input terminal in the D flip-flop is rising edge triggering.
4. The asynchronous counter according to claim 1, wherein: The clock input end of each D flip-flop is used to receive an inverted clock signal and a non-inverted clock signal; wherein, the inverted clock signal is obtained by passing the clock input signal through a first-stage inverter; the non-inverted clock signal received by the odd-numbered flip-flop is obtained by passing the clock input signal through two-stage inverters, and the non-inverted clock signal received by the even-numbered flip-flop is consistent with the clock input signal.
5. The asynchronous counter according to claim 4, wherein: The clock input signal received by the even-numbered trigger is obtained by performing an OR logic operation on the inverted output signal output from the inverting output terminal of the previous odd-numbered trigger and the clock input signal input to the clock input terminal.
6. The asynchronous counter according to claim 4, characterized in that The clock input signal received by the odd-numbered trigger is obtained by performing a NOT logic operation on the positive output signal provided by the positive output terminal of the previous even-numbered trigger, the positive output signal provided by the positive output terminal of the previous odd-numbered trigger, and the inverted clock signal; wherein, the inverted clock signal represents the clock input signal input to the clock input terminal of the previous odd-numbered trigger, which is obtained after passing through a first-level inverter; the external clock signal of the first-level trigger is directly provided by the external clock signal.
7. A ramp generator, characterized in that: The ramp generator comprises: an asynchronous counter according to any one of claims 1 to 6, a thermometer code conversion device, a binary code conversion device and a signal generation module; Among them, the input end of the thermometer code conversion device is connected to the output end of the asynchronous counter, and a first digital signal is generated based on the minimum counting bit width; the input end of the binary code conversion device is connected to the output end of the asynchronous counter, and a second digital signal is generated based on the floating counting bit width; the input end of the signal generating module is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device, and a corresponding ramp voltage signal is generated based on the first digital signal and the second digital signal.
8. The ramp generator according to claim 7, characterized in that: The signal generating module includes: a reference current generating circuit, a current source unit and a compensation unit; The input end of the current source unit is connected to the output end of the thermometer code conversion device and the output end of the binary code conversion device; the reference current generating circuit is connected to the input end of the current source unit to provide a reference current to the current source unit; and the compensation unit is connected to the output end of the current source unit to balance the power supply ripple suppression ratio of the current source unit.
9. An analog-to-digital converter, characterized in that: include: At least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit comprising: a comparator, a column counter, and a ramp generator as described in any one of claims 7 or 8, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; and the input terminal of the column counter is connected to the output terminal of the comparator.
10. An image sensor, characterized in that: include: A pixel circuit, a digital logic circuit, and an analog-to-digital converter according to claim 9, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; The digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.