Code pattern recognizer and automatic extinction ratio control system

Abstract

The invention provides a code pattern recognizer and an automatic extinction ratio control system, in the code pattern recognizer, a conversion module can output a code pattern reference signal after converting a differential input signal, a code pattern counter can count the number of overturning times from 0 to 1 in the code pattern reference signal in a sampling clock period, and the number of overturning times in the code pattern reference signal can be calculated according to the number of overturning times. The output counting result comprises information of a short code type signal, the problem of short code type signal loss is avoided, the processing module determines a final control signal and sends the final control signal to the preset automatic extinction ratio control circuit according to the counting result, a preset control reference value, and a pre-received working state identifier and a pre-received burst signal identifier, and the automatic extinction ratio control circuit outputs the control signal. The stability of loop control of the automatic extinction ratio control circuit can be improved.

Description

Technical Field

[0001] The present invention relates to the field of laser technology, in particular to a code type identifier and an automatic extinction ratio control system. Background Art

[0002] In the Automatic Exposure Control (AER) scheme used in high-speed laser driver circuits exceeding 10 Gbps, the large parasitic capacitance of the MPD (Motor Photo Diode) output in the feedback loop and the need for low power consumption and high reliability often hinder the design of a high-speed Transimpedance Amplifier (TIA) to reduce input impedance. This results in low bandwidth at the TIA input, making it impossible to recognize high-speed signals with short code patterns such as 0101, and to accurately determine the characteristics of the feedback signal. Furthermore, due to the loss of the short code pattern in the feedback, in some cases, such as during the registration phase of the Optical Network Unit (OPU) in a PON (Passive Optical Network) system, there can be long periods of short code patterns, causing unidirectional overshoot in the AER loop, deteriorating stability, and even causing the AER loop to lose control due to the prolonged presence of the short code pattern. Summary of the Invention

[0003] The object of the present invention is to provide a code pattern identifier and an automatic extinction ratio control system to improve the stability of the loop control of the automatic extinction ratio control circuit.

[0004] The present invention provides a pattern identifier, comprising: a conversion module for receiving a differential input signal, converting the differential input signal, and outputting a pattern reference signal; a sampling clock for generating a clock signal; a pattern counter for receiving the pattern reference signal and the clock signal, counting the number of flips from 0 to 1 in the pattern reference signal within a current sampling clock cycle, and outputting a count result; wherein the count result is used to indicate whether a short pattern signal exists in the differential input signal within the sampling clock cycle; and a processing module for receiving the count result, outputting a control signal based on the count result, a preset control reference value, and a pre-received working state identifier and a burst signal identifier, and sending the control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit determines whether to freeze a current control value output by the automatic extinction ratio control circuit based on the control signal; wherein the working state identifier is used to indicate whether the automatic extinction ratio control circuit is in a working state, and the burst signal identifier is used to indicate whether the differential input signal is a burst packet signal.

[0005] Furthermore, the processing module includes: a digital comparator, used to receive the counting result, compare the counting result with a preset control reference value, and output the comparison result; a signal generation module, used to receive the comparison result, perform logical processing on the comparison result, the pre-received working status identifier and the burst signal identifier, and output a control signal.

[0006] Furthermore, the signal generation module includes: a first AND gate, used to perform a logical operation on the comparison result and a pre-received working status identifier, and output a first logic signal; a NOT gate, used to perform a logical operation on the first logic signal, and output a second logic signal; a second AND gate, used to perform a logical operation on the second logic signal and the burst signal identifier, and output a control signal.

[0007] Furthermore, when the counting result is less than the control reference value, the comparison result is a low level; when the counting result is greater than the control reference value, the comparison result is a high level; when the counting result is equal to the control reference value, the comparison result outputted last time is maintained.

[0008] Furthermore, the differential input signal is a CML logic signal, and the code reference signal is a CMOS logic signal.

[0009] Furthermore, the code pattern counter is also used to: after sending the counting result corresponding to the current sampling clock cycle to the processing module, wait for a preset time and clear the counting result; use the next sampling clock cycle as the new current sampling clock cycle, and repeatedly execute the step of statistically counting the number of flips from 0 to 1 in the code pattern reference signal within the current sampling clock cycle.

[0010] Furthermore, the sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein, the first preset period is greater than the second preset period; the first preset period is the preset minimum clock period corresponding to the automatic extinction ratio control circuit; the second preset period is the period corresponding to the preset highest rate code reference signal.

[0011] Furthermore, the processing module is also used to: if the control signal is at a low level, send the low-level control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal; if the control signal is at a high level, send the high-level control signal to the automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high-level control signal.

[0012] Furthermore, the switch tubes in the conversion module are all high-speed switch tubes.

[0013] The present invention provides an automatic extinction ratio control system, which includes: a laser driving unit, a switch unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and a code type identifier as described in any one of the above items; the laser driving unit is used to receive a differential input signal, output a switch control signal, and control the on or off of the switch unit according to the switch control signal; the current source is used to provide current to the laser when the switch unit is turned on, so that the laser emits laser light; the laser feedback unit is used to generate a feedback signal based on the laser light emitted by the laser, and send it to the automatic extinction ratio control circuit. control circuit; the reference signal unit is used to generate a preset reference signal and send the preset reference signal to the automatic extinction ratio control circuit; the code type identifier is used to receive the differential input signal, the preset control reference value, the working state identifier and the burst signal identifier, and output a control signal according to the differential input signal, the control reference value, the working state identifier and the burst signal identifier, and send the control signal to the automatic extinction ratio control circuit; the automatic extinction ratio control circuit is used to output a current control value according to the feedback signal, the preset reference signal and the control signal, so as to adjust the current of the current source according to the current control value.

[0014] The present invention provides a code pattern identifier and an automatic extinction ratio control system. In the code pattern identifier, a conversion module can output a code pattern reference signal after converting a differential input signal. A code pattern counter can count the number of flips from 0 to 1 in the code pattern reference signal within a sampling clock cycle. The output counting result includes information about short code pattern signals, thereby avoiding the problem of short code pattern signal loss. A processing module determines a final control signal based on the counting result, a preset control reference value, and a pre-received working status identifier and a burst signal identifier, and sends the final control signal to a preset automatic extinction ratio control circuit, thereby improving the stability of the loop control of the automatic extinction ratio control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic structural diagram of a code pattern identifier provided by an embodiment of the present invention; Figure 2 A circuit diagram of a signal generating module provided by an embodiment of the present invention; Figure 3 A schematic structural diagram of a code pattern identifier provided by an embodiment of the present invention; Figure 4 A schematic diagram of a CML to CMOS circuit provided in an embodiment of the present invention; Figure 5 A schematic diagram of an automatic extinction ratio control system provided by an embodiment of the present invention; Figure 6 Schematic diagram of an automatic extinction ratio control system in the prior art. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] Related technologies have problems such as inability to recognize high-speed signals with short code patterns such as 0101 due to low bandwidth, and inability to correctly determine the characteristics of feedback signals. There is also the problem of deteriorated AER loop stability. Based on this, an embodiment of the present invention provides a code pattern identifier and an automatic extinction ratio control system, which can be applied to laser drive control scenarios.

[0019] To facilitate understanding of this embodiment, a code pattern identifier disclosed in an embodiment of the present invention is first introduced. Figure 1 As shown, the code pattern identifier includes: a conversion module 10, a sampling clock 11, a code pattern counter 12 and a processing module 13.

[0020] The conversion module 10 is configured to receive a differential input signal, convert the differential input signal, and output a pattern reference signal. The conversion module 10 is a high-speed differential input-to-single-ended output circuit implemented using analog circuitry. The differential input signal is a CML (Current Mode Logic) logic signal, and the pattern reference signal is a CMOS (Complementary Metal Oxide Semiconductor) logic signal. In practical applications, laser drivers operating at speeds exceeding 10 Gbps typically require a differential signal amplifier with a CML logic architecture in the main path based on bandwidth considerations. To facilitate subsequent signal extraction and processing, the differential CML logic signal must first be converted to a CMOS logic signal. Specifically, the conversion module 10 receives a differential input signal at a CML logic level as input and outputs a pattern reference signal at a CMOS logic level as output. This pattern reference signal is then sent to the pattern counter 12. In some scenarios, if an inverter is used as the main path, the inverter output can be directly sent to the subsequently connected pattern counter 12 because the inverter output is either 0 or 1.

[0021] The sampling clock 11 is used to generate a clock signal; the sampling clock 11 is usually provided by a high-precision crystal oscillator, a phase-locked loop or a clock generator, and can be used to generate a clock signal and send the clock signal to the pattern counter 12. The clock signal is usually a low-speed signal.

[0022] The pattern counter 12 is used to receive the pattern reference signal and the clock signal, count the number of flips from 0 to 1 in the pattern reference signal during the current sampling clock cycle, and output a count result. The count result indicates whether a short pattern signal exists in the differential input signal during the sampling clock cycle. The sampling clock cycle can be understood as the time interval between two adjacent rising or falling edges in the clock signal. The pattern counter 12 is typically implemented using a digital circuit. After receiving the pattern reference signal and the clock signal, the pattern counter 12 calculates the number of flips from 0 to 1 in the pattern reference signal during the current sampling clock cycle, obtains a count result, and outputs it. Because the pattern reference signal originates from an internal high-speed circuit branch, i.e., converted by the conversion module 10, it does not require the MPD, thus preventing pattern loss. The rising edge of the sampling clock triggers the pattern counter 12 to output the count result. The count result is typically multi-bit and can be designed to fit the actual situation, such as 8 bits. For example, in a 10Gbps laser driver circuit, the shortest pattern, 0101, has a period of 200ps. When the sampling clock 11 frequency is 20MHz, the maximum number of 0-to-1 transitions that can be counted within one period is 250. Therefore, the designed output bit count must be greater than 250. In this example, the minimum output bit count is 8 bits, or 2^8 = 256.

[0023] The processing module 13 is used to receive the counting result, and output a control signal based on the counting result, a preset control reference value, and a pre-received working status identifier and a burst signal identifier, and send the control signal to a preset automatic extinction ratio control circuit so that the automatic extinction ratio control circuit determines whether to freeze the current control value output by the automatic extinction ratio control circuit based on the control signal; wherein the working status identifier is used to indicate whether the automatic extinction ratio control circuit is in a working state, and the burst signal identifier is used to indicate whether the differential input signal is a burst packet signal.

[0024] The above-mentioned control reference value can be set according to actual needs, and the number of bits of the control reference value needs to be the same as the number of bits of the counting result; the above-mentioned working status identifier can be used to indicate whether the automatic extinction ratio control circuit is in working state. The automatic extinction ratio control circuit can send a corresponding working status identifier to the processing module 13 according to its own working state. For example, if the working status identifier is 0, it can be considered that the automatic extinction ratio control circuit has not started working. If the working status identifier is 1, it can be considered that the automatic extinction ratio control circuit has started working. The above-mentioned burst signal identifier is used to indicate whether the differential input signal is a burst packet signal. The burst packet signal can be understood as a data packet signal that is sent discontinuously and intermittently. The burst signal identifier can be sent to the processing module 13 through an external host computer. For example, if the burst signal identifier is 0, the differential input signal can be considered to be a burst packet signal. If the burst signal identifier is 1, the differential input signal can be considered not to be a burst packet signal. In actual implementation, after receiving the counting result, the processing module 13 can process it in combination with the pre-received control reference value, working status identifier and burst signal identifier, and output a control signal. The control signal may be 0 or 1. The control signal can be sent to the automatic extinction ratio control circuit, and the automatic extinction ratio control circuit can determine whether the output current control value needs to be frozen based on the control signal. For example, when the control signal is 0, the automatic extinction ratio control circuit can freeze the output current control value. When the control signal is 1, the automatic extinction ratio control circuit can work normally to adjust the output current control value.

[0025] In the above-mentioned code pattern identifier, the conversion module can output a code pattern reference signal after converting the differential input signal. The code pattern counter can count the number of flips from 0 to 1 in the code pattern reference signal within a sampling clock cycle. The output counting result contains information about short code pattern signals, avoiding the problem of short code pattern signal loss. The processing module determines the final control signal based on the counting result, the preset control reference value, and the pre-received working status identifier and burst signal identifier, and sends it to the preset automatic extinction ratio control circuit, which can improve the stability of the loop control of the automatic extinction ratio control circuit.

[0026] Furthermore, the processing module includes: a digital comparator and a signal generation module; the digital comparator is used to receive the counting result, compare the counting result with a preset control reference value, and output the comparison result; in actual implementation, the digital comparator is usually implemented using a digital circuit; the control reference value can be pre-stored in a register, and the digital comparator can obtain the control reference value from the register and compare it with the received counting result, and output the comparison result, that is, the code detection value, which may be a low level or a high level.

[0027] Specifically, when the counting result is less than the control reference value, the comparison result is a low level; when the counting result is greater than the control reference value, the comparison result is a high level; when the counting result is equal to the control reference value, the comparison result outputted last time is maintained, that is, the comparison result corresponding to the previous logic is maintained.

[0028] The signal generation module is configured to receive the comparison result, perform logical processing on the comparison result, the previously received operating state identifier, and the burst signal identifier, and output a control signal. In actual implementation, the signal generation module may be composed of logic gate circuits. Upon receiving the comparison result, the signal generation module may perform corresponding logical processing on the comparison result, the operating state identifier, and the burst signal identifier, and output a final control signal.

[0029] Furthermore, the signal generation module includes: a first AND gate, a NOT gate, and a second AND gate; The first AND gate is used to perform a logical operation on the comparison result and the pre-received working status identifier, and output a first logic signal; specifically, the first AND gate can receive the comparison result, perform an AND logical operation on the comparison result and the working status identifier, and generate a first logic signal. For example, if the comparison result and the working status identifier are both high levels, the first logic signal is high level; if any one of the comparison result and the working status identifier is low level, or both are low level, the first logic signal is low level; the first AND gate sends the generated first logic signal to the NOT gate.

[0030] The NOT gate is used to perform a logical operation on the first logic signal and output a second logic signal; for example, if the first logic signal is a high level, then after processing by the NOT gate, the output second logic signal is a low level; if the first logic signal is a low level, then after processing by the NOT gate, the output second logic signal is a high level; the NOT gate sends the generated second logic signal to the second AND gate.

[0031] The second AND gate is used to perform a logical operation on the second logic signal and the burst signal identifier to output a control signal; specifically, after receiving the second logic signal, the second AND gate can perform an AND logical operation on the second logic signal and the burst signal identifier to generate a control signal. For example, if the second logic signal and the burst signal identifier are both high levels, the control signal is high level; if either the second logic signal or the burst signal identifier is low level, or both are low level, the control signal is low level.

[0032] like Figure 2The circuit diagram of a signal generation module shown in the figure shows that after the comparison result and the AER work start signal (corresponding to the above-mentioned work state identifier) ​​are processed by a first AND gate, the output first logic signal is further processed by a NOT gate to output a second logic signal. The second logic signal and the BEN signal (corresponding to the above-mentioned burst signal identifier) ​​are processed by a second AND gate to output a control signal.

[0033] As can be seen from the above embodiment, when a short pattern signal is present, the pattern reference signal flips from 0 to 1 more frequently. When the count result is greater than the control reference value, the digital comparator outputs a high comparison result. After logic processing by the signal generation module, the output control signal is 0. In this case, the current control value output by the automatic extinction ratio control circuit is frozen. When the BEN signal is 0, the control signal is also 0, in which case the current control value output by the automatic extinction ratio control circuit is also frozen.

[0034] Furthermore, the pattern counter is further configured to: after sending the count result corresponding to the current sampling clock cycle to the processing module, wait for a preset time and clear the count result; and use the next sampling clock cycle as the new current sampling clock cycle to repeatedly perform the step of counting the number of flips from 0 to 1 in the pattern reference signal within the current sampling clock cycle. The preset time can be set according to actual application. Typically, within this preset time, the processing module can complete corresponding processing based on the received count result and output a control signal. In actual implementation, after sending the count result corresponding to the current sampling clock cycle to the processing module, the pattern counter can delay for a preset time, then clear the count result corresponding to the current sampling clock cycle, use the next sampling clock cycle as the new current sampling clock cycle, and repeat the process of counting the number of flips to output a new count result. After processing by the processing module, the corresponding control signal is output.

[0035] Furthermore, the sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein the first preset period is greater than the second preset period; the first preset period is the preset minimum clock period corresponding to the automatic extinction ratio control circuit; and the second preset period is the period corresponding to the preset highest-rate pattern reference signal. The first and second preset periods are typically pre-determined. In practical applications, when setting the sampling clock period, it is typically required that the sampling clock period be less than or equal to the first preset period and significantly longer than the second preset period. For example, in a 10Gbps laser driver circuit, the maximum rate is generated by a 0101 pattern, with a period of 200ps. The fastest control frequency of an automatic extinction ratio control circuit (AER) is 20MHz (with a period of 50ns), so it is recommended that the sampling clock frequency be set faster than 20MHz.

[0036] Furthermore, the processing module is also used to: if the control signal is at a low level, send the low-level control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal; if the control signal is at a high level, send the high-level control signal to the automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high-level control signal.

[0037] In this embodiment, the processing module finally outputs a 1-bit control signal. When the control signal is 0, the current control value output by the automatic extinction ratio control circuit is frozen. When the control signal is 1, the automatic extinction ratio control circuit continues to work normally.

[0038] Furthermore, the switching tubes in the conversion module are all high-speed switching tubes; usually the switching tubes in the code counter also use high-speed switching tubes, which can be specifically high-speed transistors, etc. High-speed transistors generally refer to transistors with an operating frequency between hundreds of megahertz and several gigahertz. The use of high-speed switching tubes can meet the application requirements of high-speed laser driving circuits exceeding 10Gbps.

[0039] For easier understanding, see Figure 3 The schematic diagram of the structure of a code pattern recognizer shown in FIG. 1 is composed of the following parts: a CML to CMOS circuit (analog circuit; corresponding to the above-mentioned conversion module), a code pattern counter (digital circuit), a sampling clock (analog circuit), a digital comparator (digital circuit), and a control signal generation (digital circuit; corresponding to the above-mentioned signal generation module).

[0040] The input of the CML to CMOS circuit is a differential input signal of CML logic level, and its output is a code reference signal of CMOS logic, such as Figure 4 A schematic diagram of a CML-to-CMOS conversion circuit is shown, including switches P1, P2, P3, P4, P5, and P6, as well as switches N1, N2, N3, N4, N5, and N6. Switches P1-P6 may be P-channel MOS transistors, and switches N1-N6 may be N-channel MOS transistors. The circuit also includes a current source. The gates of switches N1 and N2 may be connected to Vin+ and Vin-, respectively, i.e., the differential input signal. A common terminal of switches P6 and N6 outputs Vo, i.e., the pattern reference signal. The specific operating principle can be found in related art and will not be described in detail here.

[0041] The sampling clock is used to generate a clock signal; the pattern counter is used to receive the pattern reference signal and the clock signal, and count the number of flips from 0 to 1 in the pattern reference signal within the current sampling clock cycle, and output the counting result; the digital comparator compares the counting result with a preset control reference value and outputs the comparison result; the control signal generation circuit performs logical processing on the comparison result, the AER work start signal and the BEN signal, and outputs a control signal.

[0042] An embodiment of the present invention discloses an automatic extinction ratio control system, comprising: a laser driving unit, a switch unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and a code pattern identifier according to any one of the above embodiments; The laser driving unit is used to receive a differential input signal, output a switch control signal, and control the switching unit to be turned on or off according to the switch control signal; The current source is used to provide current to the laser when the switch unit is turned on, so that the laser emits laser light; The laser feedback unit is used to generate a feedback signal according to the laser light emitted by the laser, and send the feedback signal to the automatic extinction ratio control circuit; The reference signal unit is used to generate a preset reference signal and send the preset reference signal to the automatic extinction ratio control circuit; The code pattern identifier is used to receive the differential input signal, a preset control reference value, a working state identifier and a burst signal identifier, output a control signal according to the differential input signal, the control reference value, the working state identifier and the burst signal identifier, and send the control signal to the automatic extinction ratio control circuit; The automatic extinction ratio control circuit is used to output a current control value according to the feedback signal, the preset reference signal and the control signal, so as to adjust the current of the current source according to the current control value.

[0043] In an automatic extinction ratio control system, before the AER (Automatic Extinction Ratio) begins operation, the IMODDAC value (corresponding to the current control value described above) is at its initial value. Once the AER begins operation, the AER adjusts the IMODDAC value from this initial value. Therefore, the AER start signal determines whether pattern detection values ​​begin to be emitted. Combinatorial logic uses AND logic to ensure that when the AER start signal = 0, no pattern detection information is output to subsequent circuits. When the AER start signal = 1, pattern detection information is allowed to be generated.

[0044] For burst systems, the burst mode uses the BEN signal to freeze or release the AER's IMODDAC value. In conventional AER circuits, the BEN signal serves as a direct control signal. When BEN = 0, the IMODDAC value output by the AER control circuit is frozen. When BEN = 1, the AER control circuit continues operating, and the output IMODDAC value continues to adjust based on the previously frozen value. For continuous systems, the BEN signal is constantly 1, so there is no freezing.

[0045] In this solution, the final output is a 1-bit control signal, which is sent to the AER control circuit. When the control signal = 0, the IMODDAC value output by the AER control circuit is frozen. When the control signal = 1, the AER control circuit continues to operate. In other words, in addition to freezing the AER control circuit when BEN = 0, it also freezes the circuit when a short pattern is recognized. In a continuous system, when the BEN signal input is always 1, it is additionally modulated to include information from the pattern recognizer. Therefore, a continuous system freezes the AER control circuit when a short pattern is recognized.

[0046] The pattern identifier calculates the number of flips from 0 to 1 in the pattern reference signal within a fixed sampling clock period, compares it with the control reference value, and then outputs a control signal to the AER control circuit.

[0047] When the control signal is 1 (i.e., during the long pattern period, the AER feedback circuit bandwidth is sufficient to capture the low-speed feedback signal), the AER control circuit operates normally. When the control signal is 0 (i.e., during short code periods, the AER feedback circuit bandwidth is insufficient to capture the high-speed feedback signal), the AER control circuit suspends operation. The IMODDAC value output by the AER control circuit is temporarily frozen and released when the control signal is 1, resuming operation.

[0048] This solution uses pattern recognition to circumvent issues that can arise when operating with short patterns for extended periods, often due to factors such as excessive MPD capacitance. During extended periods of short patterns, the AER control circuit is suspended and the AER output is frozen. When the longer pattern resumes, the AER control circuit resumes operation and dynamically adjusts the IMODDAC value from the frozen value. Furthermore, because this solution avoids the impact of the AER loop bandwidth, laser systems exceeding 10Gbps can still utilize existing extinction ratio circuit designs and MPD components, significantly reducing design costs. Because the pattern recognizer converts the extracted high-speed signal into digital CMOS logic for direct recognition and processing, it achieves a very fast response speed of 50ns-100ns for bursts as short as 200ns, making it ideal for burst mode applications. This eliminates the need for lengthy pattern training and extensive analog circuitry on the feedback side to identify the pattern, minimizing false positives and enabling mass production.

[0049] This solution incorporates a circuit design for high-speed laser driver circuits to ensure that even prolonged periods of short code patterns prevent the AER control circuit from continuously adjusting the IMODDAC value in one direction, potentially causing the IMODDAC value to fluctuate. Furthermore, for ONU applications in PON systems, this solution enables rapid response to burst signals. Therefore, this solution mitigates bandwidth issues while ensuring the rapid response required by the automatic extinction ratio control circuit.

[0050] like Figure 5The figure shows a schematic diagram of an automatic extinction ratio control system. The diode on the left corresponds to the laser. The input of the high-speed laser driver D (corresponding to the above-mentioned laser driver unit) is a code type, and its output is used as a modulation signal to adjust the on and off of the switch unit S. After the switch unit S is turned on, the current of the current source I1 is provided to the laser Z1. According to the magnitude of the current, the intensity of the laser emitted by the laser Z1 can be controlled, and the magnitude of the current is proportional to the laser intensity. After receiving the laser signal from laser Z1, diode Z2 converts it into a current signal, which is then converted into a voltage signal via TIA1 and resistor R1. The voltage signal is sent as a feedback signal to the AER control circuit. Diode Z2, TIA1, and resistor R1 form a laser feedback unit. Current source I2, TIA2, and resistor R2 form a reference signal unit for generating a preset reference signal. The pattern identifier is configured to receive the differential input signal, a preset control reference value, an operating state identifier, and a burst signal identifier, and output a control signal based on the differential input signal, the control reference value, the operating state identifier, and the burst signal identifier. The AER control circuit (corresponding to the aforementioned automatic extinction ratio control circuit) outputs an IMODDAC value based on the feedback signal, the preset reference signal, and the control signal. If the control signal is 1 and the preset reference signal is greater than the feedback signal, the IMODDAC value is increased to increase the current of current source I1, thereby increasing the laser intensity of laser Z1. The amplitude or phase of the preset reference signal and the feedback signal are compared in the AER control circuit, and the feedback modulates the IMODDAC value to ensure that the extinction ratio of the laser Z1 output signal remains consistent at all temperatures.

[0051] like Figure 6 The schematic diagram of an automatic extinction ratio control system in the prior art is shown, and Figure 5 In contrast, this diagram directly sends the BEN signal as a control signal to the AER control circuit, where the BEN signal is exclusive to the burst mode circuit and is always 1 in the continuous mode circuit. This system diagram has the problem that the input bandwidth of TIA1 is too low, resulting in the inability to recognize high-speed signals such as 0101 and short code patterns, and the inability to correctly judge the characteristics of the feedback signal such as signal amplitude and phase, which in turn leads to poor stability of the AER loop. Figure 5 The control system in can solve the above problems.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A code pattern identifier, characterized in that: include: A conversion module, configured to receive a differential input signal, perform conversion processing on the differential input signal, and output a code pattern reference signal; Sampling clock, used to generate clock signal; a pattern counter, configured to receive the pattern reference signal and the clock signal, count the number of flips from 0 to 1 in the pattern reference signal within a current sampling clock cycle, and output a count result; wherein the count result is used to indicate whether a short pattern signal exists in the differential input signal within the sampling clock cycle; A processing module is configured to receive the counting result, output a control signal based on the counting result, a preset control reference value, and a pre-received working status identifier and a burst signal identifier, and send the control signal to a preset automatic extinction ratio control circuit so that the automatic extinction ratio control circuit determines whether to freeze the current control value output by the automatic extinction ratio control circuit based on the control signal; wherein the working status identifier is used to indicate whether the automatic extinction ratio control circuit is in a working state, and the burst signal identifier is used to indicate whether the differential input signal is a burst packet signal.

2. The code pattern identifier according to claim 1, characterized in that The processing module includes: a digital comparator, configured to receive the counting result, compare the counting result with a preset control reference value, and output a comparison result; The signal generating module is used to receive the comparison result, perform logic processing on the comparison result, the working state identifier and the burst signal identifier received in advance, and output a control signal.

3. The code pattern identifier according to claim 2, characterized in that The signal generating module comprises: a first AND gate, configured to perform a logic operation on the comparison result and a pre-received working status identifier, and output a first logic signal; a NOT gate, configured to perform a logic operation on the first logic signal and output a second logic signal; The second AND gate is used to perform a logic operation on the second logic signal and the burst signal identifier, and output a control signal.

4. The code pattern identifier according to claim 2, characterized in that When the counting result is less than the control reference value, the comparison result is a low level; When the counting result is greater than the control reference value, the comparison result is a high level; When the counting result is equal to the control reference value, the comparison result outputted last time is maintained.

5. The code pattern identifier according to claim 1, characterized in that The differential input signal is a CML logic signal, and the code reference signal is a CMOS logic signal.

6. The code pattern identifier according to claim 1, characterized in that The pattern counter is also used to: After sending the counting result corresponding to the current sampling clock cycle to the processing module, waiting for a preset time and clearing the counting result; The next sampling clock cycle is used as a new current sampling clock cycle, and the step of counting the number of flips from 0 to 1 in the code reference signal within the current sampling clock cycle is repeatedly performed.

7. The code pattern identifier according to claim 1, characterized in that The sampling clock period of the clock signal is less than or equal to a first preset period and greater than a second preset period; wherein the first preset period is greater than the second preset period; the first preset period is the preset shortest clock period corresponding to the automatic extinction ratio control circuit; the second preset period is the period corresponding to the preset highest rate code reference signal.

8. The code pattern identifier according to claim 1, characterized in that The processing module is further configured to: If the control signal is at a low level, sending the low-level control signal to a preset automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit freezes the current control value output by the automatic extinction ratio control circuit according to the low-level control signal; If the control signal is at a high level, the high level control signal is sent to the automatic extinction ratio control circuit, so that the automatic extinction ratio control circuit adjusts the current control value output by the automatic extinction ratio control circuit according to the high level control signal.

9. The code pattern identifier according to claim 1, characterized in that: The switch tubes in the conversion module are all high-speed switch tubes.

10. An automatic extinction ratio control system, characterized in that: The system comprises: a laser driving unit, a switch unit, a current source, a laser, a laser feedback unit, a reference signal unit, an automatic extinction ratio control circuit, and the code pattern identifier according to any one of claims 1 to 9; The laser driving unit is used to receive a differential input signal, output a switch control signal, and control the on or off of the switch unit according to the switch control signal; The current source is used to provide current to the laser when the switch unit is turned on, so that the laser emits laser light; The laser feedback unit is used to generate a feedback signal according to the laser light emitted by the laser, and send the feedback signal to the automatic extinction ratio control circuit; The reference signal unit is used to generate a preset reference signal and send the preset reference signal to the automatic extinction ratio control circuit; The code pattern identifier is used to receive the differential input signal, a preset control reference value, a working state identifier and a burst signal identifier, output a control signal according to the differential input signal, the control reference value, the working state identifier and the burst signal identifier, and send the control signal to the automatic extinction ratio control circuit; The automatic extinction ratio control circuit is used to output a current control value according to the feedback signal, the preset reference signal and the control signal, so as to adjust the current of the current source according to the current control value.

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