Miniaturized high-precision non-binary R-2R DAC with digital correction

Abstract

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and in particular relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Background Art

[0002] DACs can convert digital signals into analog signals and are widely used in driver circuits. Driver circuits can be divided into three main structures based on their structure and control method: pixel-level driver, row-column driver, and chip-level driver.

[0003] In pixel-level driver circuits, each pixel requires a DAC. For dense array driver chips with K or more channels, the area of ​​a single-channel DAC becomes crucial to limiting the number of array channels within a limited area. Furthermore, an increasing number of applications require high-precision DACs to provide more precise adjustable voltages for high-precision control. However, for every additional bit of accuracy in traditional DACs, the DAC area increases fourfold. Therefore, the design of miniaturized, high-precision DACs for dense array driver circuit applications has become a challenge.

[0004] The area of ​​the resistor array in a traditional R-2R DAC increases fourfold with each bit increase in DAC precision, and the switch area also rises exponentially. The limited area of ​​a single-channel DAC in dense array drive circuits and the random mismatch of resistors limit the increase in the effective number of bits in resistive DACs. For pixel-level dense array drive circuits, each DAC must achieve a drive voltage accuracy of at least 10 bits, necessitating a compact, high-precision R-2R DAC.

[0005] To achieve accuracy exceeding 10 bits, R-2R DACs must be calibrated to reduce the impact of resistor mismatch on static performance. This is achieved through two main methods: analog and digital calibration. Analog calibration requires an additional calibration DAC to perform current or voltage injection to calibrate the main DAC, which incurs additional power consumption and area overhead, leading to increased cost. Digital calibration primarily involves ordered element matching (OEM) technology and non-binary DACs.

[0006] During the DAC test phase, OEM technology obtains the DAC output voltage when each branch of the thermometer decoding segment is individually connected to a high reference voltage and the other branches are connected to a low reference voltage, and sorts the voltage. The sorting result can characterize the relative size of the resistors. Because the larger the resistance value, the lower the weight, and the corresponding output voltage is smaller, the static error of the thermometer segment can be corrected by re-ordering and combining the thermometer segment resistors through the decoding circuit. However, the size of the switch of this method needs to increase by a multiple of 2 from low to high to maintain the ratio of R to 2R unchanged, resulting in a large switch area. In addition, the number of thermometer segments cannot be too many, otherwise the area of ​​the resistor array will increase exponentially, and the INL error caused by the nonlinearity of the resistor cannot be corrected. Therefore, the traditional DAC using OEM technology cannot be applied to dense array drive circuits.

[0007] Non-binary DACs introduce a lower weight than traditional binary DACs by setting a larger resistor value at a middle or high position in the resistor array, giving the DAC output a non-binary characteristic. When a carry occurs in the input digital code at that position, the reduced weight causes a negative step, ultimately resulting in one analog voltage state corresponding to multiple digital input codes. Ideally, DAC input digital codes correspond to output voltages one-to-one, so the extra digital codes are redundant. Therefore, this method requires determining the number of redundant digital codes at each negative step in the DAC output characteristic curve during testing to adjust the input code. Ultimately, this correction yields a DAC with binary output characteristics. However, for dense array drive circuits with up to K DACs, this method requires extensive calibration and requires storing numerous variables, resulting in high resource consumption in the external digital control circuitry. Therefore, traditional non-binary DACs cannot be applied to dense array drive circuits. Summary of the Invention

[0008] In response to the problems or shortcomings of the above-mentioned DAC correction scheme, the present invention proposes a miniaturized high-precision non-binary R-2R DAC with digital correction, which can significantly reduce the area of ​​the DAC while achieving high precision.

[0009] A miniaturized high-precision non-binary R-2R DAC with digital correction, the structure of which is as follows Figure 1 As shown, it is an m+n+k-bit 3-segment voltage output R-2R structure, which combines OEM correction technology with non-binary technology to realize a miniaturized high-precision DAC, including: R-2R switch resistor array, LSB segment delay equalization circuit, ISB segment OEM decoding circuit and MSB segment OEM decoding circuit.

[0010] The R-2R switch resistor array comprises an m-bit LSB segment, an n-bit ISB segment, and a k-bit MSB segment, a total of m+n+k bits; the ISB segment is a unary decoding from R m+1 to R m+i Total 2 n-1 The MSB segment is also unary decoded from Rm+i+1 to R m+i+j Total 2 k-1 Resistor branch.

[0011] Resistors R0 to R in the switch resistor array m+i+j The resistance value is 2R, RB1 to RB m-1 The resistance is R; RB m The bridge resistor between the LSB segment and the ISB segment is smaller than R, so that the equivalent resistance R lsbout Less than R m+1 ~R m+i The resistance value is 2R; RB m+1 The bridge resistor between the ISB segment and the MSB segment has a resistance value less than R, so that the equivalent resistance R seen from the right port to the left is isbout Less than R m+i+1 ~R m+i+j The resistance value is 2R, thereby introducing non-binary characteristics at both segments.

[0012] RB1~RB m+1 Connect in series, R0~R m The lower end of the MOS switches SW0 to SW m ; The upper ends of R0 and R1 are connected to the left end of RB1; R2~R m The upper end of R2 is connected to the right end of RB1 and the left end of RB2, ..., R m The upper end is connected to RB m-1 The right end and RB m The left end of .

[0013] R m+1 ~R m+i The lower ends of the MOS switches SW are connected one by one. m+1 ~SW m+i ; R m+1 ~R m+i The upper ends are connected to RB m Right end and RB m+1 Between the left ends, i = 2 n -1.

[0014] R m+i+1 ~R m+i+j The lower ends of the MOS switches SW are connected one by one. m+i+1 ~SW m+i+j , whose upper ends are connected to RB m+1 Right end, RB m+1 The right end is also the output end VOUT, j = 2 k -1.

[0015] SW0~SWm+i+j All of them are MOS switches, consisting of an NMOS tube and a PMOS tube. Switches SW1~SW m The width-to-length ratio of the MOS tube increases by 2 times, and the switches SW0 and SW m+1 ~SW m+i+j The width-to-length ratio of the MOS tube is the same as that of SW1; m+1 ~SW m+i+j The on-resistance is r0, SW2~SW m The on-resistance is r1~r m-1 And it decreases in 2-fold order, and the final on-resistance value of R1 is R0 / 2, R m-1 The on-resistance is r0 / 2 m-1 The MOS switch size of the ISB and MSB segments no longer maintains a multiple of 2 relationship with the MOS switch of the LSB segment, and the on-resistance r0 of the MOS switch is greater than r0 / 2. m The equivalent resistance of each branch is increased, thereby further introducing non-binary characteristics into the ISB segment and the MSB segment.

[0016] Switch SW0 is a normally closed switch and is always connected to VREFL. SW1 to SW m+i+j The outputs of LSB segment delay equalization circuit, ISB segment OEM decoding circuit and MSB segment OEM decoding circuit control R1~R m+i+j Connect to VREFH or VREFL to generate the corresponding output voltage VOUT.

[0017] The LSB segment delay equalization circuit is composed of an inverter chain, whose output is connected to the m-bit LSB segment switches SW1 to SW2 corresponding to the R-2R switch resistor array. m , external input binary control signal lsb0~lsb m-1 After delaying through the inverter chain, the m-bit binary control signal is output to control SW1~SW m Switching, thereby aligning the decoding output signals of the OEM decoding circuit of the ISB and MSB segments with the output signal of the LSB segment, reducing the burrs caused by timing errors when the digital code is switched.

[0018] The ISB segment OEM decoding circuit and the MSB segment OEM decoding circuit are both composed of an address selection register and a multiplexer: for n-bit and k-bit input digital codes, a specific 2R resistor branch is selected for each bit of the digital input code through the address selection register, and finally OEM correction is completed for the ISB segment and the MSB segment respectively.

[0019] Furthermore, the RB m The resistance value is set between 0.1R and 0.5R, RB m+1The resistance value is set between 0.5R and 0.9R. The bridge resistor value affects the output swing and effective number of bits after calibration. Therefore, the bridge resistor value needs to be reasonably set according to application requirements to ensure that the effective number of bits of the DAC after calibration reaches m+n+k-1 bits.

[0020] Furthermore, the external input signal of the ISB segment OEM decoding circuit is an n-bit binary control signal isb0~isb n-1 , its i-bit output signal is connected to the ISB segment MOS switch SW corresponding to the R-2R switch resistor array m+1 ~SW m+i Each 2R branch is controlled by an address selection register and a multiplexer. The i address selection registers are connected in series. The address selection signal controls the address selection signal serial input register under the action of the clock signal. Each register output controls the corresponding n-to-1 multiplexer; the number of resistor branches selected by the corresponding bit ranges from isb0 to isb n-1 The relationship increases by 2 times. When the first bit is 1, it corresponds to a 2R branch connected to VREFH. When the nth bit is 1, it corresponds to 2 n-1 The 2R branches are connected to VREFH; each bit of the digital input code controls the corresponding position and number of 2R resistor branches through the address selection register, and finally the OEM correction of the ISB segment is completed.

[0021] Furthermore, the external input signal of the MSB segment OEM decoding circuit is a k-bit binary control signal msb0~msb k-1 , its j-bit output signal is connected to the MSB segment MOS switch SW corresponding to the R-2R switch resistor array m+i+1 ~SW m+i+j Each 2R branch is controlled by an address selection register and a multiplexer, and j address selection registers are connected in series. The address selection signal controls the address selection signal serial input register under the action of the clock signal, and each register output controls the corresponding k-select-1 multiplexer; the number of resistor branches selected by the corresponding bit is from msb0 to msb k-1 The relationship increases by 2 times. When the first bit is 1, it corresponds to a 2R branch connected to VREFH. When the kth bit is 1, it corresponds to 2 k-1 The 2R branches are connected to VREFH; each bit of the digital input code controls the corresponding position and number of 2R resistor branches through the address selection register, and finally the OEM correction of the MSB segment is completed.

[0022] Furthermore, the miniaturized high-precision non-binary R-2R DAC with digital correction is applied to dense array driving circuits.

[0023] In summary, the present invention sets the bridge resistor RBm , RB m+1 The resistance value introduces non-binary characteristics, making the LSB segment a binary weight segment, and the ISB and MSB segments non-binary weight segments; thus making the switch SW m+1 ~SW m+i+j The width-to-length ratio of the MOS tube of SW1 is equal to that of the MOS tube, so there is no need to increase it proportionally. In addition, the non-binary characteristic is further introduced by setting the switch on-resistance. The selection of the unit resistor R only needs to meet the matching accuracy of the LSB segment, which greatly reduces the area of ​​the switch resistor array. OEM correction technology is further used to correct the static error in the ISB and MSB segments respectively. It only needs to measure the digital code redundancy between the LSB segment and the ISB segment, and the digital code redundancy between the ISB segment and the MSB segment. By adjusting the digital input code LSB0~LSB m-1 、isb0~isb n-1 、msb0~msb k-1 By removing redundant digital codes and calibrating an m+n+k-1-bit binary DAC, the digital calibration algorithm is memory-efficient and effectively reduces algorithm complexity. Ultimately, this invention achieves a miniaturized, high-precision, non-binary R-2R DAC with digital correction. This achieves high precision while significantly reducing the DAC's footprint, making it particularly suitable for dense array drive circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the circuit structure of the present invention;

[0025] Figure 2 This is a schematic structural diagram of the OEM decoding circuit of Example 4;

[0026] Figure 3 Schematic diagram of the structure of the +4+4 three-segment non-binary R-2R DAC of Example 8;

[0027] Figure 4 1 is a graph showing the output characteristic of a non-binary DAC after OEM correction in an embodiment;

[0028] Figure 5 This is a flow chart of an algorithm for obtaining a correction digital code according to an embodiment of the correction algorithm. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0030] This embodiment specifically designs a 16-bit 8+4+4 three-segment structure with digital correction miniaturized high-precision non-binary R-2R DAC. Figure 3As shown in the figure, the LSB segment has 8 bits, the ISB segment and the MSB segment are both 4 bits, and the effective number of bits can reach 15 bits after calibration. The selection of the unit resistor R needs to meet the 8-bit matching accuracy of the LSB segment, so as to ensure that the DNL error of the LSB segment is less than 1 / 2LSB. 38 The resistance of RB1 to RB7 is set to 2R, and the resistance of RB1 to RB7 is R. The bridge resistor RB8 between LSB and ISB, and the bridge resistor RB9 between ISB and MSB are set to: RB8 = 0.2R, RB9 = 0.8R respectively.

[0031] The width-to-length ratio of the MOS tubes of the LSB segment switches SW1 to SW8 increases in sequence by a factor of 2, so that their on-resistance decreases by a factor of 2. 38 The size of SW1 is the same as SW1, and the corresponding on-resistance is equal and r0. The final bridge resistance and the switch on-resistance work together to make the ISB and MSB segments of this DAC non-binary.

[0032] In this embodiment, the ISB segment OEM decoding circuit and the MSB segment OEM decoding circuit are both composed of an address selection register and a multiplexer, as shown in the attached figure. Figure 2 Figure 2 shows the circuit structure of a 4-bit OEM decoder circuit, which includes 15 2-bit address selection registers and 15 4-to-1 multiplexers. For a 4-bit input signal, the address selection signal must be at least 2 bits to control the selection of each of the 4 input bits. The address select signals ADR<1:0>, driven by the clock signal CLK, control the serial input registers of the address select signal. Each register output controls the corresponding 4-to-1 multiplexer. The 4-to-1 multiplexer inputs a 4-bit binary control signal, and its output is connected to a MOS switch.

[0033] The external input signal of the ISB segment OEM decoding circuit is n = 4-bit binary control signal b8~b 11 , output signal control switch SW9~SW 23 The external input signal of the MSB segment OEM decoding circuit is k = 4-bit binary control signal b 12 ~b 15 , output signal control switch SW 24 ~SW 38 Through the address selection register, each bit of the digital input code controls a specific position and number of 2R resistor branches, and finally completes the OEM correction for the ISB segment and the MSB segment respectively.

[0034] Taking the ISB segment as an example, when input b8=1, one 2R branch corresponding to the address of b8 after the OEM correction operation is selected and connected to VREFH. When b9=1, two 2R branches corresponding to the address of b9 after the OEM correction operation are selected and connected to VREFH. 10=1, select OEM calibration operation after b 10 The four 2R branches of the corresponding address are connected to VREFH, b 11 =1, then select OEM calibration operation b 11 The eight 2R branches corresponding to the addresses are connected to VREFH.

[0035] As attached Figure 4 As shown in the figure, when the input digital code carries from LSB to ISB or MSB, the non-binary characteristics make the weights of the ISB segment and MSB segment lower than those of a normal binary DAC, resulting in a negative step in the DAC output characteristic curve at the carry position due to the reduction in weight. That is, one analog voltage corresponds to multiple digital input codes, so the overlapping digital input codes are redundant and the digital input codes b0 to b1 need to be adjusted. 15 Redundant digital codes are removed to obtain the corresponding binary DAC after calibration. With traditional non-binary DACs, the amount of digital code redundancy at each negative step generated when the digital input code carries from the LSB segment to a higher bit varies. Therefore, it is necessary to measure the amount of redundancy that needs to be removed each time a digital code carries to achieve a more accurate calibration effect. This calibration workload is large, and the need to store many variables consumes a lot of control circuit resources.

[0036] During DAC calibration, the present invention first performs off-chip OEM calibration on the ISB segment and the MSB segment. After the OEM calibration is completed, it can be ensured that when a carry occurs in the DAC digital input code, the error between the voltage redundancy introduced at all negative steps due to the non-binary characteristics of the DAC output characteristic curve, i.e., the overlap error is less than 1 least significant bit (LSB). In other words, the error between the digital code redundancy corresponding to each negative step is less than 1. Therefore, by using the digital code redundancy at any negative step to perform DAC calibration, it can be ensured that the DNL error at the carry after calibration is less than 1 LSB. As shown in the attached figure, Figure 4 FIG. 1 shows the output characteristic curve of the DAC of the embodiment after OEM calibration. When a carry from the LSB to the ISB occurs, a small negative step is introduced by the bridge resistor RB8. The amount of digital code redundancy that needs to be removed in the overlapping portion is x. When a carry from the ISB to the MSB occurs, another large negative step is introduced by the bridge resistor RB9. The amount of digital code redundancy that needs to be removed in the overlapping portion is y. Therefore, the DAC of this embodiment needs to store two variables, x and y, for generating the digital correction code.

[0037] After OEM calibration, the redundancy x when the digital input code first carries from LSB to ISB and the redundancy y when the digital input code first carries from ISB to MSB are measured off-chip. Figure 5The figure shows the calibration algorithm flow chart. A single DAC channel only needs to save two variables, x and y. For any 15-bit binary digital input code Din, the algorithm can be used to obtain the corresponding 16-bit correction digital code D_cal, which corresponds to the binary digital codes b0 to b 15 As the input of a non-binary DAC, the DAC can finally be used as a high-precision binary R-2R DAC with an effective number of 15 bits.

[0038] The above examples demonstrate that the miniaturized, high-precision, non-binary R-2R DAC with an 8+4+4 three-segment structure and digital correction described in this embodiment can be used as a 15-bit high-precision binary DAC after calibration. Traditional DAC structures using OEM correction technology require that the width-to-length ratio of the switches in the ISB and MSB segments be maintained at a ratio twice that of the LSB segment switches. This large switch size consumes a significant area. Because the number of thermometer segments cannot be too large, high-precision DACs typically use a three-segment structure. However, the bridge resistor between the ISB and MSB segments introduces significant static error, necessitating the design of a sub-DAC for additional analog correction, further increasing the DAC area.

[0039] In traditional non-binary DAC, due to the different redundancy of digital codes at negative steps generated when a carry occurs, it is necessary to test and save the redundancy of each carry. In order to ensure the correction effect of this 8+4+4 structure embodiment, at least 2 8 For dense array drive circuits, if the number of circuit channels is 2000, you need to save 2000*2 8 Variables are used to obtain the correction code for each channel, and the calibration workload, memory consumption of the control circuit, and computing resource consumption are unacceptable.

[0040] In the embodiment of the present invention, the unit resistor only needs to meet 8-bit matching accuracy. The MOS switches for the ISB and MSB are the same size as SW1 and do not need to be proportionally increased, thus significantly reducing the area of ​​the switch resistor array. By combining OEM calibration technology with non-binary DAC technology, no additional syndrome DAC is required. A single DAC channel only needs to store two variables to obtain the digital calibration code, greatly simplifying the calibration work and achieving significant calibration results. This significantly reduces the memory consumption and algorithm complexity of the calibration algorithm.

[0041] Modeling and actual circuit simulations show that the DAC structure proposed in this invention achieves very high static performance and effective number of bits while exponentially reducing the overall area compared to traditional digitally calibrated R-2R DACs. This makes it suitable for dense array drive circuits requiring miniaturized, high-precision R-2R DACs.

Claims

1. A miniaturized high-precision non-binary R-2R DAC with digital correction, characterized by: It is an m+n+k bit 3-segment voltage output type R-2R structure, including an R-2R switch resistor array, an LSB segment delay equalization circuit, an ISB segment OEM decoding circuit, and an MSB segment OEM decoding circuit; The R-2R switch resistor array comprises an m-bit LSB segment, an n-bit ISB segment, and a k-bit MSB segment, a total of m+n+k bits; the ISB segment is a unary decoding from R m+1 to R m+i Total 2 n-1 The MSB segment is also unary decoded from R m+i+1 to R m+i+j Total 2 k-1 resistance branches; Resistors R0 to R in the switch resistor array m+i+j The resistance value is 2R, RB1 to RB m-1 The resistance is R; RB m The bridge resistor between the LSB segment and the ISB segment is smaller than R, so that the equivalent resistance R lsbout Less than R m+1 ~R m+i The resistance value is 2R; RB m+1 The bridge resistor between the ISB segment and the MSB segment has a resistance value less than R, so that the equivalent resistance R seen from the right port to the left is isbout Less than R m+i+1 ~R m+i+j The resistance value is 2R, thus introducing non-binary characteristics at both segments; RB1~RB m+1 Connect in series, R0~R m The lower end of the MOS switches SW0 to SW m ; The upper ends of R0 and R1 are connected to the left end of RB1; R2~R m The upper end of R2 is connected to the right end of RB1 and the left end of RB2, ..., R m The upper end is connected to RB m-1 The right end and RB m The left end of R m+1 ~R m+i The lower ends of the MOS switches SW are connected one by one. m+1 ~SW m+i ; R m+1 ~R m+i The upper ends are connected to RB m Right end and RB m+1 Between the left ends, i = 2 n -1; R m+i+1 ~R m+i+j The lower ends of the MOS switches SW are connected one by one. m+i+1 ~SW m+i+j , whose upper ends are connected to RB m+1 Right end, RB m+1 The right end is also the output end VOUT, j = 2 k -1; SW0~SW m+i+j All of them are MOS switches, consisting of an NMOS tube and a PMOS tube. Switches SW1~SW m The width-to-length ratio of the MOS tube increases by 2 times, and the switches SW0 and SW m+1 ~SW m+i+j The width-to-length ratio of the MOS tube is the same as that of SW1; m+1 ~SW m+i+j The on-resistance is r0, SW2~SW m The on-resistance is r1~r m-1 And it decreases in 2-fold order, and the final on-resistance value of R1 is R0 / 2, R m-1 The on-resistance is r0 / 2 m-1 The MOS switch size of the ISB and MSB segments no longer maintains a multiple of 2 relationship with the MOS switch of the LSB segment, and the on-resistance r0 of the MOS switch is greater than r0 / 2. m The equivalent resistance of each branch is increased to further introduce non-binary characteristics in the ISB segment and the MSB segment; Switch SW0 is a normally closed switch and is always connected to VREFL. SW1 to SW m+i+j The outputs of LSB segment delay equalization circuit, ISB segment OEM decoding circuit and MSB segment OEM decoding circuit control R1~R m+i+j Connect to VREFH or VREFL to generate the corresponding output voltage VOUT; The LSB segment delay equalization circuit is composed of an inverter chain, whose output is connected to the m-bit LSB segment switches SW1 to SW2 corresponding to the R-2R switch resistor array. m , external input binary control signal lsb0~lsb m-1 After delaying through the inverter chain, the m-bit binary control signal is output to control SW1~SW m Switching, thereby aligning the decoding output signals of the OEM decoding circuit of the ISB and MSB segments with the timing of the output signal of the LSB segment; The ISB segment OEM decoding circuit and the MSB segment OEM decoding circuit are both composed of an address selection register and a multiplexer: for n-bit and k-bit input digital codes, a specific 2R resistor branch is selected for each bit of the digital input code through the address selection register, and finally OEM correction is completed for the ISB segment and the MSB segment respectively.

2. The miniaturized high-precision non-binary R-2R DAC with digital correction according to claim 1, wherein: The RB m The resistance value is set between 0.1R and 0.5R, RB m+1 The resistance value is set between 0.5R and 0.9R.

3. The miniaturized high-precision non-binary R-2R DAC with digital correction according to claim 1, wherein: The external input signal of the ISB segment OEM decoding circuit is an n-bit binary control signal isb0~isb n-1 , its i-bit output signal is connected to the ISB segment MOS switch SW corresponding to the R-2R switch resistor array m+1 ~SW m+i Each 2R branch is controlled by an address selection register and a multiplexer. The i address selection registers are connected in series. The address selection signal controls the address selection signal serial input register under the action of the clock signal. Each register output controls the corresponding n-to-1 multiplexer. The number of resistor branches selected by the corresponding bit ranges from isb0 to isb n-1 The relationship increases by 2 times. When the first bit is 1, it corresponds to a 2R branch connected to VREFH. When the nth bit is 1, it corresponds to 2 n-1 The 2R branches are connected to VREFH; each bit of the digital input code controls the corresponding position and number of 2R resistor branches through the address selection register, and finally the OEM correction of the ISB segment is completed.

4. The miniaturized high-precision non-binary R-2R DAC with digital correction according to claim 1, wherein: The external input signal of the MSB segment OEM decoding circuit is a k-bit binary control signal msb0~msb k-1 , its j-bit output signal is connected to the MSB segment MOS switch SW corresponding to the R-2R switch resistor array m+i+1 ~SW m+i+j Each 2R branch is controlled by an address selection register and a multiplexer, and j address selection registers are connected in series; the address selection signal controls the address selection signal serial input register under the action of the clock signal, and each register output controls the corresponding k-select-1 multiplexer; the number of resistor branches selected by the corresponding bit is from msb0 to msb k-1 The relationship increases by 2 times. When the first bit is 1, it corresponds to a 2R branch connected to VREFH. When the kth bit is 1, it corresponds to 2 k-1 The 2R branches are connected to VREFH; each bit of the digital input code controls the corresponding position and number of 2R resistor branches through the address selection register, and finally the OEM correction of the MSB segment is completed.

5. The miniaturized high-precision non-binary R-2R DAC with digital correction according to claim 1, wherein: Applicable to dense array driving circuits.

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