MSCL decoding method and system based on error pattern

Abstract

The invention provides an MSCL decoding method based on an error pattern, which comprises the following steps: receiving a log-likelihood ratio and an information bit position information set Ac transmitted in a channel by a polarization code with a parameter of (N, K), determining a multi-bit judgment number M and a list number L, and constructing an error pattern table; performing serial elimination decoding on the current bit segment, and calculating and transmitting log-likelihood information and hard decision bit information; executing multi-bit judgment, and selecting a corresponding error pattern table expansion path according to the bit mode of the current bit segment; calculating a metric value of each expansion path generated by the existing list, sorting the paths, and reserving no more than L paths as a subsequent list; and repeating the process until all bits are decoded, and outputting a path decoding result with the minimum accumulated path metric value. By adopting the scheme, the multi-bit decoding parallelism is improved, and the decoding delay is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of polar code decoding, and in particular to a method and system for MSCL decoding based on error patterns. Background Art

[0002] With the advancement of technology, fifth-generation mobile communication (5G) systems have gradually become a major research hotspot in the mobile communications field. Numerous scholars and engineers are dedicated to pursuing the Shannon capacity limit. Polar codes, as the first coding scheme to theoretically and rigorously prove the capacity limit in a binary-input symmetric discrete memoryless channel (BI-BDC), have rapidly become a research hotspot. Polar codes have now been standardized for use in 5G eMBB data channels.

[0003] Polar codes use the serial cancellation (SC) algorithm in their decoding algorithms. However, due to the incomplete polarization of the low-code long-duration partial channel, their decoding performance is inferior to that of turbo codes and LDPC codes.

[0004] Subsequent research has made a series of improvements based on the characteristics of this algorithm. The serial cancellation decoding algorithm (Successive Cancellation List, SCL) reduces the bit error rate by generating multiple paths in SC decoding and calculating the path metric (Path Meiric, PM), and finally selecting the optimal path. The serial cancellation stack (Successive Cancellation, SCH) decoding algorithm stores paths in a stack form and places the current optimal path at the top of the stack, and only expands the top path, effectively reducing the computational complexity. Using the cyclic redundancy check (CRC) cascaded with SCL, a CRC-assisted SCL decoding method (CRC Assitant Successive Cancellation List, CA-SCL) is obtained. The SCL decoding result is tested by CRC, which further improves the decoding performance.

[0005] Although decoding performance has been greatly improved, in order to promote the application of polar codes, its decoding delay still needs to be further reduced. Summary of the Invention

[0006] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0007] To this end, the first object of the present application is to propose an MSCL decoding method based on error patterns, which improves the parallelism of multi-bit decoding and reduces decoding delay.

[0008] The second objective of this application is to propose an MSCL decoding system based on error patterns.

[0009] To achieve the above objectives, the first embodiment of the present application proposes an MSCL decoding method based on error patterns, comprising:

[0010] Step S1: Receive the log-likelihood ratio and information bit position information set A of the polar code with parameters (N, K) transmitted in the channel c , determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table;

[0011] Step S2: Perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information;

[0012] Step S3: performing multi-bit judgment and selecting a corresponding error pattern table expansion path according to the bit pattern of the current bit segment;

[0013] Step S4: Calculate the metric value of each expansion path generated by the existing list and sort them, retaining no more than L paths as the subsequent list;

[0014] Step S5: Repeat steps S2-S4 until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

[0015] To achieve the above-mentioned object, a second embodiment of the present invention provides an MSCL decoding system based on error patterns, comprising:

[0016] The channel information receiving module is used to receive the log-likelihood ratio and information bit position information set A transmitted by the polar code with parameters (N, K) in the channel. c , determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table;

[0017] a serial elimination decoding module, configured to perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information;

[0018] A multi-bit decision module, configured to perform multi-bit decision and select a corresponding error pattern table expansion path according to the bit pattern of the current bit segment;

[0019] The path selection module is used to calculate the metric value and sort the expansion paths generated by each existing list, and retain no more than L paths as the subsequent list;

[0020] The iterative module is used to repeatedly execute the decoding module, the decision module and the path screening module until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

[0021] The error pattern-based MSCL decoding method and system of the embodiments of the present application can effectively reduce the number of path extensions and the calculation of invalid paths through multi-bit path expansion based on error patterns. While stabilizing decoding performance, it can reduce the computational complexity and computational complexity of the multi-bit decoding path metric and sorting process, thereby reducing the overhead of computing resources in hardware implementation.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0024] Figure 1 A flowchart of an MSCL decoding method based on an error pattern provided in Example 1 of the present application;

[0025] Figure 2 Technical route implemented for this application Figure 1 ;

[0026] Figure 3 Technical route implemented for this application Figure 2 ;

[0027] Figure 4 A schematic structural diagram of an MSCL decoding system based on error patterns provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0029] The following describes the error pattern-based MSCL decoding method and system according to an embodiment of the present application with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart of an MSCL decoding method based on error patterns provided in Example 1 of the present application.

[0031] like Figure 1 As shown, the MSCL decoding method based on the error pattern includes the following steps:

[0032] Step S1: Receive the log-likelihood ratio and information bit position information set A of the polar code with parameters (N, K) transmitted in the channel c, determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table;

[0033] In this embodiment, N represents the code length, K represents the number of information bits, and A c Represents a set of length N, consisting of elements {0, 1}, where 1 represents the position of the information bit and 0 represents the position of the frozen bit. According to the SCL decoding principle, let s represent the current decision layer, 0≤s≤log2N. 0 represents the decoding information layer, log2N represents the channel information layer, after determining M, let s=log2M, when determining the number of multi-bit decisions, make an error pattern table and set A c The inner elements are divided into groups of M.

[0034] In this embodiment, based on the given number M of single bit decisions and the number L of lists, a table of error patterns is created, which maps the bit patterns (distribution of information bits and frozen bits) and the decision results to the path extension direction. Specifically, the table includes:

[0035] Step 1: Based on the number of bits M to be judged, determine the number of all existing bit patterns and judgment codewords to be 2 M .

[0036] Step 2: Calculate the 2 generated by the K information bits according to the current bit pattern K The information bits and frozen bits are combined to generate all possible decoding results.

[0037] Step 3: Map the decoding result in step 2 to a multi-bit decision layer by constructing a matrix to obtain an extended path set.

[0038] Step 4: Calculate the Hamming distance between the current decision codeword and all paths in the expansion path set, and save the L codeword expansion paths with the minimum distance.

[0039] Step 5: Jump to step 4 until all decision codeword types are traversed.

[0040] Step 6: Jump to step 2 until all bit patterns are traversed.

[0041] Step S2: Perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information;

[0042] In this embodiment, the SCL decoding algorithm, based on multi-bit decision, makes a decoding decision at a specific layer s based on the number of decision bits M. Therefore, execution only needs to proceed up to layer s. The binary tree structure of the decoding shows that at layer s, each node carries M log-likelihood ratio information. The decision results at this layer are mapped to the final decoding result using the polar code construction matrix.

[0043] Step S3: performing multi-bit judgment and selecting a corresponding error pattern table expansion path according to the bit pattern of the current bit segment;

[0044] In this embodiment, the bit pattern information is divided into three scenarios:

[0045] Case 1: All bits in the bit pattern are information bits. The current decision result is copied and expanded in column form and then added to the following matrix. The result is the subsequent expansion path codeword:

[0046]

[0047] The size of this matrix is ​​M×(M+1). Since this matrix consists of an all-zero column vector and a unit matrix, it represents the set of positions where a single bit error occurs in the current decision codeword. Therefore, the result of the codeword and the matrix represents the original codeword and the expanded set of single-bit error codewords. According to the path metric accumulation rule of the serial elimination list decoding algorithm, when there is a difference between the decision layer value and the expanded path codeword, the absolute value of the maximum likelihood ratio will be accumulated as the path metric. PM is used as the criterion for path screening because the probability of metric retention accumulated by its single-bit difference type is much greater than that of multiple bits, and when the codeword is longer, the expanded path will converge to the low-metric path, so that the decoding performance can remain stable while reducing the number of path expansions. The number of expanded paths generated by this method is M+1, while the number of paths generated by the traditional MSCL decoding method is 2. M , so the calculation of redundant paths can be effectively reduced.

[0048] Case 2: The current bit is a mixture of information bits and frozen bits, and the number of information bits is no less than log2L. The current decision codeword and bit pattern are used as input to the error pattern table, which is then looked up to output an extended path. The principle is similar to the previous example, but due to the inclusion of frozen bits, their positions vary and their values ​​are fixed (usually 0). Extending the path becomes more complex when the number of information bits is large. Preparing a table and then looking it up during decoding can save computational resources and decoding time.

[0049] Case 3: The current bit is a mixture of information bits and frozen bits, and the number of information bits is less than log2L. Direct path expansion is performed based on the number and position of the current information bits. Since the number of path expansions is small, direct calculation is possible. In this case, the path requires the mapping operation mentioned in the table construction process. This is because the path expansion using information bits and frozen bit position information is performed at layer 0, while the multi-bit decoding decision and expansion operations are performed at layer s. Direct expansion when the number of path expansions is small can reduce the size of the lookup table and save hardware storage resources.

[0050] Step S4: Calculate the metric value of each expansion path generated by the existing list and sort them, retaining no more than L paths as the subsequent list;

[0051] In this embodiment, the metric value is calculated and sorted for each expansion path generated by the existing list, and no more than L paths are retained as the subsequent list. The decoding results are mapped from the s layer to the 0 layer using the constructed matrix. Because the above-mentioned decision and expansion operations are both performed at the s layer, the output decoding information is at the 0 layer.

[0052] Step S5: Repeat steps S2-S4 until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

[0053] The MSCL decoding method based on error pattern in the embodiment of the present application adopts Figure 2 、 Figure 3 The technical roadmap shown can effectively reduce the number of path extensions and the calculation of invalid paths through multi-bit path expansion based on error patterns. It can also reduce the computational complexity and computational complexity of the multi-bit decoding path metric and sorting process while maintaining stable decoding performance, thereby reducing the computational resource overhead in hardware implementation.

[0054] This embodiment also proposes a method for implementing MSCL decoding based on error patterns. In this decoding method, a polar code with a code length of N = 1024 and a code rate of 0.5, that is, K = 512, is used. Its construction matrix is ​​generated by Krone integrable iteration of [1, 0; 1, 1]. The position bit information is A c , the number of multi-bit decisions M=8, and the number of decoding lists used L is 8.

[0055] Step 1: Determine the parameter information and create an error pattern table.

[0056] For multi-bit decoding with M=8, there are 256 bit patterns, denoted by x i ,1≤i≤256, its binary representation ranges from 00000000 to 11111111, where 0 represents the frozen bit and 1 represents the information bit. All possible expansion paths are calculated based on the bit pattern of the current decoding block. For example, for the bit pattern of 00001111, since the frozen bit is always decoded to 0, only 16 decoding results can be generated from the first four information bits, which are recorded as k i ,1≤i≤16 In this example, the range is 00000000 to 00001111. At this time, all the results correspond to the decoding information at the 0th layer. i After the calculation of the constructed matrix is ​​mapped to the sth layer, the codeword t is obtained i

[0057] For multi-bit decoding with M=8, there are 256 possible decision results at the decision layer, denoted as y j ,1≤j≤256. Its binary representation range is also 00000000 to 11111111.

[0058] In the bit pattern x i and the judgment result is y j Under the condition that all possible expansion paths are T=(t1,t2,t3,...,t n ). Now calculate y j , and the Hamming distance of all paths in the T set, save the L paths with the smallest Hamming distance as the expansion path, and save the path as P = (p1, p2, p3, ..., p L The mapping relationship of the error pattern table record is (x i ,y j )→P(p1,p2,p3,...,p L ), recorded as P = f(x i ,y j ), that is, during the decoding process, the current bit pattern and judgment result are input, and the expansion path can be obtained by table lookup. In this example, the error pattern table is 256×256×8 in size, but some data in this table is not needed in the subsequent optimized decoding process, reducing storage resource consumption in the hardware implementation.

[0059] Step 2: Divide the code with code length N according to the number of multi-bit decisions M, and record each group of bits as For the current bit group ρ i Execute the calculation process of the serial elimination list algorithm, iteratively calculate the received channel layer log-likelihood ratio according to the f, g operation rules, and when it reaches the s=log2M layer, use the M llr information retained in the current layer to make a decision according to the following rules to obtain the decision codeword u s , represents the M codeword decision information at the s layer.

[0060] Step 3: Perform multi-bit decision according to ρ i The bit pattern of , select the corresponding path expansion scheme. The following is a specific example. If ρ i The bit pattern δ i is the full information bit, that is, [1,1,1,1,1,1,1,1], then the decision code word u in step 2 s , use the single-bit error pattern matrix to calculate its expansion path, and u s Copy in the column direction to get D=[u s ,u s ,u s ,...,u s], then the extended path P=(D+v). If ρ i The bit pattern δ i is a mixture of information bits and frozen bits, and the number of information bits is greater than or equal to log2L, such as δ i =[1,0,0,1,1,1,1,1], then use the error pattern lookup table, and use the current bit pattern δ i and judgment bit u s To address, P = f(δ i ,y s ) is the required expansion path. If ρ i The bit pattern δ i It is a mixture of information bits and frozen bits, and the number of information bits is less than log2L, such as δ i =[1,1,0,0,0,0,0,0], then according to the number of information bits and their positions, all possible paths are expanded to [0,0,0,0,0,0,0,0], [0,1,0,0,0,0,0,0], [1,0,0,0,0,0,0,0], [1,1,0,0,0,0,0,0], and the information result of the expanded path codeword at layer 0 is mapped to layer s through the mapping matrix. The path set after mapping is the P expanded path retention result.

[0061] Step 4: For all expansion paths P=(p1,p2,p3,...,p L ) and the current decision codeword are used to calculate the PM path metric value according to the following formula:

[0062]

[0063] In the above formula represents the bit distribution of the current expansion path p, α j and are the jth bit of the extended path codeword and the current decoded codeword respectively. After all extended paths are calculated, the PM value set (pm1, pm2, pm3, ..., pm N ). Sort all paths by PM value and keep L paths with the smallest PM value. i The bit decoding and path expansion of the group have been confirmed, and then the retained path information is mapped to the 0th layer through the construction matrix, merged with the previous decoding results and saved in the corresponding path, that is,

[0064] Step 5: Return to step 2 until all bit groups are decoded. Finally, output the U of the path with the minimum PM value. L The final decoding result.

[0065] In order to implement the above embodiment, the present application also proposes an MSCL decoding system based on error patterns.

[0066] Figure 4 A schematic structural diagram of an MSCL decoding system based on error patterns provided in an embodiment of the present application.

[0067] like Figure 4 As shown, the MSCL decoding system based on error pattern includes:

[0068] The channel information receiving module is used to receive the log-likelihood ratio and information bit position information set A transmitted by the polar code with parameters (N, K) in the channel. c , determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table;

[0069] a serial elimination decoding module, configured to perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information;

[0070] A multi-bit decision module, configured to perform multi-bit decision and select a corresponding error pattern table expansion path according to the bit pattern of the current bit segment;

[0071] The path selection module is used to calculate the metric value and sort the expansion paths generated by each existing list, and retain no more than L paths as the subsequent list;

[0072] The iterative module is used to repeatedly execute the decoding module, the decision module and the path screening module until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

[0073] Furthermore, in the embodiment of the present application, the channel information receiving module is specifically configured to:

[0074] N represents the code length, K represents the number of information bits, and A c Represents a set of length N consisting of elements {0, 1}, where 1 represents an information bit and 0 represents a frozen bit.

[0075] According to the SCL decoding principle, let s represent the current decision layer, 0≤s≤log2N, 0 represents the decoding information layer, and log2N represents the channel information layer;

[0076] After determining M, let s = log2M, and construct an error pattern table that maps the bit pattern and the judgment result to the path expansion direction based on the given single bit judgment number M and the number of lists L, and then set A c The inner elements are divided into groups of M. β iRepresents the bit pattern of the i-th bit segment, and the code length of each bit segment is

[0077] Specifically, in the embodiment of the present application, based on the given number M of single bit decisions and the number L of lists, an error pattern table is constructed that maps bit patterns and decision results to path extension directions, including:

[0078] Step S1: According to the number of bits M to be judged, determine the number of all existing bit patterns and judgment codewords to be 2 M ;

[0079] Step S2: Calculate the 2 generated by the K information bits according to the current bit pattern. K The information bits and frozen bits are combined to generate all possible decoding results.

[0080] Step S3: Map all possible current decoding results in step S2 to a multi-bit decision layer through a constructed matrix to obtain a current set of candidate expansion paths;

[0081] Step S4: Calculate the Hamming distance between the current decision codeword and all paths in the current candidate extension path set, and sort them from small to large according to the calculated distance, retaining the first L codeword extension paths;

[0082] Step S5: Repeat step S4 until all decision codeword types are traversed;

[0083] Step S6: Repeat steps S2-S5 until all bit patterns are traversed, and obtain an error pattern table that maps the bit patterns and judgment results to the path extension direction.

[0084] Furthermore, in the embodiment of the present application, the serial elimination decoding module is specifically configured to:

[0085] The calculation process of the serial elimination list is executed for the current bit segment. When it reaches the s layer, the M log-likelihood ratio information retained in the current layer is used to make a decision to obtain the current decision codeword, which represents the M codeword decision information at the s layer.

[0086] Specifically, in the embodiment of the present application, the multi-bit decision module is specifically used to:

[0087] When the bit pattern is full information bit, the current decision codeword is copied and expanded in column form and then added to the matrix V. The result is the extended path codeword, where the size of the matrix V is M×(M+1). The matrix V consists of an all-zero column vector and an identity matrix. The matrix V is expressed as:

[0088]

[0089] When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is not less than log2L, the bit pattern of the current decision codeword and the current bit segment is used as the input of the error pattern table, and the table is looked up to determine the extension path.

[0090] When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is less than log2L, the path is directly expanded according to the number and position of the current information bits.

[0091] It should be noted that the aforementioned explanation of the embodiment of the MSCL decoding method based on an error pattern is also applicable to the MSCL decoding system based on an error pattern in this embodiment, and will not be repeated here.

[0092] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0093] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0094] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0095] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0096] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0097] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0098] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0099] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A MSCL decoding method based on error patterns, characterized in that: The method comprises: Step S1: Receive the log-likelihood ratio and information bit position information set A of the polar code with parameters (N, K) transmitted in the channel c , determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table; Step S2: Perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information; Step S3: performing multi-bit judgment and selecting a corresponding error pattern table expansion path according to the bit pattern of the current bit segment; Step S4: Calculate the metric value of each expansion path generated by the existing list and sort them, retaining no more than L paths as the subsequent list; Step S5: Repeat steps S2-S4 until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

2. The method according to claim 1, wherein The step S1 specifically includes: N represents the code length, K represents the number of information bits, and A c Represents a set of length N consisting of elements {0, 1}, where 1 represents an information bit and 0 represents a frozen bit. According to the SCL decoding principle, let s represent the current decision layer, 0≤s≤log2N, 0 represents the decoding information layer, and log2N represents the channel information layer; After determining M, let s = log2M, and construct an error pattern table that maps the bit pattern and the judgment result to the path expansion direction based on the given single bit judgment number M and the number of lists L, and then set A c The inner elements are divided into groups of M. β i Represents the bit pattern of the i-th bit segment, and the code length of each bit segment is 3. The method according to claim 2, wherein The step of constructing an error pattern table based on a given number M of single bit decisions and a given number L of lists, which maps bit patterns and decision results to path extension directions, includes: Step S1: According to the number of bits M to be judged, determine the number of all existing bit patterns and judgment codewords to be 2 M ; Step S2: Calculate the 2 generated by the K information bits according to the current bit pattern. K The information bits and frozen bits are combined to generate all possible decoding results. Step S3: Map all possible current decoding results in step S2 to a multi-bit decision layer through a constructed matrix to obtain a current set of candidate expansion paths; Step S4: Calculate the Hamming distance between the current decision codeword and all paths in the current candidate extension path set, and sort them from small to large according to the calculated distance, retaining the first L codeword extension paths; Step S5: Repeat step S4 until all decision codeword types are traversed; Step S6: Repeat steps S2-S5 until all bit patterns are traversed, and obtain an error pattern table that maps the bit patterns and judgment results to the path extension direction.

4. The method according to claim 2, wherein The step S2 specifically includes: The calculation process of the serial elimination list is executed for the current bit segment. When it reaches the s layer, the M log-likelihood ratio information retained in the current layer is used to make a decision to obtain the current decision codeword, which represents the M codeword decision information at the s layer.

5. The method according to claim 4, wherein The step S3 specifically includes: When the bit pattern is full information bit, the current decision codeword is copied and expanded in column form and then added to the matrix V. The result is the extended path codeword, where the size of the matrix V is M×(M+1). The matrix V consists of an all-zero column vector and an identity matrix. The matrix V is expressed as: When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is not less than log2L, the bit pattern of the current decision codeword and the current bit segment is used as the input of the error pattern table, and the table is looked up to determine the extension path. When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is less than log2L, the path is directly expanded according to the number and position of the current information bits.

6. An MSCL decoding system based on error patterns, characterized in that: include: The channel information receiving module is used to receive the log-likelihood ratio and information bit position information set A transmitted by the polar code with parameters (N, K) in the channel. c , determine the number M of multi-bit decisions and the number L of lists, and construct an error pattern table; a serial elimination decoding module, configured to perform serial elimination decoding on the current bit segment, calculate and transmit log-likelihood information and hard decision bit information; A multi-bit decision module, configured to perform multi-bit decision and select a corresponding error pattern table expansion path according to the bit pattern of the current bit segment; The path selection module is used to calculate the metric value and sort the expansion paths generated by each existing list, and retain no more than L paths as the subsequent list; The iterative module is used to repeatedly execute the decoding module, the decision module and the path screening module until all bits are decoded, and output the path decoding result with the minimum accumulated path metric value.

7. The system according to claim 6, wherein: The channel information receiving module is specifically configured to: N represents the code length, K represents the number of information bits, and A c Represents a set of length N consisting of elements {0, 1}, where 1 represents an information bit and 0 represents a frozen bit. According to the SCL decoding principle, let s represent the current decision layer, 0≤s≤log2N, 0 represents the decoding information layer, and log2N represents the channel information layer; After determining M, let s = log2M, and construct an error pattern table that maps the bit pattern and the judgment result to the path expansion direction based on the given single bit judgment number M and the number of lists L, and then set A c The inner elements are divided into groups of M. β i Represents the bit pattern of the i-th bit segment, and the code length of each bit segment is 8. The system according to claim 7, wherein: The step of constructing an error pattern table based on a given number M of single bit decisions and a given number L of lists, which maps bit patterns and decision results to path extension directions, includes: Step S1: According to the number of bits M to be judged, determine the number of all existing bit patterns and judgment codewords to be 2 M ; Step S2: Calculate the 2 generated by the K information bits according to the current bit pattern. K The information bits and frozen bits are combined to generate all possible decoding results. Step S3: Map all possible current decoding results in step S2 to a multi-bit decision layer through a constructed matrix to obtain a current set of candidate expansion paths; Step S4: Calculate the Hamming distance between the current decision codeword and all paths in the current candidate extension path set, and sort them from small to large according to the calculated distance, retaining the first L codeword extension paths; Step S5: Repeat step S4 until all decision codeword types are traversed; Step S6: Repeat steps S2-S5 until all bit patterns are traversed, and obtain an error pattern table that maps the bit patterns and judgment results to the path extension direction.

9. The system according to claim 7, wherein: The serial elimination decoding module is specifically used to: The calculation process of the serial elimination list is executed for the current bit segment. When it reaches the s layer, the M log-likelihood ratio information retained in the current layer is used to make a decision to obtain the current decision codeword, which represents the M codeword decision information at the s layer.

10. The system according to claim 9, wherein: The multi-bit decision module is specifically used to: When the bit pattern is full information bit, the current decision codeword is copied and expanded in column form and then added to the matrix V. The result is the extended path codeword, where the size of the matrix V is M×(M+1). The matrix V consists of an all-zero column vector and an identity matrix. The matrix V is expressed as: When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is not less than log2L, the bit pattern of the current decision codeword and the current bit segment is used as the input of the error pattern table, and the table is looked up to determine the extension path. When the bit pattern is a mixture of information bits and frozen bits, and the number of information bits is less than log2L, the path is directly expanded according to the number and position of the current information bits.

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