Multi-channel HART dynamic communication system

Abstract

The invention provides a multichannel HART (Highway Addressable Remote Transducer) dynamic communication system. The multichannel HART dynamic communication system comprises a modulation circuit and a demodulation circuit, the demodulation circuit of each channel comprises a hysteresis Schmitt trigger module and an analog quantity acquisition module which are parallel, the hysteresis Schmitt trigger module is configured to separate HART signals to obtain FSK signals in the HART signals, and the analog quantity acquisition module is configured to acquire the FSK signals in the HART signals. The FSK signal is converted into a digital pulse signal through the hysteresis Schmitt trigger and then is output to the controller, and the logic level of the digital pulse signal corresponds to the first frequency and the second frequency of the FSK signal; and the analog quantity acquisition module is configured to separate the HART signal to obtain a 4-20mA direct current component in the HART signal, convert the 4-20mA direct current component into a digital signal and output the digital signal to the controller.

Description

Technical Field

[0001] The present invention relates to the field of industrial communications, and in particular to a multi-channel HART dynamic communication system. Background Art

[0002] In modern industrial automation systems, the HART (Highway Addressable Remote Transducer) protocol is a widely used hybrid communication protocol. By superimposing a digital modulation signal (1200Hz / 2200Hz FSK frequency-shift keying signal) on a 4-20mA analog signal, it enables dual support for bidirectional digital communication and analog data acquisition for field instruments. With the development of the Industrial Internet of Things (IIoT) and smart factories, industrial sites are increasingly demanding the integration, low cost, and high real-time performance of multi-channel HART devices. However, traditional HART communication solutions have significant limitations in multi-channel scenarios.

[0003] Existing multi-modem solutions require a separate HART modem for each channel, resulting in high hardware costs. For example, a 16-channel system requires 16 separate modems, which consumes a large amount of PCB space and consumes high power. Furthermore, resource utilization is low and resources cannot be dynamically allocated based on channel load.

[0004] Existing solutions combining time-division multiplexing and software demodulation implement multi-channel HART communication by using analog switches to time-division multiplex signals and combining them with MCU software demodulation to replace hardware modems. However, when HART signals share lines with analog signals, transient noise during the switching process can cause signal distortion and lead to software demodulation errors. Furthermore, software demodulation requires high-frequency sampling (e.g., above 8kHz), which consumes a large amount of CPU resources, making it difficult to handle multi-channel tasks and high-precision analog data acquisition simultaneously.

[0005] The existing single-modem combined with a multiplexer solution uses a single HART modem and analog switches to multiplex multi-channel signals to reduce costs. However, this solution lacks an intelligent scheduling mechanism, resulting in high switching latency (typically greater than 1ms) and long multi-channel polling cycles (for example, greater than 16ms for 16 channels), making it unable to meet the real-time requirements of high-speed control scenarios.

[0006] In addition, the FPGA-based HART signal modulation and demodulation method proposed in the prior art CN116094884A uses a zero-crossing comparator to perform FSK signal demodulation to replace the HART modem. However, this method leads to a complex architecture, high cost, and requires a negative power supply design, which increases circuit complexity. At the same time, it does not solve the problem of coordinated operation of multi-channel HART protocol stacks. The ADC sampling-based HART signal modulation and demodulation solution disclosed in the prior art CN117614791A supports multi-channel parallel processing, but consumes a lot of hardware resources, does not involve dynamic scheduling or noise reduction optimization, and has difficulty balancing low power consumption and performance requirements. The prior art CN119728364A uses "input interrupt" and "input capture" technologies to capture signal pulses, relying on hardware circuit filtering and demodulation, but has limited noise reduction capabilities. There are technical barriers to analog signal conditioning in multi-channel applications, making it difficult to ensure demodulation accuracy and lacking analog acquisition functions.

[0007] The ultimate goal of these existing technologies is to replace the more expensive professional HART Modem chips, without considering the actual design difficulty and the collaborative operation effect with the HART protocol stack, which violates the design concepts of reducing hardware complexity, reducing PCB area, and reducing costs.

[0008] In order to overcome the above-mentioned defects of the existing technology, this field urgently needs a multi-channel HART dynamic communication system that can reduce hardware complexity, realize the status perception of each channel by extracting the timing characteristics of the HART signal through hardware demodulation, and ensure that there is no conflict between digital communication and analog quantity acquisition, thereby ensuring data integrity. Summary of the Invention

[0009] The following is a brief summary of one or more aspects to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceivable aspects and is neither intended to identify key or critical elements of all aspects nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be provided later.

[0010] In order to overcome the above-mentioned defects of the prior art, the present invention provides a multi-channel HART dynamic communication system, which can reduce hardware complexity, realize the status perception of each channel by extracting the timing characteristics of the HART signal through hardware demodulation, and ensure that there is no conflict between digital communication and analog quantity acquisition, thereby ensuring data integrity.

[0011] Specifically, the multi-channel HART dynamic communication system provided according to the present invention includes a modulation circuit and a demodulation circuit, and the demodulation circuit of each channel includes a parallel hysteresis Schmitt trigger module and an analog quantity acquisition module, wherein the hysteresis Schmitt trigger module is configured to separate the HART signal to obtain the FSK signal in the HART signal, and convert the FSK signal into a digital pulse signal through the hysteresis Schmitt trigger and output it to the controller, and the logic level of the digital pulse signal corresponds to the first frequency and the second frequency of the FSK signal; and the analog quantity acquisition module is configured to separate the HART signal to obtain the 4-20mA DC component in the HART signal, and convert the 4-20mA DC component into a digital signal and output it to the controller.

[0012] Preferably, in one embodiment of the present invention, the hysteresis Schmitt trigger module includes a first signal conditioning unit, and the FSK signal in the HART signal is separated by the first signal conditioning unit. The first signal conditioning unit includes a filtering module and a unidirectional amplifier for amplifying the signal.

[0013] Preferably, in one embodiment of the present invention, the analog quantity acquisition module includes a second signal conditioning unit, and the 4-20mA DC component in the HART signal is separated by the second signal conditioning unit, and the second signal conditioning unit includes a low-pass filter.

[0014] Preferably, in an embodiment of the present invention, the demodulation circuit collects the HART signal through a differential amplification unit and amplifies the HART signal.

[0015] Preferably, in an embodiment of the present invention, a digital isolator is provided between the hysteresis Schmitt trigger module and the controller, and between the analog quantity acquisition module and the controller.

[0016] Preferably, in an embodiment of the present invention, an isolation transformer for isolating external devices is further included.

[0017] Preferably, in one embodiment of the present invention, the modulation circuit includes a HART modulation chip and an analog switch connected to the controller, and the modulation circuit is configured to modulate the HART signal output by the controller through the HART modulation chip, and send the modulated HART signal to the designated channel through the analog switch.

[0018] Preferably, in an embodiment of the present invention, the controller is configured to adjust the polling mode of the HART command according to the HART command priority queue.

[0019] Preferably, in an embodiment of the present invention, the controller is further configured to adjust the priority of the HART command in the HART command priority queue and / or the polling mode of the HART command based on the response status of the HART command.

[0020] Preferably, in one embodiment of the present invention, the controller is further configured to, in response to the enabling of the preemption flag of the HART command when the output condition is triggered, use an interrupt mechanism to adjust the polling order to give priority to polling the HART command. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or characteristics may have the same or similar reference numerals.

[0022] Figure 1 An architectural diagram of a multi-channel HART dynamic communication system provided according to some embodiments of the present invention is shown;

[0023] Figure 2 A flowchart of HART signal processing in a demodulation circuit provided by some embodiments of the present invention is shown;

[0024] Figure 3 shows a schematic diagram of a demodulation circuit provided by some embodiments of the present invention;

[0025] Figure 4 A flowchart of HART polling according to some embodiments of the present invention is shown; and

[0026] Figure 5 A flowchart of a preemptive output function provided according to some embodiments of the present invention is shown.

[0027] Reference numerals:

[0028] 101: channel;

[0029] 102: Isolation transformer;

[0030] 103: Double-pole four-throw analog bus switch;

[0031] 104: HART modulation chip;

[0032] 105: first signal conditioning unit;

[0033] 106: Hysteresis Schmitt trigger;

[0034] 107: second signal conditioning unit;

[0035] 108: ADC unit;

[0036] 109: Digital isolator;

[0037] 110: controller;

[0038] 201: Figure;

[0039] 202: first signal conditioning unit;

[0040] 203: Figure;

[0041] 204: reference voltage;

[0042] 205: Figure;

[0043] 206: Hysteresis Schmitt trigger;

[0044] 207: Hysteresis trigger process;

[0045] 208: Figure;

[0046] 209: pulse sequence scanning module;

[0047] 210: second signal conditioning unit;

[0048] 211: Figure;

[0049] 212: ADC sampling module;

[0050] 301: differential amplifier module;

[0051] 302: bandpass filter module;

[0052] 303: first coupling unit;

[0053] 304: low-pass filter;

[0054] 305: second coupling unit;

[0055] 306: same direction amplifier;

[0056] 307: reference voltage coupling module;

[0057] 308: hysteresis comparison module;

[0058] 309: low-pass filter module;

[0059] 310: ADC module;

[0060] 320: signal;

[0061] 321: First signal;

[0062] 322: Second signal;

[0063] 323: The third signal;

[0064] 324: Fourth signal;

[0065] 325: Fifth signal;

[0066] 326: Sixth signal;

[0067] 327: Seventh signal;

[0068] 328: square wave signal;

[0069] 329: Eighth Signal;

[0070] 330: analog ADC sampling signal;

[0071] 401-418: Steps; and

[0072] 501~514: Steps. DETAILED DESCRIPTION

[0073] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. Note that the various aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention.

[0074] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0075] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood to refer to the orientations depicted in that section and the accompanying drawings. These relative terms are used solely for convenience of description and do not necessarily imply that the devices described herein must be manufactured or operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0076] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various components, regions, layers, and / or portions, these components, regions, layers, and / or portions should not be limited by these terms, and these terms are merely used to distinguish different components, regions, layers, and / or portions. Thus, a first component, region, layer, and / or portion discussed below may be referred to as a second component, region, layer, and / or portion without departing from some embodiments of the present invention.

[0077] As mentioned above, traditional HART communication solutions have significant limitations in multi-channel scenarios. Existing multi-modem solutions have high hardware costs and low resource utilization. Existing time-division multiplexing combined with software demodulation solutions, due to the shared wiring between HART signals and analog quantities, are prone to signal distortion during switching, leading to software demodulation errors and making it difficult to simultaneously handle multi-channel tasks and high-precision analog acquisition. Existing single-modem combined with multiplexer solutions lack intelligent scheduling mechanisms and cannot meet the real-time requirements of high-speed control scenarios. Furthermore, some existing technologies that replace specialized HART modem chips fail to consider the actual design difficulties and the effectiveness of their interoperability with the HART protocol stack, violating design principles such as reducing hardware complexity, PCB area, and cost.

[0078] In order to overcome the above-mentioned defects of the prior art, the present invention provides a multi-channel HART dynamic communication system, which can reduce hardware complexity, realize the status perception of each channel by extracting the timing characteristics of the HART signal through hardware demodulation, and ensure that there is no conflict between digital communication and analog quantity acquisition, thereby ensuring data integrity.

[0079] The multi-channel HART dynamic communication system may include a modulation circuit, a demodulation circuit, and a controller, wherein the controller may be an MCU (Micro Controller Unit).

[0080] The modulation circuit can use a single HART Modem to modulate the signal sent by the controller.

[0081] Each channel may be provided with a demodulation circuit, which may include a parallel hysteresis Schmitt trigger module and an analog quantity acquisition module.

[0082] The hysteresis Schmitt trigger module can be configured to separate the HART signal to obtain the FSK signal within it. Using the hysteresis Schmitt trigger, the FSK signal is converted into a digital pulse signal and output to the controller. The FSK signal carries the HART command, and the controller transmits the HART command by sending and receiving the FSK signal within the HART signal.

[0083] The hysteresis Schmitt trigger is a low-cost, low-power signal detection device that ensures accurate signal detection in complex electromagnetic environments and accurately extracts the signal's timing characteristics. The accuracy of timing feature extraction relies on the hysteresis voltage (±10mV) of the hysteresis Schmitt trigger to suppress noise interference.

[0084] In this way, the output signal of the demodulation circuit is combined with the real-time monitoring of the controller to determine the communication status of each channel (such as whether the signal is active or interrupted) to support the optimized operation of the multi-channel HART dynamic communication system, thereby realizing channel status perception.

[0085] For example, in one embodiment, after the hysteresis Schmitt trigger module converts the FSK signal in the HART signal into a digital pulse signal and outputs it to the controller, the controller can first identify the load condition of the channel by monitoring the level status of these signals. Secondly, the controller performs a preliminary analysis of the monitored level signal. In the HART protocol, communication uses more than 5 0xFF bytes as a preamble, which represents the start of the message. If the channel load detection is normal, but the preamble is incorrect, it is judged that the line is abnormal and the demodulated data is discarded. Channel status perception can provide basic data for subsequent dynamic adjustment of polling strategies and resource allocation.

[0086] In addition, the analog quantity acquisition module can be configured to receive the HART signal and separate the 4-20mA DC component in the HART signal, and convert the 4-20mA DC component into a digital signal and output it to the controller.

[0087] The following are some specific non-limiting preferred embodiments, based on which the multi-channel HART dynamic communication system proposed in the present invention and its technical effects are described in detail.

[0088] Please refer to Figure 1 , Figure 1 An architectural diagram of a multi-channel HART dynamic communication system provided according to some embodiments of the present invention is shown.

[0089] like Figure 1 As shown, Figure 1 The embodiment shown uses a 4-channel application as an example. The multi-channel HART dynamic communication system may include channel 101, which may include four channels: HART1, HART2, HART3, and HART4. Channel 101 may be used to send HART signals to an external device or receive HART signals returned by an external device.

[0090] Preferably, the multi-channel HART dynamic communication system may include an isolation transformer 102. The isolation transformer 102 may be used to isolate the electrical connection between the external device and the HART line, thereby protecting the HART circuit in the multi-channel HART dynamic communication system.

[0091] The multi-channel HART dynamic communication system may include a modulation circuit and a demodulation circuit. The modulation circuit may modulate the signal sent by the controller into a HART signal sent to an external device, and the demodulation circuit may demodulate the HART signal sent by the external device and send it to the controller.

[0092] The modulation circuit may include a HART modulation chip and an analog switch connected to the controller. The HART modulation chip is used to modulate the HART signal output by the controller and send the modulated HART signal to a designated channel through the analog switch.

[0093] In this preferred embodiment, the modulation circuit may include a HART modulation chip 104 , a HART signal line (Hart-Loop), and a double-pole four-throw analog bus switch 103 .

[0094] Specifically, the controller 110 can initiate a HART communication request and communicate with the HART modulation chip 104 through the UART interface. Then, the HART modulation chip 104 connected to the controller 110 can modulate the HART signal received by the serial port TX pin and send the modulated HART signal to the double-pole four-throw analog switch 103 through the HART signal line Hart-Loop. The double-pole four-throw analog switch 103 is connected to the HART modulation chip 104, and the isolation transformer 102 can also be connected to the double-pole four-throw analog switch 103. The double-pole four-throw analog switch 103 can switch channels so that the modulated HART signal (Hart-Loop+ and Hart-Loop-) is sent to a specified channel in the channel 101.

[0095] Based on the above modulation circuit, this preferred embodiment can realize the modulation and transmission of HART signals.

[0096] The demodulation circuit may include a parallel hysteresis Schmitt trigger module and an analog quantity acquisition module. The received HART signal may be decoded and conditioned by the demodulation circuit.

[0097] The hysteresis Schmitt trigger module may include a first signal conditioning unit 105 and a hysteresis Schmitt trigger 106 .

[0098] The hysteresis Schmitt trigger module separates the FSK signal from the HART signal through the first signal conditioning unit 105. Preferably, the first signal conditioning unit 105 may include a filtering module and a non-inverting amplifier for amplifying the signal.

[0099] After performing signal processing such as filtering and amplification on the signal, the first signal conditioning unit 105 outputs the separated FSK signal to the hysteresis Schmitt trigger 106 . The hysteresis Schmitt trigger 106 decodes the timing characteristics of the FSK signal to generate a digital pulse signal.

[0100] The analog acquisition module includes a second signal conditioning unit 107 and an ADC (Analog-to-Digital Converter) unit 108. The analog acquisition module separates the 4-20mA DC component in the HART signal through the second signal conditioning unit 107. Preferably, the second signal conditioning unit 107 may include a low-pass filter.

[0101] The second signal conditioning unit 107 can condition the 4-20mA DC current signal in the HART signal into a measurable analog signal and transmit the analog signal to the ADC unit 108. In this preferred embodiment, the ADC unit 108 can be a 4-channel ADC. The ADC unit 108 converts the conditioned analog signal into a digital signal.

[0102] In addition, in this preferred embodiment, a digital isolator 109 may be provided between the hysteresis Schmitt trigger 106 and the controller 110, and between the ADC unit 108 and the controller 110. The digital isolator 109 may be used to isolate digital signals from analog signals to prevent signal interference, and may transmit the digital pulse signal decoded by the hysteresis Schmitt trigger 106 and the digital signal conditioned by the ADC unit 108 back to the controller 110. Here, the digital signal conditioned by the ADC unit 108 is transmitted to the controller 110 via the IIC interface through the digital isolator 109.

[0103] Based on the above demodulation circuit, this preferred embodiment can achieve the reception, decoding, and conditioning of HART signals. Thus, the multi-channel HART dynamic communication system completes the modulation and transmission of HART signals through the modulation circuit, and completes the reception, decoding, and conditioning of HART signals through the demodulation circuit, and finally returns the HART signals to the controller to form a closed loop.

[0104] Further, to better illustrate the signal processing process of the demodulation circuit, please refer to Figure 2 , Figure 2 A flowchart of HART signal processing in a demodulation circuit provided by some embodiments of the present invention is shown.

[0105] like Figure 2 As shown, the signal processing process may include signal separation, decoding and conditioning.

[0106] The HART signal received by the demodulation circuit is shown in Figure 201. The HART signal may include a 4-20 mA DC component and an FSK signal (1200 Hz and 2200 Hz) superimposed on the DC component.

[0107] exist Figure 2In the illustrated embodiment, the received HART signal is distributed to the first signal conditioning unit 202 of the hysteresis Schmitt trigger module and the second signal conditioning unit 210 of the analog acquisition module.

[0108] The first signal conditioning unit 202 may include a filtering module and a unidirectional amplifier for amplifying the signal. The filtering module may be a high-pass filter that removes low-frequency DC signals from the HART signal, thereby retaining the 1200 Hz and 2200 Hz FSK signals shown in FIG203.

[0109] Preferably, Figure 2 In the illustrated embodiment, the FSK signal output by the first signal conditioning unit 202 as shown in FIG. 203 may also be superimposed on the reference voltage 204 to obtain a reference FSK signal as shown in FIG. 205 .

[0110] Next, the reference FSK signal, shown in FIG205, is input into a hysteresis Schmitt trigger 206. Based on the trigger value preset in the hysteresis Schmitt trigger 206, a hysteresis triggering process 207 generates a digital pulse signal representing the FSK signal, as shown in FIG208. The logical values ​​0 and 1 of the digital pulse signal correspond to the two frequencies of the FSK signal, respectively. The resulting digital pulse signal is processed by a pulse sequence scanning module 209 to decode the FSK signal.

[0111] At the same time, the second signal conditioning unit 210 may include a low-pass filter. The low-pass filter removes the high-frequency FSK signal, retaining the 4-20mA DC component, and generating a conditioned analog signal as shown in FIG211. As shown in FIG211, the analog signal represents the amplitude of the 4-20mA DC current. The analog signal is then input into the ADC sampling module 212, which converts the analog signal into a digital signal. The digital signal converted by the ADC sampling module 212 can be further processed by the controller.

[0112] In this embodiment, the HART signal is separated by the high-pass filter of the first signal conditioning unit 202 and the low-pass filter of the second signal conditioning unit 210 , providing a basis for dynamic demodulation of the multi-channel HART dynamic communication system.

[0113] Please refer to Figure 3 , Figure 3 A schematic diagram of a demodulation circuit provided by some embodiments of the present invention is shown.

[0114] like Figure 3As shown, the demodulation circuit can receive the input HART signal 320 through the differential amplifier module 301. The input HART signal 320 includes a 4-20mA DC component and an FSK signal, and the FSK signal includes a first frequency (corresponding to logic "1") and a second frequency (corresponding to logic "0").

[0115] The differential amplifier module 301 can collect the HART signal through the sampling resistor, then amplify the input HART signal, preliminarily adjust the amplitude of the FSK signal in the HART signal, and output the HART signal that retains the FKS signal and DC component, which is recorded as the first signal 321 here.

[0116] Afterwards, the first signal 321 is distributed to two parallel paths for processing. The first path first enters the hysteresis Schmitt trigger module.

[0117] In this embodiment, the hysteresis Schmitt trigger module may include a bandpass filtering module 302 , a first coupling unit 303 , a low-pass filter 304 , a second coupling unit 305 , a non-inverting amplifier 306 , a reference voltage coupling module 307 and a hysteresis comparison module 308 .

[0118] In the first path, the first signal 321 first enters the bandpass filtering module 302. The bandpass filtering module 302 may include a high-pass filtering unit and a low-pass filtering unit. The high-pass filtering unit filters out the low-frequency DC component in the first signal 321, and the low-pass filtering unit filters out the high-frequency noise in the first signal 321, thereby outputting a second signal 322.

[0119] Subsequently, the second signal 322 enters the first coupling unit 303 , and the DC bias in the second signal 322 is eliminated by the first coupling unit 303 to ensure that the signal fluctuates around zero voltage, thereby outputting a third signal 323 .

[0120] Then, the third signal 323 enters the low-pass filter 304 to further filter out high-frequency noise and output a fourth signal 324 . The signal-to-noise ratio of the fourth signal 324 is improved while retaining the main frequency components in the FSK signal.

[0121] Fourth signal 324 then passes through second coupling unit 305 to remove residual DC offset, ensuring signal purity, and outputs fifth signal 325. Fifth signal 325 enters non-inverting amplifier 306 for amplification, and outputs sixth signal 326. Output sixth signal 326 is amplified and still fluctuates around zero voltage, with its amplitude increased to a level suitable for subsequent demodulation.

[0122] Next, the sixth signal 326 enters the reference voltage coupling module 307 to obtain the seventh signal 327, which is then input into the hysteresis comparison module 308. The hysteresis comparison module 308 compares the seventh signal 327 with a preset threshold and a hysteresis voltage (±10 mV) and outputs a square wave signal 328, thereby completing the demodulation of the FSK signal.

[0123] By configuring an independent hysteresis Schmitt trigger for each HART channel, the FSK signal (1200Hz / 2200Hz sine wave) in the HART signal is converted into a square wave pulse sequence. At the same time, the hysteresis voltage (±10mV) effectively suppresses false triggering caused by noise, improving signal detection accuracy.

[0124] The controller scans the GPIO pin's level and further analyzes the timing characteristics of the square wave pulse sequence to distinguish the first and second frequencies in the FSK signal, thereby parsing the HART digital message. In this case, the first and second frequencies are 1200Hz and 2200Hz.

[0125] In the above parallel paths, the second path is an analog quantity acquisition module. In this embodiment, the analog quantity acquisition module may include a low-pass filter module 309 and an ADC module 310.

[0126] In the second path, the first signal 321 is directly sent to the low-pass filter module 309 (preferably with a cutoff frequency of 100 Hz) to filter out high-frequency components, retain the 4-20 mA DC component, suppress the HART high-frequency residual noise, and output the eighth signal 329. Subsequently, the ADC module 310 collects the eighth signal and outputs the analog ADC sampling signal 330, thereby achieving analog acquisition.

[0127] The simulation results show that Figure 3 The demodulation circuit shown can still stably demodulate the HART FSK signal in a complex noise environment. The output square wave signal logic level accurately corresponds to the first and second frequencies of the FSK signal. At the same time, the second channel can accurately extract the 4-20mA DC component, providing a reliable analog signal for subsequent data processing. Figure 3 The demodulation circuit shown has a reasonable overall structure, low hardware complexity, strong anti-noise capability, and no conflict between digital communication and analog quantity acquisition.

[0128] In some embodiments, Figure 3 The demodulation circuit shown can be applied to Figure 1In the architecture of the embodiment shown, based on the setting of the filters in each signal conditioning unit, as well as the isolation transformer 102 and the digital isolator 109, the multi-channel HART dynamic communication system can simultaneously suppress power frequency noise and channel switching transient interference, meeting the stringent requirements of the industrial environment for high reliability and anti-interference capabilities.

[0129] Furthermore, in the multi-channel HART dynamic communication system provided by the present invention, based on the channel status sensing implemented by the demodulation circuit, the controller can further dynamically schedule and process HART signals. The HART signals sent and received by the controller can carry HART commands via FSK signals. HART commands are digital information encoded according to the format and rules specified by the HART protocol. After parsing the HART message to obtain the HART command, the controller can perform corresponding operations based on the type and content of the HART command.

[0130] Traditional polling mechanisms use a fixed cycle to traverse all channels, making it difficult to dynamically respond to sudden communication demands. For example, during a burst of HART message transmission, analog acquisition may be blocked, resulting in the loss of critical data. Furthermore, traditional polling mechanisms use a uniform polling frequency for all commands, making it impossible to prioritize commands based on their importance. This prevents optimizing the response speed of key commands, such as primary variable polling. When a channel or command fails due to device malfunction or interference, the system cannot automatically adjust the polling strategy, potentially leading to wasted resources or interrupted data collection. Furthermore, when the polling cycle is long, traditional polling output or on-change output methods result in high latency in sending key commands, making it difficult to meet the real-time requirements of urgent parameter updates.

[0131] Therefore, the controller can be configured to adjust the polling method of HART commands based on the HART command priority queue, including the polling frequency and polling order. For example, the controller can adopt a HART polling command fast and slow scanning mechanism, that is, optimize the polling efficiency of HART commands by defining a fast and slow scanning strategy.

[0132] Specifically, the controller can maintain a preset HART command priority queue, in which HART commands can be divided into fast scan commands and slow scan commands by priority flags (fast / slow). Fast scan commands include high-priority commands such as primary variable polling (such as HART command 1, used to read the primary variable PV), and slow scan commands include low-priority commands such as device status query (such as HART command 0). In some embodiments, the controller can dynamically adjust the polling order according to the communication load and command type of the channel based on the dynamic adjustment mechanism, and increase the polling frequency of the fast scan command to 2 to 3 times that of the slow scan command. For example, the fast scan command is executed 3 times per polling cycle, while the slow scan command is executed once. In this way, for the fast scan command, the system prioritizes the allocation of communication time slots to ensure that its response delay is less than 1ms; for the slow scan command, it is executed in the gap between the fast scan commands to avoid resource competition.

[0133] Based on the HART polling command fast and slow scanning mechanism, users can customize the fast scanning command list and polling frequency to adapt to the needs of different industrial scenarios. This mechanism significantly improves the real-time collection of key data such as primary variables, thereby better meeting the real-time monitoring needs of key parameters in industrial control. For example, in Figure 1 In the 4-channel system shown, the polling frequency of the main variable of each channel is increased from 1 time in the traditional solution to 3 times, which effectively improves the real-time collection of key data.

[0134] Preferably, the controller can also employ an automatic degradation and recovery mechanism to optimize the aforementioned fast and slow scanning mechanism, improving its adaptability and enhancing the robustness of the multi-channel HART dynamic communication system. Based on the automatic degradation and recovery mechanism, the controller can be configured to adjust the priority of HART commands in the HART command priority queue and / or the polling method of HART commands based on the response status of the HART commands.

[0135] The controller can dynamically monitor the response status of HART commands. If a high-priority fast scan command (such as HART command 1) fails to receive a response three times in a row in fast scan mode, the controller can automatically downgrade it to a slow scan command and reduce its polling frequency (for example, from three times per second to one time per second) to reduce the use of communication resources. After that, the controller continues to monitor the response status of the downgraded HART command in slow scan mode. If the HART command resumes normal response in slow scan mode (for example, it responds successfully two times in a row), the controller automatically restores the HART command to a fast scan command, increasing its priority and polling frequency (for example, returning it to three times per second).

[0136] Specifically, the controller can maintain a priority flag (fast / slow) and a counter (number of unresponsive times / number of successful responses) for each HART command. When the unresponsive times counter reaches a preset threshold (for example, 3 times), the HART command is downgraded. After downgrading, if the successful response times counter reaches the recovery threshold (for example, 2 times), the HART command is recovered. The state switching process is completed through interrupt drive to ensure that the switching delay is less than 500μs.

[0137] This automatic degradation and recovery mechanism allows users to configure the number of automatic degradation and recovery times. This mechanism improves resource utilization by 30% in multi-channel HART dynamic communication systems in communication anomalies, effectively addressing device failures or communication interruptions while ensuring rapid response to critical commands after communication is restored.

[0138] Please refer to Figure 4 , Figure 4 A flowchart of HART polling according to some embodiments of the present invention is shown.

[0139] like Figure 4 As shown, the multi-channel HART dynamic communication system can start from step 401 and enter the running state. Step 402 is the HART command classification, which divides the HART command into fast scan commands and slow scan commands according to the user definition. Step 403 is the priority queue management, and the controller can initialize the status and priority of the HART command. Step 404 is the polling execution, and the controller executes the HART command polling according to the priority queue order. Step 405 determines whether the HART command responds. If there is no response, enter the "no" branch and determine whether the number of unresponsive times is greater than k through step 406, where k is the maximum number of unresponsive retries. If the number of unresponsive times is greater than k, enter the "yes" branch and, based on step 412, force the current command to be set to the short address of the current node to continue communication and wait for a response; if the number of unresponsive times is less than or equal to k, enter the "no" branch and determine whether all command polling is completed through step 417.

[0140] Accordingly, in step 405, if the HART command is responded to, the "Yes" branch is entered, and the long address of the response is used to communicate with the device in step 407. During the communication process using the long address in step 407, step 408 determines whether the HART command reply status is normal. Regardless of the judgment result, step 409 determines whether the current HART command is a fast command type before continuing with the subsequent process.

[0141] If the command reply status is normal in step 408 and the command is a fast command type in step 409, step 410 is entered to determine the number of consecutive normal times of the command reply status. When it is determined that the number of consecutive normal times is ≥ n, the "yes" branch is entered, and the HART command of the current fast command type is restored or maintained in fast scanning mode through step 413; when it is determined that the number of consecutive normal times is < n, the "no" branch is entered, and the command is downgraded to slow scanning mode through step 415.

[0142] It is understandable that in this embodiment, the type of HART command is fixed (fast command or slow command). When the HART command is a fast command type, it indicates a high priority and the default is the fast scan mode; during the polling scan process, the controller can adjust the scan mode corresponding to the HART command according to the response status.

[0143] If it is determined in step 408 that the command status is normal and in step 409 that the command is not a fast command, the process proceeds to step 414 to keep processing the current command at a slow speed.

[0144] If the command status is judged to be abnormal in step 408 and the command is judged to be a fast command in step 409, then step 411 is entered to judge the number of consecutive abnormal times of the command reply status. When it is judged that the number of consecutive abnormal times is ≥m, step 415 is entered to downgrade the current command to a slow scanning mode, thereby reducing its polling efficiency; when it is judged that the number of consecutive normal times is <m, step 416 is entered to maintain the fast scanning mode processing of the command.

[0145] If it is determined in step 408 that the command status is abnormal and in step 409 that the command is not a fast command, the process proceeds to step 414 to maintain the slow scan mode processing for the current command.

[0146] Then, step 417 determines whether the polling command has been completed. If so, the process proceeds to step 418 and ends. If not, the process returns to step 403 to update the latest priority management of the current command list and continue polling. This closed-loop process, based on the automatic degradation and recovery mechanism, enables the multi-channel HART dynamic communication system to have excellent dynamic adaptability and real-time optimization, ensuring the robustness of the multi-channel HART dynamic communication system in the event of device failure or communication interruption.

[0147] Those skilled in the art will understand that Figure 4 The embodiment shown is only a non-restrictive implementation method provided by the present invention, which is intended to clearly demonstrate the main concepts of the fast and slow polling mechanism and the automatic degradation and recovery mechanism in the present invention, and to provide some specific solutions that are convenient for the public to implement, rather than to limit all functions or all working modes of the fast and slow polling mechanism and the automatic degradation and recovery mechanism in the multi-channel HART dynamic communication system.

[0148] In addition, the controller can also be configured with a preemptive output function, that is, when the output condition is triggered, the preemption flag of the HART command is enabled, and the interrupt mechanism is used to adjust the polling order to give priority to polling the HART command.

[0149] The output functions of the multi-channel HART dynamic communication system can include output upon change, polling output, initialization output and no output. Among them, output upon change means writing data into the data mapping area when the data changes, and executing the output when the command is polled; polling output means outputting the commands in the data mapping area in sequence according to the polling order; initialization output means executing when the multi-channel HART dynamic communication system is started, and is used for device initialization; no output means not executing the output when the data has not changed or the command has not been triggered.

[0150] The preemptive output function is a further improvement on the on-change output function. When data changes, the controller not only writes the data to the data map area, but also immediately triggers polling for the HART command, giving priority to output operations without waiting for the regular polling cycle.

[0151] Specifically, the controller can set a preemption flag for each HART command. Users can specify commands that require preemptive output (such as emergency parameter update commands) and enable the preemption flag for commands that require preemptive output. When a data change triggers a change output condition, the controller can check the preemption flag of the command. If the flag is enabled, the interrupt mechanism immediately adjusts the polling order to prioritize polling for the command and send data. If the flag is not enabled, the controller follows the normal change output process.

[0152] The preemptive output function significantly reduces the transmission delay of key commands and increases the transmission priority of key commands. It is suitable for the high real-time requirements of urgent parameter updates (such as valve control parameters) in industrial control, thereby further optimizing the output mechanism of HART commands and improving the real-time performance of multi-channel HART dynamic communication systems.

[0153] Please refer to Figure 5 , Figure 5 A flowchart of a preemptive output function provided according to some embodiments of the present invention is shown.

[0154] like Figure 5 As shown, the multi-channel HART dynamic communication system can start from step 501 and enter the operating state. Step 502 is to monitor data changes. At step 502, data changes in the data mapping area are monitored in real time. Then, step 503 determines whether the data has changed. If the data has changed, the "yes" branch is taken to step 504, and the data is written to the data mapping area. If the data has not changed, the "no" branch is taken.

[0155] In step 504, the controller can write the changed data to the data mapping area. Then, in step 505, it determines whether the command is a preemptive output command. If so, it proceeds to step 506 to perform an immediate polling operation, and in step 508, it performs the command output operation, such as sending data to the device. If not, it proceeds to step 507 to wait for polling, waiting for the command to be executed according to the normal polling sequence, and then performs post-output processing in step 509. The controller can then record the output results and determine whether the output is successful in step 510. If successful, it enters the "yes" branch and records the success status in step 512. If unsuccessful, it enters the "no" branch and records the failure status in step 511. The output failure status and success status recorded in steps 511 and 512 can be used for subsequent status management analysis.

[0156] Finally, step 513 is used to determine whether all commands have been processed. If not, the process returns to step 502 to continue monitoring data changes. If they have been processed, the process ends at step 514. This process is closed-loop. Figure 5 This can reflect the improvement of the priority mechanism by the preemptive output function and the real-time optimization of dynamic scheduling.

[0157] Those skilled in the art will understand that Figure 5 The embodiment shown is only a non-restrictive implementation method provided by the present invention, which is intended to clearly demonstrate the main concept of the preemptive output function in the present invention and provide some specific solutions that are convenient for the public to implement, rather than to limit all functions or all working modes of the preemptive output function in the multi-channel HART dynamic communication system.

[0158] In this way, the multi-channel HART dynamic communication system can optimize the communication of the HART application layer protocol through the collaboration of fast and slow scanning mechanisms, automatic degradation and recovery mechanisms, and preemptive output functions, thereby maximizing the communication efficiency of key variables while maintaining a low-cost design of single-modem multi-channel multiplexing.

[0159] In addition, in some embodiments, the multi-channel HART dynamic communication system provided by the present invention can also be provided with a lightweight management and configuration interface to realize multi-channel configuration and status monitoring. The lightweight management and configuration interface displays the communication status of each channel, the real-time value of the analog quantity, and the fault alarm information through a graphical user interface (GUI), and can be used to support the user to manually configure the channel priority, adjust the sampling frequency (1Hz-1kHz), set the filter parameters, etc. The lightweight management and configuration interface can integrate the PROFINET protocol, adapt to the Industrial Internet of Things (IIoT) scenario, support remote monitoring and data export of the host computer, thereby meeting diverse industrial needs.

[0160] The multi-channel HART dynamic communication system provided by the present invention can use a single modem combined with a hysteresis Schmitt trigger to replace the traditional multi-modem architecture, reducing hardware costs by 60%. The use of the hysteresis Schmitt trigger can avoid the introduction of a negative power supply, simplifying the hardware design and reducing the PCB area by 50%. Combined with fast and slow scanning and an automatic degradation recovery mechanism, the multi-channel polling efficiency is doubled, and the analog sampling error is less than 0.05% (in the case of a 16-bit ADC). The dual isolation design (isolation transformer and digital isolator) combined with the hysteresis Schmitt trigger enables the multi-channel HART dynamic communication system to operate stably in an industrial noise environment with a bit error rate less than 0.05%. In addition, the multi-channel HART dynamic communication system can support channel expansion and adapt to the high-density equipment interconnection requirements of industrial sites, comprehensively improving the economy, real-time performance and reliability of the multi-channel HART dynamic communication system.

[0161] In summary, the multi-channel HART dynamic communication system provided by the present invention can synchronously demodulate the 4-20mA signal and the FSK signal of the HART signal, ensuring the independence of analog quantity acquisition and FSK signal demodulation, and avoiding the conflict between the two; reducing hardware complexity, and realizing the status perception of each channel by extracting the timing characteristics of the HART signal while hardware demodulation.

[0162] Although the above methods are illustrated and described as a series of acts for simplicity of explanation, it is to be understood and appreciated that these methods are not limited by the order of the acts, as some acts may occur in a different order and / or concurrently with other acts from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art according to one or more embodiments.

[0163] Those skilled in the art will appreciate that information, signals, and data may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips cited throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0164] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0165] Although the controller described in the above embodiments can be implemented through a combination of software and hardware, it is understood that the controller can also be implemented in software or hardware. For hardware implementation, the controller can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic devices for performing the functions described above, or a selected combination of the above devices. For software implementation, the controller can be implemented through independent software modules such as procedures and functions running on a general-purpose chip, where each module performs one or more functions and operations described herein.

[0166] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-channel HART dynamic communication system, comprising a modulation circuit and a demodulation circuit, characterized in that: The demodulation circuit of each channel includes a parallel hysteresis Schmitt trigger module and an analog acquisition module, wherein: The hysteresis Schmitt trigger module is configured to separate the HART signal to obtain an FSK signal in the HART signal, and convert the FSK signal into a digital pulse signal through the hysteresis Schmitt trigger and output it to the controller, wherein the logic level of the digital pulse signal corresponds to the first frequency and the second frequency of the FSK signal; and The analog quantity acquisition module is configured to separate the HART signal to obtain a 4-20mA DC component in the HART signal, and convert the 4-20mA DC component into a digital signal and output it to the controller.

2. The multi-channel HART dynamic communication system according to claim 1, wherein: The hysteresis Schmitt trigger module includes a first signal conditioning unit, and the FSK signal in the HART signal is separated by the first signal conditioning unit. The first signal conditioning unit includes a filtering module and a non-inverting amplifier for amplifying the signal.

3. The multi-channel HART dynamic communication system according to claim 1, wherein: The analog quantity acquisition module includes a second signal conditioning unit, which is used to separate the 4-20mA DC component in the HART signal. The second signal conditioning unit includes a low-pass filter.

4. The multi-channel HART dynamic communication system according to claim 1, wherein: The demodulation circuit collects the HART signal through a differential amplifier unit and amplifies the HART signal.

5. The multi-channel HART dynamic communication system according to claim 1, wherein: A digital isolator is provided between the hysteresis Schmitt trigger module and the controller, and between the analog quantity acquisition module and the controller.

6. The multi-channel HART dynamic communication system according to claim 5, characterized in that: Also included is an isolation transformer for isolating external equipment.

7. The multi-channel HART dynamic communication system according to claim 1, wherein: The modulation circuit includes a HART modulation chip and an analog switch connected to the controller. The modulation circuit is configured to modulate the HART signal output by the controller through the HART modulation chip, and send the modulated HART signal to a designated channel through the analog switch.

8. The multi-channel HART dynamic communication system according to claim 1, wherein: The controller is configured to adjust a polling mode of HART commands according to a HART command priority queue.

9. The multi-channel HART dynamic communication system according to claim 8, characterized in that: The controller is further configured to adjust a priority of the HART command in the HART command priority queue and / or a polling mode of the HART command based on a response status of the HART command.

10. The multi-channel HART dynamic communication system according to any one of claims 8 or 9, characterized in that: The controller is further configured to, in response to the enabling of the preemption flag of the HART command when the output condition is triggered, use an interrupt mechanism to adjust the polling order to give priority to polling the HART command.

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