BC battery suede optimization process

Abstract

The invention discloses a BC battery suede optimization process. The BC battery suede optimization process comprises the following steps: sequentially performing texturing and pre-cleaning on a silicon wafer; putting the pre-cleaned silicon wafer into a first mixed acid solution for primary acid pickling; the first mixed acid liquor is an aqueous solution composed of an oxidizing agent, hydrochloric acid and hydrofluoric acid; cleaning the silicon wafer after the primary acid pickling, and putting the silicon wafer into a second mixed acid solution for secondary acid pickling; the second acid liquor is an aqueous solution composed of hydrochloric acid and hydrofluoric acid; and cleaning the silicon wafer subjected to secondary acid pickling. Aiming at the problem of silicon wafer surface treatment residues in the texturing process, the invention provides an optimized process, so that the regional oxide layer and B / PSG treatment on the back surface of the silicon wafer are more thorough in the texturing process, and meanwhile, the specific surface area of the textured surface on the front surface of the silicon wafer is further increased, so that the deposition of aluminum oxide in the subsequent process is more facilitated, and the good efficiency of a battery is improved.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, in particular to a BC cell velvet surface optimization process. Background Art

[0002] To increase the power generation capacity of photovoltaic cells, cost reduction and efficiency improvement are the two main themes of photovoltaic manufacturing. Currently, the mainstream photovoltaic cells are crystalline silicon solar cells. The BC structure successfully solves the problem of shading by the grid lines on the front of the cell, improves the area utilization rate, and greatly enhances the appearance, efficiency and practical value of the photovoltaic cell. The TBC structure cell superimposed with TOPCon technology has become one of the most promising new high-efficiency cell technologies due to its good compatibility with the traditional PERC cell production line and its obvious efficiency gain.

[0003] In the TBC process, the wet process texturing process (medium) follows the following steps: pre-clean (H2O2+NaOH) - water rinse (DI) - texturing (ADD+NaOH) - post-clean (H2O2+NaOH) - water rinse (DI) - pickling (HF+HCl) - slow pull (DI) - drying (CDA gas). The pickling tank removes the tunneling oxide layer and B / PSG from the exposed backside area after the patterning process. However, in actual production, relying solely on a single pickling tank makes it difficult to completely remove the oxide layer and B / PSG from the backside of the silicon wafer, resulting in low cell efficiency. To address the problem of surface treatment residue on the silicon wafer during the texturing process, an optimized process was developed to more thoroughly treat the oxide layer and B / PSG from the backside of the silicon wafer during the texturing process. This also further increases the surface area of ​​the textured surface on the front side of the silicon wafer, further facilitating the deposition of aluminum oxide in subsequent steps, thereby improving cell efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a BC battery texturing optimization process. Aiming at the problem of silicon wafer surface treatment residues in the texturing process, an optimization process is provided, so that the regional oxide layer and B / PSG on the back of the silicon wafer can be treated more thoroughly in the texturing process, and at the same time, the texturing specific surface area on the front of the silicon wafer can be further improved, which is more conducive to the deposition of aluminum oxide in the subsequent process, thereby improving the efficiency of the battery.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention discloses a BC battery texture optimization process, comprising the following steps:

[0007] S1, texturing and pre-cleaning the silicon wafer in sequence;

[0008] S2, placing the pre-cleaned silicon wafer into a first mixed acid solution for pickling; the first mixed acid solution is an aqueous solution composed of an oxidant, hydrochloric acid, and hydrofluoric acid;

[0009] S3, cleaning the silicon wafer after the primary pickling, and placing it in a second mixed acid solution for secondary pickling; the second mixed acid solution is an aqueous solution composed of hydrochloric acid and hydrofluoric acid;

[0010] S4. Cleaning the silicon wafer after the second pickling.

[0011] As a further solution of the present invention: in step S2, the mass concentration of the oxidant in the first mixed acid solution is 40-60 PPM, the mass concentration of hydrochloric acid is 0.05%-0.5%, and the mass concentration of hydrofluoric acid is 1%-2%.

[0012] As a further solution of the present invention: in step S2, the temperature of the first pickling is room temperature, and the pickling time is 200-400s.

[0013] As a further solution of the present invention: in step S3, in the second mixed acid solution, the mass concentration of hydrochloric acid is 0.05%-0.5%, and the mass concentration of hydrofluoric acid is 1%-2%.

[0014] As a further solution of the present invention: in step S3, the temperature of the secondary pickling is room temperature, and the pickling time is 200-400s.

[0015] As a further solution of the present invention: the time of the first pickling is not shorter than the time of the second pickling.

[0016] As a further embodiment of the present invention: the oxidant is ozone.

[0017] In a second aspect, the present invention discloses a preparation process for a BC battery, which includes the above-mentioned BC battery velvet optimization process.

[0018] In a third aspect, the present invention discloses a BC battery, which is prepared by the above-mentioned preparation process.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The single pickling process of the present invention dynamically regulates the synergistic reaction of the mixed acid and the oxidant, and in the process of controllable corrosion tunneling through the oxide layer and the doped glass layer, synchronously induces the longitudinal extension and lateral refinement of the velvet pyramid structure, forming a denser and more uniform three-dimensional nanotexture. The increased velvet specific surface area not only provides a higher active site density for the atomic layer deposition (ALD) passivation film, but also improves the effective absorption path of the incident light by enhancing the light capture effect. Although extending the pickling time can further reduce the concentration of metal impurities, it is necessary to balance the corrosion rate and structural integrity to avoid excessive etching that causes the top of the pyramid to collapse or subsurface damage, thereby maintaining the stability of high-efficiency devices.

[0021] The secondary pickling in the present invention uses a gradient etching strategy to preferentially remove residual contaminants and weak oxidation areas on the surface of the pyramid, while reshaping the micromorphology of the velvet surface to form a smooth transition passivation-friendly interface. This process not only deeply strips off the adsorption layer of heavy metal ions, but also reduces the density of surface microcracks and sharp defects through selective corrosion, effectively alleviating the risk of localized carrier recombination. The optimized surface chemical state and the energy band matching degree of the subsequent passivation layer are significantly improved, reducing the obstruction of the interface barrier to carrier transport, which is manifested as a higher open circuit voltage and fill factor on a macro scale. The timing coordination of the two picklings not only ensures the thoroughness of cleaning, but also avoids the limitations of a single process, ultimately promoting an overall leap in battery efficiency without the risk of photodegradation. DETAILED DESCRIPTION

[0022] To facilitate understanding of the present invention, the present invention will be described more fully below in conjunction with specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0024] Example 1

[0025] Cleaning: Pre-clean a 182*182mm, 130μm thick silicon wafer by immersing it in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafer is then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0026] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide and 35wt.% hydrogen peroxide in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed in a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0027] Acid wash: The first pickling step uses a mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, infused with 60ppm ozone, at 25°C for 300 seconds. This treatment continuously oxidizes and etches the tunneling oxide layer, B / PSG, and front textured surface in the exposed areas of the front and back surfaces after the laser secondary treatment. The wafer is then rinsed in a 25°C pure water tank for 120 seconds to remove any residual chemical residue. The second pickling step uses a second mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, at 25°C for 260 seconds. This treatment passivates the textured surface and further removes any residual heavy metal ions.

[0028] Post-processing: The silicon wafer is then washed in a 25°C pure water tank for 120 seconds to clean the residual liquid on the surface of the silicon wafer, then passed through a 60°C slow pull tank for 80 seconds, and finally dried at 98°C for 700 seconds.

[0029] Example 2

[0030] Cleaning: Pre-clean 182 x 182 mm, 130 μm thick silicon wafers by immersing them in a mixture of 45 wt.% sodium hydroxide solution and 35 wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafers are then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0031] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed in a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0032] Acid wash: The first pickling step uses a mixed acid solution of 49wt.% HF and 37wt.% HCl in a volume ratio of 1:1.5, then injects 50ppm ozone. Treatment is performed at 25°C for 280 seconds. This continuously oxidizes and corrodes the front and back surfaces of the wafer, exposing the exposed areas after the laser secondary treatment, through the tunneling oxide layer, B / PSG, and front textured surface. The wafer is then rinsed in a 25°C pure water tank for 120 seconds to remove any residual chemical residue. The second pickling step uses a mixed acid solution of 49wt.% HF and 37wt.% HCl in a volume ratio of 1:1.5, at 25°C for 260 seconds. This passivates the textured surface of the front surface and further removes any residual heavy metal ions.

[0033] Post-processing: The silicon wafer is cleaned in a 25℃ pure water tank for 120 seconds to clean the residual liquid on the surface of the silicon wafer, then passed through a 60℃ slow pull tank for 80 seconds, and finally dried at 98℃ for 700 seconds.

[0034] Example 3

[0035] Cleaning: Pre-clean 182 x 182 mm, 130 μm thick silicon wafers by immersing them in a mixture of 45 wt.% sodium hydroxide solution and 35 wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafers are then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0036] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0037] Acid wash: The first pickling step uses a mixed acid solution of 49wt.% HF and 37wt.% HCl in a volume ratio of 1:1.5, then infused with 40ppm ozone. Treatment is performed at 25°C for 270 seconds. This mixture continuously oxidizes and etches the front and back surfaces of the wafer, exposing the laser secondary treatment to the tunneling oxide layer, B / PSG, and front textured surface. The wafer is then rinsed in a 25°C pure water tank for 120 seconds to remove any residual chemical residue. A second pickling step uses a mixed acid solution of 49wt.% HF and 37wt.% HCl in a volume ratio of 1:1.5, also at 25°C for 270 seconds. This passivates the textured surface of the front surface and further removes any residual heavy metal ions.

[0038] Post-processing: The silicon wafer is cleaned in a 25℃ pure water tank for 120 seconds to clean the surface liquid residue, then slowly pulled in a 60℃ pulling tank for 80 seconds, and finally dried at 98℃ for 700 seconds.

[0039] Comparative Example 1

[0040] Cleaning: Pre-clean a 182*182mm, 130μm thick silicon wafer by immersing it in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafer is then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0041] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide and 35wt.% hydrogen peroxide in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed in a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0042] Acid pickling: A mixed acid solution consisting of 49wt.% HF solution and 37wt.% HCl solution in a volume ratio of 1:1.5 was used at 25°C for 540 seconds to passivate the velvet surface on the front side of the silicon wafer and remove residual heavy metal ions on the silicon wafer surface.

[0043] Post-processing: The silicon wafer is then washed in a 25°C pure water tank for 120 seconds to clean the residual liquid on the surface of the silicon wafer, then passed through a 60°C slow pull tank for 80 seconds, and finally dried at 98°C for 700 seconds.

[0044] Comparative Example 2

[0045] Cleaning: Pre-clean a 182*182mm, 130μm thick silicon wafer by immersing it in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafer is then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0046] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide and 35wt.% hydrogen peroxide in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed in a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0047] Acid wash: The first pickling step uses a mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, infused with 50ppm ozone, at 25°C for 380 seconds. This treatment continuously oxidizes and etches the tunneling oxide layer, B / PSG, and front textured surface in the exposed areas of the front and back surfaces after the laser secondary treatment. The wafer is then rinsed in a 25°C pure water tank for 120 seconds to remove any residual chemical residue. The second pickling step uses a second mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, at 25°C for 310 seconds. This treatment passivates the textured surface and further removes any residual heavy metal ions.

[0048] Post-processing: The silicon wafer is then washed in a 25°C pure water tank for 120 seconds to clean the residual liquid on the surface of the silicon wafer, then passed through a 60°C slow pull tank for 80 seconds, and finally dried at 98°C for 700 seconds.

[0049] Comparative Example 3

[0050] Cleaning: Pre-clean a 182*182mm, 130μm thick silicon wafer by immersing it in a mixture of 45wt.% sodium hydroxide solution and 35wt.% hydrogen peroxide solution in a volume ratio of 1:5 at 65°C for 150 seconds to remove organic matter from the wafer surface. The wafer is then rinsed in a sink of pure water at 25°C for 90 seconds to remove any residual chemical residue from the wafer surface.

[0051] Texturing: The silicon wafer enters the texturing tank. The texturing liquid is a mixture of 45wt.% sodium hydroxide solution and Shichuang TS56V35 additive in a volume ratio of 5:2. It reacts at 82℃ for 420 seconds, then passes through a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer. The surface of the silicon wafer is then pre-cleaned and immersed in a mixture of 45wt.% sodium hydroxide and 35wt.% hydrogen peroxide in a volume ratio of 1:5. It is treated at 65℃ for 150 seconds to remove organic matter on the surface of the silicon wafer; then it is rinsed in a water tank with 25℃ pure water for 90 seconds to clean the residual liquid on the surface of the silicon wafer.

[0052] Acid wash: The first pickling step uses a mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, infused with 40ppm ozone, at 25°C for 340 seconds. This treatment continuously oxidizes and etches the tunneling oxide layer, B / PSG, and front textured surface in the exposed areas of the front and back surfaces after the laser secondary treatment. The wafer is then rinsed in a 25°C pure water tank for 120 seconds to remove any residual chemical residue. The second pickling step uses a second mixed acid solution consisting of a 1:1.5 volume ratio of 49wt.% HF solution and a 37wt.% HCl solution, at 25°C for 260 seconds. This treatment passivates the textured surface and further removes any residual heavy metal ions.

[0053] Post-processing: The silicon wafer is then washed in a 25°C pure water tank for 120 seconds to clean the residual liquid on the surface of the silicon wafer, then passed through a 60°C slow pull tank for 80 seconds, and finally dried at 98°C for 700 seconds.

[0054] Test Case

[0055] The Zeta3D microscope was used to test the velvet morphology of the battery obtained in the embodiment and the comparative example respectively. The eyepiece was selected at 100 times, the focusing range was 200-500um, and the test silicon wafer size was 182mm*182mm (N-type battery). The test results are shown in Table 1. The heavy metal and alkali metal content on the back of the silicon wafer (N-type, 182mm*182mm) was measured by atomic absorption spectroscopy (AAS). The measurement results are shown in Table 2. The photoelectric conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, fill factor FF, series resistance Rs, and parallel resistance Rsh of the motor were tested using a halm tester. The test results are shown in Table 3. The spectrum adopts AM1.5A and the light intensity is 1000W / m 2 , room temperature 25℃, spectral test range 400-1100nm. Test silicon wafer size 182mm*182mm (N-type cell).

[0056] Table 1 Silicon wafer front texture morphology data

[0057]

[0058]

[0059] As can be seen from Table 1, in Examples 1-3 and Comparative Examples 2-3, as the ozone concentration and the time of the first pickling step increase, the velvet size and specific surface area of ​​the front side of the prepared silicon wafer are larger, showing higher values ​​(the pickling time for Examples 3, 2, and 1 is 270 seconds, 280 seconds, and 300 seconds, respectively, and the velvet sizes are 1.561, 1.581, and 1.629, respectively, and the specific surface areas are 1.270, 1.283, and 1.320, respectively; the pickling time for Comparative Examples 2 and 3 is 340 seconds and 380 seconds, respectively, and the velvet sizes are 1.601 and 1.651, respectively, and the specific surface areas are 1.324 and 1.342, respectively). The larger velvet size and specific surface area of ​​the embodiments provide higher conditions for aluminum oxide deposition in the subsequent ALD process, improve the passivation performance, and thus improve the opening voltage and filling electrical properties.

[0060] Table 2

[0061] type Heavy metal concentration (ppb) Total pickling time (seconds) Example 1 12 560 Example 2 29 540 Example 3 31 540 Comparative Example 1 30 540 Comparative Example 2 8 690 Comparative Example 3 10 600

[0062] It can be seen from Table 2 that, compared with the comparative example, the heavy metal ion concentration on the silicon wafer surface gradually decreases with the increase of the total pickling time in the embodiment.

[0063] Table 3

[0064]

[0065]

[0066] As can be seen from Table 3, compared with Example 2 and Example 3, the silicon wafer prepared in Example 1 shows high filling and high opening pressure as a whole, and the efficiency performance is more outstanding (the efficiency is 26.742%, 26.751%, and 26.766% respectively). Compared with the efficiency of the comparative example, it is 0.03% higher as a whole. Corresponding to the high opening pressure of the theoretical large velvet surface, the silicon wafer also has a greater efficiency Eta gain than the comparative example. Compared with Comparative Example 1, Comparative Example 2, and Comparative Example 3, Comparative Example 1 has the lowest efficiency because there is no ozone involved. Compared with Examples 1 and 2, Comparative Examples 2 and 3, the greater the time difference between the two pickling times (the time difference between Comparative Examples 1 and 2 is 70 and 80 respectively, and the time difference between the embodiment is 40 and 20 respectively), the longer the time difference between the two pickling times of the silicon wafer surface is, the lower the efficiency is due to the excessive corrosion time.

[0067] Although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0068] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent modifications made according to the scope of the claims of the present application are within the scope of protection of the claims of the present application.

Claims

1. A BC battery texture optimization process, characterized in that: The following steps are involved: S1, texturing and pre-cleaning the silicon wafer in sequence; S2, placing the pre-cleaned silicon wafer into a first mixed acid solution for pickling; the first mixed acid solution is an aqueous solution composed of an oxidant, hydrochloric acid, and hydrofluoric acid; S3, cleaning the silicon wafer after the primary pickling, and placing it in a second mixed acid solution for secondary pickling; the second mixed acid solution is an aqueous solution composed of hydrochloric acid and hydrofluoric acid; S4. Cleaning the silicon wafer after the second pickling.

2. The BC battery texture optimization process according to claim 1, characterized in that: In step S2, the mass concentration of the oxidant in the first mixed acid solution is 40-60 PPM, the mass concentration of hydrochloric acid is 0.05%-0.5%, and the mass concentration of hydrofluoric acid is 1%-2%.

3. The BC battery texture optimization process according to claim 1, characterized in that: In step S2, the temperature of the first pickling is room temperature, and the pickling time is 200-400s.

4. The BC battery texture optimization process according to claim 1, characterized in that: In step S3, in the second mixed acid solution, the mass concentration of hydrochloric acid is 0.05%-0.5%, and the mass concentration of hydrofluoric acid is 1%-2%.

5. The BC battery texture optimization process according to claim 1, characterized in that: In step S3, the temperature of the secondary pickling is room temperature, and the pickling time is 200-400s.

6. The BC battery texture optimization process according to claim 1, characterized in that: The time of the first pickling should not be shorter than that of the second pickling.

7. The BC battery texture optimization process according to claim 1, characterized in that: The oxidant is ozone.

8. A BC battery preparation process, comprising the BC battery velvet optimization process according to any one of claims 1 to 7.

9. A BC battery prepared by the preparation process according to claim 8.

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