Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a memory management method and a memory controller for managing physical blocks in poor health. Background Art

[0002] Solid-state drives (SSDs), as a primary storage device, have a lifespan limited by the limited number of erase cycles of NAND flash memory devices. When a flash block reaches its erase cycle threshold, its probability of failure increases due to its Error Probability Rate (EPR), resulting in reduced device reliability. Traditional storage management methods often recommend discontinuing devices after they reach their expected lifespan to prevent data loss. This leads to premature retirement of storage devices and waste of resources.

[0003] Existing technologies lack effective mechanisms for maintaining secure use of storage devices during their aging phase, particularly methods for dynamically adjusting data protection policies based on device health. Furthermore, existing RAID protection schemes are mostly static configurations, unable to dynamically adjust based on the device's actual condition, and unable to achieve a flexible balance between capacity requirements and data security. Summary of the Invention

[0004] In view of this, the present disclosure provides a memory management method and a memory controller, which provide additional data protection for the aging stage of the storage device through an enhanced block mapping method linked to the health status of the physical block, maintain the data reliability of the storage device, and achieve a dynamic balance between capacity requirements and data security.

[0005] The present disclosure provides a memory management method, which is applied to a storage device configured with a memory module. The method comprises: evaluating the health status of multiple virtual blocks of the memory module; selecting one or more target virtual blocks from the multiple virtual blocks based on the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than the health status of other virtual blocks; performing an enhancement block mapping operation on each target virtual block, pairing multiple physical blocks within the target virtual block in pairs, and mapping the two physical blocks in each pair into an enhancement block; when writing target data to the target enhancement block, writing the target data in parallel to a first physical block and a second physical block of the target enhancement block; and when reading the target data from the target enhancement block, selecting one of the first physical block or the second physical block to read the target data according to a preset read strategy.

[0006] The present disclosure also provides a memory controller for controlling a storage device configured with a memory module. The memory controller includes a memory interface control circuit for electrically connecting to the memory module, and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device for electrically connecting to a host system. The processor is configured to execute the aforementioned memory management method.

[0007] Based on the above, the memory management method and memory controller provided by the present disclosure can achieve accurate monitoring and predictive maintenance of the memory module status by obtaining error bit statistics and evaluating the health status of virtual blocks. By selecting a target virtual block with poor health to perform an enhanced block mapping operation, the enhanced block mechanism is used to provide additional protection for high-risk physical blocks, thereby maintaining data reliability. The design of pairing the physical blocks within the target virtual block in pairs and mapping them to enhanced blocks implements a mirror backup mechanism. When any physical block fails, data can be recovered from another physical block, thereby improving data reliability. In addition, the parallel write mechanism ensures data synchronization and utilizes the parallel characteristics of different chips or planes to improve write performance. The preset read strategy effectively disperses the read pressure through the rotation reading mechanism, prevents a single physical block from generating read interference due to excessive reading, and extends the service life of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0009] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0010] Figure 3 Schematic diagram of a virtual block structure according to an embodiment of the present disclosure;

[0011] Figure 4 FIG1 is a schematic diagram of cross-chip enhancement block pairing according to an embodiment of the present disclosure;

[0012] Figure 5 1 is a schematic diagram of cross-chip and cross-plane enhancement block pairing according to an embodiment of the present disclosure;

[0013] Figure 6 1 is a schematic diagram showing pairing of same-chip enhancement blocks according to an embodiment of the present disclosure;

[0014] Figure 7 1 is a schematic diagram of a flow chart of a round-robin reading strategy according to an embodiment of the present disclosure;

[0015] Figure 8FIG. 1 is a schematic diagram of an enhanced block mapping table and corresponding access operations according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 FIG is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120 (also referred to as a host memory), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0018] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0019] In this embodiment, memory module 220 is a NAND Flash memory module, comprising multiple virtual blocks. Each virtual block has multiple physical blocks belonging to multiple planes of multiple chips. As the flash memory module ages, the number of erases per physical block gradually increases. Once the number reaches a certain threshold, the error rate rises, affecting data reliability. The memory management method proposed in this disclosure uses dynamic enhanced block mapping technology to provide additional data protection for virtual blocks in poor health, thereby extending the lifespan of the storage device.

[0020] In this embodiment, the host system 10 is electrically connected to the storage device 20 via the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0021] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless method. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), etc., based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a display, and a speaker via the system bus.

[0022] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0023] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0024] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like. However, it should be understood that the present disclosure is not limited thereto, and the host memory 120 may also be other suitable memories.

[0025] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading, and erasing data in the memory module 220 according to instructions from the host system 10 .

[0026] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities that controls the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control instructions / program codes, and when the storage device 20 is operating, these control instructions / program codes are executed to perform operations such as writing, reading, and erasing data. Furthermore, the processor 211 is configured to execute the memory management method provided herein.

[0027] In other embodiments, the control instructions / program codes corresponding to the data reading method may be further implemented as a circuit unit in the form of hardware to realize the memory management method provided by the present disclosure.

[0028] It is worth mentioning that in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0029] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered as operations performed by the memory controller 210.

[0030] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is configured to receive instructions from the processor 211 to transmit data. For example, the data management circuit 212 reads data from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213 (e.g., performing corresponding write operations based on various write instructions from the host system 10). For another example, the data management circuit 212 performs a read operation based on a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 (the data may be read from one or more storage cells in the one or more physical units) via the memory interface control circuit 213, and writes the read data to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230. In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0031] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also known as programming) operation, a read operation, or an erase operation on the memory module 220 .

[0032] In addition, the data to be written to the memory module 220 will be converted into a format acceptable to the memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and corresponding instruction sequences for instructing various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0033] In addition, the memory controller 210 establishes a mapping table to record the mapping information between logical addresses and physical addresses. In traditional memory management, the memory controller typically establishes a logical to physical address mapping table and a physical to logical address mapping table, which are used to find the physical unit (e.g., physical erase unit / physical block, physical page) mapped to the logical unit (e.g., logical block, logical page), and to find the logical unit mapped to the physical unit. In addition, the physical to logical mapping table can also be used to quickly determine valid data and invalid data in a specific physical block.

[0034] In the present disclosure, the memory controller 210 further establishes an enhancement block mapping table to record the mapping relationship between each enhancement block and the first and second physical blocks paired with the enhancement block, and simultaneously records the mapping relationship between the host logical address and the corresponding enhancement block identifier in the logical-to-physical mapping table. In addition, in one embodiment, the enhancement block mapping table may also record the priority read identifier corresponding to each enhancement block, the priority read identifier being used to indicate whether the target read physical block selected for priority reading from the target enhancement block is the first physical block or the second physical block.

[0035] The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10 , data from the memory module 220 , and various system data for managing the storage device 20 .

[0036] In this embodiment, the buffer memory 214 is configured to provide the required cache resources and system data (such as a logical-to-physical mapping table, a physical-to-logical mapping table, and an enhanced block mapping table, etc.) when the processor 211 executes the memory management method of the present disclosure. Specifically, the processor 211 is configured to execute the memory management method of the present disclosure, including obtaining multiple virtual blocks of the memory module 220 and error bit statistics corresponding to each virtual block, evaluating the health status of each virtual block based on the error bit statistics, and selecting a target virtual block with poor health to perform an enhanced block mapping operation. The processor 211 is also configured to maintain an enhanced block mapping table, record the mapping relationship between the enhanced block and the paired physical block, and implement a rotating read mechanism according to a preset read strategy to prevent read interference.

[0037] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0038] Specifically, memory module 220 includes multiple chips, each of which is further subdivided into multiple planes, each of which contains multiple physical blocks. Furthermore, each physical block in memory module 220 includes multiple physical pages, each of which contains multiple memory cells. It should be noted that this disclosure is not limited to the size of each physical page or logical page.

[0039] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure.

[0040] Reference Figure 2 In one embodiment, the memory management method provided by the present disclosure includes the following main process steps:

[0041] First, in step S210, the processor 211 obtains multiple virtual blocks of the memory module 220 and error bit statistics corresponding to each virtual block. Each virtual block has multiple physical blocks belonging to multiple planes of multiple chips. Specifically, the processor 211 regularly collects error bit statistics for each virtual block within a preset time period. The error bit statistics may include, but are not limited to, indicators such as the number of error correction code (ECC) corrections, the frequency of bit flips, the number of read failures, and the number of erase failures. The processor 211 may temporarily store this statistical information in the buffer memory 214 for subsequent health status assessment.

[0042] Figure 3 Schematic diagram of a virtual block structure according to an embodiment of the present disclosure.

[0043] Reference Figure 3 , for example, in one embodiment, the memory module 220 includes a plurality of chips, such as Figure 3 The first chip D1 and the second chip D2 are further divided into multiple planes. The first chip D1 includes a first plane PL1 and a second plane PL2, and the second chip D2 also includes a first plane PL1 and a second plane PL2. The memory module 220 organizes and manages its multiple physical blocks using virtual blocks. Each virtual block spans the corresponding planes of multiple chips, forming a unified logical management unit.

[0044] Specifically, the processor 211 can group multiple virtual blocks according to the order of the physical blocks of each plane. For example, the first virtual block VB1 includes the first physical block BK1 located in the first plane PL1 of the first chip D1, the first physical block BK1 located in the second plane PL2 of the first chip D1, the first physical block BK1 located in the first plane PL1 of the second chip D2, and the first physical block BK1 located in the second plane PL2 of the second chip D2. Similarly, the second virtual block VB2 includes the second physical block BK2 located in the two planes of the two chips, and the Nth virtual block VBN includes the Nth physical block BKN located in the two planes of the two chips. Through this cross-chip and cross-plane virtual block structure design, each virtual block has multiple physical blocks belonging to multiple planes of multiple chips, providing a flexible pairing selection space for subsequent enhanced block mapping operations.

[0045] When processor 211 performs an enhanced block mapping operation on a target virtual block, the virtual block structure provides multiple possible combinations for pairing physical blocks. Processor 211 can select two physical blocks within the target virtual block that belong to different chips for pairing, for example, pairing a physical block on the first plane PL1 of the first chip D1 with a physical block on the first plane PL1 of the second chip D2. This cross-chip pairing fully leverages the parallel processing capabilities of different chips, resulting in improved performance when performing parallel write or read operations.

[0046] In another embodiment, processor 211 may also select two physical blocks belonging to different planes within the target virtual block for pairing. For example, pairing a physical block on the first plane PL1 of the first chip D1 with a physical block on the second plane PL2 of the same chip. While this pairing approach offers slightly limited parallelism compared to cross-chip pairing, it can still disperse the risk of failure on a single plane to a certain extent, making it suitable for resource-constrained applications.

[0047] In one embodiment, processor 211 may also select two physical blocks within the target virtual block that belong to different chips and different planes for pairing. For example, pairing a physical block on the first plane PL1 of the first chip D1 with a physical block on the second plane PL2 of the second chip D2. This pairing strategy, which maximizes separation, can achieve both chip-level and plane-level fault domain isolation, providing the highest level of data protection.

[0048] The design of the virtual block structure also facilitates dynamic resource scheduling. When the processor 211 selects the target virtual block based on the health status assessment results, it can fully consider the wear distribution of each chip and plane, and give priority to virtual blocks containing physical blocks with poor health for enhanced protection. In addition, the cross-chip and cross-plane characteristics of the virtual block ensure that the enhanced block mapping operation will not cause excessive load on a single chip or plane. When the processor 211 writes the target data to the paired first physical block and the second physical block in parallel, since the two physical blocks belong to different chips or planes, the write operation can be performed simultaneously, effectively reducing the impact on the overall write performance. Similarly, when executing the rotation reading strategy, switching between different chips or planes can also better disperse the reading pressure and prevent a single area from generating read interference due to excessive reading.

[0049] It is worth noting that the present disclosure is not limited to grouping multiple virtual blocks based on the order of the physical blocks in each plane. For example, in another embodiment, the processor 211 can dynamically reorganize the composition of virtual blocks based on the health, wear level, or performance characteristics of the physical blocks. Specifically, the processor 211 can group physical blocks with similar health scores into the same virtual block, or mix physical blocks with different wear levels to achieve a more balanced load distribution.

[0050] In one embodiment, processor 211 can also adjust the virtual block composition strategy based on data access patterns. For frequently accessed hot data areas, processor 211 can prioritize physical blocks with better performance to form the corresponding virtual blocks; for infrequently accessed cold data areas, processor 211 can use relatively aged but still functional physical blocks. Furthermore, processor 211 can also implement a time-based reorganization strategy, regularly evaluating the state changes of each physical block and dynamically adjusting the internal composition of the virtual blocks to ensure optimal performance of the overall storage system.

[0051] Back to Figure 2 , next, the processor 211 executes step S220 to evaluate the health status of each virtual block based on the error bit statistical information. In one embodiment, the processor 211 calculates the health score of each virtual block by analyzing the number of errors and the number of error bits in the error bit statistical information. Specifically, the processor 211 counts the number of errors and the number of error bits that occur in each virtual block within a preset time period, and obtains the health score of each virtual block based on the number of errors and the number of error bits. In a certain embodiment, the processor 211 may use a weighted average algorithm to assign different weight coefficients to different types of error indicators, and comprehensively calculate a numerical score that reflects the overall health status of the virtual block. The lower the health score value, the worse the health status of the corresponding virtual block.

[0052] Then, the processor 211 executes step S230, and selects one or more target virtual blocks from the multiple virtual blocks according to the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than the health status of other virtual blocks. The processor 211 can obtain the one or more target virtual blocks by comparing the health score and the health score threshold of each virtual block. In another embodiment, the processor 211 sorts the multiple virtual blocks from low to high according to the health score, and selects the first P virtual blocks as the one or more target virtual blocks, wherein P is the preset number of target virtual blocks. It is worth mentioning that in one embodiment, the processor 211 can also dynamically adjust the number of selected target virtual blocks according to the current available capacity status of the storage device 20, and balance the efficiency of storage capacity utilization while ensuring data security. For example, the higher the current available capacity, the P value can be set to a higher value.

[0053] It should be noted that, in one embodiment, the processor 211 may also monitor the average erase count of the memory module 220. When the average erase count reaches a predetermined erase count threshold, the processor 211 begins selecting the one or more target virtual blocks for performing the enhanced block mapping operation. In other words, the processor 211 begins performing the enhanced block mapping operation only when the memory module 220 has aged to a certain extent to prevent data errors.

[0054] Next, in step S240, the processor 211 performs an enhancement block mapping operation on each target virtual block, pairing multiple physical blocks within the target virtual block in pairs, and mapping each pair of two physical blocks into an enhancement block, where the effective storage capacity of each enhancement block is equal to the storage capacity of a single physical block. When performing pairing, the processor 211 may select two physical blocks within the target virtual block that belong to different chips for pairing, or select two physical blocks within the target virtual block that belong to different planes for pairing, or select two physical blocks within the target virtual block that belong to different chips and different planes for pairing.

[0055] In one embodiment, processor 211 prioritizes cross-chip pairing because parallel write and read capabilities between different chips are generally superior to parallel capabilities between different planes, resulting in better performance. Simultaneously, processor 211 establishes an enhancement block mapping table that records the mapping relationship between each enhancement block and the first and second physical blocks paired with the enhancement block.

[0056] Figure 4 FIG. 1 is a schematic diagram of cross-chip enhancement block pairing according to an embodiment of the present disclosure.

[0057] Reference Figure 4For example, as shown by arrow A41, the processor 211 selects the physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block. The processor 211 selects the physical block BK1 in the first plane PL1 of the second chip D2 as the second physical block, and pairs the two physical blocks belonging to different chips. Through this cross-chip pairing method, the processor 211 maps the two paired physical blocks into an enhanced block. The enhanced block is Figure 4 The first enhancement block EBK1 is shown in FIG.

[0058] Similarly, the processor 211 can perform the same pairing operation on other physical blocks within the virtual block VB1. As another pairing example, as shown by arrow A42, the processor 211 selects the physical block BK1 in the second plane PL2 of the first chip D1 as the first physical block, and selects the physical block BK1 in the second plane PL2 of the second chip D2 as the second physical block to form the second enhanced block EBK2.

[0059] When establishing the enhancement block mapping table, processor 211 records in detail the mapping relationship between each enhancement block and its corresponding paired physical block. Specifically, the enhancement block mapping table contains the identification information of the first enhancement block EBK1, as well as the physical address of its corresponding first physical block located on the first plane PL1 of the first chip D1, and the physical address of its corresponding second physical block located on the first plane PL1 of the second chip D2. Similarly, the mapping record for the second enhancement block EBK2 contains the physical addresses of its paired physical blocks located on the second plane PL2 of the first chip D1 and the second plane PL2 of the second chip D2, respectively.

[0060] When processor 211 performs write operations on enhancement blocks, the cross-chip pairing design plays a key role. Taking the first enhancement block EBK1 as an example, processor 211 can simultaneously send write instructions to the first plane PL1 of the first chip D1 and the first plane PL1 of the second chip D2. Because the two target locations belong to different chips, the write operations can be truly executed in parallel, avoiding resource competition and maintaining good write performance. Similarly, write operations on the second enhancement block EBK2 can be performed simultaneously on the second plane PL2 of the first chip D1 and the second plane PL2 of the second chip D2, fully utilizing the parallel processing capabilities of different chips.

[0061] This pairing strategy also offers performance advantages during read operations. Based on the pre-set read strategy's rotation mechanism, processor 211 alternates between the two paired physical blocks of the first enhancement block EBK1. Because the first physical block is located on the first chip D1 and the second physical block is located on the second chip D2, switching between read operations does not cause resource conflicts within the chip. It also effectively distributes read pressure, preventing read disturb from excessive reading on a single chip, thereby extending the lifespan of each physical block.

[0062] also, Figure 4 The cross-chip pairing scheme shown provides powerful support for fault recovery. If a fault occurs in any physical block within the first enhancement block EBK1, the fault is effectively isolated within a single chip because the paired physical block is located on a completely different chip. Processor 211 can immediately recover complete data from the corresponding physical block in a functioning chip, ensuring continuous and reliable data access. This chip-level fault domain isolation design is particularly suitable for applications requiring high data security.

[0063] Notably, the cross-chip pairing approach also offers unique advantages when performing garbage collection operations. When processor 211 needs to release an enhancement block to increase available storage capacity, it can independently process paired physical blocks located on different chips, avoiding performance bottlenecks caused by simultaneous garbage collection of multiple physical blocks on the same chip.

[0064] Figure 5 FIG. 1 is a schematic diagram of cross-chip and cross-plane enhancement block pairing according to an embodiment of the present disclosure.

[0065] Reference Figure 5 In another embodiment, the processor 211 uses a cross-chip and cross-plane pairing strategy to perform the enhancement block mapping operation. As shown by arrow A51, the processor 211 selects the physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block, and selects the physical block BK1 in the second plane PL2 of the second chip D2 as the second physical block, pairing these two physical blocks belonging to different chips and different planes to form a first enhancement block EBK1. Similarly, as shown by arrow A52, the processor 211 selects the physical block BK1 in the second plane PL2 of the first chip D1 as the first physical block, and selects the physical block BK1 in the first plane PL1 of the second chip D2 as the second physical block to pair them to form a second enhancement block EBK2.

[0066] This cross-chip, cross-plane pairing approach achieves maximum fault domain isolation. When establishing the enhancement block mapping table, processor 211 records in detail the pairing relationship of the first enhancement block EBK1, where its first physical block is located at the physical address of the first plane PL1 of the first chip D1, and its second physical block is located at the physical address of the second plane PL2 of the second chip D2. Similarly, the mapping record for the second enhancement block EBK2 includes the physical address of its first physical block at the physical address of the second plane PL2 of the first chip D1, and the physical address of its second physical block at the physical address of the first plane PL1 of the second chip D2.

[0067] The cross-chip, cross-plane pairing strategy offers superior parallel processing capabilities. When processor 211 performs a write operation on the first enhancement block EBK1, it simultaneously sends a write instruction to the first plane PL1 of the first chip D1 and the second plane PL2 of the second chip D2. Because the target locations belong to different planes of different chips, the two write operations can be executed completely in parallel, eliminating any competition for hardware resources and achieving optimal write performance.

[0068] In terms of fault tolerance, cross-chip, cross-plane pairing provides the highest level of data protection. If any physical block in the first enhancement block EBK1 fails, whether at the chip or plane level, the other physical block in the pair is located in a completely independent hardware domain, ensuring complete data recovery. For example, even if the first plane PL1 of the first chip D1 fails, processor 211 can still fully recover all data in the first enhancement block EBK1 from the second plane PL2 of the second chip D2.

[0069] Cross-chip and cross-plane pairing also plays a crucial role in executing the read rotation strategy. Processor 211 can switch reads between different planes on different chips, minimizing read pressure. For example, when processor 211 reaches a preset threshold of reads from plane PL1 of chip D1, it can switch to plane PL2 of chip D2 to continue reading.

[0070] Furthermore, cross-chip and cross-plane pairing offers unique advantages during garbage collection operations. When processor 211 needs to release an enhancement block to reclaim storage space, it can independently process the paired physical blocks located on different planes of different chips, avoiding the performance disruption that might otherwise arise from multiple operations within the same hardware domain. This design enables the storage system to maintain stable performance during capacity management operations, ensuring unimpeded access to user data.

[0071] The cross-chip and cross-plane pairing method represents the highest level of data protection strategy disclosed in this disclosure. By simultaneously achieving fault isolation at the chip level and the plane level, it provides the most reliable security protection for critical data. It is particularly suitable for application environments with extremely high requirements for data integrity and system reliability.

[0072] It's worth noting that, in one embodiment, processor 211 can also leverage cross-chip, cross-plane parallel read capabilities to improve data access speed. Specifically, when the host system 10 requests to read a large amount of target data, processor 211 can split the target data into a first portion and a second portion, and simultaneously read the data from the first and second physical blocks of the first enhancement block EBK1. Processor 211 reads the first portion of the target data from the first physical block EBK1 on the first plane PL1 of the first chip D1, while simultaneously reading the second portion of the target data from the second physical block EBK2 on the second plane PL2 of the second chip D2. Because the two read operations are performed on different planes of different chips, there is no hardware resource conflict, enabling true parallel processing. This reduces the read time to nearly half of the time required to read a single physical block, significantly accelerating overall data read speed. This parallel read mechanism is particularly suitable for applications involving large-scale file transfers or high-frequency data access.

[0073] Figure 6 FIG. 1 is a schematic diagram illustrating pairing of same-chip enhancement blocks according to an embodiment of the present disclosure.

[0074] Reference Figure 6 In another embodiment, when the target virtual block VB1 is located in a single chip D1 comprising four planes, the processor 211 may employ multiple same-chip, cross-plane pairing strategies to perform the enhanced block mapping operation. As indicated by arrow A61, the processor 211 selects the physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block, and selects the physical block BK1 in the second plane PL2 of the same chip as the second physical block for pairing, thereby forming the first enhanced block EBK1. Similarly, as indicated by arrow A62, the processor 211 selects the physical block BK1 in the third plane PL3 of the first chip D1 as the first physical block, and selects the physical block BK1 in the fourth plane PL4 as the second physical block for pairing, thereby forming the second enhanced block EBK2. This pairing method fully utilizes the resource configuration of multiple planes within a single chip, providing plane-level fault tolerance for the target virtual block.

[0075] For another example, in one embodiment, when the first chip D1 only includes two planes, the processor 211 adopts a corresponding dual-plane pairing strategy. Specifically, the processor 211 selects the physical block BK1 in the first plane PL1 of the first chip D1 as the first physical block, and selects the physical block BK1 in the second plane PL2 of the first chip D1 as the second physical block for pairing, forming a corresponding enhanced block. This dual-plane pairing approach also utilizes the plane-level parallelism within the chip. When the processor 211 performs a write operation, it can simultaneously send write instructions to the first plane PL1 and the second plane PL2, achieving parallel writes between the planes. During read operations, the processor 211 switches alternately between the two planes according to a preset read strategy, effectively distributing read pressure and extending the lifespan of the physical blocks. Although the degree of parallelism and fault tolerance of dual-plane pairing are somewhat limited compared to cross-chip pairing, it can still provide basic plane-level protection for data and is suitable for storage device configurations with dual-plane chip architectures.

[0076] In a preferred embodiment, when performing enhanced block pairing mapping, processor 211 prioritizes pairing with physical blocks located on different chips, followed by pairing with physical blocks located on the same chip but different planes. If no free physical blocks exist within the target virtual block for cross-chip pairing, processor 211 falls back to pairing with physical blocks located across different planes. This ensures data reliability while improving parallel read and write performance and enhancing fault tolerance.

[0077] Back to Figure 2 Then, the processor 211 executes step S250. When writing target data to the target enhancement block, the target data is written in parallel to the first physical block and the second physical block of the target enhancement block. Specifically, the processor 211 assigns a corresponding target enhancement block identifier to the target enhancement block, obtains the first physical address of the first physical block and the second physical address of the second physical block corresponding to the target enhancement block identifier through the enhancement block mapping table, writes the target data to the first physical address and the second physical address simultaneously, and records the mapping relationship between the host logical address corresponding to the target data and the target enhancement block identifier in the logical-to-physical mapping table. Since the two paired physical blocks belong to different chips or planes, this parallel write operation can effectively utilize the parallel processing capability of the memory module 220 and reduce the impact on the overall write performance.

[0078] In step S260 , when reading the target data from the target enhanced block, the processor 211 selects one of the first physical block and the second physical block to read the target data according to a preset reading strategy.

[0079] In one embodiment, the processor 211 searches for the target enhanced block identifier corresponding to the host logical address according to the logic-to-physical mapping table, determines that the target physical address is the first physical address or the second physical address through the enhanced block mapping table and the preset read strategy corresponding to the target enhanced block identifier, and reads the target data from the target physical address.

[0080] Specifically, the preset read strategy adopts a rotation reading mechanism, and the processor 211 obtains a priority read identifier, which is used to indicate whether the target read physical block that is preferentially selected for reading in the target enhancement block is the first physical block or the second physical block. When the priority read identifier is a first value, the processor 211 determines that the first physical block is the target read physical block, so as to give priority to reading the target data from the first physical block. When the priority read identifier is a second value, the processor 211 determines that the second physical block is the target read physical block, so as to give priority to reading the target data from the second physical block. After completing the read operation, the processor 211 updates the number of reads corresponding to the target read physical block.

[0081] In one embodiment, when the read count reaches a read count threshold, the read count corresponding to the target read physical block is reset, and the read priority flag is changed to change the read priority flag from the first physical block originally indicated to the second physical block, or from the second physical block originally indicated to the first physical block. In short, the processor 211 switches the physical block to be read first.

[0082] It is worth mentioning that, in one embodiment, when reading the target data from the first physical block or the second physical block of the target enhancement block fails, the processor 211 can directly read the same target data from another physical block in the target enhancement block, thereby providing immediate fault recovery capability.

[0083] It should be noted that, since the enhanced block mapping operation actually utilizes twice the storage space to ensure the security of the stored data, the actual available space of the storage device 20 will be consumed faster.

[0084] In one embodiment, the processor 211 may calculate a temporary storage capacity value after applying the enhancement block mapping operation, and monitor the occupancy ratio of the user's valid data relative to the temporary storage capacity value. When the occupancy ratio reaches an occupancy ratio threshold, the processor 211 releases some enhancement blocks through a garbage collection operation to increase the temporary storage capacity value, thereby reducing the occupancy ratio.

[0085] Specifically, the temporary storage capacity value refers to the effective capacity of the storage device 20 that is actually available for user data storage after the enhanced block mapping operation is performed on some virtual blocks. Because the enhanced block mapping operation uses a dual-physical block mirroring mechanism, the effective storage capacity of each enhanced block is equal to the storage capacity of a single physical block. Compared to the original single-physical block storage method, the actual available storage space is reduced by half. Therefore, the processor 211 needs to recalculate the actual available capacity after the enhanced block mapping.

[0086] The processor 211 calculates the temporary storage capacity value as follows: the temporary storage capacity value is equal to the number of virtual blocks that have not yet undergone the enhanced block mapping operation multiplied by the original capacity of the single virtual block, plus the number of target virtual blocks that have undergone the enhanced block mapping operation multiplied by the original capacity of the single virtual block, divided by two. Through this calculation method, the processor 211 can accurately determine the impact of the enhanced block mapping operation on the overall storage capacity. The original capacity of a single virtual block is the preset total storage space of all physical blocks possessed by the single virtual block.

[0087] For example, assume that the storage device 20 is originally rated to have a capacity of 512MB multiplied by 100 virtual blocks (each of which is 512MB in size), for a total storage capacity of 51,200MB. When the processor 211 performs an enhanced block mapping operation on 40 virtual blocks of poor quality based on the health status assessment results, since the physical blocks within these 40 virtual blocks use a dual physical block mirroring mechanism, the effective data volume of these 40 target virtual blocks is halved, that is, each virtual block is 256MB. Therefore, the temporary storage capacity value calculated by the processor 211 is 512MB multiplied by 60 virtual blocks that do not perform enhanced block mapping, plus 256MB multiplied by 40 virtual blocks that perform enhanced block mapping, for a total of 40,960MB.

[0088] When the occupancy ratio between the amount of user valid data and the temporary storage capacity value in the storage device 20 reaches an occupancy ratio threshold (for example, 90% or other preset ratio), the processor 211 prioritizes the storage capacity demand and gradually releases some enhancement blocks through garbage collection operations.

[0089] In one embodiment, when releasing some enhanced blocks, the processor 211 evaluates the health status of each target virtual block, and based on the health status, preferentially selects virtual blocks with relatively good health status as candidate virtual blocks to ensure that the restored physical blocks can operate stably in the normal storage mode. The processor 211 preferentially selects virtual blocks with relatively high health scores and low error rates to perform enhanced block release operations (for example, virtual blocks with health scores ranked in the top M to perform enhanced block release operations), because the physical blocks within these virtual blocks can still maintain good data integrity and read and write performance after being restored as independent storage units, and are suitable for continuing to undertake single-mode storage tasks. This selection strategy ensures that the capacity release process does not introduce additional reliability risks, while retaining the necessary mirror backup mechanism for virtual blocks that are indeed in poor health and still require enhanced protection.

[0090] Next, by performing the garbage collection operation on the candidate virtual block, multiple candidate enhancement blocks of the candidate virtual block are released, thereby restoring each candidate enhancement block into two independent and blank physical blocks. This increases the available storage capacity, resulting in a lower ratio between the user's effective data volume and the temporary storage capacity value, ensuring the user's available storage space and maintaining a good user experience.

[0091] In a preferred embodiment, when the proportion of user valid data occupying the currently available temporary capacity reaches a preset threshold, processor 211 initiates a garbage collection process to free up space. This process includes: generating a candidate release list based on the health score of each virtual block, ranked from high to low; processor 211 sequentially processes the candidate enhancement blocks, restoring them to two independent, unused physical blocks, and updating the corresponding mapping table, thereby achieving rapid release and avoiding the migration of valid data to physical blocks with poor health.

[0092] Figure 7 2 is a flowchart of a round-robin reading strategy according to an embodiment of the present disclosure.

[0093] The following use Figure 7 To illustrate the specific process of the round-robin reading strategy, refer to Figure 7 In one embodiment, in step S710 , the processor 211 obtains a read instruction, where the read instruction instructs to read target data corresponding to a host logical address.

[0094] Specifically, when the host system 10 sends a read request through the connection interface circuit 230, the processor 211 parses the read instruction, obtains the host logical address, and determines the target enhancement block identifier (also called virtual enhancement block physical address) of the target enhancement block corresponding to the host logical address through the logical to physical mapping table.

[0095] Next, the processor 211 executes step S720 to read the first physical block of the target enhanced block according to the priority read flag having the first value corresponding to the target enhanced block to obtain the target data, and update the first read count corresponding to the first physical block.

[0096] Specifically, the processor 211 searches the enhanced block mapping table stored in the buffer memory 214 to determine the specific value of the priority read identifier corresponding to the target enhanced block identifier, thereby determining whether the target physical address to be read first is the first physical address corresponding to the first physical block or the second physical address corresponding to the second physical block. For example, when the priority read identifier is a first value (e.g., 0), the processor 211 determines that the first physical block is the current target read physical block (the target physical address is the first physical address corresponding to the first physical block). The processor 211 sends a read instruction to the first physical block through the memory interface control circuit 213, reads the target data from the specified first physical address, and transmits the read target data to the host system 10. At the same time, the processor 211 increments the first read count corresponding to the first physical block to record this read operation.

[0097] Next, processor 211 executes step S730 to determine whether the first read count reaches a read count threshold. Processor 211 compares the currently accumulated first read count with a preset read count threshold, which can be set based on the specific configuration and performance requirements of the storage device. This determination ensures that the round-robin read mechanism switches at the appropriate time, preventing read disturb from occurring on a single physical block due to excessive reads.

[0098] If the result of step S730 is negative, processor 211 executes step S740 without changing the priority read flag. At this point, the first physical block remains the priority read physical block, and subsequent read operations will continue from the first physical block. Processor 211 maintains the current read configuration to ensure the continuity and stability of the read operation.

[0099] If the result of step S730 is yes, processor 211 executes step S750, resetting the first read count (to prepare for the next read cycle) and changing the priority read flag to a second value (e.g., 1). Because processor 211 changes the priority read flag from the first value to the second value, subsequent read operations are switched to the second physical block. This switching mechanism implements alternating reads between the two paired physical blocks, effectively distributing read pressure and delaying the time when read interference occurs for each physical block.

[0100] In one embodiment, after the priority read flag is switched to the second value, the processor 211 will prioritize reading target data from the second physical block in subsequent read operations and begin accumulating the number of reads of the second physical block. When the number of reads of the second physical block reaches the same read count threshold, the processor 211 switches again and resets the priority read flag to the first value, thus forming a continuous alternating read cycle.

[0101] This alternating read strategy is designed with full consideration for the physical characteristics of NAND flash memory devices. By periodically switching the read source, processor 211 can prevent a single physical block from being overloaded with read operations, thereby delaying the occurrence of read disturb. Furthermore, because the two paired physical blocks store the same target data, switching the read source does not affect data integrity and accuracy, ensuring reliable user data access. This dynamic load balancing mechanism is one of the key technical means used by the disclosed memory management method to extend the lifespan of storage devices.

[0102] Figure 8 FIG. 4 is a schematic diagram of an enhanced block mapping table and corresponding access operations according to an embodiment of the present disclosure.

[0103] Reference Figure 8 In one embodiment, the processor 211 establishes an enhancement block mapping table T81 to manage the mapping relationship between the enhancement block and the paired physical block. The enhancement block mapping table T81 includes multiple mapping records, each of which describes in detail the enhancement block identifier, the corresponding first physical block physical address, the second physical block physical address, and the current priority read identifier.

[0104] For example, assume that the first enhancement block EPBA1 corresponds to the first physical block PBA11 and the second physical block PBA12, and its priority read flag is currently set to 0. The second enhancement block EPBA2 corresponds to the first physical block PBA21 and the second physical block PBA22, and its priority read flag is set to 1, and so on. This mapping table structure provides the processor 211 with complete enhancement block management information, ensuring that data access operations can accurately locate the corresponding physical block location.

[0105] During the execution of the write operation, as shown by arrow A81, when the processor 211 receives a write request for the target data TD, it first assigns the corresponding target enhancement block identifier EPBA1 to the target enhancement block. Subsequently, as shown by arrow A82, the processor 211 obtains the first physical address PBA11 of the first physical block and the second physical address PBA12 of the second physical block corresponding to the target enhancement block identifier EPBA1 through the enhancement block mapping table T81. Then, the processor 211 writes the target data TD to the first physical address PBA11 and the second physical address PBA12 at the same time, completing the parallel write operation of the mirrored data. After the data is written, the processor 211 records the mapping relationship between the host logical address corresponding to the target data TD and the target enhancement block identifier EPBA1 in the logic-to-physical mapping table to ensure that subsequent read operations can correctly locate the corresponding enhancement block. This write process ensures the integrity of the mirror backup of the data, and at the same time establishes a complete address mapping relationship, which provides a basis for subsequent data access operations. Since the paired physical blocks belong to different chips or planes, the write operation can be truly executed in parallel to maintain good write performance.

[0106] During the execution of the read operation, the processor 211 adopts a rotation strategy based on the priority read identifier to select the read source. As shown by arrow A83, when the processor 211 receives a read request, it first searches for the target enhanced block identifier EPBA1 corresponding to the host logical address according to the logic-to-entity mapping table. Subsequently, the processor 211 checks the priority read identifier of the corresponding target enhanced block identifier EPBA1 through the enhanced block mapping table T81. Since the priority read identifier of the first enhanced block identifier EPBA1 is currently 0, the processor 211 determines that the first physical address PBA11 is the target physical address. As shown by arrow A84, the processor 211 reads the target data TD from the first physical address PBA11 and increments the corresponding number of reads. When the cumulative number of reads reaches the preset threshold, the processor 211 changes the priority read identifier to 1, so that the subsequent read operation switches to the second physical address PBA12, thereby realizing a rotation reading mechanism between paired physical blocks.

[0107] The design of the enhancement block mapping table T81 supports dynamic read strategy adjustments. Processor 211 can flexibly adjust the switching frequency and strategy of priority read identifiers based on the health status, load distribution, or performance requirements of each physical block. Furthermore, enhancement block mapping table T81 records the pairing relationship of each enhancement block. When processor 211 needs to perform garbage collection or data migration operations, it can accurately identify the paired physical blocks that need to be processed simultaneously, ensuring the integrity and consistency of the enhancement blocks.

[0108] It's worth noting that enhanced block mapping table T81 works in conjunction with the traditional logical-to-physical mapping table to form a complete address translation system. The logical address sent by host system 10 is first converted into an enhanced block identifier using the logical-to-physical mapping table, and then further parsed into a specific physical block address using enhanced block mapping table T81. This two-tier mapping mechanism maintains compatibility with existing storage management architectures while supporting the specialized management requirements of enhanced blocks, achieving a balance between data protection and system performance.

[0109] In one embodiment, the processor 211 may also record additional metadata information in the enhanced block mapping table T81, such as the health score of each physical block, WL index, P / E cycle, cumulative read count, and last access time. This extended information helps the processor 211 make more sophisticated storage management decisions, including more complex management functions such as dynamic adjustment of read strategies, predictive maintenance, and intelligent capacity management.

[0110] In a certain embodiment, the processor 211 may also implement a threshold-type automatic read voltage optimization technology during the alternating read switching process. Specifically, whenever the cumulative number of reads reaches a preset threshold and triggers the target read physical block switching (also known as the read source switching operation), the processor 211 not only changes the priority read flag, but also automatically checks and fine-tunes the read reference voltage setting value of the physical block based on the health index, cumulative number of erases, or recent error correction code correction statistics of the physical block that has just completed the read cycle. The processor 211 can dynamically adjust the voltage level and optimization strategy in combination with the read retry mechanism or the aging characteristic lookup table to ensure that the reliability of the read operation is compensated accordingly as the degree of aging of the physical block. Such preset values ​​and adjustment strategies can be personalized according to the storage particle type and the accumulated wear condition to achieve refined read performance optimization management.

[0111] In another embodiment, the processor 211 implements an integrated mechanism of threshold rotation allocation and health check, converting the rotation switching into a trigger point for active health monitoring. Whenever the cumulative number of reads reaches a preset threshold value, the processor 211 not only performs a read source switching operation, but also performs a comprehensive health assessment of the physical block that has just completed intensive reading, including bit flip statistics, error correction code performance analysis, and cumulative erase count check. Based on the evaluation results, the processor 211 can automatically start data refresh operations, read voltage optimization adjustments, and even trigger a data re-mirroring backup mechanism when a health deterioration is detected. This integrated design transforms the rotation reading strategy from a passive load balancing to an active preventive maintenance system. Through regular health monitoring and adaptive adjustments, the overall service life of the storage device 20 is further extended and the level of data security is improved.

[0112] In one embodiment, processor 211 may also maintain a cumulative read cycle counter to record the total number of cycles each physical block has been selected as a read source. Specifically, whenever processor 211 switches read sources due to the cumulative read count reaching a threshold, it not only resets the current read cycle counter but also increments the cumulative read cycle count for the corresponding physical block. This cumulative cycle counter reflects the total amount of read pressure experienced by the physical block throughout the enhancement block's lifecycle, providing a more comprehensive reference for assessing the physical block's health.

[0113] When the cumulative number of read cycles reaches a read cycle threshold, the processor 211 can trigger a more proactive data protection operation. For example, when the cumulative number of read cycles of a physical block exceeds a first read cycle threshold, the processor 211 can initiate a preventive data migration operation, migrating the data of the enhanced block to a new enhanced block in better health, and re-establishing a mirror backup relationship. When the cumulative number of read cycles reaches a second read cycle threshold, the processor 211 can perform a data rewrite operation, refreshing the charge state within the physical block through a rewrite mechanism, and delaying the degradation of data retention capabilities. This multi-level cumulative cycle monitoring mechanism implements rotating load balancing and active life management, providing a more proactive data protection strategy for the storage device 20.

[0114] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code is executed in a processor, the processor performs the steps of the above-mentioned memory management method. The computer program product can be implemented in hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK).

[0115] Based on the above, the memory management method and memory controller provided by this disclosure achieve precise monitoring of the memory module status by acquiring error bit statistics and evaluating the health of virtual blocks. This allows for timely identification of areas with poor health and the implementation of targeted protection measures. By selecting target virtual blocks with lower health status than other virtual blocks for enhanced block mapping operations, this disclosure avoids impacting the performance of the entire storage system, providing additional data security only for high-risk virtual blocks (lower health status) requiring protection, thus achieving efficient resource utilization.

[0116] The design pairs physical blocks within the target virtual block and maps them to enhancement blocks, establishing a complete mirroring mechanism for each enhancement block. If any physical block fails, data can be recovered from the paired physical block, improving data reliability and system fault tolerance. The pairing strategy supports multiple combinations, including cross-chip and cross-plane combinations, leveraging the hardware architecture of the memory module to isolate fault domains across different chips or planes, enhancing overall system stability.

[0117] Furthermore, the parallel write mechanism ensures the synchronization and consistency of mirrored data by simultaneously writing the same data to the paired first and second physical blocks. Because the paired physical blocks belong to different hardware resources, write operations can be performed in true parallel, reducing write latency compared to traditional sequential write methods and maintaining good system performance.

[0118] Furthermore, the pre-set read strategy employs a rotating read mechanism that effectively distributes read pressure. By periodically switching the read source between paired physical blocks, it prevents read disturb from excessive reads on a single physical block, thereby extending the lifespan of the storage device. Combined with dynamic monitoring of read count thresholds, this strategy achieves balanced load distribution, ensuring continued use of the storage device during its aging phase.

[0119] Finally, this disclosure achieves a flexible balance between data security and storage capacity requirements by establishing a dynamic management mechanism for enhancement block mapping and temporary storage capacity values. When user data volume increases, leading to capacity constraints, the system intelligently releases healthy enhancement blocks, restoring their original storage capacity and ensuring the storage device can continue to meet user needs. This invention balances data reliability, access efficiency, and capacity flexibility, making it suitable for a variety of application scenarios, including consumer and enterprise-level solid-state storage devices, and provides a technical solution for extending the lifespan of storage devices.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management method, applied to a storage device equipped with a memory module, characterized in that: The method comprises: evaluating health of a plurality of virtual blocks of the memory module; selecting one or more target virtual blocks from the plurality of virtual blocks according to the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than the health status of other virtual blocks; Performing an enhanced block mapping operation on each target virtual block, pairing multiple physical blocks in the target virtual block in pairs, and mapping each pair of two physical blocks into an enhanced block; When writing target data to the target enhanced block, writing the target data to the first physical block and the second physical block of the target enhanced block in parallel; and When the target data is read from the target enhanced block, one of the first physical block and the second physical block is selected to read the target data according to a preset reading strategy.

2. The memory management method according to claim 1, wherein: Wherein evaluating the health status of the plurality of virtual blocks of the memory module comprises: Counting the number of errors and the number of error bits in each virtual block within a preset time period; and A health score of each virtual block is obtained based on the number of errors and the number of erroneous bits.

3. The memory management method according to claim 2, wherein: Wherein, selecting the one or more target virtual blocks from the plurality of virtual blocks according to the health status of each virtual block comprises one of the following steps: Obtaining the one or more target virtual blocks by comparing the health score of each virtual block with a health score threshold; and The plurality of virtual blocks are sorted from low to high according to the health scores, and the first P virtual blocks are selected as the one or more target virtual blocks, where P is a preset number of target virtual blocks.

4. The memory management method according to claim 1, wherein: Pairing the multiple physical blocks in the target virtual block in pairs includes one of the following methods: Select two physical blocks belonging to different chips in the target virtual block for pairing; Select two physical blocks belonging to different planes in the target virtual block for pairing; and Two physical blocks belonging to different chips and different planes in the target virtual block are selected for pairing. The memory management method according to claim 1 , wherein: The method further comprises: monitoring an average erase count of the memory module; and When the average erase count reaches a preset erase count threshold, the one or more target virtual blocks are selected to perform the enhanced block mapping operation. The memory management method according to claim 1 , wherein: The method further comprises: Recording the number of reads of the target read entity block that is preferentially selected for reading in the target enhanced block; When the number of reads of the target read physical block reaches a read number threshold, changing the target read physical block from the first physical block to the second physical block, or from the second physical block to the first physical block; and Resets the read count.

7. The memory management method according to claim 1, wherein: According to the preset reading strategy, selecting one of the first physical block or the second physical block to read the target data includes: Obtaining a priority read flag, wherein the priority read flag is used to indicate whether a target read physical block preferentially selected for reading in the target enhanced block is the first physical block or the second physical block; When the priority read identifier is a first value, determining the first physical block as the target read physical block, so as to preferentially read the target data from the first physical block; and When the priority read identifier is a second value, the second physical block is determined as the target read physical block, so as to preferentially read the target data from the second physical block.

8. The memory management method according to claim 1, wherein: The method further comprises: When reading the target data from the first physical block or the second physical block of the target enhanced block fails, the same target data is directly read from another physical block in the target enhanced block.

9. The memory management method according to claim 1, wherein: The method further comprises: Establishing an enhancement block mapping table to record the enhancement block identifier of each enhancement block and the mapping relationship between the first physical block and the second physical block paired with the enhancement block; and The mapping relationship between the host logical address and the corresponding enhanced block identifier is recorded in the logic-to-entity mapping table.

10. The memory management method according to claim 1, wherein: The method further comprises: calculating a temporary storage capacity value after applying the enhanced block mapping operation; Monitoring the proportion of the user's valid data volume relative to the temporary storage capacity value; and When the occupancy ratio reaches an occupancy ratio threshold, some enhancement blocks are released through a garbage collection operation to increase the temporary storage capacity value, thereby reducing the occupancy ratio.

11. The memory management method according to claim 10, wherein: Releasing the part of the enhancement blocks by the garbage collection operation includes: Evaluate the health of each target virtual block; According to the health status, preferentially selecting a virtual block with relatively better health status as a candidate virtual block; and The garbage collection operation is performed on the candidate virtual block to release multiple candidate enhancement blocks of the candidate virtual block, thereby restoring each candidate enhancement block into two independent and blank physical blocks.

12. A memory controller for controlling a storage device equipped with a memory module, characterized in that: The memory controller comprises: a memory interface control circuit for electrically connecting to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: evaluating health of a plurality of virtual blocks of the memory module; selecting one or more target virtual blocks from the plurality of virtual blocks according to the health status of each virtual block, wherein the health status of the one or more target virtual blocks is lower than the health status of other virtual blocks; Performing an enhanced block mapping operation on each target virtual block, pairing multiple physical blocks in the target virtual block in pairs, and mapping each pair of two physical blocks into an enhanced block; When writing target data to the target enhanced block, writing the target data to the first physical block and the second physical block of the target enhanced block in parallel; and When the target data is read from the target enhanced block, one of the first physical block and the second physical block is selected to read the target data according to a preset reading strategy.

13. The memory controller according to claim 12, wherein: Wherein evaluating the health status of the plurality of virtual blocks of the memory module comprises: Counting the number of errors and the number of error bits in each virtual block within a preset time period; and A health score of each virtual block is obtained based on the number of errors and the number of erroneous bits.

14. The memory controller according to claim 13, wherein: Wherein, selecting the one or more target virtual blocks from the plurality of virtual blocks according to the health status of each virtual block comprises one of the following steps: Obtaining the one or more target virtual blocks by comparing the health score of each virtual block with a health score threshold; and The plurality of virtual blocks are sorted from low to high according to the health scores, and the first P virtual blocks are selected as the one or more target virtual blocks, where P is a preset number of target virtual blocks.

15. The memory controller according to claim 12, wherein: The processor is further configured to pair the multiple physical blocks within the target virtual block in pairs using one of the following methods: Select two physical blocks belonging to different chips in the target virtual block for pairing; Select two physical blocks belonging to different planes in the target virtual block for pairing; and Two physical blocks belonging to different chips and different planes in the target virtual block are selected for pairing.

16. The memory controller according to claim 12, wherein: The processor is further configured to: monitoring an average number of erase times of the memory module; as well as When the average erase count reaches a preset erase count threshold, the one or more target virtual blocks are selected to perform the enhanced block mapping operation.

17. The memory controller according to claim 12, wherein: The processor is further configured to: Recording the number of reads of the target read entity block that is preferentially selected for reading in the target enhanced block; When the number of reads of the target read physical block reaches a read number threshold, changing the target read physical block from the first physical block to the second physical block, or from the second physical block to the first physical block; as well as Resets the read count.

18. The memory controller according to claim 12, wherein: According to the preset reading strategy, selecting one of the first physical block or the second physical block to read the target data includes: Obtaining a priority read flag, wherein the priority read flag is used to indicate whether a target read physical block preferentially selected for reading in the target enhanced block is the first physical block or the second physical block; When the priority read identifier is a first value, determining the first physical block as the target read physical block, so as to preferentially read the target data from the first physical block; and When the priority read identifier is a second value, the second physical block is determined as the target read physical block, so as to preferentially read the target data from the second physical block.

19. The memory controller according to claim 12, wherein: The processor is further configured to: When reading the target data from the first physical block or the second physical block of the target enhanced block fails, the same target data is directly read from another physical block in the target enhanced block.

20. The memory controller according to claim 12, wherein: The processor is further configured to: Establishing an enhancement block mapping table to record an enhancement block identifier of each enhancement block and a mapping relationship between a first entity block and a second entity block paired with the enhancement block; as well as The mapping relationship between the host logical address and the corresponding enhanced block identifier is recorded in the logic-to-entity mapping table.

21. The memory controller according to claim 12, wherein: The processor is further configured to: calculating a temporary storage capacity value after applying the enhanced block mapping operation; Monitor the proportion of the user's valid data volume relative to the temporary storage capacity value; as well as When the occupancy ratio reaches an occupancy ratio threshold, some enhancement blocks are released through a garbage collection operation to increase the temporary storage capacity value, thereby reducing the occupancy ratio.

22. The memory controller according to claim 21, wherein: The part of the enhancement block is released by the garbage collection operation: Evaluate the health of each target virtual block; According to the health status, preferentially selecting a virtual block with relatively better health status as a candidate virtual block; as well as The garbage collection operation is performed on the candidate virtual block to release multiple candidate enhancement blocks of the candidate virtual block, thereby restoring each candidate enhancement block into two independent and blank physical blocks.

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