Heterogeneous trusted execution environment architecture construction method and device and processor

Abstract

The invention relates to a heterogeneous trusted execution environment architecture construction method and device, and the method comprises the following steps: constructing a tensor analyzer which is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; and providing memory protection with uniform tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

Description

Technical Field

[0001] The present invention relates to the field of computer science and technology, and in particular to the field of heterogeneous intelligent security architecture for large model training. Background Art

[0002] In applications such as machine learning training, neural network processing units (NPUs) are used to handle critical computations. To ensure secure and efficient computing, recent research has expanded the CPU TEE (Trusted Execution Environment) to heterogeneous TEEs. Heterogeneous NPU TEEs can be categorized as integrated or discrete based on how they connect to the CPU. Integrated NPU TEEs have performance limitations, making them insufficient for demanding applications like LLM training, which involves large-scale computation. Discrete heterogeneous NPU TEEs are now more widely adopted in production environments.

[0003] The main problems of existing discrete heterogeneous NPU TEE designs include: (1) Inefficient CPU TEE computation at cache line granularity. In heterogeneous collaborative LLM training, the CPU is responsible for optimizer updates, such as the Adam optimizer that performs parameter updates. Due to performance requirements and its inherent parallelism, Adam is always executed in parallel in the CPU. Figure 3 As shown in the figure (blue tiles represent non-secure environments, orange tiles represent SGX environments), the introduction of a TEE can lead to a performance degradation of up to 3.7 times in an SGX environment. It can be observed that in an SGX environment, the performance benefit gradually decreases as the number of threads increases, indicating a transition from compute-intensive to memory-intensive tasks. The increase in memory accesses is primarily attributed to metadata such as VN (tensor version number) and MAC (message authentication code).

[0004] (2) NPU cache line granularity MAC results in significant storage and performance overhead. Memory resources on NPUs are limited, typically only 40GB in capacity, compared to up to 512GB of CPU memory on server CPUs. Limited memory capacity leads to a shortage of memory resources, which is further exacerbated by the storage footprint of enclave metadata such as VNs and MACs. Since the cache line granularity is 64B, both VNs and MACs require 56 bits of storage overhead, resulting in an unacceptable 20% storage overhead for the Merkle Tree. Recent NPU research has managed VNs at the tensor level, reducing VN storage and memory access overhead, but the nearly 10% storage overhead and 12% performance overhead of MAC remain unresolved.

[0005] (3) The data transmission protocol is inefficient. In non-secure mode, communication (gradient communication Comm G, weight communication CommW) only accounts for 16% of the overhead, but in the baseline system composed of SGX and MGX TEE, the communication overhead increases to 55%, as shown in Figure 2. Figure 4 (Dark grey tiles represent NPU, light grey tiles represent CPU, light orange tiles represent weight communication, and orange tiles represent gradient communication) as shown.

[0006] Mismatched protection granularity leads to additional re-encryption: The CPU and NPU have a mismatched granularity because the CPU performs protection on the cache line granularity, while the NPU performs protection on the tensor granularity. Due to the incompatible granularity, even if the same key is used, the encrypted data of the CPU (or NPU) cannot be correctly decrypted by the NPU (or CPU) because they have fixed incompatible hardware cryptographic engines. Therefore, the communication relies on insecure memory as a relay. The sender needs to decrypt the data in the secure memory area and save it in the non-secure area. After the communication is over, the receiver loads the data into the secure area. In order to protect the privacy of the data, the data in the non-secure area needs to be re-encrypted. Figure 5 The communication protocol is illustrated, showing that it involves 4 additional memory accesses, including read, write and re-encryption / decryption operations.

[0007] The inventors found that the main problems of the existing design are the security management overhead of the cache line granularity and the granularity conversion overhead caused by the mismatched management granularity of the CPU and NPU. Summary of the Invention

[0008] In order to solve the problem of additional storage and performance overhead caused by the mismatch between CPU and NPU granularity in the current heterogeneous TEE architecture, the present invention discloses a method for constructing a heterogeneous trusted execution environment architecture, including the following steps:

[0009] Building a tensor analyzer, wherein the tensor analyzer is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture;

[0010] The tensor analyzer provides memory protection with unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit.

[0011] In one embodiment of the above method of the present invention, the step of constructing a tensor analyzer is performed by implementing memory management.

[0012] In one embodiment of the above method of the present invention, the step of constructing a tensor analyzer by implementing memory management further includes:

[0013] Build a unary table to maintain the tensor data structure;

[0014] Constructing a tensor filter for maintaining the metatable when a metatable entry is missing;

[0015] The metatable is maintained according to memory access received by the tensor analyzer from the computing core of the central processing unit.

[0016] In one embodiment of the above method of the present invention, the step of building a tensor analyzer by implementing memory management further includes:

[0017] Determining a data protection type based on the memory access address and the memory region binding register;

[0018] A bitmap is used to indicate the update status of the tensor cache line in the metatable.

[0019] In one embodiment of the above method of the present invention, the step of maintaining the metatable based on the memory access received by the tensor analyzer from the computing core of the central processing unit further includes:

[0020] Processing when the address of a memory access hits the address of an entry in the metatable;

[0021] Processing when the address of a memory access does not hit the address of an entry in the metatable;

[0022] Processed when the address of a memory access hits the address boundary of an entry in the metatable.

[0023] In one embodiment of the above method of the present invention, the processing step when the address of the memory access hits the address of an entry in the metatable further includes:

[0024] The memory access address and version number are sent to the encryption and decryption module for encryption for subsequent operations.

[0025] In one embodiment of the above method of the present invention, the processing step when the address of the memory access does not hit the address of an entry in the metatable further includes:

[0026] Access the memory and obtain data information and version number;

[0027] Send the data information and version number to the encryption and decryption module for encryption for subsequent operations;

[0028] Send data information and version number to tensor filter for recording or updating;

[0029] Tensor filters record or update the metatable.

[0030] In one embodiment of the above method of the present invention, the processing step when the address of the memory access hits the address boundary of an entry in the metatable further includes:

[0031] Send the memory access address and version number to the encryption and decryption module for encryption;

[0032] Access the memory and obtain data information and version number;

[0033] If the version number of the memory access is consistent with the version number obtained by accessing the memory, the corresponding entry in the metatable is updated using the data information obtained by accessing the memory.

[0034] In one embodiment of the above method of the present invention, the step of maintaining the metatable based on the memory access received by the tensor analyzer from the computing core of the central processing unit further includes:

[0035] When checking through the bitmap that all cache line update states corresponding to a tensor in the metatable are updated, the version number of the tensor is increased.

[0036] In one embodiment of the above method of the present invention, the step of providing memory protection of a unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer further includes:

[0037] Aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor;

[0038] Utilizing the tensor message authentication code management module in the tensor analyzer and the tensor message authentication code management module in the memory control unit of the neural network processor to provide tensor-level message authentication code delayed verification for data interaction between the neural network processor and the central processing unit;

[0039] A direct data transmission protocol is used for data exchange between the central processing unit and the neural network processor.

[0040] In one embodiment of the above method of the present invention, the step of aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor further includes:

[0041] When the address range of the central processing unit tensor and the address range of the neural network processor tensor overlap by an alignment threshold of the address range of the central processing unit tensor, the address range of the central processing unit tensor is replaced with the address range of the neural network processor tensor.

[0042] In one embodiment of the above method of the present invention, the tensor-level message authentication code delayed verification step further includes:

[0043] The calculation of the decrypted data of the tensor is performed in parallel with the regeneration of the tensor message authentication code;

[0044] After completing the regeneration of the tensor message authentication code, performing integrity verification on the tensor;

[0045] If the integrity verification fails, the neural network processor enclave discards the tensor that failed the integrity verification and requests the CPU enclave to retransmit the tensor that failed the integrity verification;

[0046] The CPU enclave maintains a failure counter to record the number of tensor integrity verification failures. If the number of failures exceeds a failure threshold, the tensor integrity verification is suspended and an exception is reported.

[0047] In one embodiment of the above method of the present invention, the step of using the direct data transmission protocol to perform data exchange between the central processing unit and the neural network processor further includes:

[0048] Authentication phase processing;

[0049] Data transmission phase processing.

[0050] In one embodiment of the above method of the present invention, the identity verification stage processing step further includes:

[0051] The CPU creates the first enclave and obtains the first enclave report;

[0052] The central processor requests the neural network processor to create a second enclave and obtains a second enclave report;

[0053] The first enclave and the second enclave conduct mutual authorization based on the first enclave report and the second enclave report;

[0054] The CPU and the NPU use the same key during data encryption and decryption to authenticate between the first and second enclaves.

[0055] In one embodiment of the above method of the present invention, the data transmission phase processing step further includes:

[0056] Trusted metadata data transmission, which transmits data including the tensor address range through the trusted encrypted channel created in the authentication phase;

[0057] Direct tensor transfer, for tensor data corresponding to the tensor address range, is directly transferred between the dynamic random access memory of the central processing unit and the dynamic random access memory of the neural network processor.

[0058] The present invention also discloses a device for constructing a heterogeneous trusted execution environment architecture, which is used to execute any of the above methods, including:

[0059] A tensor analyzer building module, configured to build a tensor analyzer, wherein the tensor analyzer is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture;

[0060] A memory protection module with unified tensor granularity is used to provide memory protection with unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

[0061] The present invention also discloses a heterogeneous processor, including a central processing unit, a neural network processor, a memory and an input and output unit that are interconnected, and also includes the above-mentioned heterogeneous trusted execution environment architecture construction device.

[0062] The present invention also discloses a storage medium for storing a computer control program, wherein the computer control program is used to execute the steps of any of the above methods.

[0063] The present invention discloses a method, device, and heterogeneous processor for constructing a heterogeneous trusted execution environment architecture, achieving matching of CPU and NPU granularity in a heterogeneous TEE architecture, reducing additional storage and performance overhead. The invention also implements delayed-verifiable tensor granularity MAC management based on tensor backup, reducing storage overhead while also reducing additional memory access. Through the implementation of a direct data transmission protocol, a unified heterogeneous tensor granularity TEE facilitates direct data transmission within secure memory, eliminating transit through non-secure areas and the need for re-encryption and decryption, thereby achieving parallelization of data transmission and computation. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 This is the heterogeneous TEE data flow in the existing technology.

[0065] Figure 2 This is a memory protection solution in the prior art.

[0066] Figure 3 This is the performance overhead caused by the additional memory access of the CPU TEE in the existing technology.

[0067] Figure 4 This is the overhead generated by heterogeneous TEE communication in the existing technology.

[0068] Figure 5 This is a comparison between data transmission in non-secure areas and data transmission in secure areas in the prior art.

[0069] Figure 6 This is a flowchart of a method for constructing a heterogeneous trusted execution environment architecture in one embodiment of the present invention.

[0070] Figure 7This is an overall block diagram of a heterogeneous trusted execution environment architecture in one embodiment of the present invention.

[0071] Figure 8 Schematic diagram of the working principle of a tensor analyzer in one embodiment of the present invention.

[0072] Figure 9 Schematic diagram of delayed verification of a tensor-level message authentication code according to an embodiment of the present invention.

[0073] Figure 10 This is a schematic diagram of unifying tensor management granularity to reduce data transmission overhead in one embodiment of the present invention.

[0074] Figure 11 A block diagram of a device for constructing a heterogeneous trusted execution environment architecture according to an embodiment of the present invention.

[0075] Figure 12 The figure is a block diagram of a heterogeneous processor according to an embodiment of the present invention.

[0076] Figure 13 This is a comparison of the overall performance of the architecture of the present invention and other architectures in one embodiment of the present invention.

[0077] Figure 14 This is an analysis of the overhead ratios of the architecture of the present invention and other architectures under different configurations in one embodiment of the present invention.

[0078] Figure 15 The following is an analysis of the metatable hit situation in the architecture of the present invention in one embodiment of the present invention.

[0079] Figure 16 It is the average performance overhead of the architecture of the present invention relative to SGX and SoftVN at different numbers of iterations in one embodiment of the present invention.

[0080] Figure 17 This figure shows the performance comparison and storage overhead of tensor-level MAC delay verification of the present invention architecture in one embodiment of the present invention.

[0081] Figure 18 It is the overhead ratio of different operations during communication of the architecture of the present invention in one embodiment of the present invention.

[0082] Wherein, the reference numerals:

[0083] 1: Memory control unit

[0084] 2: Tensor Analyzer

[0085] 21: Metatable

[0086] 22: Tensor Filters

[0087] 23: Memory region binding register

[0088] 24: Bitmap

[0089] 3: Encryption and decryption module

[0090] 4: Tensor Manager

[0091] 10: A device for building a heterogeneous trusted execution environment architecture

[0092] 11: Tensor Analyzer Building Blocks

[0093] 12: Memory protection module with unified tensor granularity

[0094] 100: A heterogeneous processor

[0095] 110: Memory

[0096] 120: Input and output unit DETAILED DESCRIPTION

[0097] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments to further understand the purpose, solution and beneficial technical effects of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0098] It should be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article or device. In the absence of further restrictions, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0099] Certain terms are used in this specification and the appended claims to refer to specific components or parts. Persons skilled in the art will understand that technology users or manufacturers may use different nouns or terms to refer to the same component or part. This specification and the appended claims do not distinguish components or parts based on differences in name, but rather on differences in their functions.

[0100] In the present invention, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0101] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0102] Furthermore, the terms "installed," "disposed," "provided with," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0103] About collaborative computing: Due to the different computing models and limitations of CPU and NPU, collaborative computing has become more and more popular. Large Language Model LLM CPU-NPU Collaborative Computing: Due to the limited DRAM capacity of NPU, large-scale language model training tends to adopt heterogeneous collaborative computing of NPU and CPU. This article focuses on the ZeRO-Offload framework, which is widely used in collaborative training. The main reason is that ZeRO-Offload can transfer the stage with low computational load but high memory usage from NPU to CPU, effectively reducing the memory storage pressure of NPU, thereby enabling larger-scale model training. For example, by offloading gradients, optimizer states, and optimizer calculations from NPU to CPU, while keeping forward and reverse calculations on NPU, ZeRO-Offload can increase the training model size by 10 times. As Figure 1 As shown in Figure 1, the computational flow of ZeRO-Offload consists of three main stages. First, the NPU performs forward and backward computations, passing the updated gradients to the CPU during backpropagation. Then, the CPU performs optimizer iterations, updating the optimizer state and weights. Finally, the CPU transmits the updated weights back to the NPU.

[0104] About memory protection: Figure 2Two different granularities are described for managing tensor version numbers VN (hereinafter abbreviated as VN). Figure 2 Legend: Gray tiles represent off-chip VNs, green tiles represent on-chip VNs, pink tiles represent metadata, blue tiles represent cache line data, and orange tiles represent tensor data. First, considering that the CPU is a general-purpose processor, each cache line has its own dedicated VN to support random memory access ( Figure 2 (a)). However, using fine granularity, such as using 56-bit VN for 64B data blocks, introduces about 11% storage overhead. Such large storage requirements require off-chip storage, which exacerbates memory access overhead. In addition, off-chip VN relies on Merkle tree data structures to ensure its integrity. Secondly, recent NPU TEE research adopts tensor-based VN granularity to exploit the regular memory access patterns prevalent in NPU workloads ( Figure 2 (b)). At the tensor granularity level, one VN is used for all cache lines of the entire tensor. This approach significantly reduces storage pressure and allows VNs to be stored on-chip, reducing memory access requirements for the VN and eliminating the need for Merkle trees. Recent NPU research manages VNs at the tensor level, reducing VN storage and memory access overhead. However, to ensure the integrity of tensor storage, a message authentication code (MAC) must be generated for the tensor, resulting in nearly 10% storage overhead and 12% performance overhead. Therefore, efficient MAC management remains an unresolved issue.

[0105] Based on the above, please refer to Figures 6 and 7 The present invention discloses a method for constructing a heterogeneous trusted execution environment architecture, comprising the following steps:

[0106] S1: constructing a tensor analyzer 2, wherein the tensor analyzer 2 is located in a memory control unit 1 of a central processing unit of a heterogeneous trusted execution environment architecture;

[0107] S2: The tensor analyzer 2 provides memory protection with a unified tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit.

[0108] according to Figure 8 As shown, in one embodiment of the above method of the present invention, the step of constructing the tensor analyzer 2 is performed by implementing memory management.

[0109] In one embodiment of the above method of the present invention, the step of constructing the tensor analyzer 2 by implementing memory management further includes:

[0110] Construct a unary table 21 for maintaining the tensor data structure;

[0111] Constructing a tensor filter 22 for maintaining the metatable 21 when an entry in the metatable 21 is missing;

[0112] The metatable 21 is maintained according to the memory access received by the tensor analyzer 2 from the computing core of the central processing unit.

[0113] Specifically, a hardware-based tensor analyzer 2 is used for tensor memory protection. Tensor analyzer 2 receives and analyzes memory access requests from the CPU cores, building and maintaining a metatable 21 data structure at runtime. Each entry in metatable 21 contains metadata, such as the VN, used to manage all cache lines within a tensor. Metatable 21 resides on-chip, eliminating the overhead of accessing the VN from memory in subsequent memory requests.

[0114] The benefits of Tensor Analyzer 2 directly receiving memory access requests from the core are: avoiding the interference of cache eviction and prefetching on memory access analysis; utilizing the core's virtual address to break through the page limit of the physical address and maximize the mining of continuity in tensors; the detection, maintenance and access of tensor data structures can be executed in parallel with multi-level caches, effectively hiding their performance overhead.

[0115] In one embodiment of the above method of the present invention, the step of constructing the tensor analyzer 2 by implementing memory management further includes:

[0116] Determining the data protection type according to the memory access address and the memory region binding register 23;

[0117] The bitmap 24 is used to indicate the update status of the tensor cache line in the metatable 21 .

[0118] In one embodiment of the above method of the present invention, the step of maintaining the metatable 21 based on the memory access received by the tensor analyzer 2 from the computing core of the central processing unit further includes:

[0119] Processing when the address of the memory access hits the address of an entry in metatable 21;

[0120] Processing when the address of the memory access does not hit the address of the entry in metatable 21;

[0121] Processing when the address of a memory access hits the address boundary of an entry in metatable 21.

[0122] In one embodiment of the above method of the present invention, the processing step when the address of the memory access hits the address of an entry in the metatable 21 further includes:

[0123] The memory access address and version number are sent to the encryption and decryption module 3 for encryption for subsequent operations.

[0124] In one embodiment of the above method of the present invention, the processing step when the address of the memory access does not hit the address of an entry in the metatable 21 further includes:

[0125] Access the memory and obtain data information and version number;

[0126] Send the data information and version number to the encryption and decryption module 3 for encryption for subsequent operations;

[0127] Send the data information and version number to the tensor filter 22 for recording or updating;

[0128] The tensor filter 22 records or updates the metatable 21 .

[0129] In one embodiment of the above method of the present invention, the processing step when the address of the memory access hits the address boundary of an entry in the metatable 21 further includes:

[0130] Send the memory access address and version number to the encryption and decryption module 3 for encryption;

[0131] Access the memory and obtain data information and version number;

[0132] If the version number of the memory access is consistent with the version number obtained by accessing the memory, the corresponding entry in the metatable 21 is updated using the data information obtained by accessing the memory.

[0133] In one embodiment of the above method of the present invention, the step of maintaining the metatable 21 according to the memory access received by the tensor analyzer 2 from the computing core of the central processing unit further includes:

[0134] When checking through the bitmap 24 that the update status of all cache lines corresponding to a tensor in the metatable 21 is updated, the version number of the tensor is increased.

[0135] Specifically, if Figure 8 As shown, metatable 21 receives access requests from the core. When a hit occurs, it passes the address and VN to encryption / decryption module 3 to perform encryption operations, thus avoiding additional access to metadata in memory. Metatable 21 utilizes the LRU replacement strategy and attempts to merge with other entries before eviction to improve storage efficiency.

[0136] The tensor filter 22 handles the missing metatable 21 and collects and analyzes adjacent access addresses. Specifically, the tensor filter 22 first groups the memory access requests into multiple groups with similar addresses (while ensuring that the VNs are the same, otherwise all addresses of this entry are discarded), and then sorts the addresses in each group and determines whether they are continuous addresses (there may be a stride).

[0137] When a particular entry in the tensor filter 22 reaches its collection address limit (reaching a preset number of addresses), it checks whether the entry meets the tensor condition: having the same VN and a consistent pattern between addresses. The information of the successful entry is then filled into the metadata table as the initialization entry of the tensor.

[0138] The tensor analyzer 2 also includes a memory region binding register 23, which determines the data protection type (tensor management or traditional cache line management) based on the relationship between the address and this register, and a bitmap 24 to indicate the update status of the cache lines in the tensor. When all cache lines of a tensor are updated, the metatable 21 increments the VN. This can be confirmed by checking whether the status (updated status) of the corresponding bitmap 24 area in the metatable 21 is the same.

[0139] For details, please refer to Figure 8 As shown, when a memory access arrives, Tensor Analyzer 2 has three access situations: hit, boundary hit, and miss.

[0140] A hit indicates that the memory access hits the address range of a certain entry in the meta table 21, and then the corresponding VN will be transmitted to the encryption / decryption module 3 to start the encryption / decryption process.

[0141] A boundary hit indicates that a memory access hits the boundary of the address range of an entry in metatable 21 (for example, if an entry ranges from 0x04 to 0x12 and has a stride of 4, then 0x00 and 0x10 are hit boundaries). In this case, the correctness of the VN cannot be guaranteed. In this case, the VN is still sent to the MEE, assuming it is correct, and an access to the VN in the dynamic random access memory (DRAM) is initiated. If the VN in the DRAM matches the assumed VN, the relevant entry in metatable 21 is updated and the address range is expanded.

[0142] A miss indicates that there is no match in the metatable 21, then the VN is obtained through DRAM access, and this memory access is sent to the tensor filter 22 for subsequent pattern detection and filtering (a pattern such as a sequential address pattern with stride. Filtering is to find the tensor filter 22 entry that meets the above pattern and fill it into the metatable 21, which is equivalent to finding a tensor structure).

[0143] In one embodiment of the above method of the present invention, the step of providing memory protection of a unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer 2 further includes:

[0144] Aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor;

[0145] Utilizing the tensor message authentication code management module in the tensor analyzer 2 and the tensor message authentication code management module in the memory control unit 1 in the neural network processor, tensor-level message authentication code delayed verification is provided for data interaction between the neural network processor and the central processing unit;

[0146] A direct data transmission protocol is used for data exchange between the central processing unit and the neural network processor.

[0147] In one embodiment of the above method of the present invention, the step of aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor further includes:

[0148] When the address range of the central processing unit tensor and the address range of the neural network processor tensor overlap by an alignment threshold of the address range of the central processing unit tensor, the address range of the central processing unit tensor is replaced with the address range of the neural network processor tensor.

[0149] Specifically, in order to achieve direct data transmission between the CPU and NPU enclaves, the tensor structures in the two should match each other. However, the tensor structure obtained by the hardware based on the present invention has a boundary problem and cannot be guaranteed to be completely consistent with the tensor structure in the NPU. In this case, data transmission still needs to be re-encrypted and decrypted, resulting in low communication efficiency. In order to solve the inconsistency problem, in one embodiment of the present invention, the tensor structure in the CPU is aligned with the NPU. The data transmission instructions between the CPU and NPU usually include tensor structure information, such as Figure 7 The tensor address, size, and stride are shown. Because the NPU has an explicit tensor structure from the kernel, the CPU tensor is aligned with the tensor structure in the NPU data transfer request. In one embodiment, if the address range of a CPU tensor overlaps with the address range of the tensor transferred from the NPU by more than an alignment threshold (e.g., 50%) of the CPU tensor range, the CPU address range is replaced with the NPU tensor range. After the request handshake, the tensor analyzer 2 uses the request to update the metatable 21.

[0150] In one embodiment of the above method of the present invention, the tensor-level message authentication code delayed verification step further includes:

[0151] The calculation of the decrypted data of the tensor is performed in parallel with the regeneration of the tensor message authentication code;

[0152] After completing the regeneration of the tensor message authentication code, performing integrity verification on the tensor;

[0153] If the integrity verification fails, the neural network processor enclave discards the tensor that failed the integrity verification and requests the CPU enclave to retransmit the tensor that failed the integrity verification;

[0154] The CPU enclave maintains a failure counter to record the number of tensor integrity verification failures. If the number of failures exceeds a failure threshold, the tensor integrity verification is suspended and an exception is reported.

[0155] Specifically, the granularity of MAC is a trade-off between storage overhead and verification overhead. Cache-line-by-cache-line MAC results in high storage overhead in the NPU, which further restricts the deployment of LLM workloads on the NPU due to its limited memory capacity.

[0156] Please refer to Figure 9 In the figure, white blocks represent DRAM access, blue blocks represent decryption, gradient orange blocks (including light orange, orange, and dark orange blocks) represent MAC recalculation, green blocks represent MAC verification, and gray blocks represent the calculation process. Recent studies have chosen a 512-byte MAC granularity to establish a balance between storage overhead and verification delay. However, using a large granularity MAC will result in excessively long verification delays, such as Figure 9 As shown in (b), the calculation of the decrypted data is paused.

[0157] To reduce storage overhead while ensuring low verification latency, this paper leverages the collaborative nature of LLM computing and introduces tensor-level delayed integrity verification. During collaborative LLM training, weights and data in the NPU are transferred from the CPU via communication. In other words, the NPU data is backed up in the CPU, enabling rollback in the event of a MAC verification failure.

[0158] The existence of the rollback mechanism makes it possible to delay MAC verification. In one embodiment of the present invention, the calculation of the decrypted data ( Figure 12 The middle grey area) is performed in parallel with the regeneration of the tensor MAC, as Figure 9 As shown in (c) in the figure. After completing the tensor-level MAC, the integrity of the entire tensor is verified. In this way, the storage overhead and memory traffic are significantly reduced, while avoiding the following problems: Figure 9 (b) shows a long pause due to MAC verification. If verification fails, the NPU enclave discards the relevant tensor and sends a request to the CPU enclave to retrieve the tensor data, then restarts verification and computation. The enclave maintains a failure counter, Counter_fault, to record the number of verification failures, incrementing the counter each time a tensor verification fails. If this counter exceeds the failure threshold, execution is paused and an exception is thrown. This mechanism enables the present invention to achieve enhanced fault tolerance without compromising security. The tensor message authentication code management module is located in the CPU's tensor analyzer 2 and the NPU's tensor manager 4.

[0159] For tensor-level MAC calculations, a simple and efficient algorithm is used that involves performing an XOR operation on the MAC values ​​of all cache lines, similar to Intel SGX. The algorithm can be expressed as follows, where MAC_i represents the MAC value of the i-th cache line in the tensor, and n is the number of cache lines: Because the XOR algorithm is not sensitive to order, the design of this invention is compatible with various optimization operations such as tensor splitting in NPU calculations (such as dot products, dot additions, matrix multiplications, convolutions, etc.).

[0160]

[0161] In one embodiment of the above method of the present invention, the step of using the direct data transmission protocol to perform data exchange between the central processing unit and the neural network processor further includes:

[0162] Authentication phase processing;

[0163] Data transmission phase processing.

[0164] In one embodiment of the above method of the present invention, the identity verification stage processing step further includes:

[0165] The CPU creates the first enclave and obtains the first enclave report;

[0166] The central processor requests the neural network processor to create a second enclave and obtains a second enclave report;

[0167] The first enclave and the second enclave conduct mutual authorization based on the first enclave report and the second enclave report;

[0168] The CPU and the NPU use the same key during data encryption and decryption to authenticate between the first and second enclaves.

[0169] In one embodiment of the above method of the present invention, the data transmission phase processing step further includes:

[0170] Trusted metadata data transmission, which transmits data including the tensor address range through the trusted encrypted channel created in the authentication phase;

[0171] Direct tensor transfer, for tensor data corresponding to the tensor address range, is directly transferred between the dynamic random access memory of the central processing unit and the dynamic random access memory of the neural network processor.

[0172] Specifically, regarding the direct data transmission protocol implemented by the present invention: the protocol eliminates the need for re-encryption and decryption, and achieves parallelism between calculation and data transmission.

[0173] Optimization based on unified tensor granularity: Existing heterogeneous CPU and NPU TEEs have different memory protection granularities, which leads to significant overhead in data transmission between the CPU and NPU enclaves: First, data transmission relies on non-secure memory areas for transit, which incurs re-encryption overhead. Second, because both computation and data transmission rely on re-encryption, the limited Advanced Encryption Standard (AES) bandwidth makes data transmission and computation in parallel.

[0174] Based on the unified tensor management granularity proposed in this invention to reduce data transmission overhead, the optimized data flow is as follows Figure 10 (In the figure, the blue blocks represent NPU reverse calculations, the yellow blocks represent gradient data transmission, the pink blocks represent encryption and decryption calculations, and the dotted shaded blocks represent encryption and decryption occupancy). On the one hand, the enclaves of the CPU and NPU have a unified tensor data structure, which means that the off-chip encrypted memory can be decrypted on both sides. Therefore, data transmission between the two does not need to rely on transmission in the non-secure area, which makes direct data transmission between secure areas possible. On the other hand, after eliminating the need for AES for data transmission, the AES limitation that restricts parallel scheduling optimization is broken. Based on a unified management granularity, data transmission (communication data transmission) is hidden in the calculation, which greatly reduces the data transmission overhead, that is, parallelizing communication and calculation. By eliminating AES occupancy, data transmission can be executed in parallel with calculation. In other words, communication is not on the critical path, eliminating its overhead.

[0175] Protocol implementation: The protocol mainly consists of two stages: authentication and data transmission.

[0176] Authentication Phase: During the authentication phase, the CPU and NPU establish mutual trust through remote attestation and cryptographic key exchange. First, at the start of workload execution, the CPU initiates the enclave creation process, copies code and data from non-secure memory to secure memory, and obtains the enclave's report. Second, the CPU enclave sends an enclave creation request to the NPU, which uses a similar process to create an NPU enclave without code or data. The two enclaves then mutually authorize each other based on the report.

[0177] To achieve low-cost data transmission, the CPU and NPU TEEs share the same key during encryption and decryption. After authentication, a key exchange protocol similar to Diffie-Hellman is performed between the two enclaves, allowing the same key to be used in both enclaves without leaking key information. After the exchange, the key remains stored in on-chip memory for security.

[0178] Communication phase: In the data transmission phase, there are two types of transmission, namely, cell data transmission and direct tensor transmission. This process is described by taking the data transmission from CPU to NPU as an example. Figure 7 As shown in the architecture overview, during the metadata transmission phase, the NPU sends a data transmission request containing the tensor address range. The CPU memory controller queries the meta table 21 to obtain the metadata. The obtained tensor VN, MAC, and address are transmitted to the NPU through a trusted encryption channel for subsequent decryption and verification. At the same time, the tensor data corresponding to the address range is directly transferred from the CPU DRAM to the NPU's DRAM, without involving a direct channel between the CPU and the NPU. It should be pointed out that these two stages (trusted metadata transmission and direct tensor transmission) can be executed in parallel, and only a synchronization mechanism is required after the transmission is completed (the transmission is considered to be completed only after both channels have completed the transmission (the amount of trusted metadata data is small and the transmission time is short, so it is necessary to wait for the direct tensor transmission to end).

[0179] The present invention also discloses a heterogeneous trusted execution environment architecture construction device 10, which is used to execute any of the above methods, including:

[0180] A tensor analyzer construction module 11 is used to construct a tensor analyzer 2, wherein the tensor analyzer 2 is located in a memory control unit 1 of a central processing unit of a heterogeneous trusted execution environment architecture;

[0181] The memory protection module 12 with unified tensor granularity is used to provide memory protection with unified tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer 2.

[0182] The present invention also discloses a heterogeneous processor 100, including a central processing unit, a neural network processor, a memory 110 and an input and output unit 120 that are interconnected, and also includes the above-mentioned heterogeneous trusted execution environment architecture construction device 10.

[0183] The memory may include nonvolatile and / or volatile memory. Nonvolatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0184] The present invention discloses a storage medium for storing a computer control program, wherein the computer control program is used to execute the steps of any one of the above methods.

[0185] The computer program that can be executed by the processor can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the technical field.

[0186] Experimental results:

[0187] CPU simulator: In order to evaluate the performance of CPU workloads on baseline SGX and the TensorTEE architecture of the present invention, the Gem5 simulator is extended with the baseline SGX security mechanism and the tensor-based memory protection mechanism proposed in the present invention. Gem5 is a cycle-accurate event-driven CPU performance simulator that supports multi-core, full-system and memory simulation. SGX adds a 56-bit VN and MAC to each cache line, and adds an 8-ary Merkle tree. Each memory request reaching the memory controller triggers additional access for VN and MAC. MEE performs decryption operations on read requests and encryption operations on write requests. MEE adds a metadata cache to reduce the pressure of accessing VN or MAC. For the TensorTEE architecture of the present invention, the present invention implements the metatable and tensor filtering components in Gem5. In order to meet the requirements of collaborative computing, a multi-core out-of-order CPU and a multi-channel large-capacity DRAM were selected.

[0188] The NPU simulator adopts the TPU architecture, including the array of compute units (PEs), on-chip temporary memory, and control logic. The simulator uses static data flow outputs and combines automatic slicing and inter-layer optimization. Simulation comparisons show that the simulator achieves computational performance similar to that of the A100 GPU. The NPU simulator is extended by implementing an on-chip VN management and memory protection component similar to MGX between the NPU and DRAM.

[0189] Communication: To evaluate the communication performance between the CPU and NPU, we modeled a Graviton-based basic protocol and the proposed direct data transfer protocol. We then performed communication simulations using CPU and NPU simulators along with a communication simulator. We used the commonly used PCIe 4.0*16 bus as the communication bus between the CPU and NPU.

[0190] The inventors selected various popular large-scale language model architectures as workloads, with model parameter sizes ranging from 100 million to 7 billion. The inventors employed the dataflow scheduling method from the DeepSpeed ​​framework and optimized collaborative heterogeneous computing. In this paper, the inventors focused on the scenario of LLM training using a host multi-core CPU and a single NPU. To accommodate the NPU's memory capacity, different batch sizes were selected for different models. Three configurations were compared in the experiments: 1) Non-secure configuration: In this setup, neither the CPU nor the NPU utilizes isolation and memory protection mechanisms like TEE. This configuration serves as a performance reference. 2) CPU SGX + NPU MGX configuration: In this setup, the CPU utilizes a cache line granularity protection mechanism similar to SGX, while the NPU utilizes a tensor granularity protection mechanism similar to MGX. Due to the granularity mismatch, communication between the CPU and NPU requires additional encryption and decryption. 3) TensorTEE: In this setup, performance improvements were achieved using the tensor-based management method and optimization techniques proposed in this paper.

[0191] Total performance improvement: According to Figure 13 (Blue tiles represent non-secure environments, orange tiles represent SGX+MGX environments, and grey tiles represent the architecture of the present invention) and Figure 14 (Blue tiles represent NPU, orange tiles represent CPU, light grey tiles represent weight communication, dark grey tiles represent gradient communication), we can draw the following observations: 1) Figure 13 It is shown that the baseline SGX+MGX approach incurs considerable overhead. In addition, Figure 14It is shown that this overhead mainly comes from the communication process of weights and gradients. 2) The TensorTEE architecture of the present invention shows significant performance improvements over the baseline method. Compared with the baseline, the maximum performance improvement of the TensorTEE architecture of the present invention can reach 6 times, and the average improvement is 4.5 times. In addition, compared with the non-secure configuration, the average performance overhead of the TensorTEE architecture of the present invention is only 2.2%. 3) The performance of the TensorTEE architecture of the present invention improves significantly as the model size increases. Large models lead to more communication and CPU computation, as shown in Figure 13 As shown, this provides more optimization opportunities for the TensorTEE architecture of the present invention, resulting in a significant performance improvement.

[0192] Performance improvement of tensor-granular CPU TEE: LLM training requires thousands of iterations to update model parameters. Figure 15 (The blue line indicates the hit situation, the orange line indicates the hit situation, and the gray line indicates the hit boundary situation) illustrates the two access hit modes in the Meta table when the CPU uses the Adam optimizer for update at different numbers of iterations. "hit_in" indicates that the memory address is successfully matched in the Meta table, while "hit_boundary" indicates that the boundary of the existing pattern is hit; "hit_all" indicates that the hit situation includes hit_in and hit_boundary. It can be observed that the average hit_all is already high enough after one iteration, and gradually converges to 1 as the number of iterations increases. As for the average hit_in, it reaches 80% at the 5th iteration and 95% at the 20th iteration. The fast convergence and high accuracy of Meta table access prove the effectiveness of the tensor-based management design of the present invention.

[0193] Figure 16The figure (blue tiles represent 4-thread performance overhead, orange tiles represent 8-thread performance overhead) shows the average performance overhead of the VN tensor management proposed by the TensorTEE architecture, compared to SGX and SoftVN at different iteration numbers. The following observations can be made from the figure: 1) The baseline SGX approach incurs significant overhead, reaching a 3.65x performance overhead at 8 threads. SGX's encryption and decryption overhead, as well as the additional memory accesses, significantly impacts memory-intensive Adam workloads on the CPU. Furthermore, as the number of threads increases, memory pressure increases, leading to further performance overhead. 2) Once the Meta table is established, the TensorTEE architecture of the present invention exhibits a significant performance advantage as the number of iterations increases. It can be observed that, except for the higher overhead of the initial iterations, the performance overhead decreases to 11% after 10 iterations in the 8-thread configuration. Considering that LLM training typically involves tens of thousands of iterations, the overhead of the initialization phase is negligible. Therefore, the performance of the TensorTEE architecture of the present invention is generally comparable to that of SoftVN. It is worth noting that the MAC delayed verification proposed by the inventive architecture TensorTEE reduces MAC memory access and MAC verification, resulting in performance gains that exceed the VN optimization provided by SoftVN.

[0194] Improvements to delayed validation: Figure 17 (The blue block represents the non-secure environment, and the orange block represents MGX) shows the performance comparison and storage overhead of NPU TEE at different MAC granularities. It can be observed that the storage overhead decreases as the MAC granularity increases. However, although the performance is improved at smaller granularities due to fewer additional memory accesses, at larger granularities greater than 256B, the overhead increases with the increase in granularity due to the aggravation of the blocking problem. Previous works such as MGX chose a MAC granularity of 512B to minimize storage and memory access overhead, but resulted in a performance loss of 9.0%. In contrast, the MAC tensor-based management proposed in the present invention reduces the storage overhead to a negligible level. In addition, due to the benefits of delayed verification, the performance loss is only 3.8%.

[0195] Improvements to data transfer protocols: Figure 18(Dark gray blocks represent re-encryption, orange blocks represent communication, and light gray blocks represent decryption) shows the overhead ratio of different operations during communication. The following observations can be made from the figure: 1) Due to granularity mismatch, re-encryption and decryption operations are introduced before and after communication to align the granularity. 2) The existence of re-encryption and decryption prevents the parallelization of gradient transmission and gradient calculation of NPU. Therefore, the communication time is further increased. The TensorTEE architecture of the present invention eliminates the need for re-encryption and decryption, allowing parallel execution of communication and calculation. As a result, the communication performance is improved by 18.3 times.

[0196] Based on the above invention, the present invention discloses a heterogeneous trusted execution environment architecture construction method, device, and heterogeneous processor, which achieves matching of CPU and NPU granularity in the heterogeneous TEE architecture, reduces additional storage and performance overhead, and implements delayed-verifiable tensor granularity MAC management based on tensor backup, thereby reducing storage overhead and additional memory access. Through the implementation of a direct data transmission protocol, a unified heterogeneous tensor granularity TEE facilitates direct data transmission in secure memory, eliminating transit through non-secure areas, thereby eliminating the need for re-encryption and decryption, and further achieving parallelization of data transmission and computation.

[0197] In summary, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may evolve various corresponding changes and deformations based on the present invention, but these corresponding changes and deformations should all fall within the scope of protection of the patent applied for the present invention.

Claims

1. A method for constructing a heterogeneous trusted execution environment architecture, characterized in that: The following steps are involved: Building a tensor analyzer, wherein the tensor analyzer is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; The tensor analyzer provides memory protection with unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit.

2. The method according to claim 1, wherein The step of building a tensor analyzer is done by implementing memory management.

3. The method according to claim 2, wherein The steps of building a tensor analyzer by implementing memory management further include: Build a unary table to maintain the tensor data structure; Constructing a tensor filter for maintaining the metatable when a metatable entry is missing; The metatable is maintained according to memory access received by the tensor analyzer from the computing core of the central processing unit.

4. The method according to claim 3, wherein The steps to build a tensor analyzer by implementing memory management also include: Determining a data protection type based on the memory access address and the memory region binding register; A bitmap is used to indicate the update status of the tensor cache line in the metatable.

5. The method according to claim 4, wherein The step of maintaining the metatable according to the memory access received by the tensor analyzer from the computing core of the central processing unit further includes: Processing when the address of a memory access hits the address of an entry in the metatable; Processing when the address of a memory access does not hit the address of an entry in the metatable; Processed when the address of a memory access hits the address boundary of an entry in the metatable.

6. The method according to claim 5, wherein When the address of the memory access hits the address of an entry in the metatable, the processing step further includes: The memory access address and version number are sent to the encryption and decryption module for encryption for subsequent operations.

7. The method according to claim 5, wherein The processing step further includes: Access the memory and obtain data information and version number; Send the data information and version number to the encryption and decryption module for encryption for subsequent operations; Send data information and version number to tensor filter for recording or updating; Tensor filters record or update the metatable.

8. The method according to claim 5, wherein The processing step further includes: Send the memory access address and version number to the encryption and decryption module for encryption; Access the memory and obtain data information and version number; If the version number of the memory access is consistent with the version number obtained by accessing the memory, the corresponding entry in the metatable is updated using the data information obtained by accessing the memory.

9. The method according to claim 3, wherein The step of maintaining the metatable according to the memory access received by the tensor analyzer from the computing core of the central processing unit further includes: When checking through the bitmap that all cache line update states corresponding to a tensor in the metatable are updated, the version number of the tensor is increased.

10. The method according to claim 1, wherein The step of providing memory protection of a unified tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer further includes: Aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor; Utilizing the tensor message authentication code management module in the tensor analyzer and the tensor message authentication code management module in the memory control unit of the neural network processor to provide tensor-level message authentication code delayed verification for data interaction between the neural network processor and the central processing unit; A direct data transmission protocol is used for data exchange between the central processing unit and the neural network processor.

11. The method according to claim 10, wherein The step of aligning the tensor structure of the transmission data of the central processing unit with the tensor structure of the transmission data of the neural network processor further includes: When the address range of the central processing unit tensor and the address range of the neural network processor tensor overlap by an alignment threshold of the address range of the central processing unit tensor, the address range of the central processing unit tensor is replaced with the address range of the neural network processor tensor.

12. The method according to claim 10, wherein The tensor-level message authentication code delayed verification step further includes: The calculation of the decrypted data of the tensor is performed in parallel with the regeneration of the tensor message authentication code; After completing the regeneration of the tensor message authentication code, performing integrity verification on the tensor; If the integrity verification fails, the neural network processor enclave discards the tensor that failed the integrity verification and requests the CPU enclave to retransmit the tensor that failed the integrity verification; The CPU enclave maintains a failure counter to record the number of tensor integrity verification failures. If the number of failures exceeds a failure threshold, the tensor integrity verification is suspended and an exception is reported.

13. The method according to claim 10, wherein The step of using the direct data transmission protocol to perform data interaction between the central processing unit and the neural network processor further includes: Authentication phase processing; Data transmission phase processing.

14. The method according to claim 13, wherein The identity verification phase further includes: The CPU creates the first enclave and obtains the first enclave report; The central processor requests the neural network processor to create a second enclave and obtains a second enclave report; The first enclave and the second enclave conduct mutual authorization based on the first enclave report and the second enclave report; The CPU and the NPU use the same key during data encryption and decryption to authenticate between the first and second enclaves.

15. The method according to claim 14, wherein The data transmission phase processing steps further include: Trusted metadata data transmission, which transmits data including the tensor address range through the trusted encrypted channel created in the authentication phase; Direct tensor transfer, for tensor data corresponding to the tensor address range, is directly transferred between the dynamic random access memory of the central processing unit and the dynamic random access memory of the neural network processor.

16. A device for constructing a heterogeneous trusted execution environment architecture, for executing the method according to any one of claims 1 to 15, characterized in that: include: A tensor analyzer building module, configured to build a tensor analyzer, wherein the tensor analyzer is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; A memory protection module with unified tensor granularity is used to provide memory protection with unified tensor granularity for data interaction between a neural network processor of a heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

17. A heterogeneous processor comprising a central processing unit, a neural network processor, a memory and an input / output unit connected to each other, characterized in that: It also includes the heterogeneous trusted execution environment architecture construction device as described in claim 16.

18. A storage medium for storing a computer control program, characterized in that: The computer control program is used to execute the steps of the method according to any one of claims 1 to 15.

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