Multi-channel cooperative communication method

Abstract

The invention discloses a multi-path cooperative communication method, belongs to the technical field of wireless communication, and is used for solving the problems of inaccurate path selection, unreasonable power distribution and inaccurate signal combination caused by dynamic change of a channel state in multi-path communication. The method comprises the following steps: acquiring channel state information of at least three communication paths in real time through a transmitting end, wherein the channel state information comprises signal strength, frequency offset and noise power spectral density; dynamically dividing and distributing the data stream to each path based on the path quality factor, and adjusting the transmitting power by combining the signal strength and the noise difference value; a receiving end carries out time domain alignment by adopting a sliding window cross-correlation algorithm, and carries out phase compensation based on a minimum mean square error criterion; path reallocation is triggered when the continuous bit error rate exceeds a threshold. According to the method, the multi-path resource utilization rate can be optimized, and the communication stability and the data transmission efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of communications, and more specifically, to a multi-channel cooperative communication method. Background Art

[0002] In multipath cooperative communication systems, existing technologies present several pressing challenges. Traditional methods for path quality assessment typically rely on a single parameter or static threshold. For example, they focus solely on signal strength while ignoring the combined effects of frequency offset and noise. Because parameters such as frequency offset and ambient noise power spectral density in channel state information have different dimensions, direct quantitative comparison is difficult, leading to biased path quality assessment results. This bias can prevent high-interference paths from being promptly identified, allowing low-quality paths to continue transmitting critical data, ultimately degrading communication link performance. Furthermore, the dynamic transmit power adjustment strategy lacks correlation with real-time signal-to-noise ratio changes. Fixed step-size designs are prone to power fluctuations in low signal-to-noise ratio ranges, and significant response delays in sudden interference scenarios further exacerbate link instability.

[0003] When it comes to signal merging at the receiving end, multipath delay differences make signal alignment difficult. Traditional methods use a fixed-length sliding window for time domain alignment, but the window length cannot adapt to the dynamically changing delay spread range. When multipath interference exists in the channel, the main peak detection of the cross-correlation algorithm is easily interfered with by secondary peaks, and existing technologies lack a mechanism to dynamically expand the window based on the number of secondary peaks, resulting in continuous accumulation of alignment errors. In addition, in high-speed mobile scenarios, the carrier frequency offset changes rapidly over time. Traditional phase correction models only compensate based on the current frequency offset value and do not consider the dynamic correction of the frequency offset change rate. The residual frequency offset problem is difficult to completely eliminate, seriously affecting the accuracy of signal merging.

[0004] The optimization of correction parameters also has obvious limitations. Existing technologies lack unified evaluation standards for the joint correction of phase and amplitude distortion. Usually, error functions are only designed for a single type of distortion, making it difficult to balance the combined impact of the two types of distortion on system performance. In addition, the weight coefficients of pre-distortion technology are usually fixed and cannot be dynamically adjusted according to long-term changes in the channel, resulting in the correction effect degrading with the environment. In power adjustment and path allocation strategies, the utilization efficiency of historical data is low, and the prediction model does not effectively integrate the time attenuation factor, making it difficult to accurately capture the gradual trend of channel status. When faced with high-frequency channel fluctuations, traditional prediction algorithms converge slowly due to their high computational complexity. In actual deployment, it is necessary to repeatedly balance resource overhead and prediction accuracy, further increasing the difficulty of system design.

[0005] The causes of these problems involve the inherent contradictions between multi-dimensional parameter fusion, dynamic adaptation mechanisms, and algorithmic complexity. For example, path quality assessment requires normalizing parameters of different dimensions, but the selection of normalization coefficients lacks a theoretical basis and is prone to introducing subjective biases. Dynamic window adjustment requires a balance between delay measurement accuracy, computational real-time performance, and hardware resource consumption, and the quantitative standards for expansion conditions are difficult to unify. In addition, high-frequency operations in intensive correction mode place extremely high demands on the processor's parallel computing capabilities, while adaptive parameter adjustment under long-term channel changes requires a balance between stability and sensitivity. The closed-loop coupling design of bit error rate feedback and correction parameters faces the dual challenges of algorithm convergence and real-time performance. Summary of the Invention

[0006] An object of the present invention is to solve at least the above problems and to provide at least the advantages which will be described hereinafter.

[0007] In order to achieve these objectives and other advantages according to the present invention, a multi-channel cooperative communication method is provided, comprising: The channel state monitoring module deployed at the transmitter acquires channel state information of at least three independent communication paths in the target area in real time. The channel state information includes the current signal strength measurement value, frequency offset, and ambient noise power spectrum density of each communication path. In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel status monitoring module and the ambient noise power spectrum density. When the path quality factor falls below a preset switching threshold, the load weight of the communication path is reduced by 40-60%. In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectrum density; The signal merging module at the receiving end performs time domain alignment and phase compensation on the data sub-blocks from each communication path. The time domain alignment uses a cross-correlation algorithm with a sliding window length of 8 to 32 μs. The phase compensation uses pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6 to π / 6. A bit error rate monitoring unit is set in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10 -4 When the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

[0008] In multipath communications, dynamic changes in channel states can lead to inaccurate path selection, irrational power allocation, and time delays and phase mismatches when signals are combined at the receiving end, degrading overall communication quality. This invention optimizes path selection efficiency through real-time channel monitoring and dynamic load distribution. Combining power adjustment with signal combining techniques improves multipath signal alignment accuracy, reduces bit error rates, and enhances communication stability.

[0009] Preferably, the method for calculating the path quality factor includes: normalizing the frequency offset and the ambient noise power spectrum density, wherein the normalization coefficient of the frequency offset is 1 / (15kHz), and the normalization coefficient of the ambient noise power spectrum density is 1 / (10 -3 W / Hz), generating a dimensionless path quality factor Q = Δf norm ×P noise_norm , where Δf norm is the normalized frequency offset, P noise_norm is the normalized power spectrum density of ambient noise; The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio according to the difference between the path quality factor Q and the switching threshold, and when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5×10 -3 The unit Q value corresponds to a 10% increase in weight reduction, and the upper limit of the weight reduction is 60% and the lower limit is 40%; During data sub-block segmentation, delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to communication paths with Q values ​​greater than 1.2 times the switching threshold based on historical bit error rate statistics of the communication paths. The length of the delay-sensitive data sub-blocks is set to 256 bytes to 512 bytes. Add a path allocation identification field to each data sub-block. This field contains the Q value verification code of the target communication path and the sequence check code of the data sub-block. The Q value verification code is generated by retaining three significant digits of the binary floating point number of the Q value. When the load weight of the communication path is adjusted downward, the remapping operation of the data sub-block is triggered, and the data sub-blocks that have not been transmitted in the original path are reallocated in descending order of Q value to the communication path whose current Q value is higher than the switching threshold.

[0010] Traditional path quality assessments lack normalization, resulting in inconsistent quantification standards across parameters (such as frequency offset and noise) and an inability to effectively prioritize data allocation strategies. This invention achieves standardized evaluation of multi-dimensional parameters by calculating a normalized path quality factor (Q). Combined with a priority allocation strategy, this approach prioritizes critical data transmission on paths with high Q values, improving resource utilization efficiency.

[0011] Preferably, the power control module dynamically adjusts the transmit power of each communication path according to the difference between the real-time measured signal strength and the ambient noise power spectrum density, specifically including: Establish a mapping relationship between the transmit power adjustment amount and the signal strength-noise difference ΔS. ΔS is defined as the difference between the current signal strength measurement value and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step size is used for adjustment. When ΔS is in the range of -85 to -70 dBm, a 0.5 dB step size is used for adjustment. During the power adjustment process, the instantaneous interference mutation rate of the target communication path is monitored simultaneously. When the ΔS change after two consecutive power increases is less than 20% of the adjustment step size, the burst interference suppression mode is activated, the transmit power adjustment period is shortened from 100ms to 50ms, and the step size is increased to 150% of the original step size. A power adjustment history table is established for each communication path, recording a triplet of data including a timestamp, a ΔS value, and the actual transmit power value. When a ΔS fluctuation of more than 15dB within 300ms is detected, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the most recent five cycles in the history table. After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is terminated and the backup frequency band is switched; A saturation protection mechanism is set for transmit power adjustment. When the cumulative power increase of a single communication path reaches 25% of the initial transmit power, a cross-path power rebalancing operation is triggered. The power value exceeding the threshold is proportionally distributed to other communication paths with Q values ​​higher than 1.5 times the switching threshold.

[0012] Fixed-step power adjustment strategies cannot adapt to varying noise environments, and the power response lags under sudden interference, increasing the risk of link interruption. This invention optimizes power control sensitivity by dynamically adjusting the step size within the ΔS interval. It also shortens response time through a burst interference suppression mode, reducing the impact of sudden interference on the communication link.

[0013] Preferably, the step length correction coefficient of the next adjustment period is predicted based on the ΔS gradient values ​​of the latest five periods in the history table, specifically including: The ΔS gradient values ​​of the last five cycles were processed by a cubic polynomial fitting algorithm to generate a prediction model including a time decay factor, which was calculated as 0.8. n The exponential law of decaying historical data weights is used, where n represents the number of intervals between the current cycle and the historical cycle; Substitute the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max+β·G min , where α is 0.6~0.8, β is 0.2~0.4, G max and G min Represent the maximum and minimum absolute values ​​of gradients within five cycles respectively; The step size correction coefficient K=1+0.15·sign(∂G / ∂t)·|∂G / ∂t| is generated based on the equation solution. 0.5 ,When the K value exceeds the range of 0.7-1.3, it is forced to be limited to the interval endpoint value and triggers the prediction model parameter reset; After each power adjustment operation is performed, the actual ΔS change gradient and the predicted gradient are compared to calculate the residual. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, it automatically switches to the moving weighted average prediction mode, which uses the weight distribution of 60%, 30%, and 10% of the gradient values ​​of the previous three cycles; Configure the validity duration parameter for the correction coefficient K. When K is greater than 1, the validity duration is set to 150-300 ms. When K is less than 1, the validity duration is set to 400-600 ms. During the validity period, power rebalancing operations on other communication paths are frozen.

[0014] Traditional power adjustment relies on current state data and lacks historical trend prediction, causing the adjustment strategy to lag behind rapid channel changes. This invention utilizes cubic polynomial fitting and historical gradient prediction to improve the forward-looking nature of power adjustment. A residual monitoring mechanism adaptively switches the prediction model to enhance robustness in nonlinear environments.

[0015] Preferably, the time domain alignment adopts a cross-correlation algorithm with a sliding window length of 8 to 32 μs, specifically including: Calculate the maximum delay difference Δτ between each communication path at the receiver end and set the basic length of the sliding window to 3 to 5 times Δτ, constrained to the range of 8 to 32 μs. Δτ is calculated by the timestamp difference between adjacent path data sub-blocks. During the execution of the cross-correlation algorithm, the number and amplitude of correlation peaks are monitored in real time. When two or more secondary peaks are detected within the 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value. The extended window length does not exceed 32μs. The window movement step size is dynamically modified according to the data sub-block length. When the data sub-block length is 256-512 bytes, the step size is set to 1 / 8-1 / 4 of the window length. When the data sub-block length is 1024-2048 bytes, the step size is reduced to 1 / 16-1 / 12 of the window length. Doppler frequency shift pre-correction is performed synchronously during the window sliding process. The signal samples in the window are phase rotated using the carrier frequency offset measurement value. The rotation angle θ=2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points in the window. After each window adjustment, the alignment effect is verified through the bit error rate monitoring unit of the feedback link. If the bit error rate of three consecutive data sub-blocks after adjustment does not decrease by 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

[0016] Multipath delay variations prevent precise alignment of signals at the receiving end, especially in dynamic channels where fixed window parameters deteriorate the merging effect. This invention dynamically adjusts the sliding window length and step size to match channel delay characteristics. This approach, combined with secondary peak detection and window expansion, suppresses multipath interference and improves time-domain alignment accuracy.

[0017] Preferably, Doppler frequency shift pre-correction is synchronously performed during the window sliding process, and the signal samples in the window are phase rotated using the carrier frequency offset measurement value, specifically including: Calculate the rate of change of Δf in real time during the window sliding process rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two adjacent frequency offset measurements. The phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t; Set the phase rotation angle constraint. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz. After the phase rotation operation, residual frequency offset compensation is performed and the compensation factor C is calculated based on the divergence of the constellation diagram of the rotated signal. measured / EVM threshold ), where EVM measured is the measured error vector magnitude, EVM threshold Set to 8-12%, the compensation factor is applied to the Δf measurement values ​​of subsequent windows to form a closed-loop correction; A segmented correction strategy is used. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the intensive correction mode is activated, increasing the execution interval of the phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value. After each window sliding, the correction effect is verified by comparing the mean change in θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimated value is written to the frequency calibration field of the path allocation table.

[0018] In high-speed mobile scenarios, Doppler frequency shift leads to phase rotation error accumulation, and traditional correction methods cannot track fast frequency deviation changes in real time. This invention introduces the frequency deviation change rate Δf rate Correct the phase rotation angle and dynamically compensate for the Doppler effect; closed-loop compensation and segmented correction strategies further eliminate residual frequency offset and ensure signal integrity under high-speed movement.

[0019] Preferably, the phase compensation adopts predistortion correction based on the minimum mean square error criterion, specifically including: Construct a joint error function E = γ·(Δε) that includes phase difference and amplitude fluctuation 2 +δ·(ΔA / A ref ) 2 , where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The value is set to 80-120% of the average amplitude of the received signal, the weight coefficient γ is set to 0.6-0.8, and the weight coefficient δ is set to 0.2-0.4; The minimum value of the error function is solved by the recursive least squares algorithm to generate a predistortion vector containing the I / Q correction amount. The constraint step parameter μ is 0.05~0.15 during the iterative calculation process, and the residual convergence threshold is set to 1×10 -4 ~5×10 -4 ; The predistortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the paths with a phase difference Δε exceeding π / 12. In the second stage, the remaining paths are progressively compensated using 50-70% of the correction vector. After the correction operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification indicator. When the EVM measurement value is higher than 8%, the correction vector update module is triggered to recalculate the predistortion parameters in a period of 200-500ms. A dynamic adjustment mechanism for correction parameters is established to reversely correct the weight coefficients γ and δ according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is lower than 10% / sub-block, γ will be increased by 5% to 10% and the corresponding proportion of δ will be reduced simultaneously.

[0020] A single error function cannot account for both phase and amplitude distortion, and traditional correction parameters are fixed, making them incapable of adapting to long-term channel variations. This invention combines weighted optimization of phase and amplitude errors to improve the comprehensiveness of pre-distortion correction. Dynamic adjustment of weight coefficients and a phased compensation strategy enable adaptive parameter optimization under long-term channel conditions.

[0021] Other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below with reference to the embodiments so that those skilled in the art can implement the invention with reference to the description.

[0023] The present invention provides a multi-channel collaborative communication method, comprising: The channel state monitoring module deployed at the transmitter acquires channel state information of at least three independent communication paths in the target area in real time. The channel state information includes the current signal strength measurement value, frequency offset, and ambient noise power spectrum density of each communication path. In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel status monitoring module and the ambient noise power spectrum density. When the path quality factor falls below a preset switching threshold, the load weight of the communication path is reduced by 40-60%. In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectrum density; The signal merging module at the receiving end performs time domain alignment and phase compensation on the data sub-blocks from each communication path. The time domain alignment uses a cross-correlation algorithm with a sliding window length of 8 to 32 μs. The phase compensation uses pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6 to π / 6. A bit error rate monitoring unit is set in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10 -4 When the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

[0024] Specifically, the channel state monitoring module can be deployed between the antenna array and the baseband processing unit at the transmitter, connected via the RF front-end circuit. This module can use a spectrum analyzer that supports multi-channel synchronous sampling, such as a device with at least three independent receiving channels. Its signal strength measurement range can be set to -100dBm to -50dBm, and the frequency offset measurement accuracy is ±0.1kHz. The measurement bandwidth of the ambient noise power spectral density can be set to 1MHz, with a resolution bandwidth of 10kHz. The module's circuit substrate material can be FR-4 epoxy resin laminate, and the RF connector can use an SMA interface.

[0025] Signals are extracted from each communication path via a directional coupler, amplified by a low-noise amplifier, and then fed into an analog-to-digital converter with a sampling rate of 20MS / s. Signal strength is measured using a logarithmic detection circuit. Frequency offset is calculated by comparing it with a reference clock using a digital phase detector, and noise power spectral density is extracted using an FFT spectrum analysis module. The channel status monitoring module should be installed close to the transmit antenna feed point to minimize the impact of transmission line losses on measurement accuracy.

[0026] The channel status monitoring module ensures the accuracy of channel status information through high-precision real-time monitoring, providing reliable input for subsequent path allocation and power control.

[0027] The priority allocation algorithm can be run on the FPGA chip or embedded processor at the transmitter. The number of blocks N for data stream segmentation can be set to 4 to 8 sub-blocks. The switching threshold of the path quality factor Q can be set to 0.6×10 -3 The load weight reduction range is 40%~60%, and the specific reduction ratio is linearly adjusted according to the difference between the Q value and the threshold. For example, when the Q value decreases by 0.5×10 -3 , the weight reduction increases by 10%. The length of the data sub-block can be configured as 256 bytes or 512 bytes. The delay-sensitive sub-blocks are preferentially allocated to the sub-blocks with a Q value higher than 0.72×10 -3 path.

[0028] During algorithm execution, the data stream segmentation module can be implemented using a circular buffer. The Q-value verification code of the path assignment identifier field uses the IEEE 754 single-precision floating-point format, retaining three significant digits. After load weight adjustment, unfinished data sub-blocks are redistributed in descending Q-value order to paths with Q-values ​​above a threshold. The relevant computing resources can be integrated into the shared memory of the baseband processing unit and communicate with the main control unit via the PCIe interface.

[0029] The data stream segmentation module optimizes data stream distribution efficiency, reduces the transmission load of high-interference paths, and improves overall communication reliability.

[0030] The power control module can be deployed before the power amplifier circuit on the transmitter side. The measurement period for the difference between signal strength and noise, ΔS, is 10ms. When ΔS is between -90 and -85dBm, the power adjustment step size is 2dB; when ΔS is between -85 and -70dBm, the step size is 0.5dB. The monitoring window for the transient interference mutation rate is 50ms. If the change in ΔS after two consecutive adjustments is less than 20% of the step size, the adjustment period is shortened to 50ms and the step size is increased to 150% of the original value. The power adjustment history table is stored in EEPROM with a recording interval of 100ms.

[0031] Transmit power is adjusted using a digitally controlled attenuator, which is converted into an analog control voltage via a DAC. The saturation protection mechanism's threshold is set at 25% of the initial power, with any excess distributed to other paths based on the Q factor. In burst interference suppression mode, the dynamic range of the power amplifier bias voltage is extended to ±5V to support rapid power switching.

[0032] The power control module implements refined control of transmit power to avoid power waste and suppress the impact of sudden interference on communication quality.

[0033] The signal merging module can be integrated into the digital signal processor at the receiving end. The sliding window length can be selected as 8μs, 16μs, or 32μs, and the window movement step size is dynamically set to 1 / 8 to 1 / 4 of the window length based on the length of the data sub-block. The main peak detection threshold of the cross-correlation algorithm is set to -3dB. When the number of secondary peaks exceeds two, the window length is extended to 1.5 times the current value. The minimum mean square error iterative convergence threshold for phase compensation is 1×10 -4 , the pre-distortion correction angle range is limited to -π / 6~π / 6.

[0034] The received signal is sampled by the ADC and stored in a dual-port RAM. Time domain alignment is achieved by a parallel correlator array with a sliding window, and the phase compensation coefficient is calculated by the CORDIC algorithm. The bit error rate monitoring unit uses a CRC check circuit. The bit error rate of three consecutive sub-blocks exceeds 1×10 -4 When a signal is detected, an interrupt signal is sent to the channel status monitoring module. The module should be installed close to the mixer output on the receiving end to reduce phase errors introduced by clock jitter. The signal combining module improves the accuracy of combining multipath signals and reduces the bit error rate degradation caused by delay and phase mismatch.

[0035] Furthermore, the path quality factor calculation method includes: normalizing the frequency offset and the ambient noise power spectrum density, wherein the normalization coefficient of the frequency offset is 1 / (15kHz), and the normalization coefficient of the ambient noise power spectrum density is 1 / (10 -3 W / Hz), generating a dimensionless path quality factor Q = Δf norm ×P noise_norm , where Δf norm is the normalized frequency offset, P noise_norm is the normalized power spectrum density of ambient noise; The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio according to the difference between the path quality factor Q and the switching threshold, and when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5×10 -3 The unit Q value corresponds to a 10% increase in weight reduction, and the upper limit of the weight reduction is 60% and the lower limit is 40%; During data sub-block segmentation, delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to communication paths with Q values ​​greater than 1.2 times the switching threshold based on historical bit error rate statistics of the communication paths. The length of the delay-sensitive data sub-blocks is set to 256 bytes to 512 bytes. Add a path allocation identification field to each data sub-block. This field contains the Q value verification code of the target communication path and the sequence check code of the data sub-block. The Q value verification code is generated by retaining three significant digits of the binary floating point number of the Q value. When the load weight of the communication path is adjusted downward, the remapping operation of the data sub-block is triggered, and the data sub-blocks that have not been transmitted in the original path are reallocated in descending order of Q value to the communication path whose current Q value is higher than the switching threshold.

[0036] Specifically, the path quality factor Q can be calculated based on the frequency offset Δf and the ambient noise power spectrum density P noise_norm The normalization coefficient of the frequency offset can be set to 1 / (15kHz), and the normalization coefficient of the ambient noise power spectrum density can be set to 1 / (10 -3 W / Hz). Normalized Δf norm With P noise_norm Multiplying them generates a dimensionless Q value, calculated as Q=Δf norm ×P noise_norm Frequency offset can be measured using a digital frequency counter with a range of ±50kHz and a resolution of at least 0.1kHz. Noise power spectral density can be measured using a spectrum analyzer with a dynamic range of -120 to -20dBm and a configurable RBW (resolution bandwidth) of 1 to 10kHz.

[0037] The normalization module can be integrated into the baseband processing unit's FPGA, using a 32-bit floating-point unit for multiplication. The frequency offset measurement circuit can be deployed at the output of the local oscillator module on the transmitter side, and the noise power measurement circuit is located after the low-noise amplifier on the receiver side. Normalization coefficients are stored in EEPROM and can be dynamically configured via the SPI interface. The module's substrate material can be FR-4 epoxy resin, and the RF path uses gold-plated microstrip traces to reduce losses. The normalization module eliminates dimensional differences through normalization, providing a unified standard for path quality assessment and improving algorithm robustness.

[0038] In the priority allocation algorithm, the load weight reduction ratio can be dynamically calculated as follows: when the Q value is lower than the switching threshold of 0.6×10 -3 When the -3The unit Q value corresponds to a 10% weight reduction, with an upper limit of 60% and a lower limit of 40%. The length of the data sub-block can be set to 256 bytes or 512 bytes. Delay-sensitive sub-blocks are preferentially allocated to sub-blocks with a Q value higher than 0.72×10 -3 The data stream segmentation module can be implemented based on a circular queue, and the queue depth can be configured to 8 to 16 sub-blocks.

[0039] During algorithm execution, the real-time value of the path quality factor (Q) is transmitted to the allocation decision unit via shared memory. Load weight adjustment signals are sent to the data routing controller via GPIO pins, and the routing table update cycle can be set to 10ms. The identification field for latency-sensitive sub-blocks can occupy two bits in the packet header to indicate priority. The allocation policy decision logic can be deployed in the real-time task thread of the embedded processor, with the task scheduling cycle synchronized with channel status updates. Dynamically adjusting path load distribution prioritizes the transmission quality of high-priority data and reduces the risk of link congestion.

[0040] The path allocation identification field can include a 16-bit Q value verification code and a 32-bit sequence check code. The Q value verification code can be generated based on the IEEE 754 single-precision floating point format, retaining three significant digits, for example, Q = 0.72 × 10 -3 The code is 0x3A3D70A4. The sequence check code can be generated using the CRC-32 algorithm, with the generating polynomial being 0x04C11DB7. The identification field can be inserted at the head of the data sub-block, occupying 48 bits.

[0041] The data sub-block remapping operation is triggered by the routing controller. When the path load weight drops by more than 40%, the unfinished sub-blocks are redistributed in descending order of Q value to the sub-blocks with a Q value higher than 0.6×10 -3 The routing table can be stored in SRAM and supports dynamic updates, with a maximum of 256 entries. The remapping process latency can be controlled within 5ms, accelerated by a priority sorting module implemented in a hardware description language. The routing controller should be installed close to the output interface of the data buffer to minimize signal transmission delay. An identification field ensures traceability of data sub-blocks, and the remapping mechanism improves data transmission continuity during link interruptions.

[0042] Furthermore, the power control module dynamically adjusts the transmit power of each communication path based on the difference between the real-time measured signal strength and the ambient noise power spectrum density, specifically including: Establish a mapping relationship between the transmit power adjustment amount and the signal strength-noise difference ΔS. ΔS is defined as the difference between the current signal strength measurement value and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step size is used for adjustment. When ΔS is in the range of -85 to -70 dBm, a 0.5 dB step size is used for adjustment. During the power adjustment process, the instantaneous interference mutation rate of the target communication path is monitored simultaneously. When the ΔS change after two consecutive power increases is less than 20% of the adjustment step size, the burst interference suppression mode is activated, the transmit power adjustment period is shortened from 100ms to 50ms, and the step size is increased to 150% of the original step size. A power adjustment history table is established for each communication path, recording a triplet of data including a timestamp, a ΔS value, and the actual transmit power value. When a ΔS fluctuation of more than 15dB within 300ms is detected, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the most recent five cycles in the history table. After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is terminated and the backup frequency band is switched; A saturation protection mechanism is set for transmit power adjustment. When the cumulative power increase of a single communication path reaches 25% of the initial transmit power, a cross-path power rebalancing operation is triggered. The power value exceeding the threshold is proportionally distributed to other communication paths with Q values ​​higher than 1.5 times the switching threshold.

[0043] Specifically, the measurement range for the signal strength-to-noise difference ΔS can be divided into two sections: -90 to -85dBm and -85 to -70dBm. When ΔS is between -90 and -85dBm, the power adjustment step size can be set to 2dB; when ΔS is between -85 and -70dBm, the step size can be adjusted to 0.5dB. ΔS can be measured using a digital signal strength indicator with a dynamic range of -100dBm to -50dBm and a measurement accuracy of ±0.5dB. The power adjustment module can be deployed between the digitally controlled attenuator and the power amplifier at the transmitter, converting the digital control signal into an analog voltage via a DAC module.

[0044] The ΔS value is updated every 10ms. The baseband processing unit's ADC sampling circuit acquires the instantaneous values ​​of signal strength and ambient noise and calculates the difference. A step size mapping table can be stored in a lookup table within the FPGA, with the corresponding adjustment step size indexed by the real-time ΔS value. The control voltage range of the digitally controlled attenuator can be set to 0–5V, corresponding to an attenuation of 0–30dB. The module should be mounted close to the power amplifier input port to minimize control signal transmission delay. An inter-partition adjustment strategy optimizes the response speed and accuracy of power control to meet the dynamic requirements of varying channel conditions.

[0045] The monitoring window for the transient interference mutation rate can be set to 50ms. When the change in ΔS after two consecutive power increases is less than 20% of the adjustment step size (for example, a change of more than 0.4dB for a 2dB step size), burst interference suppression mode is activated. In this mode, the power adjustment period can be shortened from 100ms to 50ms, and the step size can be increased to 150% of the original value (for example, from 2dB to 3dB). The monitoring module can use a digital comparator circuit, whose input is the differential signal output of the ΔS measurement unit. The threshold comparison result triggers the mode switch through an interrupt signal.

[0046] After each power adjustment, the ΔS change is calculated in real time by a subtractor circuit, and the result is stored in a shift register for two consecutive comparisons. When the trigger condition is met, the control logic resets the adjustment cycle counter to 50ms and modifies the step size parameter via a multiplier circuit. The activation signal for the burst interference suppression mode is transmitted to the power control unit via an optocoupler isolator to ensure signal integrity in high-noise environments. The module's circuit substrate can be made of aluminum-based copper-clad laminate to improve heat dissipation. Rapid response to sudden interference events and dynamic adjustment reduce the probability of communication link interruption.

[0047] The power adjustment history table stores a triplet of data: timestamp, ΔS value, and actual transmit power. The recording interval is 100ms, and the storage depth is the most recent 50 sets of data. When a ΔS fluctuation of more than 15dB within 300ms is detected, the prediction module uses a cubic polynomial fitting algorithm to process the ΔS gradient values ​​of the last five cycles to generate the step size correction coefficient K for the next adjustment cycle. This fitting operation can be implemented in a DSP chip, whose floating-point unit supports matrix inversion and polynomial coefficient calculation. Historical data can be stored in SRAM, with access latency less than 10ns.

[0048] The ΔS gradient value is obtained by differential calculation and stored in the ring buffer after each update. The coefficients of the cubic polynomial fitting are solved by the least squares method, and the time decay factor is 0.8. nWeighted historical data is used. The prediction result K value is limited to a range of 0.7 to 1.3. If it exceeds this range, it will be forcibly truncated and the fitting parameters reset. The prediction module should be installed close to the computing core of the main control unit to reduce data bus transmission latency. The circuit connector can use a high-speed board-to-board connector with a matching impedance of 50Ω. Learning from historical data improves the foresight of power adjustment and reduces the impact of sudden environmental changes on system stability.

[0049] The effectiveness of power adjustment can be verified by setting the following parameters: if the bit error rate of two consecutive data sub-blocks does not decrease by 30% compared to the pre-adjustment bit error rate, the power boost on the current path is terminated and a switch is made to the backup frequency band. The backup frequency band can be preset to the 2.4 GHz or 5.8 GHz ISM band, with a switchover delay of less than 20 ms. The saturation protection mechanism threshold can be set to 25% of the initial transmit power, with the excess distributed proportionally to other paths with Q values ​​greater than 1.5 times the switchover threshold. Power rebalancing can be implemented using an analog switch matrix, with a switching speed of no more than 5 μs.

[0050] The bit error rate monitoring unit uses a CRC check circuit to calculate the bit error rate and transmits the result to the control unit via the I2C interface. When the abort condition is triggered, a control signal drives the RF switch to switch to the backup frequency band filter path. The saturation protection module's power allocation calculation can run in a dedicated coprocessor on the microcontroller, and the allocation ratio is determined using a table lookup method. The module should be mounted close to the power amplifier's output matching network to monitor the output power status in real time. This prevents excessive power concentration from causing device saturation losses and ensures balanced utilization of multipath resources.

[0051] Furthermore, the step length correction coefficient of the next adjustment cycle is predicted based on the ΔS gradient values ​​of the last five cycles in the history table, specifically including: The ΔS gradient values ​​of the last five cycles were processed by a cubic polynomial fitting algorithm to generate a prediction model including a time decay factor, which was calculated as 0.8. n The exponential law of decaying historical data weights is used, where n represents the number of intervals between the current cycle and the historical cycle; Substitute the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max +β·G min , where α is 0.6~0.8, β is 0.2~0.4, G max and G min Represent the maximum and minimum absolute values ​​of gradients within five cycles respectively; The step size correction coefficient K=1+0.15·sign(∂G / ∂t)·|∂G / ∂t| is generated based on the equation solution. 0.5 ,When the K value exceeds the range of 0.7-1.3, it is forced to be limited to the interval endpoint value and triggers the prediction model parameter reset; After each power adjustment operation is performed, the actual ΔS change gradient and the predicted gradient are compared to calculate the residual. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, it automatically switches to the moving weighted average prediction mode, which uses the weight distribution of 60%, 30%, and 10% of the gradient values ​​of the previous three cycles; Configure the validity duration parameter for the correction coefficient K. When K is greater than 1, the validity duration is set to 150-300 ms. When K is less than 1, the validity duration is set to 400-600 ms. During the validity period, power rebalancing operations on other communication paths are frozen.

[0052] Specifically, the cubic polynomial fitting algorithm can process the ΔS gradient values ​​of the last five cycles. The time decay factor weights the historical data according to the exponential law of 0.8^n, where n represents the number of intervals between the current cycle and the historical cycle. The coefficient solution of the fitting model can be achieved through the least squares method. The weight coefficient α can be set to 0.6~0.8, and β can be set to 0.2~0.4. The gradient change equation ∂G / ∂t=α·G max +β·G min In, G max and G min are the maximum and minimum absolute values ​​of gradient within five cycles, respectively.

[0053] This algorithm can be deployed in a digital signal processor (DSP), whose floating-point unit supports matrix operations. Historical gradient data can be stored in SRAM with a storage depth of five groups, each containing a timestamp and a ΔS gradient value. The time decay factor calculation module can be integrated into the logic unit of an FPGA, implementing exponential weighting via shift registers. The module should be mounted close to the data bus interface of the main control unit to reduce data transmission latency. FR-4 epoxy resin can be used as the circuit substrate material, and the signal trace impedance should be matched to 50Ω. Polynomial fitting is used to improve the accuracy of gradient prediction and adapt to dynamic changes in the channel environment.

[0054] The calculation formula of the step size correction coefficient K is K=1+0.15·sign(∂G / ∂t)·|∂G / ∂t| 0.5 , the calculated results are limited to the range of 0.7 to 1.3. When the K value exceeds this range, it is forcibly truncated to the interval endpoint, triggering a reset of the prediction model parameters. The calculation module can use the arithmetic logic unit of the embedded processor, which supports sign functions and square root operations. The parameter reset signal can be sent to the fitting module via the interrupt controller, with a reset time of 10 μs.

[0055] After each gradient prediction is completed, the calculated K value is stored in a register, and a comparator circuit determines whether it has exceeded the specified bounds. If K > 1.3 or K < 0.7, a reset pulse is sent to the fitting module, and the K value is simultaneously written to the exception log area of ​​the non-volatile memory. The correction coefficient takes effect for a configurable duration of 150–300 ms when K > 1 and 400–600 ms when K < 1. The module should be mounted close to the interrupt response circuit of the power control unit to shorten the signal transmission path. Correction coefficient constraints improve the stability of power regulation and prevent system oscillations caused by prediction errors.

[0056] Residual calculation can be based on the difference between the actual ΔS gradient and the predicted gradient. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, the system automatically switches to a moving weighted average prediction mode. The moving weighted average weights can be set to 60%, 30%, and 10% of the gradient values ​​for the previous three cycles. The residual monitoring module utilizes a digital subtractor and absolute value circuit, with a threshold comparator set to a 30% tolerance.

[0057] After each power adjustment, the actual gradient value is obtained through differential calculation and compared with the predicted value to generate residual data. The residual sequence is stored in a FIFO buffer. When the limit is exceeded three times in a row, a switching control signal drives the multiplexer to switch the prediction algorithm. The moving weighted average calculation can be run on the processor's fixed-point arithmetic unit, and the weight coefficients are stored in registers. The module assembly location must be close to the feedback loop of the gradient prediction unit to respond to residual changes in real time. The circuit connector can use a board-to-board high-speed connector, and the signal delay is controlled within 2ns. Residual monitoring enables adaptive switching of the prediction algorithm, enhancing the robustness of the system in nonlinear environments.

[0058] Furthermore, the time domain alignment adopts a cross-correlation algorithm with a sliding window length of 8 to 32 μs, specifically including: Calculate the maximum delay difference Δτ between each communication path at the receiver end and set the basic length of the sliding window to 3 to 5 times Δτ, constrained to the range of 8 to 32 μs. Δτ is calculated by the timestamp difference between adjacent path data sub-blocks. During the execution of the cross-correlation algorithm, the number and amplitude of correlation peaks are monitored in real time. When two or more secondary peaks are detected within the 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value. The extended window length does not exceed 32μs. The window movement step size is dynamically modified according to the data sub-block length. When the data sub-block length is 256-512 bytes, the step size is set to 1 / 8-1 / 4 of the window length. When the data sub-block length is 1024-2048 bytes, the step size is reduced to 1 / 16-1 / 12 of the window length. Doppler frequency shift pre-correction is performed synchronously during the window sliding process. The signal samples in the window are phase rotated using the carrier frequency offset measurement value. The rotation angle θ=2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points in the window. After each window adjustment, the alignment effect is verified through the bit error rate monitoring unit of the feedback link. If the bit error rate of three consecutive data sub-blocks after adjustment does not decrease by 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

[0059] Specifically, the basic length of the sliding window can be set to 3–5 times the maximum delay difference Δτ between communication paths, constrained to a range of 8–32 μs. Δτ can be measured by calculating the timestamp differences between data sub-blocks on each path at the receiving end, with timestamp accuracy set to ±0.1 μs. The window length adjustment module can be deployed in the digital signal processing unit at the receiving end, using programmable logic devices for dynamic configuration. For example, if Δτ is measured to be 6 μs, the window length can be set to 18 μs (3 times Δτ).

[0060] The received signal is sampled by the ADC and stored in a dual-port RAM. The timestamp extraction circuit uses the synchronization code in the packet header to locate the start time of each sub-block. The Δτ calculation unit uses a subtractor circuit to generate the inter-path delay difference in real time, writing the result to a register for the window control module to access. The initial sliding window length is configured as an integer multiple of Δτ and is dynamically updated via the SPI interface. The module should be mounted close to the ADC output to minimize signal transmission delay. FR-4 epoxy resin can be used as the circuit substrate material, and gold plating is used for RF signal lines to reduce losses. Dynamic window length is used to match channel delay characteristics to improve time domain alignment accuracy.

[0061] The cross-correlation algorithm's main peak detection threshold can be set to -3dB. When two or more secondary peaks are detected within a 3dB bandwidth on either side of the main peak, the sliding window length is expanded to 1.2 to 1.8 times its current value, with an upper limit of no more than 32μs. The correlation peak detection module can utilize a peak detection integrated circuit with a dynamic range of -30 to 10dBm and a resolution of at least 0.1dB. Secondary peak counts are performed using a comparator array with a -3dB threshold.

[0062] The received signal is input into the correlator array, and the output correlation peak data is stored in the FIFO buffer. The main peak position is determined by the maximum value detection circuit, and the secondary peak counter counts the number of peaks that exceed the threshold. When the number of secondary peaks is ≥2, the control logic triggers the window length multiplier to multiply the original length by the expansion factor (for example, 1.5 times). The expanded window parameters are transmitted to the RAM controller via the parallel bus to update the window capture range. The assembly position of the module needs to be close to the output end of the digital down-converter to ensure signal phase consistency. The circuit heat dissipation design can use aluminum-based copper-clad laminates, and the operating temperature range covers -40~85℃. Suppress the influence of secondary peaks caused by multipath interference and enhance the robustness of time domain alignment. The window movement step size can be dynamically adjusted based on the data sub-block length: when the sub-block length is 256-512 bytes, the step size is set to 1 / 8 to 1 / 4 of the window length; when the sub-block length is 1024-2048 bytes, the step size is reduced to 1 / 16 to 1 / 12 of the window length. The Doppler shift pre-correction module can be integrated into the FPGA. The phase rotation angle θ = 2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling point. The phase rotation operation is implemented using the CORDIC algorithm with a calculation accuracy of ±0.01 radians.

[0063] The window sliding controller uses a preset step size ratio indexed by the sub-block length. For example, a 512-byte sub-block corresponds to a 1 / 4 step size (8 μs for a 32 μs window). Doppler shift measurements are acquired via a digital frequency discriminator and input into the phase rotation calculation unit. The CORDIC algorithm processes 16-bit fixed-point numbers per cycle and outputs rotated I / Q signal samples. The corrected data is stored in a buffer for subsequent merging modules. The module must be assembled near the clock recovery circuit to synchronize sampling timing. The signal path material can be low-loss polytetrafluoroethylene (PTFE) substrates with a stable dielectric constant of 2.2. Window movement efficiency is dynamically optimized to compensate for phase errors caused by Doppler shift and improve signal merging quality.

[0064] Furthermore, Doppler frequency shift pre-correction is synchronously performed during the window sliding process, and the signal samples in the window are phase rotated using the carrier frequency offset measurement value, specifically including: Calculate the rate of change of Δf in real time during the window sliding process rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two adjacent frequency offset measurements. The phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t; Set the phase rotation angle constraint. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz. After the phase rotation operation, residual frequency offset compensation is performed and the compensation factor C is calculated based on the divergence of the constellation diagram of the rotated signal. measured / EVM threshold ), where EVM measured is the measured error vector magnitude, EVM threshold Set to 8-12%, the compensation factor is applied to the Δf measurement values ​​of subsequent windows to form a closed-loop correction; A segmented correction strategy is used. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the intensive correction mode is activated, increasing the execution interval of the phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value. After each window sliding, the correction effect is verified by comparing the mean change in θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimated value is written to the frequency calibration field of the path allocation table.

[0065] Specifically, the phase rotation angle θ can be calculated based on the frequency offset Δf and its change rate Δf rate The real-time measurement value, the correction formula is θ=2π×(Δf+Δf rate ×t)×t, where Δt is the time interval between two adjacent measurements. A digital frequency discriminator can be used to measure Δf, with a range of ±10kHz and a resolution of no less than 1Hz. rate The calculation can be achieved through a differential circuit. The input signal comes from two consecutive output values ​​of the frequency discriminator, and the time interval Δt can be set to 1ms.

[0066] The received signal is input into the frequency detector after down-conversion, and the Δf value is captured by the counter circuit to measure the carrier offset. rate The phase rotation calculation unit is implemented in real time by subtractor and divider circuits. The phase rotation calculation unit is deployed in the FPGA, using a 32-bit floating-point multiplier to implement the correction formula. The rotated I / Q signal samples are output to the combining module via a digital upconverter. The module should be mounted close to the local oscillator input of the mixer at the receiver to minimize signal path latency. FR-4 epoxy resin can be used as the circuit substrate material, and the RF trace impedance is matched to 50Ω. Dynamic correction of phase errors caused by Doppler shift improves signal stability in high-speed mobile scenarios.

[0067] The absolute value of the phase rotation angle θ can be set to π / 3. If the calculated value exceeds this range, the angle limiter constrains θ to between -π / 3 and π / 3. Limiting is implemented using a saturation arithmetic circuit with an input range of -π to π and an output resolution of at least 0.01 radians. Frequency calibration can be triggered if θ exceeds the limit three times in a row. At this point, the calibration signal generator outputs a test tone signal between 1 and 5 kHz, with a configurable test tone duration of 10 ms.

[0068] The calculated phase rotation angle is input into a comparator circuit. Exceeding the limit triggers the limiter to output the constraint value, and a counter records the number of limit violations. The calibration signal generator utilizes direct digital frequency synthesis technology, and its output signal is injected into the feedback loop of the frequency offset measurement module via a digital-to-analog converter. The module must be mounted close to the calibration port of the frequency discriminator to ensure low-loss transmission of the test tone signal. Aluminum-clad copper laminate can be used for circuit heat dissipation, with an operating temperature range of -20°C to 70°C. Signal distortion caused by excessive phase rotation is prevented, and frequency measurement accuracy is maintained through regular calibration.

[0069] The calculation formula of the residual frequency offset compensation factor C is C=1-(EVM measured / EVM threshold ), where EVM threshold Can be set to 10%, EVM measured The measurement accuracy is ±0.5% and is obtained through the constellation diagram analysis module. Within the segmented correction strategy, the intensive correction mode is triggered when Δf fluctuates by more than ±2kHz for three consecutive cycles. At this point, the phase rotation interval is shortened to once per sampling point, and Δt is reduced to 25% of its original value. The compensation factor C can be limited to a range of 0.8 to 1.2, automatically resetting to 1.0 if exceeded.

[0070] Constellation data is input into the EVM calculation unit, and the result is transmitted to the compensation factor generation module via the SPI interface. If Δf fluctuations exceed the limit, the control logic switches to intensive correction mode, shortening the phase rotation execution period to synchronize with the sampling clock. The compensation factor is applied to subsequent Δf measurements via a multiplier, forming a closed-loop correction. The module should be mounted near the output of the error vector analyzer to obtain real-time EVM data. SMA connectors are recommended for circuit connectors to ensure high-frequency signal integrity. Closed-loop compensation further eliminates residual frequency offset and adapts to rapidly changing channel environments.

[0071] Furthermore, phase compensation uses pre-distortion correction based on the minimum mean square error criterion, specifically including: Construct a joint error function E = γ·(Δε) that includes phase difference and amplitude fluctuation 2 +δ·(ΔA / A ref ) 2, where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The value is set to 80-120% of the average amplitude of the received signal, the weight coefficient γ is set to 0.6-0.8, and the weight coefficient δ is set to 0.2-0.4; The minimum value of the error function is solved by the recursive least squares algorithm to generate a predistortion vector containing the I / Q correction amount. The constraint step parameter μ is 0.05~0.15 during the iterative calculation process, and the residual convergence threshold is set to 1×10 -4 ~5×10 -4 ; The predistortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the paths with a phase difference Δε exceeding π / 12. In the second stage, the remaining paths are progressively compensated using 50-70% of the correction vector. After the correction operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification indicator. When the EVM measurement value is higher than 8%, the correction vector update module is triggered to recalculate the predistortion parameters in a period of 200-500ms. A dynamic adjustment mechanism for correction parameters is established to reversely correct the weight coefficients γ and δ according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is lower than 10% / sub-block, γ will be increased by 5% to 10% and the corresponding proportion of δ will be reduced simultaneously.

[0072] Specifically, the joint error function can be defined as E = γ·(Δε) 2 +δ·(ΔA / A ref ) 2 , where Δε is the measured phase deviation and ΔA is the amplitude fluctuation. Reference amplitude A ref It can be set to 80% to 120% of the average amplitude of the received signal. The weight coefficient γ can be configured between 0.6 and 0.8, and δ between 0.2 and 0.4. Phase deviation Δε can be measured using a digital phase detector with a range of -π to π and a resolution of at least 0.01 radians. Amplitude fluctuation ΔA can be measured using a logarithmic detection circuit with a dynamic range of -30 to 10 dBm.

[0073] The I / Q components of the received signal are input to the error calculation unit. Δε is generated by comparing the phase detector with the reference phase, and ΔA is calculated by the difference between the peak detection circuit and the reference amplitude. The error function calculation is deployed in the DSP chip, and the floating-point operation unit supports real-time calculation. Reference amplitude A refDynamic updates are achieved through a sliding average filter, and the filter window length can be set to 100 sampling points. The module should be mounted close to the input interface of the receiving baseband processing unit to reduce signal transmission delay. FR-4 epoxy resin can be used as the circuit substrate material, and silver-plated microstrip lines are used for the RF path. A joint error function is used to comprehensively evaluate phase and amplitude distortion, improving the comprehensiveness of the correction parameters.

[0074] The iterative step size parameter μ of the recursive least squares algorithm can be set to 0.05~0.15, and the residual convergence threshold can be configured to 1×10 -4 ~5×10 -4 During algorithm execution, the I / Q components of the predistortion vector are generated through matrix inversion. The initial value of the covariance matrix can be set to 0.1 times the identity matrix. The iterative calculation module can be integrated into the FPGA's logic unit, supporting parallel multiplication and addition operations with a calculation cycle of no more than 10μs. The residual monitoring circuit can use a digital comparator with a threshold accuracy of ±0.5%.

[0075] The initial predistortion vector is loaded into a register, and the covariance matrix and weight coefficients are updated after each iteration. The calculated residual is compared with a threshold. If it falls below the threshold three times in a row, the iteration is terminated and the output vector is locked. The algorithm interrupt signal is transmitted to the control unit via a priority arbiter to ensure real-time performance. The module should be mounted near the read and write ports of the correction vector memory to shorten data access time. A copper-based heat sink with a thermal conductivity of at least 400 W / m·K can be used for circuit heat dissipation. Predistortion parameters are optimized through adaptive iteration to reduce algorithm complexity and computational resource usage.

[0076] In a phased correction strategy, the first phase can be set to apply a full correction vector to paths with a phase difference Δε exceeding π / 12. The second phase gradually compensates the remaining paths using 50% to 70% of the correction vector. The pilot symbol EVM verification threshold can be set to 8%. When the measured EVM exceeds this value, the predistortion parameter update period can be triggered to 200 to 500 ms. In dynamic parameter adjustment, the correction step size of the weight coefficient γ can be configured to 5% to 10%, and the adjustment direction of δ is opposite to that of γ.

[0077] A comparator circuit determines whether the phase difference Δε exceeds the π / 12 threshold, triggering a full correction enable signal. In progressive compensation mode, the correction vector is scaled proportionally by a digitally controlled attenuator. The EVM monitoring unit extracts data from a constellation diagram analyzer, and the results are fed back to the control unit via the I2C bus. The dynamic parameter adjustment logic runs as a background task on the embedded processor, with a lower priority than real-time correction operations. The module must be mounted close to the power amplifier's feedforward correction node to directly affect the output signal. High-speed board-to-board connectors can be used for the circuit connector, keeping signal latency to less than 1ns. Staged correction balances processing speed and accuracy, and the dynamic adjustment mechanism adapts to long-term changes in channel conditions.

[0078] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and embodiments shown and described herein.

Claims

1. A multi-channel cooperative communication method, characterized in that: include: The channel state monitoring module deployed at the transmitter acquires channel state information of at least three independent communication paths in the target area in real time. The channel state information includes the current signal strength measurement value, frequency offset, and ambient noise power spectrum density of each communication path. In the data stream segmentation module, based on a preset priority allocation algorithm, the data stream to be transmitted is divided into N data sub-blocks and dynamically allocated to each communication path. The priority allocation algorithm generates a path quality factor based on the product of the frequency offset output by the channel status monitoring module and the ambient noise power spectrum density. When the path quality factor falls below a preset switching threshold, the load weight of the communication path is reduced by 40-60%. In the power control module, the transmit power of each communication path is dynamically adjusted based on the difference between the real-time measured signal strength and the ambient noise power spectrum density; The signal merging module at the receiving end performs time domain alignment and phase compensation on the data sub-blocks from each communication path. The time domain alignment uses a cross-correlation algorithm with a sliding window length of 8 to 32 μs. The phase compensation uses pre-distortion correction based on the minimum mean square error criterion, with a correction angle range of -π / 6 to π / 6. A bit error rate monitoring unit is set in the feedback link. When the bit error rate of three consecutive data sub-blocks exceeds 1×10 -4 When the channel status monitoring module is triggered to rescan the target area and update the communication path allocation table.

2. The multi-channel cooperative communication method according to claim 1, wherein: The calculation method of the path quality factor includes: normalizing the frequency offset and the ambient noise power spectrum density, wherein the normalization coefficient of the frequency offset is 1 / (15kHz), and the normalization coefficient of the ambient noise power spectrum density is 1 / (10 -3 W / Hz), generating a dimensionless path quality factor Q = Δf norm ×P noise_norm , where Δf norm is the normalized frequency offset, P noise_norm is the normalized power spectrum density of ambient noise; The priority allocation algorithm includes: dynamically calculating the load weight reduction ratio according to the difference between the path quality factor Q and the switching threshold, and when Q is lower than the switching threshold, the load weight reduction ratio is increased by 0.5×10 -3 The unit Q value corresponds to a 10% increase in weight reduction, and the upper limit of the weight reduction is 60% and the lower limit is 40%; During data sub-block segmentation, delay-sensitive data sub-blocks in the data stream to be transmitted are preferentially allocated to communication paths with Q values ​​greater than 1.2 times the switching threshold based on historical bit error rate statistics of the communication paths. The length of the delay-sensitive data sub-blocks is set to 256 bytes to 512 bytes. Add a path allocation identification field to each data sub-block. This field contains the Q value verification code of the target communication path and the sequence check code of the data sub-block. The Q value verification code is generated by retaining three significant digits of the binary floating point number of the Q value. When the load weight of the communication path is adjusted downward, the remapping operation of the data sub-block is triggered, and the data sub-blocks that have not been transmitted in the original path are reallocated in descending order of Q value to the communication path whose current Q value is higher than the switching threshold.

3. The multi-channel cooperative communication method according to claim 1, wherein: The power control module dynamically adjusts the transmit power of each communication path based on the difference between the real-time measured signal strength and the ambient noise power spectrum density. Specifically, it includes: Establish a mapping relationship between the transmit power adjustment amount and the signal strength-noise difference ΔS. ΔS is defined as the difference between the current signal strength measurement value and the ambient noise power spectral density. When ΔS is in the range of -90 to -85 dBm, a 2 dB step size is used for adjustment. When ΔS is in the range of -85 to -70 dBm, a 0.5 dB step size is used for adjustment. During the power adjustment process, the instantaneous interference mutation rate of the target communication path is monitored simultaneously. When the ΔS change after two consecutive power increases is less than 20% of the adjustment step size, the burst interference suppression mode is activated, the transmit power adjustment period is shortened from 100ms to 50ms, and the step size is increased to 150% of the original step size. A power adjustment history table is established for each communication path, recording a triplet of data including a timestamp, a ΔS value, and the actual transmit power value. When a ΔS fluctuation of more than 15dB within 300ms is detected, the step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the most recent five cycles in the history table. After the power boost operation is executed, the effectiveness of the power adjustment is verified by the bit error rate monitoring unit of the feedback link. If the bit error rate of two consecutive data sub-blocks after the adjustment does not decrease by 30% of the bit error rate before the adjustment, the power boost of the current communication path is terminated and the backup frequency band is switched; A saturation protection mechanism is set for transmit power adjustment. When the cumulative power increase of a single communication path reaches 25% of the initial transmit power, a cross-path power rebalancing operation is triggered. The power value exceeding the threshold is proportionally distributed to other communication paths with Q values ​​higher than 1.5 times the switching threshold.

4. The multi-channel cooperative communication method according to claim 3, wherein: The step size correction coefficient for the next adjustment cycle is predicted based on the ΔS gradient values ​​of the last five cycles in the history table, specifically including: The ΔS gradient values ​​of the last five cycles were processed by a cubic polynomial fitting algorithm to generate a prediction model including a time decay factor, which was calculated as 0.

8. n The exponential law of decaying historical data weights is used, where n represents the number of intervals between the current cycle and the historical cycle; Substitute the fitted polynomial coefficients into the gradient change equation ∂G / ∂t=α·G max +β·G min , where α is 0.6~0.8, β is 0.2~0.4, G max and G min Represent the maximum and minimum absolute values ​​of gradients within five cycles respectively; The step size correction coefficient K=1+0.15·sign(∂G / ∂t)·|∂G / ∂t| is generated based on the equation solution. 0.5 ,When the K value exceeds the range of 0.7-1.3, it is forced to be limited to the interval endpoint value and triggers the prediction model parameter reset; After each power adjustment operation is performed, the actual ΔS change gradient and the predicted gradient are compared to calculate the residual. When the absolute value of the residual exceeds 30% of the predicted value for three consecutive times, it automatically switches to the moving weighted average prediction mode, which uses the weight distribution of 60%, 30%, and 10% of the gradient values ​​of the previous three cycles; Configure the validity duration parameter for the correction coefficient K. When K is greater than 1, the validity duration is set to 150-300 ms. When K is less than 1, the validity duration is set to 400-600 ms. During the validity period, power rebalancing operations on other communication paths are frozen.

5. The multi-channel cooperative communication method according to claim 1, wherein: The time domain alignment adopts a cross-correlation algorithm with a sliding window length of 8 to 32 μs, specifically including: Calculate the maximum delay difference Δτ between each communication path at the receiver end and set the basic length of the sliding window to 3 to 5 times Δτ, constrained to the range of 8 to 32 μs. Δτ is calculated by the timestamp difference between adjacent path data sub-blocks. During the execution of the cross-correlation algorithm, the number and amplitude of correlation peaks are monitored in real time. When two or more secondary peaks are detected within the 3dB bandwidth on both sides of the main peak, the sliding window length is extended to 1.2 to 1.8 times the current value. The extended window length does not exceed 32μs. The window movement step size is dynamically modified according to the data sub-block length. When the data sub-block length is 256-512 bytes, the step size is set to 1 / 8-1 / 4 of the window length. When the data sub-block length is 1024-2048 bytes, the step size is reduced to 1 / 16-1 / 12 of the window length. Doppler frequency shift pre-correction is performed synchronously during the window sliding process. The signal samples in the window are phase rotated using the carrier frequency offset measurement value. The rotation angle θ=2π·Δf·t, where Δf is the frequency offset of the current path and t is the relative time of the sampling points in the window. After each window adjustment, the alignment effect is verified through the bit error rate monitoring unit of the feedback link. If the bit error rate of three consecutive data sub-blocks after adjustment does not decrease by 15% of the bit error rate before adjustment, the sliding window parameters are reset and the delay difference Δτ measurement is re-executed.

6. The multi-channel cooperative communication method according to claim 5, wherein: Doppler frequency shift pre-correction is performed synchronously during the window sliding process, and the signal samples in the window are phase rotated using the carrier frequency offset measurement value. Specifically, it includes: Calculate the rate of change of Δf in real time during the window sliding process rate =[Δf(t)-Δf(t-Δt)] / Δt, where Δt is the time interval between two adjacent frequency offset measurements. The phase rotation angle is corrected to θ=2π×(Δf+Δf rate ×t)×t; Set the phase rotation angle constraint. When the calculated absolute value of θ exceeds π / 3, enable the angle limiter to limit θ to the range of -π / 3 to π / 3, and trigger the calibration signal generator of the frequency offset measurement module to output a test tone signal of 1 to 5 kHz. After the phase rotation operation, residual frequency offset compensation is performed and the compensation factor C is calculated based on the divergence of the constellation diagram of the rotated signal. measured / EVM threshold ), where EVM measured is the measured error vector magnitude, EVM threshold Set to 8-12%, the compensation factor is applied to the Δf measurement values ​​of subsequent windows to form a closed-loop correction; A segmented correction strategy is used. When the fluctuation amplitude of Δf exceeds ±2kHz for three consecutive measurement cycles, the intensive correction mode is activated, increasing the execution interval of the phase rotation operation from once per window to once per sampling point, while shortening Δt to 20-30% of the original value. After each window sliding, the correction effect is verified by comparing the mean change in θ between adjacent windows. If the residual carrier frequency offset after correction is still greater than 10% of Δf, the extended Kalman filter algorithm is automatically switched to re-estimate the Δf value, and the new estimated value is written to the frequency calibration field of the path allocation table.

7. The multi-channel cooperative communication method according to claim 1, wherein: Phase compensation uses pre-distortion correction based on the minimum mean square error criterion, which includes: Construct a joint error function E = γ·(Δε) that includes phase difference and amplitude fluctuation 2 +δ·(ΔA / A ref ) 2 , where Δε is the measured phase deviation, ΔA is the amplitude fluctuation, and A ref The value is set to 80-120% of the average amplitude of the received signal, the weight coefficient γ is set to 0.6-0.8, and the weight coefficient δ is set to 0.2-0.4; The minimum value of the error function is solved by the recursive least squares algorithm to generate a predistortion vector containing the I / Q correction amount. The constraint step parameter μ is 0.05~0.15 during the iterative calculation process, and the residual convergence threshold is set to 1×10 -4 ~5×10 -4 ; The predistortion correction operation is performed in stages. In the first stage, the full correction vector is applied only to the paths with a phase difference Δε exceeding π / 12. In the second stage, the remaining paths are progressively compensated using 50-70% of the correction vector. After the correction operation, the error vector magnitude (EVM) of the pilot symbol is extracted as a verification indicator. When the EVM measurement value is higher than 8%, the correction vector update module is triggered to recalculate the predistortion parameters in a period of 200-500ms. A dynamic adjustment mechanism for correction parameters is established to reversely correct the weight coefficients γ and δ according to the bit error rate change trend of three consecutive data sub-blocks. If the bit error rate decrease rate is lower than 10% / sub-block, γ will be increased by 5% to 10% and the corresponding proportion of δ will be reduced simultaneously.