Display device and display panel

Abstract

The embodiment of the invention provides a display device and a display panel, relates to the technical field of display, and is used for improving the display effect of the display panel. The display device includes a control circuit and a display panel. The control circuit outputs a first control signal when the refresh frequency of the display device is a first frequency, or outputs a second control signal when the refresh frequency of the display device is a second frequency. The first frequency is greater than the second frequency. The display panel comprises a plurality of scanning circuits and a plurality of rows of sub-pixels, and each scanning circuit is connected with at least one row of sub-pixels. The scanning circuit outputs a first scanning signal according to the first control signal, or outputs a second scanning signal according to the second control signal. Wherein the signal parameter of the first scanning signal is different from the signal parameter of the second scanning signal, so that the brightness difference when the display panel displays the set gray scale at the first frequency and the second frequency is within a preset range.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a display panel. Background Art

[0002] When a display device is in a variable refresh rate (VRR) mode and switches rapidly between different refresh rates, screen flickering may occur, affecting the display effect. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a display device and a display panel, so as to improve the display effect of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a display device is provided, comprising a control circuit and a display panel. The control circuit is configured to output a first control signal when the refresh frequency of the display device is a first frequency, or to output a second control signal when the refresh frequency of the display device is a second frequency. The first frequency is greater than the second frequency. The display panel comprises a plurality of scanning circuits and a plurality of rows of sub-pixels, each scanning circuit being connected to at least one row of sub-pixels. The scanning circuit is configured to output a first scanning signal according to the first control signal, or to output a second scanning signal according to the second control signal. The signal parameters of the first scanning signal are different from the signal parameters of the second scanning signal, so that the brightness difference when the display panel displays the set grayscale at the first frequency and the second frequency is within a preset range.

[0006] In the above-mentioned display device, the brightness consistency problem of the display device when switching between multiple refresh rates is effectively solved by adjusting the scanning signal parameters. The control circuit can output a corresponding control signal according to the current refresh frequency (first frequency or second frequency) to drive the scanning circuit to generate a scanning signal with adjustable parameters (first or second scanning signal). By differentially setting the scanning signal parameters at high and low frequencies, the brightness difference of the display panel when presenting the same grayscale at different refresh rates is controlled within a preset range, thereby eliminating brightness fluctuations and visual flickering caused by frequency switching. This solution not only ensures display efficiency at high refresh rates, but also compensates for the leakage effect at low refresh rates, achieves stable and uniform display brightness across the entire frequency band, and significantly improves the visual comfort and user experience of multi-refresh rate display devices.

[0007] In some embodiments, the signal parameters include at least one of the gate drive capability GOE time of the scan signal, the voltage value of the operating voltage of the scan signal, the voltage value of the shutdown voltage of the scan signal, and the current value of the scan signal. The gate drive capability GOE time is the time difference between the end time of the operating voltage of the scan signal and the end time of the corresponding data signal. The first scan signal and the second scan signal meet at least one of the following conditions: the gate drive capability GOE time of the first scan signal is greater than the gate drive capability GOE time of the second scan signal. The voltage value of the operating voltage of the first scan signal is less than the voltage value of the operating voltage of the second scan signal. The absolute value of the voltage value of the shutdown voltage of the first scan signal is less than the absolute value of the voltage value of the shutdown voltage of the second scan signal. The current value of the first scan signal is less than the current value of the second scan signal.

[0008] In some embodiments, the display panel further includes a source driver circuit and a plurality of data lines coupled to the source driver circuit, each data line being connected to at least one column of sub-pixels. The source driver circuit is configured to output a first data signal based on a first control signal, or to output a second data signal based on a second control signal. The operating voltage of the first scanning signal ends earlier than the operating voltage of the second scanning signal, and / or the first data signal ends later than the second data signal.

[0009] In some embodiments, the control circuit includes a memory storing a mapping table representing the correspondence between a refresh frequency of a display device and a gate drive capability (GOE) time at different grayscales. A processor configured to determine the gate drive capability (GOE) time corresponding to the current frequency based on a target grayscale of the display device, a current frequency, and the mapping table, and output corresponding control signals and data signals based on the gate drive capability (GOE) time.

[0010] In some embodiments, the display device further includes a first power management circuit, coupled to the control circuit and the display panel, and configured to output a first turn-on voltage in response to a first control signal and a second turn-on voltage in response to a second control signal. The first turn-on voltage is lower than the second turn-on voltage. The scan circuit is specifically configured to output an operating voltage of a first scan signal based on the first turn-on voltage, or to output an operating voltage of a second scan signal based on the second turn-on voltage.

[0011] In some embodiments, the display device further includes a second power management circuit, coupled to the control circuit and the display panel, and configured to output a first shutdown voltage in response to a first control signal and a second shutdown voltage in response to a second control signal. The absolute value of the first shutdown voltage is less than the absolute value of the second shutdown voltage. The scanning circuit is specifically configured to output a shutdown voltage of the first scanning signal based on the first shutdown voltage, or to output a shutdown voltage of the second scanning signal based on the second shutdown voltage.

[0012] In some embodiments, a scanning circuit includes an output subcircuit, wherein a first terminal of the output subcircuit is coupled to a pull-up node of the scanning circuit, a second terminal of the output subcircuit is coupled to a clock signal terminal of the scanning circuit, and a third terminal of the output subcircuit is coupled to a signal output terminal of the scanning circuit. The output subcircuit is configured to control the connection and disconnection between the clock signal terminal and the signal output terminal based on the potential of the pull-up node. The signal output terminal is configured to output a first scanning signal or a second scanning signal. The operating current of the first scanning signal is less than the operating current of the second scanning signal.

[0013] In some embodiments, the output sub-circuit includes: multiple transistors, the first electrode of each transistor is coupled to the clock signal terminal, the second electrode of each transistor is coupled to the signal output terminal, and the control electrode of each transistor is respectively connected to the corresponding enable signal terminal; or, multiple transistors, the first electrode of the transistor is coupled to the third terminal of the output sub-circuit, the second electrode of the transistor is coupled to the signal output terminal, and the control electrode of the transistor is respectively connected to the corresponding enable signal terminal.

[0014] In some embodiments, the display device further includes: a third power management circuit, coupled to the control circuit and the control electrode of each transistor, and configured to: in response to a first control signal, output enable signals to the control electrodes of the plurality of transistors to turn on a first number of transistors among the plurality of transistors; or, in response to a second control signal, output enable signals to the control electrodes of the plurality of transistors to turn on a second number of transistors among the plurality of transistors, where the first number is less than the second number.

[0015] In some embodiments, the display device further includes a fourth power management circuit, coupled to the control circuit and the display panel, configured to output a third shutdown voltage and a fourth shutdown voltage, wherein the absolute value of the third shutdown voltage is less than the absolute value of the fourth shutdown voltage. The display panel further includes a voltage divider circuit, coupled to the fourth power management circuit and the scan circuit, respectively. The voltage divider circuit is configured to receive the third shutdown voltage and the fourth shutdown voltage and output a fifth shutdown voltage, wherein the absolute value of the fifth shutdown voltage is greater than or equal to the absolute value of the third shutdown voltage and less than or equal to the absolute value of the fourth shutdown voltage. The absolute value of the fifth shutdown voltage is negatively correlated with the refresh rate of the display device.

[0016] In some embodiments, a voltage divider circuit includes: a plurality of switch sub-circuits, wherein a first end of the switch sub-circuit is coupled to one end of any one of a plurality of resistors connected in series between a first end and a second end of the voltage divider circuit. A second end of the switch sub-circuit serves as an output end of the voltage divider circuit. Controlled ends of the switch sub-circuits are respectively connected to corresponding enable signal ends for controlling the on and off of the switch sub-circuits.

[0017] In some embodiments, the display device further includes: a fifth power management circuit, coupled to the control circuit and the controlled terminal of the switch sub-circuit, and configured to: in response to a first control signal, output an enable signal to the controlled terminals of the plurality of switch sub-circuits, respectively, to turn on a first target switch sub-circuit among the plurality of switch sub-circuits; and in response to a second control signal, output an enable signal to the controlled terminals of the plurality of switch sub-circuits, respectively, to turn on a second target switch sub-circuit among the plurality of switch sub-circuits. The resistance between the first terminal of the first target switch sub-circuit and the first terminal of the voltage divider circuit is smaller than the resistance between the first terminal of the second target switch sub-circuit and the first terminal of the voltage divider circuit.

[0018] On the other hand, a display panel is provided. The display panel includes multiple rows of sub-pixels and multiple scanning circuits. Each scanning circuit is connected to at least one row of sub-pixels. The scanning circuit includes: an output sub-circuit, a first end of the output sub-circuit is coupled to a pull-up node of the scanning circuit, a second end of the output sub-circuit is coupled to a clock signal end of the scanning circuit, and a third end of the output sub-circuit is coupled to a signal output end of the scanning circuit. The output sub-circuit is configured to: control the on-off of the clock signal end and the signal output end based on the potential of the pull-up node. The scanning circuit is configured to: output a first scanning signal according to a first control signal, or output a second scanning signal according to a second control signal. The first control signal is used to instruct the display panel to display at a first refresh frequency, and the second control signal is used to instruct the display panel to display at a second refresh frequency. The signal output end is used to output the first scanning signal or the second scanning signal. The current value of the first scanning signal is less than the current value of the second scanning signal.

[0019] In some embodiments, the output subcircuit includes: a plurality of transistors, each having a first terminal coupled to a clock signal terminal, a second terminal coupled to a signal output terminal, and a control terminal of each transistor connected to a corresponding enable signal terminal. Different numbers of transistors that are turned on output different currents. Alternatively, a plurality of transistors, each having a first terminal coupled to a third terminal of the output subcircuit, a second terminal coupled to the signal output terminal, and a control terminal of each transistor connected to a corresponding enable signal terminal. Different numbers of transistors that are turned on output different currents.

[0020] In another aspect, a display panel is provided, comprising: a plurality of rows of sub-pixels; a plurality of scanning circuits, each scanning circuit connected to at least one row of sub-pixels; and a voltage divider circuit coupled to the scanning circuit. The voltage divider circuit is configured to receive a third shutdown voltage and a fourth shutdown voltage and output a fifth shutdown voltage, wherein an absolute value of the fifth shutdown voltage is greater than or equal to an absolute value of the third shutdown voltage and less than or equal to an absolute value of the fourth shutdown voltage. The absolute value of the fifth shutdown voltage is negatively correlated with a refresh rate of the display panel.

[0021] In some embodiments, a voltage divider circuit includes: a plurality of switch sub-circuits, wherein a first end of each switch sub-circuit is coupled to one end of any one of a plurality of resistors connected in series between the first and second ends of the voltage divider circuit. A second end of each switch sub-circuit serves as an output end of the voltage divider circuit. Controlled ends of the switch sub-circuits are respectively connected to corresponding enable signal ends for controlling the on and off of the switch sub-circuits. When different switch sub-circuits are turned on among the plurality of switch sub-circuits, different voltage values ​​are outputted at the second ends of the switch sub-circuits.

[0022] The above-mentioned display panel has the same beneficial technical effects as the display devices provided in some of the above-mentioned embodiments, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0024] Figure 1 A structure of a display device according to some embodiments Figure 1 ;

[0025] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0026] Figure 3 A structure of a scanning circuit according to some embodiments Figure 1 ;

[0027] Figure 4 A signal timing according to some embodiments Figure 1 ;

[0028] Figure 5 is a structural diagram of a sub-pixel according to some embodiments;

[0029] Figure 6A structure of a display device according to some embodiments Figure 2 ;

[0030] Figure 7 A signal timing according to some embodiments Figure 2 ;

[0031] Figure 8 is a relationship diagram of refresh frequency, gray scale and gate drive capability GOE time according to some embodiments;

[0032] Figure 9 A signal timing according to some embodiments Figure 3 ;

[0033] Figure 10 A signal timing according to some embodiments Figure 4 ;

[0034] Figure 11 A signal timing according to some embodiments Figure 5 ;

[0035] Figure 12 A signal timing according to some embodiments Figure 6 ;

[0036] Figure 13 A structure of a scanning circuit according to some embodiments Figure 2 ;

[0037] Figure 14 A structure of a scanning circuit according to some embodiments Figure 3 ;

[0038] Figure 15 A structure of a scanning circuit according to some embodiments Figure 4 ;

[0039] Figure 16 A structure of a scanning circuit according to some embodiments Figure 5 ;

[0040] Figure 17 A structure of a scanning circuit according to some embodiments Figure 6 ;

[0041] Figure 18 A structure of a display device according to some embodiments Figure 3 ;

[0042] Figure 19 A structure of a voltage divider circuit according to some embodiments is shown in FIG. Figure 1 ;

[0043] Figure 20 A structure of a voltage divider circuit according to some embodiments is shown in FIG. Figure 2 ;

[0044] Figure 21 is a diagram of a PWM signal according to some embodiments. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The terms "coupled", "communication connection" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0052] The use of "for," "adapted for," or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] First, the terms involved in the embodiments of the present invention are explained:

[0056] VBO, short for V-By-One, is a digital interface standard for image information transmission. Because it supports high-speed signal transmission up to 4.0Gbps, VBO is widely used in ultra-high-definition LCD TVs.

[0057] Pulse Width Modulation (PWM): Pulse width modulation modulates the width of a series of pulses to equivalently obtain the required waveform (including shape and amplitude).

[0058] PWM duty cycle: the proportion of the high level in a pulse cycle to the entire cycle.

[0059] Grayscale: Generally, the brightness change between the darkest and brightest is divided into several parts to facilitate screen brightness control. For example, the displayed image is composed of three colors: red, green, and blue. Each color can show a different brightness level, and the combination of red, green, and blue with different brightness levels can form different colors. For example, the grayscale bit number of the LCD panel is 6 bits, and the three colors of red, green, and blue have 64 (i.e. 2 6 ) grayscale, these 64 grayscale values ​​are Gray0-Gray63. The grayscale number of the LCD panel is 8 bits, so the three colors of red, green and blue have 256 (i.e. 2 8 ) grayscale, these 256 grayscale values ​​are Gray0-Gray255. The grayscale number of the LCD panel is 10 bits, so the three colors of red, green and blue have 1024 (i.e. 2 10 ) grayscale, these 1024 grayscale values ​​are Gray0-Gray1023. The grayscale number of the LCD panel is 12 bits, so the three colors of red, green and blue have 4096 (i.e. 2 12 ) grayscales, and these 4096 grayscale values ​​are Gray0-Gray4093.

[0060] See also Figure 1 The display device 10 includes a display panel 100 , a circuit board 200 , a backlight module 300 and a backlight control circuit 400 .

[0061] The circuit board 200 includes an interface connector 201, a timer control register IC (TCON IC) 202, a power management integrated circuit (PMIC) 203, and a level shift circuit 204. The interface connector 201 is used to connect to the front-end system on chip (SOC) 20.

[0062] The system-level chip 20, the timing control circuit 202 and the power management integrated circuit 203 can communicate through IIC, and can transmit digital video data through a high-speed serial video transmission protocol such as VBO. The system-level chip 20 is used to obtain the display signal and convert the display signal into digital video data, and transmit the digital video data to the timing control circuit 202. The system-level chip 20 also sends a PWM adjustment signal to drive the backlight module 300 of the display panel through the backlight control circuit 400 to provide a light source for the display panel to control the brightness of the display panel. The timing control circuit 202 can directly send a PWM adjustment signal to the backlight module 300 of the display panel based on the digital video data. Figure 2The source driver circuit (Source IC) 120 shown in FIG. 1 provides a timing signal and can also provide a timing signal to the source driver circuit 120 through the level conversion circuit 204. Figure 2 The gate drive circuit (Gate on Array, GOA) 110 shown provides control signals. The timing control circuit 202 can also send PWM modulation signals through the backlight control circuit 400 to drive the backlight module 300 of the display panel to provide light for the display panel 100, thereby controlling the brightness of the display panel. In other words, both the timing control circuit 202 and the system-on-chip 20 can achieve brightness control of the display panel 100.

[0063] The input end of the level shifter circuit 204 is electrically connected to the power management integrated circuit 203 and the timing control circuit 202. The output end of the level shifter circuit 204 is electrically connected to the gate driver circuit 110. The level shifter circuit 204 can be used to amplify the gate timing signal and transmit the amplified gate timing signal to the gate driver circuit 110 in the display panel 100.

[0064] The power management integrated circuit 203 is used to output gate-level signals and provide them to the gate driver circuit 110. The gate-level signals include a gate high-level signal VGH (e.g., 30V to 35V), a first gate low-level signal VGL (e.g., negative 8V to negative 9V), and a second gate low-level signal LVGL (e.g., negative 10V to negative 12V). LVGL is typically less than VGL, for example, LVGL is -10V and VGL is -8V. VGL is the turn-off voltage for the transistors in the display area AA, and LVGL is the turn-off voltage for each transistor in the scanning circuit. Using LVGL as the turn-off voltage for the scanning circuit helps to more completely turn off the transistors, thereby reducing noise in the scanning circuit. Furthermore, the power management integrated circuit 203 can also provide operating voltages to the timing control circuit 202 and the source driver circuit 120.

[0065] The timing control circuit 202 is used to receive and decode the VBO signal input by the front-end system-level chip 20, and provide a variety of voltage signals to drive the source driver circuit 120 and the gate driver circuit 110 based on the decoded data. The source driver circuit 120 and the gate driver circuit 110 then transmit the signals to the panel to enable the display panel to display.

[0066] In some embodiments, the multiple voltage signals provided by the timing control circuit 202 may include a control timing signal for driving the source driver circuit 120 and a gate timing signal for driving the gate driver circuit 110. The source driver circuit 120 provides a source driver signal to the display panel based on the control timing signal, and the gate driver circuit provides a gate driver signal to the display panel based on the gate timing signal. In addition, the multiple voltage signals may also include a start of vertical sync (STV) signal, which represents a frame start signal or a frame start signal of a frame.

[0067] like Figure 2 As shown, the display panel 100 may include a display area AA and a peripheral area BB located on at least one side of the display area AA. The peripheral area BB may include a source driving circuit 120 and a gate driving circuit 110. The display panel 100 may be provided with array-distributed sub-pixels SPX in the display area AA. The sub-pixel SPX includes a pixel electrode 02 and a transistor 01 for driving the pixel electrode 02.

[0068] The display panel 100 is further provided with a plurality of scan lines GL extending along the row direction DH in the display area AA. Each scan line GL is provided in a one-to-one correspondence with each subpixel row. The plurality of scan lines GL are coupled to the gate driver circuit 110. The transistor O1 of each subpixel SPX in a subpixel row is electrically connected to a corresponding scan line GL. The scan line GL is used to apply a scan signal to the transistor O1. The display panel 100 is further provided with a plurality of data lines DL extending along the column direction DV in the display area AA. Each data line DL is provided in a one-to-one correspondence with each subpixel column. The plurality of data lines DL are coupled to the source driver circuit 120.

[0069] The transistor 01 of each sub-pixel SPX in a sub-pixel column is electrically connected to a corresponding data line DL, which is used to apply a data voltage to the transistor 01. Thus, the transistor 01 of each sub-pixel SPX is connected to a scan line GL and a data line DL. When a scan signal is applied to the scan line GL, the data voltage applied on the data line DL is written into the transistor 01, allowing the transistor 01 to control the brightness of the pixel electrode 02 based on the written data voltage.

[0070] A thin film transistor is provided in the sub-pixel SPX, the gate of the thin film transistor is electrically connected to the gate driving circuit 110 through the scanning line GL extending horizontally in the figure, the source of the thin film transistor is electrically connected to the source driving circuit 120 through the data line DL extending vertically in the figure, and the drain of the thin film transistor is connected to the pixel electrode.

[0071] like Figure 2As shown, the gate driving circuit 110 includes a plurality of cascaded scanning circuits 111 (or shift registers) integrated on the array substrate. Each scanning circuit is connected to a scanning line GL in a one-to-one correspondence and is used to provide a scanning signal to the scanning line GL connected thereto.

[0072] like Figure 3 As shown in FIG, the circuit diagram of the scanning circuit unit is shown. Figure 3 As shown, the scanning circuit 111 includes: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein the input sub-circuit is connected to the signal input terminal INPUT and the pull-up node PU, and is configured to respond to the input signal input by the signal input terminal INPUT, and write the input signal into the pull-up node PU to charge the pull-up node PU; the output sub-circuit is connected to the pull-up node PU, the clock signal terminal CLK and the signal output terminal OUTPUT, and is configured to respond to the potential of the pull-up node PU, and output the clock signal input by the clock signal terminal CLK through the signal output terminal OUTPUT; the pull-up reset sub-circuit is connected to the pull-up node PU, the pull-up reset signal terminal RESET_PU and the low-level signal terminal LVGL, and is configured to respond to the pull-up reset signal input by the pull-up reset signal terminal RESET_PU, and reset the potential of the pull-up node PU through the low-level signal input by the low-level signal terminal LVGL.

[0073] Specifically, such as Figure 3 As shown, the input sub-circuit includes: a first transistor M1; the pull-up reset sub-circuit includes: a second transistor M2; the output sub-circuit includes: a third transistor M3 and a storage capacitor C; wherein, the gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal LVGL; the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal OUTPUT; one end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT.

[0074] like Figure 3As shown, the scanning circuit 111 further includes a pull-down control subcircuit, a pull-down subcircuit, a noise reduction subcircuit, a discharge subcircuit, and a cascade subcircuit. The pull-down control subcircuit includes a first pull-down control subcircuit and a second pull-down control subcircuit; the pull-down subcircuit includes a first pull-down subcircuit and a second pull-down subcircuit; and the noise reduction subcircuit includes a first noise reduction subcircuit and a second noise reduction subcircuit. The first pull-down control subcircuit and the second pull-down control subcircuit have the same structure and function, operating in a time-sharing manner. Similarly, the first pull-down subcircuit and the second pull-down subcircuit have the same structure and function; and the first noise reduction subcircuit and the second noise reduction subcircuit have the same structure and function.

[0075] The first pull-down control sub-circuit is connected to the first power supply voltage signal terminal VDDO and the first pull-down node PD1, and is configured to respond to the first power supply voltage input by the first power supply voltage signal terminal VDDO, input the first power supply voltage input by the first power supply voltage signal terminal VDDO to the first pull-down node PD1, so as to control the potential of the first pull-down node PD1.

[0076] The second pull-down control sub-circuit is connected to the second power supply voltage signal terminal VDDE and the second pull-down node PD2, and is configured to respond to the second power supply voltage input by the second power supply voltage signal terminal VDDE, input the second power supply voltage input by the second power supply voltage signal terminal VDDE to the second pull-down node PD2, so as to control the potential of the second pull-down node PD2.

[0077] The first pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal LVGL, the first pull-down node PD1 and the first pull-down control node PD_CN1, and is configured to respond to the potential of the pull-up node PU and pull down the potential of the first pull-down node PD1 and the first pull-down control node PD_CN1 through the low-level signal input by the low-level signal terminal LVGL.

[0078] The second pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal LVGL, the second pull-down node PD2 and the second pull-down control node PD_CN2, and is configured to respond to the potential of the pull-up node PU and pull down the potential of the second pull-down node PD2 and the second pull-down control node PD_CN2 through the low-level signal input by the low-level signal terminal LVGL.

[0079] The first noise reduction sub-circuit is connected to the first pull-down node PD1, the low-level signal terminal LVGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C, and is configured to respond to the potential of the first pull-down node PD1 and perform noise reduction on the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C ​​through the low-level signal input by the low-level signal terminal LVGL.

[0080] The second noise reduction sub-circuit is connected to the second pull-down node PD2, the low-level signal terminal LVGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C, and is configured to respond to the potential of the second pull-down node PD2 and perform noise reduction on the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C ​​through the low-level signal input by the low-level signal terminal LVGL.

[0081] The discharge subcircuit is connected to the frame start signal terminal STV, the low-level signal terminal LVGL, and the pull-up node PU, and is configured to respond to the frame start signal input by the frame start signal terminal STV and discharge the pull-up node PU through the low-level signal input by the low-level signal terminal VGL.

[0082] The cascade sub-circuit is connected to the pull-up node PU, the clock signal terminal CLK, and the cascade signal output terminal OUT_C, and is configured to output the clock signal input by the clock signal terminal CLK to other cascaded scanning circuits 111 through the cascade signal output terminal OUT_C ​​in response to the potential of the pull-up node PU.

[0083] It should be noted that the cascade signal output terminal OUT_C ​​and the signal output terminal OUTPUT output the same signal, except that the shift register unit has two output terminals: one is the signal output terminal OUTPUT connected to the gate line, and the other is the cascade signal output terminal OUT_C ​​used for cascading. The reason for providing a separate cascade sub-circuit is to reduce the load on the signal output terminal OUTPUT to avoid affecting the scan signal output by the signal output terminal OUTPUT.

[0084] Specifically, such as Figure 3 As shown, the first pull-down control subcircuit and the second pull-down control subcircuit both include a fifth transistor and a ninth transistor; wherein the fifth transistor in the first pull-down control subcircuit and the second control subcircuit are represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. The first pull-down subcircuit and the second pull-down subcircuit both include a sixth transistor and an eighth transistor; wherein the sixth transistor in the first pull-down subcircuit and the second pull-down subcircuit are represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. The first noise reduction subcircuit and the second noise reduction subcircuit both include a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein the tenth transistor in the first noise reduction subcircuit and the second noise reduction subcircuit are represented by M10 and M10', respectively, the eleventh transistor is represented by M11 and M11', respectively, and the twelfth transistor is represented by M12 and M12', respectively; and the discharge subcircuit includes a seventh transistor, M7.

[0085] Among them, the gate and source of the ninth transistor M9 are both connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down control node PD_CN1; the gate of the fifth transistor M5 is connected to the first pull-down control node PD_CN1, the source is connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down node PD1; the gate and source of the ninth transistor M9' are both connected to the second power supply voltage terminal VDDE, and the drain is connected to the second pull-down control node PD_CN2; the gate of the fifth transistor M5' is connected to the second pull-down control node PD_CN2, the source is connected to the second power supply voltage terminal VDDE, and the drain is connected to the first pull-down node PD1; the gate of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the first pull-down node PD1, and the drain is connected to the low-level signal terminal VGL; the gate of the eighth transistor M8 is connected to the pull-up node PU, the source is connected to the first pull-down control node PD_CN1, and the drain is connected to the low-level signal terminal VGL; the gate of the sixth transistor M6' is connected to the pull-up node PU , the source is connected to the second pull-down node PD2, and the drain is connected to the low-level signal terminal VGL; the gate of the eighth transistor M8' is connected to the pull-up node PU, the source is connected to the second pull-down control node PD_CN2, and the drain is connected to the low-level signal terminal; the gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected to the first pull-down node PD1, the source is connected to the signal output terminal OUTPUT, and the drain is connected to the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected to the second pull-down node PD2, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11' is connected to the second pull-down node PD2, the source is connected to the signal output terminal OUTPUT, and the drain is connected to the low-level signal terminal VGL; the gate of the seventh transistor M7 is connected to the frame start signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL. The cascade sub-circuit includes a thirteenth transistor M13, whose gate is connected to the pull-up node PU, whose source is connected to the clock signal terminal CLK, and whose drain is connected to the cascade signal output terminal OUT_C. Furthermore, a twelfth transistor, designated M12 and M12', is provided in both the first and second noise reduction sub-circuits, respectively, for performing noise reduction on the signal outputted by the cascade signal output terminal OUT_C. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, whose source is connected to the cascade signal output terminal OUT_C, and whose drain is connected to the low-level signal terminal VGL. The gate of the twelfth transistor M12' is connected to the second pull-down node PD2, whose source is connected to the cascade signal output terminal OUT_C, and whose drain is connected to the low-level signal terminal VGL.

[0086] Among them, the fifth transistor M5 and the ninth transistor M9 form a first pull-down control subcircuit, and the fifth transistor M5' and the ninth transistor M9' form a second pull-down control subcircuit, which work in time-sharing mode (i.e., work in turns); accordingly, since the first noise reduction subcircuit composed of the tenth transistor M10 and the eleventh transistor M11 and the second noise reduction subcircuit composed of the tenth transistor M10' and the eleventh transistor M11' are respectively controlled by the first pull-down control subcircuit and the second pull-down control subcircuit, the first noise reduction subcircuit and the second noise reduction subcircuit also work in time-sharing mode. The working principles of the first pull-down control subcircuit and the second pull-down control subcircuit are the same, and the working principles of the first noise reduction subcircuit and the second noise reduction subcircuit are the same; therefore, the following only describes the working principle of the scanning circuit 111 when the first pull-down control subcircuit and the first noise reduction subcircuit are working. It should be noted here that Figure 3 In the circuit structure shown, some low-level signal terminals can be represented by VGL or LVGL. The low-level signal terminal LVGL can provide a signal with a lower potential than the low-level signal terminal VGL, which can more fully lower the potential of the corresponding point.

[0087] In the input phase, a high-level signal is written into the signal input terminal INPUT, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled high by the high-level signal, and the storage capacitor C is charged.

[0088] In the output phase, since the potential of the pull-up node PU is pulled high in the input phase, the third transistor M3 is turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected to the scanning circuit 111 through the signal output terminal OUTPUT.

[0089] In the off stage, a high-level signal is input to the frame start signal terminal STV, the seventh transistor M7 is turned on, and the low-level signal input by the low-level signal terminal VGL discharges the pull-up node PU to prevent the residual charge of the pull-up node PU from causing display abnormalities. A high-level signal is input to the pull-up reset signal terminal RESET_PU, the second transistor M2 is turned on, and the low-level signal input by the low-level signal terminal VGL pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the pull-up node PU is pulled low, the third transistor M3 is turned off, and the signal output terminal OUTPUT and the cascade signal output terminal OUT_C ​​no longer output high-level signals. At the same time, the first pull-down control node PD_CN1 and the pull-down node are both high-level signals, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the outputs of the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C ​​are respectively denoised until the next frame scan starts and the potential of the pull-up node PU is pulled high.

[0090] In order to achieve different application scenarios, the display panel can be set to multiple different refresh frequencies. For example, in some application scenarios, in order to save power consumption, the display panel needs to reduce the display frequency, for example: from a higher refresh frequency to a lower refresh. In other scenarios, such as when executing high-frequency games, it is necessary to increase the frequency of the display panel, for example: from 60HZ to 144HZ or 360HZ, so as to make the picture smoother. Therefore, in order to adapt to different scenarios, the display panel can change the display frequency, that is, the variable refresh rate (VRR) to refresh the picture. In addition, the variable refresh rate can reduce the freeze and tearing of the display screen perceived by the human eye, improve the viewing experience, especially the viewing experience of competitive games, and is the development direction of display technology.

[0091] Each refresh rate cycle of the display device, i.e., the frame cycle, may include a charging time and a blanking time. In VRR mode, the charging time duration is the same for different refresh rates, and the refresh rate of the display device is dynamically adjusted by changing the blanking time duration in the display device's frame cycle.

[0092] VRR technology adjusts the LCD panel's blanking time, allowing for flexible switching between high and low refresh rates. This reduces the image delay and screen tearing that can occur when the image frame rate doesn't match the screen's refresh rate. However, because the display panel's refresh rate is fixed, adjusting to a lower refresh rate requires a longer blanking time to achieve the lower refresh rate.

[0093] like Figure 4 As shown, Figure 4 This is a schematic diagram of exemplary blanking times at different refresh frequencies. The frame time of the display panel at a high refresh frequency (such as 144Hz) is shorter than the frame time at a low refresh frequency (such as 60Hz) (TA1<TA2). The charging time of high and low refresh frequencies is the same (TB1=TB2), so the blanking time at a high refresh frequency is shorter than the blanking time at a low refresh frequency (TC1<C2). The longer the blanking time, the longer the pixel voltage needs to be maintained, and therefore the greater the pixel leakage current. At low refresh frequencies, the longer the blanking time, the greater the leakage current, resulting in noticeable flicker at low refresh frequencies.

[0094] For example, the main reason affecting the pixel leakage current of the display panel is the influence caused by the inherent characteristics of the thin film transistor in the display panel. For example, the sub-pixel SPX can be Figure 5 The circuit shown in FIG. 1 includes a thin film transistor (TFT), a storage capacitor C ST and C LCThe liquid crystal capacitor and the source driver circuit 120 are used to provide data signals to the sub-pixels SPX, and the gate driver circuit 110 is used to provide scan signals (or gate driver signals or gate timing signals) to the sub-pixels SPX. Since the display time of each frame includes charging time and blanking time, the time of each frame remains unchanged under different refresh frequencies. At a high refresh rate, the blanking time is short, the leakage time is very short, and there is basically no loss of brightness. At a low refresh rate, the blanking time is long, resulting in more leakage and loss of brightness. Therefore, the display brightness of a low refresh rate is lower than that of a high refresh rate, which will cause flickering when switching quickly.

[0095] Based on the above problems, the present disclosure provides a display device, such as Figure 6 As shown, the display device 10 includes a display panel 100 and a control circuit 600, which may be a timing control circuit 202. The gate driving circuit 110 in the display panel 100 includes a plurality of scanning circuits 111 and a plurality of rows of sub-pixels SPX, each scanning circuit 111 being connected to at least one row of sub-pixels SPX.

[0096] The control circuit 600 outputs a first control signal when the refresh frequency of the display device 10 is a first frequency, or outputs a second control signal when the refresh frequency of the display device 10 is a second frequency. The first frequency is greater than the second frequency.

[0097] The scanning circuit 111 outputs a first scanning signal according to the first control signal, or outputs a second scanning signal according to receiving a second control signal.

[0098] The signal parameters of the first scanning signal and the signal parameters of the second scanning signal are different so that the difference in brightness when the display panel displays a set grayscale at the first frequency and the second frequency is within a preset range. For example, the signal parameters may include at least one of a gate output enable (GOE) time of the scanning signal, a voltage value of an operating voltage of the scanning signal, a voltage value of a shutdown voltage of the scanning signal, and a current value of the scanning signal.

[0099] For example, the brightness difference is within a preset range. For example, to ensure a good viewing experience, it is necessary to avoid subjectively visible flickering in the image when switching between frequencies. Therefore, in the evaluation of VRR products, the preset range can be set to be less than 0.03 nit per 1 Hz for full white field brightness (less than 2.88 nit difference between 48 Hz and 144 Hz at 255 grayscale); less than 0.04 nit per 1 Hz for mid-grayscale brightness (less than 3.84 nit difference between 48 Hz and 144 Hz at 128 grayscale).

[0100] Subjectively, the preset range can be set to ensure that there is no subjective flicker when switching between 48Hz / 144Hz in full white and medium grayscale; and the subjective effects of rapid switching between other frequency bands and grayscales (such as rapid switching between 48Hz and 96Hz in low grayscale) can be observed to ensure that there is no subjective flicker.

[0101] In the above-mentioned display device, by adjusting the scanning signal parameters, the brightness consistency problem of the display device when switching between multiple refresh rates is effectively solved. The control circuit can output a corresponding control signal according to the current refresh frequency (first frequency or second frequency), and drive the scanning circuit 111 to generate a scanning signal with adjustable parameters (first or second scanning signal). By differentially setting the scanning signal parameters at high and low frequencies, the brightness difference of the display panel when presenting the same grayscale at different refresh rates is controlled within a preset range, thereby eliminating brightness fluctuations and visual flickering caused by frequency switching. This solution not only ensures the display efficiency at high refresh rates, but also compensates for the leakage effect at low refresh rates, achieves stable and uniform display brightness across the entire frequency band, and significantly improves the visual comfort and user experience of multi-refresh rate display devices.

[0102] In some possible implementations, the gate drive capability GOE time is the time difference between the end time of the operating voltage of the scan signal Gout and the end time of the corresponding data signal Sout. The scan signal Gout is a gate output signal (Gout), and the data signal Sout can be a source output signal (Sout).

[0103] like Figure 7 As shown, the scanning signal Gout may include Gout1, Gout2, Gout3, Gout4, Gout5, and Gout6, and the data signal Sout represents the turn-on timing of a column of sub-pixels. When the gate of the transistor TFT of each row of sub-pixels SPX is turned on, the time difference between the rising edge of the data signal Sout and the falling edge of the scanning signal Gout is the actual charging time of the sub-pixels SPX in this row. The difference between the row time and the actual charging time of the sub-pixels is the gate drive capability GOE time.

[0104] The first scan signal and the second scan signal satisfy at least one of the following conditions: a gate drive capability GOE time of the first scan signal is greater than a gate drive capability GOE time of the second scan signal; an operating voltage of the first scan signal is less than an operating voltage of the second scan signal; an absolute value of a shutdown voltage of the first scan signal is less than an absolute value of a shutdown voltage of the second scan signal; and a current value of the first scan signal is less than a current value of the second scan signal.

[0105] In the above-mentioned display device, adaptive brightness compensation of the display device at multiple refresh rates is achieved by precisely controlling key parameters such as the gate drive capability GOE time, operating voltage, shutdown voltage or current value of the scanning signal. Specifically, at a high refresh rate (first frequency), a fast response mode is formed by setting a longer gate drive capability GOE time, a lower operating voltage / current value and a smaller absolute value of the shutdown voltage, which ensures sufficient charging at high frequency and avoids overshoot. At a low refresh rate (second frequency), a shorter gate drive capability GOE time is combined with a higher operating voltage / current value and a larger absolute value of the shutdown voltage to construct a compensation drive mode, which effectively compensates for the leakage effect of the low frequency and long Blanking time. This multi-parameter collaborative adjustment mechanism ensures that the brightness difference of the same grayscale at high and low refresh rates is always controlled within a preset range through the differentiated setting of at least one parameter, solves the problem of brightness jump when the refresh rate is switched, achieves an imperceptible smooth transition, and significantly improves the visual comfort and user experience of multi-refresh rate display devices.

[0106] In some examples, the first scan signal and the second scan signal satisfy that the gate drive capability GOE time of the first scan signal is greater than the gate drive capability GOE time of the second scan signal, and the first control signal and the second control signal respectively include providing a timing signal, a display data signal and a data control signal to the source driver circuit 120, and / or, include a gate control signal provided to the gate driver circuit 110.

[0107] In one example, if Figure 6 As shown, the display panel 100 further includes a source driver circuit 120 and a plurality of data lines DL coupled to the source driver circuit 120, each data line DL being connected to at least one column of sub-pixels SPX. The source driver circuit 120 outputs a first data signal based on a first control signal, or outputs a second data signal based on a second control signal. The operating voltage of the first scanning signal ends earlier than the operating voltage of the second scanning signal. And / or, the first data signal ends later than the second data signal.

[0108] In the above-mentioned display device, by collaboratively controlling the timing relationship between the scan signal and the data signal, precise charging optimization of the display panel at multiple refresh rates is achieved. When working at a high refresh rate (first frequency), the source driver circuit outputs a first data signal, the end time of which is relatively delayed, or the end time of the operating voltage of the scan signal is advanced, forming a specific gate drive capability GOE time window, which ensures sufficient charging at a high refresh rate and avoids overshoot. At a low refresh rate (second frequency), a timing combination of the second data signal (ending earlier) or the scan signal (ending later) is adopted to effectively extend the effective charging time to compensate for leakage loss at a low refresh rate. This timing linkage control mechanism of the scan signal and the data signal can automatically match the optimal charging parameters at different refresh rates by dynamically adjusting the relative timing relationship between the two, so as to maintain brightness consistency when switching between high and low refresh rates and ensure picture quality.

[0109] In a specific embodiment, the control circuit 600 receives the VBO signal input from the front-end system-level chip 20. The VBO signal includes a display signal with a Blanking length. The control circuit 600 calculates the refresh frequency by calculating the length of the Blanking area in the display signal. The relationship between the Blanking length and the refresh frequency is as follows: Figure 4 As shown in the figure, the charging time of each frame is the same under different refresh rates, but the Blanking time length is different.

[0110] The control circuit 600 can provide timing signals, display data signals, and data control signals to the source driver circuit 120 based on the refresh rate. The data control signal is used to control the timing of inputting the data signal Sout to the sub-pixel based on the timing signals and the display data signal, so that the sub-pixel SPX displays at the corresponding brightness. The control circuit 600 can also provide the scanning signal Gout to the gate driver circuit 110 through the level shifter circuit 204 based on the refresh rate.

[0111] In another example, Figure 6 As shown, the control circuit 600 includes a memory and a processor.

[0112] The memory stores a mapping relationship table, which is used to represent the corresponding relationship between the refresh frequency of the display device 10 and the gate drive capability GOE time at different gray scales.

[0113] The processor is configured to determine the gate drive capability (GOE) time corresponding to the current frequency based on the target grayscale of the display device 10, the current frequency, and a mapping table (Table). The processor also outputs corresponding control signals and data signals based on the gate drive capability (GOE) time. During use, the control circuit 600 decodes the refresh frequency, detects the grayscale value to be displayed, and retrieves the corresponding gate drive capability (GOE) time from the mapping table (Table) to ensure consistent and stable screen brightness.

[0114] In one example, the mapping relationship table can be obtained as follows:

[0115] Select the target grayscale (the target grayscale can be any grayscale that the display device 10 can display, such as Gray63 in Gray0-Gray255), switch the refresh frequency in the optional frequency range (such as 48Hz~144Hz) in sequence, and record the actual brightness corresponding to each Hertz Hz. For the refresh frequency that deviates from the brightness fluctuation range, adjust its GOE. The basic principle is to reduce the gate drive capability GOE time when the brightness is too small, and increase the gate drive capability GOE time when the brightness is too large, until the brightness of all refresh frequencies under the target grayscale is adjusted to meet the test specifications.

[0116] According to the above method, the brightness of all grayscales is adjusted to meet the target brightness Spec, and the data is organized into a one-to-one mapping relationship table Table and stored in the memory, and the debugging phase ends.

[0117] like Figure 8 As shown, the grayscale is Gray0-Gray255, and the refresh frequency range is 48Hz to 144Hz, and the corresponding gate drive capability GOE time. For example, when the refresh frequency is 48Hz, the grayscale range is Gray0-Gray255, and the corresponding gate drive capability GOE time is GOE(0)-GOE(255). When the refresh frequency is 60Hz, the grayscale range is Gray0-Gray255, and the corresponding gate drive capability GOE time is GOE(N)-GOE(N+255).

[0118] In the above-described display device, a mapping table containing the gate drive capability (GOE) time corresponding to each grayscale at different refresh rates is pre-stored in the memory of the control circuit 600. The processor then looks up the table in real time based on the target grayscale and operating frequency of the currently displayed content to obtain the corresponding gate drive capability (GOE) time parameters, and accurately generates the corresponding control and data signals accordingly. This improves the brightness consistency of the display panel in complex usage scenarios.

[0119] In other examples, the first scan signal and the second scan signal satisfy the voltage value of the working voltage (or turn-on voltage) of the first scan signal being less than the voltage value of the working voltage (or turn-on voltage) of the second scan signal.

[0120] In one example, the first control signal and the second control signal can instruct the power management integrated circuit 203 to output a turn-on voltage VGH for driving the gate driver circuit 110, or to control the turn-on voltage VGH of the transistor TFT in the sub-pixel SPX. The turn-on voltage VGH output by the power management integrated circuit 203 is negatively correlated with the refresh rate of the display device 10.

[0121] Exemplarily, the display device 10 includes a first power management circuit (the first power management circuit may be a power management integrated circuit 203 or a power IC additional to the power management integrated circuit 203), coupled to the control circuit 600 and the display panel 100. The first power management circuit outputs a first turn-on voltage VGH1 in response to a first control signal and outputs a second turn-on voltage VGH2 in response to a second control signal.

[0122] The first turn-on voltage VGH1 is lower than the second turn-on voltage VGH2. The scanning circuit 111 outputs the operating voltage of the first scanning signal according to the first turn-on voltage VGH1, or outputs the operating voltage of the second scanning signal according to the second turn-on voltage VGH2.

[0123] In a specific embodiment, the control circuit 600 sends a control signal to the first power management circuit according to the refresh frequency of the VBO signal input by the front-end system-level chip 20. The first power management circuit adjusts the turn-on voltage VGH (such as the first turn-on voltage VGH1 or the second turn-on voltage VGH2) used to drive the gate driver circuit 110 in real time according to the value of the control signal, or controls the turn-on voltage VGH (such as the first turn-on voltage VGH1 or the second turn-on voltage VGH2) of the transistor TFT in the sub-pixel SPX. The turn-on voltage VGH adjusted in real time is given as an input signal to the level conversion circuit 204, and the high level of the signal input to the gate driver circuit 110 changes accordingly, thereby achieving the adjustment of the scanning signal Gout as the frame rate changes, such as Figure 9 shown.

[0124] Because lower refresh rates increase blanking time, leakage time increases for the same charging time. Therefore, at lower refresh rates, the gate voltage for the transistors in the AA area of ​​the display region increases, allowing the transistors to fully open, resulting in a larger on-current (Ion) and higher charging efficiency. For example, at 60Hz, the on-voltage VGH is set to 34V, and at 120Hz, the on-voltage VGH is set to 33V. The specific setting value can be determined based on the actual measured panel brightness.

[0125] In the above-mentioned display device, the control circuit identifies the current refresh frequency (first frequency or second frequency) and triggers the first power management circuit to output the corresponding turn-on voltage (the first turn-on voltage is smaller or the second turn-on voltage is larger), thereby providing a differentiated driving voltage reference for the scanning circuit. At a high refresh rate, a lower first turn-on voltage is used, which relatively reduces the charging efficiency of the sub-pixel. At a low refresh rate, it switches to a higher second turn-on voltage, which relatively improves the charging efficiency of the sub-pixel and effectively compensates for the leakage current caused by the long Blanking time. This adaptive matching scheme of power supply voltage and refresh rate solves the problem of brightness fluctuation when the fixed voltage design switches the frequency.

[0126] In some other examples, the first scan signal and the second scan signal satisfy the condition that the absolute value of the off voltage of the first scan signal is smaller than the absolute value of the off voltage of the second scan signal.

[0127] In one example, the first control signal and the second control signal can instruct the power management integrated circuit 203 to output a shutdown voltage VGL for driving the gate driver circuit 110, or to control the shutdown voltage VGL of the transistor TFT in the sub-pixel SPX. The absolute value of the shutdown voltage VGL output by the power management integrated circuit 203 is negatively correlated with the refresh rate of the display device 10.

[0128] Exemplarily, the display device 10 further includes a second power management circuit (the second power management circuit may be the power management integrated circuit 203 or a power IC additional to the power management integrated circuit 203), coupled to the control circuit 600 and the display panel 100, respectively. The second power management circuit outputs a first shutdown voltage VGL1 in response to a first control signal. In response to a second control signal, the second power management circuit outputs a second shutdown voltage VGL2. The absolute value of the first shutdown voltage VGL1 is less than the absolute value of the second shutdown voltage VGL2.

[0129] The scan circuit 111 outputs an off-voltage of the first scan signal according to the first off-voltage VGL1 , or outputs an off-voltage of the second scan signal according to the second off-voltage VGL2 .

[0130] In a specific embodiment, the control circuit 600 sends a control signal to the second power management circuit according to the refresh frequency of the VBO signal input by the front-end system-level chip 20. The second power management circuit adjusts the shutdown voltage VGL (such as the first shutdown voltage VGL1 or the second shutdown voltage VGL2) used to drive the gate driver circuit 110, or the shutdown voltage VGL (such as the first shutdown voltage VGL1 or the second shutdown voltage VGL2) used to control the transistor TFT in the sub-pixel SPX in real time according to the value of the control signal. The shutdown voltage VGL adjusted in real time is given as an input signal to the level conversion circuit 204, and the low level of the signal input to the gate driver circuit 110 changes accordingly, thereby achieving the adjustment of the scanning signal Gout as the frame rate changes, such as Figure 10 shown.

[0131] Because the lower the refresh rate, the longer the Blanking time, and the longer the leakage time when the charging time is the same, the lower the frequency, the greater the absolute value of the gate off voltage for the transistor TFT in the display area AA, the more completely the transistor TFT is turned off, and the smaller the off current (or leakage current) Ioff, thereby reducing leakage loss. For example, at 60Hz, the off voltage VGL is set to -10V, and at 120Hz, the off voltage VGL is set to -8V. The specific setting value can be determined based on the actual measured panel brightness.

[0132] In the above-mentioned display device, precise charge management optimization of the display device at multiple refresh rates is achieved through a dynamic shutdown voltage regulation mechanism. The second power management circuit can flexibly respond to the control signal and output a first shutdown voltage with a smaller absolute value at a high refresh rate (first frequency), which relatively reduces the charge retention capability of the pixel during the Blanking period. At a low refresh rate (second frequency), a second shutdown voltage with a larger absolute value is output, which effectively enhances the charge retention capability to compensate for the leakage loss during the long Blanking period. This solves the brightness jump problem caused by fixed parameter design and achieves the optimal balance between different refresh frequencies and leakage loss.

[0133] In some other examples, the turn-on voltage VGH and the turn-off voltage VGL of the power management integrated circuit 203 can be adjusted simultaneously. Figure 11 As shown in the figure, the charging effect is ensured from two aspects: the start voltage VGH and the shut-off voltage VGL.

[0134] In this embodiment, the turn-on voltage VGH and the turn-off voltage VGL are adjusted, such as Figure 12 As shown, the high and low levels of the signals STV / CLK1-12 (with 12 clock signals as a cycle scan period) / VDD (including VDDO and VDDE) / VGL / LVGL in the input gate drive circuit 110 change accordingly. The turn-on voltage and turn-off voltage of all transistors TFT in the display area AA are as follows: Figure 12 The high level and low level of Gout1 (corresponding to the gate scanning signal of the first row of sub-pixels in the display area AA) and Gout2 (corresponding to the gate scanning signal of the second row of sub-pixels in the display area AA) also change accordingly.

[0135] In some other examples, the first scan signal and the second scan signal satisfy the condition that the current value of the first scan signal is smaller than the current value of the second scan signal.

[0136] In one example, if Figure 13 As shown, the scan circuit 111 includes an output sub-circuit 1111. A first terminal of the output sub-circuit 1111 is coupled to a pull-up node PU of the scan circuit, a second terminal of the output sub-circuit 1111 is coupled to a clock signal terminal CLK of the scan circuit 111, and a third terminal of the output sub-circuit is coupled to a signal output terminal OUTPUT of the scan circuit. Based on the potential of the pull-up node PU, the output sub-circuit 1111 controls the connection between the clock signal terminal CLK and the signal output terminal OUTPUT.

[0137] The signal output terminal OUTPUT is used to output a first scanning signal or a second scanning signal. The operating current of the first scanning signal is smaller than the operating current of the second scanning signal.

[0138] In the above-mentioned display device, precise dynamic current control of the display device at multiple refresh rates is achieved through the design of the scanning circuit architecture. The output subcircuit adopts a three-terminal control structure, which controls the conduction state of the clock signal and the output signal by pulling up the node potential. At a high refresh rate (first frequency), a first scanning signal with a smaller operating current is output, reducing the sub-pixel charging efficiency. At a low refresh rate (second frequency), a second scanning signal with a larger operating current is output, enhancing the charging efficiency to compensate for leakage loss during low-frequency operation, thereby achieving brightness consistency when switching between different refresh frequencies.

[0139] The output sub-circuit 1111 includes the following Figure 3 The third transistor M3 shown can lead out output lines at different positions of the third transistor M3 and connect to the signal output end OUTPUT line. A transistor is set at each lead-out position, and different refresh frequencies correspond to different numbers of transistors that are turned on. Of course, when the refresh frequency is high, transistors with similar values ​​can share the same branch.

[0140] In one embodiment, Figure 14 As shown, the output sub-circuit 1111 includes: a plurality of transistors (such as a first transistor T1, a second transistor T2, ..., an n-1th transistor Tn-1 and an nth transistor Tn), a first electrode of each transistor (the first electrode can be a source electrode of the transistor, the first electrode includes Figure 14In the example, S1, S2, ..., Sn-1, and Sn are coupled to the clock signal terminal CLK, the second electrode of each transistor (the second electrode can be the drain of the transistor) is coupled to the signal output terminal OUTPUT, and the control electrode of each transistor (the control electrode can be the gate of the transistor) is respectively connected to the corresponding enable signal terminal (the enable signal terminal includes Figure 14 VEN11, VEN12, ..., VEN 1n-1 and VEN1n) are connected.

[0141] In another specific embodiment, Figure 15 As shown, a plurality of transistors are provided, wherein the first electrodes of the transistors are coupled to the third terminal of the output sub-circuit, the second electrodes of the transistors are coupled to the signal output terminal OUTPUT, and the control electrodes of the transistors are respectively connected to the corresponding enable signal terminals.

[0142] In another specific embodiment, taking 6 refresh frequencies as an example, 6 metal wires are drawn. Figure 16 As shown, the output sub-circuit 1111 includes: a plurality of transistors (such as a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6), a first electrode of each transistor (the first electrode can be a source electrode of the transistor, the first electrode includes Figure 16 The S1, S2, S3, S4, S5 and S6 in the figure are coupled to the clock signal terminal CLK, the second electrode of each transistor (the second electrode can be the drain of the transistor) is coupled to the signal output terminal OUTPUT, and the control electrode of each transistor (the control electrode can be the gate of the transistor) is respectively connected to the corresponding enable signal terminal (the enable signal terminal includes Figure 16 VEN11, VEN12, VEN13, VEN14, VEN15 and VEN16) are connected.

[0143] like Figure 17 As shown, each lead point (such as S1, S1, S2, S3, S4, S5 and S6) is connected to the first electrode (which can be the source electrode) of its corresponding transistor TFT, the first electrode (which can be the drain electrode) of the transistor TFT is connected to the signal output terminal OUTPUT, and the control electrode (which can be the gate electrode) of the transistor TFT is controlled by an external enable signal, such as Figure 16 The six transistors TFT correspond to VEN11 to VEN16 respectively.

[0144] In the above-mentioned display device, high-precision dynamic control of the scan signal output is achieved through the design of a multi-transistor array architecture. The output subcircuit adopts two optional transistor configuration schemes: the first is to connect multiple transistors in parallel between the clock signal terminal and the signal output terminal, and control the on and off of each transistor through an independent enable signal. The second is to connect the transistor array between the internal node of the output subcircuit and the signal output terminal. This flexible transistor array design can accurately adjust the output current intensity by hierarchically controlling the enable signal - at high refresh rates, fewer transistors are selectively turned on to output the first scan signal with a smaller operating current, thereby reducing the sub-pixel charging efficiency. At low refresh rates, more transistors are turned on to output the second scan signal with a larger operating current, enhancing the charging efficiency to compensate for the leakage loss during low-frequency operation, so as to achieve brightness consistency when switching between different refresh frequencies.

[0145] Furthermore, the enable signal terminal is used to couple to an external enable module, such as Figure 18 As shown, the display device 10 further includes a third power management circuit 700 (the third power management circuit 700 may be the power management integrated circuit 203 or a power IC added to the power management integrated circuit 203). The third power management circuit 700 is coupled to the control circuit 600 and the control electrode of each transistor. In response to a first control signal, the third power management circuit 700 outputs enable signals to the control electrodes of the plurality of transistors to turn on a first number of transistors among the plurality of transistors, or, in response to a second control signal, outputs enable signals to the control electrodes of the plurality of transistors to turn on a second number of transistors among the plurality of transistors. The first number is less than the second number.

[0146] In the specific implementation, Figure 18 As shown, the control circuit 600 transmits corresponding voltage generation instructions, such as VEN11, ..., VEN1n, to the third power management circuit 700 based on the refresh frequency. Taking six refresh frequencies as an example, six metal wires are drawn. For example, at 60Hz, the third power management circuit 700 generates VEN12 / VEN13 / VEN14 / VEN15 / VEN16 at 34V, and VEN11 at -12V. At 120Hz, the third power management circuit 700 generates VEN15 / VEN16 at 34V, and VEN11 / VEN12 / VEN13 / VEN14 at -12V.

[0147] At 60Hz, VEN12 / VEN13 / VEN14 / VEN15 / VEN16 are 34V. At this point, more transistors are turned on, resulting in a larger on-current (Ion) and higher charging efficiency. At 120Hz, VEN15 / VEN16 are 34V. At this point, fewer transistors are turned on, resulting in a smaller on-current (Ion) and lower charging efficiency. At 60Hz, the blanking time is longer, leading to higher leakage current. At 120Hz, the blanking time is shorter, leading to lower leakage current. This results in consistent final brightness at the same grayscale at 60Hz and 120Hz.

[0148] In the above-mentioned display device, precise graded adjustment of the scanning current of the display device at multiple refresh rates is achieved through the dynamic control mechanism of the transistor array. The third power management circuit intelligently controls the number of transistors turned on based on the current refresh frequency: at a high refresh rate (first frequency), only the first number of transistors are turned on in response to the first control signal, forming a first scanning signal with a smaller working current, thereby reducing the sub-pixel charging efficiency. At a low refresh rate (second frequency), more (second number) transistors are turned on in response to the second control signal, generating a second scanning signal with a larger working current, effectively enhancing the charge retention capability to compensate for leakage losses during the long Blanking period. By precisely controlling the number of transistors turned on, the scanning current can be adjusted, thereby improving the screen brightness consistency of the display panel under a wide range of refresh rates.

[0149] In some other examples, the display device 10 further includes a fourth power management circuit (the fourth power management circuit may be the power management integrated circuit 203, or a power chip PowerIC additionally provided in addition to the power management integrated circuit 203). The fourth power management circuit is coupled to the control circuit 600 and the display panel 100. The fourth power management circuit outputs a third shutdown voltage VGL3 and a fourth shutdown voltage VGL4, where the absolute value of the third shutdown voltage VGL3 is less than the absolute value of the fourth shutdown voltage VGL4.

[0150] The display panel 100 further includes a voltage divider circuit. The voltage divider circuit is coupled to the fourth power management circuit and the scan circuit 111. The voltage divider circuit is configured to receive the third shutdown voltage VGL3 and the fourth shutdown voltage VGL4 (which are Figure 3 The LVGL terminals in the power supply management circuit are the same terminal or come from the same source), and output the fifth shutdown voltage VGL5 (the fifth shutdown voltage VGL5 is input to Figure 3The VGL terminal in the figure represents the actual shutdown voltage output to the display area AA. The absolute value of the fifth shutdown voltage VGL5 is greater than or equal to the absolute value of the third shutdown voltage VGL3 and less than or equal to the absolute value of the fourth shutdown voltage VGL4. The absolute value of the fifth shutdown voltage VGL5 is negatively correlated with the refresh rate of the display device. The first terminal of the voltage divider circuit 130 is used to input the third shutdown voltage VGL3, and the second terminal of the voltage divider circuit 130 is used to input the fourth shutdown voltage VGL4.

[0151] In the above-mentioned display device, adaptive charge management optimization of the display panel under a wide range of refresh rates is achieved through a graded shutdown voltage regulation system. The fourth power management circuit works in conjunction with the voltage divider circuit to construct an adjustable shutdown voltage output system: the fourth power management circuit provides a basic voltage (a third shutdown voltage and a fourth shutdown voltage with a higher absolute value), and the voltage divider circuit generates a fifth shutdown voltage that can be dynamically adjusted between the third and fourth shutdown voltages through precise voltage division processing. This voltage value is negatively correlated with the refresh frequency - at high refresh rates, a fifth shutdown voltage with a smaller absolute value is output to reduce power consumption, and at low refresh rates, the absolute value is automatically increased to enhance charge retention. This closed-loop voltage regulation architecture achieves adjustable shutdown voltage through a voltage divider circuit, matching the leakage characteristics of the display panel at different refresh rates, thereby improving the consistency of display brightness under a wide range of refresh rates.

[0152] In one example, if Figure 19 As shown, the voltage divider circuit 130 includes: a plurality of switch sub-circuits 131, a first end of the switch sub-circuit 131 (which can be a transistor TFT) is coupled to any resistor (such as Figure 19 The second end of the switch sub-circuit 131 serves as the output end of the voltage divider circuit 130, and can output the shutdown voltage VGL51, the shutdown voltage VGL52, ..., the shutdown voltage VGL5(n-1) and the shutdown voltage VGL5n respectively. The controlled end of the switch sub-circuit 131 is respectively connected to the corresponding enable signal end (the enable signal end input is as follows Figure 19 The first enable signal VEN21, the second enable signal VEN22, ..., the n-1th enable signal VEN2n-1, and the nth enable signal VEN2n) shown in FIG are used to control the on / off of the switch sub-circuit 131. The second end of the switch sub-circuit 131 outputs a fifth shutdown voltage VGL5. The fifth shutdown voltage VGL5 can be any one of a shutdown voltage VGL51, a shutdown voltage VGL52, ..., a shutdown voltage VGL5(n-1), and a shutdown voltage VGL5n.

[0153] The third off-voltage VGL3 is the off-voltage of the transistor TFT in the display area AA, and the fourth off-voltage VGL4 is the off-voltage of the scanning circuit 111. The larger the absolute value of the off-voltage, the smaller the leakage current of the transistor TFT and the higher the brightness of the display panel.

[0154] The voltage divider circuit 130 can be disposed on the DP side of the display panel 100 (the location closer to the circuit board 200 is the near-end DP, and the location farther from the circuit board PCB is the far-end DPO). Specifically, resistors and transistors (TFTs) are added to the DP side of the display panel 100 to form a switch sub-circuit 131. Multiple switch sub-circuits 131 form the voltage divider circuit 130.

[0155] In one embodiment, Figure 20 As shown, the switch sub-circuit 131 is a transistor TFT, and the voltage divider circuit 130 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6 as a six-way switch sub-circuit 131. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are controlled by a first enable signal VEN21, a second enable signal VEN22, a third enable signal VEN23, a fourth enable signal VEN24, a fifth enable signal VEN25, and a sixth enable signal VEN26, respectively. For example, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5 are connected in series between the first and second ends of the voltage divider circuit 130.

[0156] Each resistor is connected to the output end of the voltage divider circuit via a transistor TFT. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 output a shutdown voltage VGL51, a shutdown voltage VGL52, a shutdown voltage VGL53, a shutdown voltage VGL54, a shutdown voltage VGL55, and a shutdown voltage VGL56, respectively. In absolute terms, |VGL51=VGL3|<|VGL52|<|VGL53|<|VGL54|<|VGL55|<|VGL56=VGL4|. The fifth shutdown voltage VGL5 can be any one of the shutdown voltages VGL51, VGL52, VGL53, VGL54, VGL55, and VGL56.

[0157] In the above-mentioned display device, precise regulation of the shutdown voltage of the display panel is achieved through the design of a voltage divider circuit. The voltage divider circuit adopts a combination architecture of multiple switch sub-circuits and a resistor network. Each switch sub-circuit is connected to a different node of the resistor network, and the on and off of each switch is independently controlled by an enable signal, thereby generating a fifth shutdown voltage of different levels between the third and fourth shutdown voltages. This design can accurately output a shutdown voltage value that matches the refresh rate through the voltage divider ratio and switch combination of the resistor network, thereby achieving high-precision regulation. At the same time, each switch sub-circuit is independently controlled, and the voltage divider ratio can be flexibly configured according to different refresh frequencies, which can ensure that the large shutdown voltage at low frequency maintains charge stability, and can also achieve a small shutdown voltage at high frequency, appropriately reducing the charge retention ability of the pixel during the Blanking period, thereby improving the consistency of the wide range refresh rate display.

[0158] Furthermore, the enable signal terminal is used to couple to an external enable module. For example, the display device 10 further includes a fifth power management circuit (the fifth power management circuit can be a power management integrated circuit 203 or a power chip Power IC provided in addition to the power management integrated circuit 203). The fifth power management circuit is coupled to the control circuit 600 and the controlled terminal of the switch sub-circuit 131, respectively. In response to the first control signal, the fifth power management circuit outputs an enable signal to the controlled terminals of the plurality of switch sub-circuits 131, respectively, to turn on a first target switch sub-circuit among the plurality of switch sub-circuits 131. In response to the second control signal, the fifth power management circuit outputs an enable signal to the controlled terminals of the plurality of switch sub-circuits 131, respectively, to turn on a second target switch sub-circuit among the plurality of switch sub-circuits. The resistance between the first terminal of the first target switch sub-circuit and the first terminal of the voltage divider circuit is less than the resistance between the first terminal of the second target switch sub-circuit and the first terminal of the voltage divider circuit.

[0159] Specifically, Figure 20 Taking the voltage divider circuit 130 shown as an example, the control circuit 600 transmits corresponding voltage generation instructions to the fifth power management circuit based on the refresh rate. For example, at 60Hz, the fifth power management circuit generates VEN25 at 34V, and VEN21 / VEN22 / VEN23 / VEN24 / VEN26 are all -12V. At 120Hz, the fifth power management circuit generates VEN22 at 34V, and VEN21 / VEN23 / VEN24 / VEN25 / VEN26 are all -12V.

[0160] At 60Hz, VEN25 is 34V, at which point VGL5 = VGL55. The absolute value of the off-state voltage of the AA transistor TFT in the display area is higher, the leakage current Ioff is lower, and the charging effect is better. At 120Hz, VEN22 is 34V, at which point VGL5 = VGL52. The absolute value of the off-state voltage of the AA transistor TFT in the display area is lower, the leakage current Ioff is slightly higher, and the charging effect is slightly worse. This results in comparable final brightness at the same grayscale at 60Hz and 120Hz.

[0161] In this embodiment, the third shutdown voltage VGL3 and the fourth shutdown voltage VGL4 output by the fourth power management circuit are not adjusted. Figure 12 As shown in FIG, the high and low levels of the signals STV / CLK1-12 (with 12 clock signals as one cycle scan period) / VDD (including VDDO and VDDE) / VGL / LVGL input to the gate driver circuit 110 remain unchanged. The adjusted VGL5 is the off-state voltage for all transistors TFT in display area AA, i.e., the low levels of Gout1 (corresponding to the gate scan signal for the first row of sub-pixels in display area AA) and Gout2 (corresponding to the gate scan signal for the second row of sub-pixels in display area AA).

[0162] In the above-mentioned display device, dynamic matching of the display panel shutdown voltage and refresh rate is achieved through a voltage division control system. The fifth power management circuit outputs a differentiated enable signal based on the current refresh frequency, and accurately controls the conduction combination of the switch sub-circuit: at a high refresh rate, the first target switch sub-circuit is turned on, a voltage division path with a smaller resistance value is selected, and a fifth shutdown voltage with a smaller absolute value is output to reduce power consumption; at a low refresh rate, the second target switch sub-circuit is turned on, and a voltage division path with a larger resistance value is switched to generate a fifth shutdown voltage with a larger absolute value to enhance the charge retention capability. This implementation scheme design ensures that the shutdown voltage and the refresh rate have a strict negative correlation characteristic through the precise voltage division ratio design of the resistor network, thereby improving the consistency of the display over a wide range of refresh rates.

[0163] It should be noted that the voltages corresponding to the enable signals VEN generated by the third power management circuit and the fifth power management circuit are different. If both schemes need to be used at the same time, the circuit board needs to generate two sets of voltages; the enable signal VEN voltage can be generated by the third power management circuit and the fifth power management circuit (both are voltage generation modules). If the original power management integrated circuit 203 circuit has idle (Dummuy) modules and channels available, it can be generated directly by the original power management integrated circuit 203; if the original power management integrated circuit 203 has no extra channels, it can also be a power chip Power IC added outside the power management integrated circuit 203.

[0164] Each of the above embodiments can be used in real time as the refresh rate changes. Since the timing control circuit 202 or the control circuit 600 has a certain amount of memory, it can store more than a dozen frames of undisplayed picture data (taking 16 frames as an example in this article), for example, if the currently displayed picture is the Nth frame, the timing control circuit 202 or the control circuit 600 has received N+1 / N+2... / N+16 data transmitted by the system board, and the timing control circuit 202 or the control circuit 600 can determine the picture information through the stored data; at the same time, the timing control circuit 202 or the control circuit 600 can read the refresh rate of each frame. In order to reduce power consumption, a prerequisite can be set, that is, it is enabled when the refresh rate changes under the same picture, and it can be disabled in other cases.

[0165] In other possible implementations, the brightness of the display device 10 is determined by the backlight brightness and the characteristics of the display panel. When the refresh rate of the display device 10 changes, the brightness of the picture is lower than when the frame rate is high because the leakage time is longer when the frame rate is lower. Therefore, the brightness of the entire device can be kept stable by adjusting the backlight brightness in conjunction with the panel characteristics when the refresh rate changes.

[0166] like Figure 1 As shown, the display device 10 can detect frame rate changes in real time, transmit the signal required by the display panel 100 to the timing control circuit 202, and send a signal to the backlight control circuit 400 at the same time. This signal includes the voltage amplitude and high-level duty cycle of the backlight lamp beads in the backlight module 300.

[0167] like Figure 21 As shown, the backlight brightness of the backlight module 300 can be adjusted by adjusting only the amplitude, adjusting only the high-level duty cycle, or adjusting both the amplitude and the high-level duty cycle; Figure 21 PWM is the initial driving signal, PWM-1 is a driving signal with a high-level amplitude reduced by 10%, PWM-2 is a driving signal with a high-level amplitude increased by 10%, PWM-3 is a driving signal with a high-level duty cycle of 25%, and PWM-4 is a driving signal with a high-level duty cycle of 35%.

[0168] Taking the adjustment of the high-level duty cycle as an example, the duty cycle is set to different gears: at 60Hz, the panel leaks more and the picture is darker. At this time, the high-level duty cycle of the backlight drive signal is appropriately increased (for example, 35%) to compensate for the brightness difference caused by panel leakage; at 120Hz, the panel leaks less and the picture is brighter, so the high-level duty cycle of the backlight drive signal is appropriately lowered (for example, 33%); so that the final brightness at the same grayscale of 60Hz and 120Hz is equivalent.

[0169] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display device, characterized in that: include: The control circuit is configured to: output a first control signal when the refresh frequency of the display device is a first frequency; or output a second control signal when the refresh frequency of the display device is a second frequency; the first frequency is greater than the second frequency; The display panel includes a plurality of scanning circuits and a plurality of rows of sub-pixels, each of the scanning circuits being connected to at least one row of sub-pixels; the scanning circuits being configured to: output a first scanning signal according to the first control signal; or output a second scanning signal according to the second control signal; The signal parameters of the first scanning signal are different from the signal parameters of the second scanning signal, so that the brightness difference of the display panel when displaying a set gray scale at the first frequency and the second frequency is within a preset range.

2. The display device according to claim 1, wherein The signal parameters include: at least one of a gate drive capability GOE time of the scan signal, a voltage value of an operating voltage of the scan signal, a voltage value of an off voltage of the scan signal, and a current value of the scan signal; wherein the gate drive capability GOE time is a time difference between an end time of the operating voltage of the scan signal and an end time of the corresponding data signal; The first scanning signal and the second scanning signal satisfy at least one of the following conditions: The gate driving capability GOE time of the first scanning signal is greater than the gate driving capability GOE time of the second scanning signal; The voltage value of the operating voltage of the first scanning signal is smaller than the voltage value of the operating voltage of the second scanning signal; The absolute value of the off voltage of the first scanning signal is smaller than the absolute value of the off voltage of the second scanning signal; A current value of the first scanning signal is smaller than a current value of the second scanning signal.

3. The display device according to claim 2, wherein: The display panel further includes a source driving circuit and a plurality of data lines coupled to the source driving circuit, each of the data lines being connected to at least one column of the sub-pixels; The source driving circuit is configured to: output a first data signal according to the first control signal; or output a second data signal according to the second control signal; The end time of the operating voltage of the first scanning signal is earlier than the end time of the operating voltage of the second scanning signal; and / or the end time of the first data signal is later than the end time of the second data signal.

4. The display device according to claim 2, wherein: The control circuit comprises: A memory storing a mapping relationship table, wherein the mapping relationship table is used to represent the corresponding relationship between the refresh frequency of the display device and the gate drive capability GOE time at different grayscales; The processor is used to determine the gate drive capability GOE time corresponding to the current frequency according to the target grayscale of the display device, the current frequency and the mapping relationship table; and output corresponding control signals and data signals according to the gate drive capability GOE time.

5. The display device according to claim 1, wherein The display device further includes: A first power management circuit is coupled to the control circuit and the display panel, and is configured to: output a first turn-on voltage in response to the first control signal; outputting a second turn-on voltage in response to the second control signal; Wherein, the first turn-on voltage is less than the second turn-on voltage; The scanning circuit is specifically configured to: output the operating voltage of the first scanning signal according to the first turn-on voltage; or output the operating voltage of the second scanning signal according to the second turn-on voltage.

6. The display device according to claim 1, wherein The display device further includes: A second power management circuit is coupled to the control circuit and the display panel, and is configured to: output a first shutdown voltage in response to the first control signal; In response to the second control signal, outputting a second shutdown voltage; an absolute value of the first shutdown voltage is smaller than an absolute value of the second shutdown voltage; The scanning circuit is specifically configured to: output the off voltage of the first scanning signal according to the first off voltage; or output the off voltage of the second scanning signal according to the second off voltage.

7. The display device according to claim 1, wherein The scanning circuit includes: an output subcircuit, wherein a first terminal of the output subcircuit is coupled to the pull-up node of the scan circuit, a second terminal of the output subcircuit is coupled to the clock signal terminal of the scan circuit, and a third terminal of the output subcircuit is coupled to the signal output terminal of the scan circuit; the output subcircuit is configured to: control the connection and disconnection of the clock signal terminal and the signal output terminal based on the potential of the pull-up node; The signal output terminal is used to output the first scanning signal or the second scanning signal; and an operating current of the first scanning signal is smaller than an operating current of the second scanning signal.

8. The display device according to claim 7, wherein: The output sub-circuit comprises: a plurality of transistors, wherein a first electrode of each transistor is coupled to the clock signal terminal, a second electrode of each transistor is coupled to the signal output terminal, and a control electrode of each transistor is connected to a corresponding enable signal terminal; or, A plurality of transistors, wherein the first electrodes of the transistors are coupled to the third terminal of the output sub-circuit, the second electrodes of the transistors are coupled to the signal output terminal, and the control electrodes of the transistors are respectively connected to the corresponding enable signal terminals.

9. The display device according to claim 8, wherein The display device further includes: A third power management circuit is coupled to the control circuit and the control electrode of each of the transistors, and is configured to: output enable signals to the control electrodes of the plurality of transistors in response to the first control signal, so as to turn on a first number of transistors among the plurality of transistors; or In response to the second control signal, outputting enable signals to control electrodes of the plurality of transistors respectively, so as to turn on a second number of transistors among the plurality of transistors; The first number is smaller than the second number.

10. The display device according to claim 1, wherein The display device further includes: a fourth power management circuit, coupled to the control circuit and the display panel, respectively; and configured to: output a third shutdown voltage and a fourth shutdown voltage, wherein an absolute value of the third shutdown voltage is smaller than an absolute value of the fourth shutdown voltage; The display panel further includes: a voltage divider circuit, the voltage divider circuit being coupled to the fourth power management circuit and the scan circuit respectively; The voltage divider circuit is configured to receive the third shutdown voltage and the fourth shutdown voltage and output a fifth shutdown voltage, wherein an absolute value of the fifth shutdown voltage is greater than or equal to an absolute value of the third shutdown voltage and less than or equal to an absolute value of the fourth shutdown voltage; The absolute value of the fifth shutdown voltage is negatively correlated with the refresh rate of the display device.

11. The display device according to claim 10, wherein: The voltage divider circuit comprises: Multiple switch sub-circuits, wherein the first end of the switch sub-circuit is coupled to one end of any one of the multiple resistors connected in series between the first end and the second end of the voltage divider circuit; the second end of the switch sub-circuit serves as the output end of the voltage divider circuit; and the controlled ends of the switch sub-circuits are respectively connected to the corresponding enable signal ends for controlling the on and off of the switch sub-circuits.

12. The display device according to claim 11, wherein The display device further includes: a fifth power management circuit, coupled to the control circuit and the controlled terminals of the switch sub-circuits, respectively, and configured to: in response to the first control signal, output an enable signal to the controlled terminals of the plurality of switch sub-circuits, respectively, so as to turn on a first target switch sub-circuit among the plurality of switch sub-circuits; In response to the second control signal, outputting enable signals to the controlled terminals of the plurality of switch sub-circuits respectively, so as to turn on a second target switch sub-circuit among the plurality of switch sub-circuits; The resistance between the first end of the first target switch subcircuit and the first end of the voltage divider circuit is smaller than the resistance between the first end of the second target switch subcircuit and the first end of the voltage divider circuit.

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