Filter circuit, clock data recovery method, circuit and receiver

Abstract

The invention discloses a filter circuit, a clock data recovery method, a circuit and a receiver, and belongs to the technical field of signal processing. The filter circuit comprises: a voting module configured to vote according to at least two groups of input data to obtain a target voting result, and send the target voting result to a selection module, each group of input data comprising a clock phase and data, and the target voting result indicating a relative relationship between the clock phase and the data; the selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient and send the clock adjustment parameter and the target adjustment coefficient to the processing module; the processing module is configured to obtain recovery parameters according to the clock adjustment parameters and the target adjustment coefficient, and the recovery parameters are used for recovering the clock and the data. The obtained recovery parameters are more accurate, noise is effectively suppressed, and the accuracy of recovering clocks and data based on the recovery parameters is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of signal processing technology, and in particular to a filtering circuit, a clock data recovery method, a circuit, and a receiver. Background Art

[0002] CDR (Clock Data Recovery) technology plays a crucial role in HDMI (High Definition Multimedia Interface) signal transmission. CDR extracts clock information from received HDMI signals and uses this information to restore the original data signal. Filters play a crucial role in HDMI CDR technology, primarily pre-processing the received HDMI signal to remove noise and interference, thereby improving the performance and stability of the CDR circuit. Summary of the Invention

[0003] The embodiments of the present application provide a filter circuit, a clock data recovery method, a circuit, and a receiver, which can be used to improve the performance and stability of a CDR circuit. The technical solution is as follows:

[0004] In one aspect, an embodiment of the present application provides a filtering circuit, the filtering circuit comprising a voting module, a selection module, and a processing module;

[0005] The voting module is configured to vote based on at least two sets of input data to obtain a target voting result, and send the target voting result to the selection module, wherein each set of input data includes a clock phase and data, and the target voting result indicates a relative relationship between the clock phase and the data;

[0006] The selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient, and send the clock adjustment parameter and the target adjustment coefficient to the processing module;

[0007] The processing module is configured to obtain a recovery parameter according to the clock adjustment parameter and the target adjustment coefficient, where the recovery parameter is used to recover clock and data.

[0008] In a possible implementation, the voting module is further configured to receive a voting mode signal, where the voting mode signal indicates a voting mode, and different voting modes correspond to different ways of obtaining voting results;

[0009] When voting according to at least two sets of input data, the voting module is configured to vote according to the voting mode indicated by the voting mode signal according to the at least two sets of input data.

[0010] In one possible implementation, the voting module is configured to, when the voting mode is the first voting mode, obtain a primary voting result based on every two sets of input data, then obtain a secondary voting result based on every two primary voting results, and determine the target voting result based on a relationship between a value of the secondary voting result and a reference value; or

[0011] When the voting mode is the second voting mode, a first-level voting result is obtained based on every two groups of input data, and then a second-level voting result is obtained based on every two first-level voting results. A third-level voting result is obtained based on the two second-level voting results. The third-level voting results and the remaining second-level voting results are combined in pairs for voting, and the target voting result is obtained based on the voting results of the pairwise combinations.

[0012] In a possible implementation, the selection module includes a first selector and a second selector;

[0013] The first selector is configured to determine the clock adjustment parameter according to the target voting result and send the clock adjustment parameter to the processing module;

[0014] The second selector is configured to receive a gear control signal, select an adjustment coefficient that matches the gear corresponding to the gear control signal, use the adjustment coefficient that matches the gear corresponding to the gear control signal as the target adjustment coefficient, and send the target adjustment coefficient to the processing module.

[0015] In a possible implementation, the processing module includes a multiplier and an accumulator;

[0016] The multiplier is configured to perform a multiplication operation on the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result, and send the first operation result to the accumulator;

[0017] The accumulator is configured to accumulate the first operation result and the feedback coefficient to obtain a second operation result, and obtain the recovery parameter based on the second operation result. The feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

[0018] In a possible implementation, the filtering circuit further includes: a clock lock detection module;

[0019] The clock lock detection module is configured to detect whether the clock is locked and obtain a detection result of clock lock.

[0020] In a possible implementation, the clock lock detection module is further configured to receive a first mode signal, where the first mode signal indicates a first mode;

[0021] When detecting whether the clock is locked, the clock lock detection module is configured to detect whether the clock is locked according to the target voting result based on the first mode indicated by the first mode signal.

[0022] In a possible implementation, the target voting result includes a first value or a second value, wherein the first value indicates that the relative relationship between the clock phase and the data is that the clock phase is earlier than the data, and the second value indicates that the relative relationship between the clock phase and the data is that the clock phase is later than the data.

[0023] The clock lock detection module is configured to detect a continuous number of the first value or the second value within a reference time period, and obtain a clock lock detection result according to the continuous number of the first value or the second value.

[0024] In a possible implementation, the clock lock detection module is further configured to receive a second mode signal, where the second mode signal indicates a second mode;

[0025] When detecting whether the clock is locked, the clock lock detection module is configured to wait for a reference number of cycles based on the second mode indicated by the second mode signal and then obtain a detection result indicating that the clock is locked.

[0026] In another aspect, a clock data recovery method is provided, the method comprising:

[0027] Voting based on at least two sets of input data to obtain a target voting result, each set of input data including a clock phase and data, the target voting result indicating a relative relationship between the clock phase and the data;

[0028] Determine a clock adjustment parameter according to the target voting result, and obtain a target adjustment coefficient;

[0029] A recovery parameter is acquired according to the clock adjustment parameter and the target adjustment coefficient, and the recovery parameter is used to recover clock and data.

[0030] In a possible implementation, before voting according to the at least two sets of input data, the method further includes: receiving a voting mode signal, the voting mode signal indicating a voting mode, where different voting modes correspond to different ways of obtaining voting results;

[0031] The voting according to at least two sets of input data includes:

[0032] Voting is performed according to the at least two sets of input data and the voting mode indicated by the voting mode signal.

[0033] In a possible implementation, voting according to the at least two sets of input data and the voting mode indicated by the voting mode signal includes:

[0034] When the voting mode is the first voting mode, a primary voting result is obtained based on every two sets of input data, and a secondary voting result is obtained based on every two primary voting results, and the target voting result is determined based on the relationship between the value of the secondary voting result and a reference value; or

[0035] When the voting mode is the second voting mode, a first-level voting result is obtained based on every two groups of input data, and then a second-level voting result is obtained based on every two first-level voting results. A third-level voting result is obtained based on the two second-level voting results. The third-level voting results and the remaining second-level voting results are combined in pairs for voting, and the target voting result is obtained based on the voting results of the pairwise combinations.

[0036] In a possible implementation, obtaining the adjustment coefficient includes:

[0037] A gear control signal is received, an adjustment coefficient that matches the gear corresponding to the gear control signal is selected, and the adjustment coefficient that matches the gear corresponding to the gear control signal is used as the target adjustment coefficient.

[0038] In a possible implementation, the acquiring the recovery parameter according to the clock adjustment parameter and the target adjustment coefficient includes:

[0039] Performing a multiplication operation on the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result;

[0040] The first operation result and the feedback coefficient are accumulated to obtain a second operation result, and the recovery parameter is obtained based on the second operation result. The feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

[0041] In a possible implementation, the method further includes:

[0042] Check whether the clock is locked and obtain a clock locked detection result.

[0043] In a possible implementation, the method further includes: receiving a first mode signal, where the first mode signal indicates a first mode;

[0044] The detecting whether the clock is locked includes: detecting whether the clock is locked according to the target voting result based on the first mode indicated by the first mode signal.

[0045] In a possible implementation, the target voting result includes a first value or a second value, wherein the first value indicates that the relative relationship between the clock phase and the data is that the clock phase is earlier than the data, and the second value indicates that the relative relationship between the clock phase and the data is that the clock phase is later than the data.

[0046] Detecting whether the clock is locked according to the target voting result includes: detecting the consecutive number of the first value or the second value within a reference time period, and obtaining a clock lock detection result according to the consecutive number of the first value or the second value.

[0047] In a possible implementation, the method further includes: receiving a second mode signal, where the second mode signal indicates a second mode;

[0048] The detecting whether the clock is locked includes: based on the second mode indicated by the second mode signal, waiting for a reference number of cycles, and obtaining a detection result indicating that the clock is locked.

[0049] On the other hand, a clock data recovery circuit is provided, which includes any one of the above-mentioned filter circuits.

[0050] On the other hand, a high-definition multimedia interface receiver is provided. The high-definition multimedia interface receiver includes the clock data recovery circuit.

[0051] The technical solutions provided by the embodiments of the present application bring at least the following beneficial effects:

[0052] The technical solution provided in the present application, after voting based on at least two sets of input data to obtain the target voting results, takes into account the target adjustment coefficient when obtaining the recovery parameters in addition to the clock adjustment parameters determined based on the target voting results, so that the obtained recovery parameters are more accurate, thereby achieving effective suppression of noise and improving the accuracy of clock and data recovery based on the recovery parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] Figure 1This is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0055] Figure 2 This is a structural diagram of a filter circuit provided in an embodiment of the present application;

[0056] Figure 3 This is a schematic diagram of the principle process of a filtering circuit provided by an embodiment of the present application;

[0057] Figure 4 This is a schematic diagram of a voting process provided by an embodiment of the present application;

[0058] Figure 5 This is another voting process diagram provided in an embodiment of the present application;

[0059] Figure 6 This is a flow chart of a clock data recovery method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] It should be noted that the terms "first," "second," etc. (if any) in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the application as detailed in the appended claims.

[0062] For HDMI signals, clock information is generally embedded into the transmitted data stream through data encoding. The clock information is then extracted at the receiving end through clock recovery, and the data is sampled using this recovered clock. Since CDR technology can extract clock information from the received HDMI signal and use it to restore the original data signal, this process is crucial to ensuring that the HDMI signal maintains high quality over long distances or in high-noise environments.

[0063] Among them, the CDR circuit is generally implemented by means of PLL (Phase-Locked Loop). Figure 1Taking the implementation environment shown as an example, the input digital signal and the PLL's VCO (voltage-controlled oscillator) undergo phase comparison. If there's a frequency difference between the data rate and the VCO's output frequency, a phase difference will occur. The phase detector then compares this phase error and converts it into a corresponding voltage control signal. This voltage control signal is filtered by a filter to generate a control signal for the VCO, thereby adjusting the VCO's output clock frequency. It's easy to see that the purpose of using a filter is to integrate the rapid phase change information and convert it into a relatively slow voltage change to adjust the VCO's output frequency. Through repeated phase comparison and adjustment, the VCO's output signal frequency eventually matches the frequency of the input digital signal, at which point the PLL phase-locked loop circuit enters a locked state.

[0064] Furthermore, similar to the principle of the above process, filters play an important role in HDMI CDR technology. Filters are mainly used to pre-process the received HDMI signal to remove noise and interference, thereby improving the performance and stability of the CDR circuit.

[0065] The embodiment of the present application provides a filtering circuit, which, as an external digital circuit, can cooperate with the analog CDR circuit to effectively suppress noise, thereby obtaining high-quality recovered clock and data. Figure 2 The filtering circuit includes a voting module 201, a selection module 202 and a processing module 203.

[0066] The voting module 201 is configured to vote based on at least two sets of input data to obtain a target voting result, and send the target voting result to the selection module 202. Each set of input data includes a clock phase and data, and the target voting result indicates the relative relationship between the clock phase and the data.

[0067] The selection module 202 is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient, and send the clock adjustment parameter and the target adjustment coefficient to the processing module 203 .

[0068] The processing module 203 is configured to obtain a recovery parameter according to the clock adjustment parameter and the target adjustment coefficient, where the recovery parameter is used to recover the clock and data.

[0069] Next, Figure 3Taking the principle process diagram of the filtering device shown in FIG. 2 as an example, the functions of the above-mentioned modules are illustrated, wherein the above-mentioned voting module 201 can be implemented by a PD (Phase Detector). PD is essentially a device that can identify the phase difference of the input signal, and is a circuit that makes the output voltage have a definite relationship with the phase difference between the two input signals. In the CDR system, PD is an important component of the PLL (Phase Locked Loop) in the CDR system. PD can keenly sense the phase difference between the input data and the local clock, provide an accurate basis for subsequent frequency adjustment, and ensure that the data can be accurately recovered and sampled. The embodiment of the present application does not limit the type of PD, for example, Figure 3 BBPD (Bang-bang Phase Detector) is used.

[0070] BBPD includes three input terminals Pn, Dn-1 and Dn, where Pn represents the clock phase at the current moment, Dn represents the data at the current moment, and Dn-1 represents the data at the previous moment. For example, Figure 3 The input terminals of BBPD are P<19:0>, D<19:0> and D_pre, P<19:0> corresponds to the aforementioned Pn, D<19:0> corresponds to the aforementioned Dn, and D_pre corresponds to the aforementioned Dn-1. Figure 3 As shown, the data input to the input terminal D<19:0> of the BBPD is d<19:0>. The data input to the input terminal D_pre of the BBPD is the data of the previous moment. For example, the data input to the input terminal D<19:0> of the BBPD is Dn <19> , the data input to the input terminal D_pre of BBPD is Dn <18> , the data of the previous moment can be stored through the cache, such as Figure 3 If the data input to the BBPD input terminal D<19:0> is Dn <19> , the data input to the input terminal D_pre of BBPD is Dn-1 <0> The data inputted into the input terminal P<19:0> of the BBPD is the clock phase p<19:0>.

[0071] For example, the logic of BBPD is shown in the truth table in Table 1 below.

[0072] Table 1

[0073] D-1 P0 D0 E L 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0

[0074] As shown in Table 1 above, when Pn equals DN-1 and Dn (for example, in Table 1, D-1, P0, and D0 are 0-0-0 and 1-1-1, respectively), the phase of this bit is biased neither toward the previous data nor toward the next data. Therefore, the output values ​​E (early) and L (late) are both 0.

[0075] When pn is equal to Dn-1 but not equal to Dn (for example, D-1, P0, and D0 in Table 1 are 1-1-0 and 0-0-1, respectively), the phase of this bit is biased toward the previous data. Therefore, the outputs E(early) = 1 and L(late) = 0.

[0076] When pn is equal to Dn but not equal to Dn-1 (for example, in Table 1, D-1, P0, and D0 are 1-0-0 and 0-1-1, respectively), the phase of this bit is biased toward the previous data. Therefore, the outputs E(early) = 0 and L(late) = 1.

[0077] In one possible implementation, the voting module 201 is further configured to receive a voting mode signal, which indicates a voting mode, and different voting modes correspond to different methods of obtaining voting results; when the voting module 201 votes based on at least two sets of input data, it is configured to vote according to the voting mode indicated by the voting mode signal based on at least two sets of input data.

[0078] Among them, the above voting mode signal is, for example, Figure 3 As shown in the bbpd_mode input signal in FIG, different values ​​of the bbpd_mode input signal can indicate different voting modes. For example, when the value of the bbpd_mode input signal is a first value, such as 1, it indicates that the voting mode is the first voting mode. When the value of the bbpd_mode input signal is a second value, such as 0, it indicates that the voting mode is the second voting mode. This embodiment of the application does not limit the magnitude of the first and second values ​​of the bbpd_mode input signal, and only uses the first value of 0 and the second value of 1 as an example.

[0079] In one possible implementation, the voting module 201 is configured to obtain a first-level voting result based on every two sets of input data when the voting mode is the first voting mode, and then obtain a second-level voting result based on every two first-level voting results, and determine the target voting result based on the relationship between the value of the second-level voting result and the reference value.

[0080] For example, the voting process of the first voting mode can be as follows: Figure 4Each set of input data includes a clock phase and data at the current moment, as well as data at the previous moment, corresponding to Figure 3 The input terminals P<19:0>, D<19:0> and D_pre of BBPD are as follows. Figure 3 As shown, the data input to the input terminal D<19:0> of BBPD is d<19:0>, for example, d<19:0> includes Figure 4 Dn <19> -Dn <0> The data input to the input terminal D_pre of BBPD is the data of the previous moment. For example, the data input to the input terminal D<19:0> of BBPD is Dn <19> , the data input to the input terminal D_pre of BBPD is Dn <18> , the data of the previous moment can be stored through the cache, such as Figure 3 If the data input to the BBPD input terminal D<19:0> is Dn <19> , the data input to the input terminal D_pre of BBPD is Dn-1 <0> The data inputted into the input terminal P<19:0> of the BBPD is the clock phase p<19:0>.

[0081] When obtaining a first-level voting result based on every two sets of input data, such as Figure 4 As shown, each PD corresponds to a set of input data, each PD outputs the value of E and L, and the output results of every two PDs correspond to a first-level voting result, that is, Figure 4 The first row of Vote (vote) outputs the values ​​of E and L. The Vote (vote) corresponding to the two PDs represents a first-level voting result, which corresponds to the voting values ​​of E and L. After that, a second-level voting result is obtained based on every two first-level voting results, which corresponds to Figure 4 The values ​​of E and L output by Vote in the second row are the values ​​of E and L output by one Vote corresponding to two Votes.

[0082] When determining the target voting result based on the relationship between the value of the secondary voting result and the reference value, including but not limited to counting the sum of the values ​​of E in all secondary voting results (corresponding to Figure 4 SUM(E) in the equation) to get the first sum value and calculate the sum of the values ​​of L (corresponding to Figure 4 SUM(L) in [ 1 ] is used to obtain the second sum. The difference between the first and second sums is then calculated. If the difference is greater than the reference value, the target voting result's E value is the first value, and the target voting result's L value is the second value. If the difference is less than the reference value, the target voting result's E value is the second value, and the target voting result's L value is the first value. If the difference is equal to the reference value, the target voting result's E value is the second value, and the target voting result's L value is the second value.

[0083] This application does not limit the size of the reference value, the first value and the second value of the value of E and L. For example, the reference value is 0, the first value is 1, and the second value is 0. Figure 4 As shown, if the difference is greater than 0 (corresponding to Figure 4 If SUM(E)-SUM(L)>0), the target voting result is E=1, L=0; if the difference is less than the reference value (corresponding to Figure 4 Else if SUM(E)-SUM(L)<0), then the target voting result is E=0, L=1; if the difference is equal to the reference value (corresponding Figure 4 Else), the target voting result is E=0, L=0.

[0084] Alternatively, the voting module 201 is configured to obtain a first-level voting result based on every two groups of input data, obtain a second-level voting result based on every two first-level voting results, obtain a third-level voting result based on the two second-level voting results, and vote on the third-level voting results in pairs with the remaining second-level voting results, and obtain the target voting result based on the voting results of the pairwise combinations.

[0085] For example, the voting process of the second voting mode can be as follows: Figure 5 shown. Figure 5 The process of obtaining the first-level voting results and the second-level voting results can be referred to above. Figure 4 The difference between the second voting mode and the first voting mode lies in the method after obtaining the secondary voting results. In the second voting mode, after obtaining the secondary voting results, a third-level voting result will be obtained based on the two secondary voting results. The third-level voting result is as follows: Figure 4 The third row of Vote, that is, the sum of the first and second level voting results, is a third level voting result. The third level voting results are combined with the remaining second level voting results in pairs for voting, such as Figure 4 As shown, the third-level voting result is combined with the third second-level voting result for voting, and the fourth second-level voting result is combined with the fifth second-level voting result for voting, resulting in two fourth-level voting results. The fourth-level voting results correspond to Figure 4 There are two Vote in the fourth row. Then, the target voting result is obtained according to the two four-level voting results, that is, Figure 4 The values ​​of E and L output by a Vote in the fifth row.

[0086] Regardless of which voting mode is used, the target voting result obtained indicates the relative relationship between the clock phase and the data. For example, the relative relationship is that the clock phase arrives earlier than the data, or the clock phase arrives later than the data. For example, the target voting result E = 1, L = 0 means that the clock phase arrives earlier than the data, or the clock phase is advanced. For another example, the target voting result E = 0, L = 1 means that the clock phase arrives later than the data, or the clock phase is lagging. In the application process, E can be replaced by DOWN and L can be replaced by UP.

[0087] In one possible implementation, the selection module 202 includes a first selector and a second selector; the first selector is configured to determine a clock adjustment parameter based on the target voting result and send the clock adjustment parameter to the processing module 203; the second selector is configured to receive a gear control signal, select an adjustment coefficient that matches the gear corresponding to the gear control signal, use the adjustment coefficient that matches the gear corresponding to the gear control signal as the target adjustment coefficient, and send the target adjustment coefficient to the processing module 203.

[0088] like Figure 3 As shown, when the value of the target voting result received by the first selector is 00, the corresponding value is 0, and the clock adjustment parameter determined by the first selector is 0; when the value of the target voting result received by the first selector is 01, the corresponding value is 1, and the clock adjustment parameter determined by the first selector is 1; when the value of the target voting result received by the first selector is 10, the corresponding value is 2, and the clock adjustment parameter determined by the first selector is -1.

[0089] Continue as Figure 3 As shown, the gear control signal received by the second selector is Figure 3 The int_gain_tune<2:0> input signal in the int_gain_tune<2:0> input signal indicates different values, corresponding to different gears, such as Figure 3 The second selector includes eight gears from 0 to 7. Each gear corresponds to a different adjustment coefficient. For example, the adjustment coefficient corresponding to gear 0 is 1 / 8, the adjustment coefficient corresponding to gear 1 is 1 / 4, the adjustment coefficient corresponding to gear 2 is 1 / 2, the adjustment coefficient corresponding to gear 3 is 1, the adjustment coefficient corresponding to gear 4 is 2, the adjustment coefficient corresponding to gear 5 is 4, the adjustment coefficient corresponding to gear 6 is 8, and the adjustment coefficient corresponding to gear 7 is 16. This embodiment of the application does not limit the gear corresponding to the value indicated by the int_gain_tune<2:0> input signal, and can be configured based on the application scenario.

[0090] In one possible implementation, the processing module 203 includes a multiplier and an accumulator; the multiplier is configured to perform a multiplication operation on the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result, and send the first operation result to the accumulator; the accumulator is configured to accumulate the first operation result and the feedback coefficient to obtain a second operation result, and obtain the recovery parameter based on the second operation result, and the feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

[0091] like Figure 3 As shown, the accumulator has two inputs, one is the output result of the multiplier, that is, the result of the first operation, and the other input is the feedback coefficient, which corresponds to Figure 3 The arrow above the accumulator corresponds to<int,frac> ,Should<int,frac> correspond Figure 3 The value of the Z-1 output corresponding to the accumulator output, that is, the feedback coefficient of the accumulation result at the previous moment.<int,frac> Represents the integer part and the decimal part, that is, the integer part and the decimal part of the accumulated value. In the embodiment of the present application, the feedback coefficient can be an integer value, that is, the integer part of the accumulated result at the previous moment. The above Z-1 corresponding to the accumulator output represents a cache, which is used to cache the accumulated result at the previous moment. When the method is executed for the first time, the Z-1 corresponding to the accumulator output may not have a cached value, so the feedback coefficient is a reference value. The embodiment of the present application does not limit the size of the reference value, and the reference value can also be called an initial value. For example, the reference value can be Figure 3 The input signal int_gain_set<9:0> is input.

[0092] Furthermore, the recovery parameter obtained based on the second operation result obtained by the accumulator can be as follows: Figure 3 The "CDRINT GAIN" parameter (Clock and Data Recovery Internal Gain) is shown in the figure. In a CDR circuit, internal gain affects the ability to detect and process data signals. Proper internal gain ensures the circuit can accurately identify clock information in the data signal, improving the accuracy and reliability of data recovery. Therefore, the "CDRINT GAIN" parameter plays a key role in the performance of the CDR circuit.

[0093] Continue with Figure 3Taking the principle process shown in the figure as an example, the clock adjustment parameter and the target adjustment coefficient are input into the multiplier for multiplication to obtain a first operation result, which is accumulated with the feedback coefficient through the accumulator. When the integer part of the accumulator changes, the calculated gain value is output to the PHY (physical layer) PMA (Physical Medium Attachment). The PHY updates the gain value and adjusts the subsequent data (data) and clock phase (phase) input to the PD, thus forming a negative feedback path.

[0094] In one possible implementation, the filtering device provided in the embodiment of the present application further adds a lock mechanism for determining whether the CDR has completed lock. CDR lock plays many important roles. For example, in high-speed serial data transmission, the clocks of the transmitting and receiving ends may have frequency differences, clock drift, and jitter. After the CDR completes lock, it can accurately extract the clock signal from the received data and use the clock signal to sample the data. For example, in a Serdes (serializer / deserializer) system, the CDR circuit at the receiving end adjusts the phase of the oscillation clock through a phase-locked loop (PLL) to track the embedded clock in the input data. When the lock is completed, it can ensure that the data is sampled at the correct time point, thereby accurately restoring the original data and avoiding data sampling errors caused by clock mismatch.

[0095] For example, achieving lock means that the clock signal output by the CDR is synchronized with the phase and frequency of the input data. This is crucial for high-speed serial bus receiver chips, as they use the recovered clock as a reference to sample and process the input signal. For example, the USB 3.0 bus has a high tolerance for low-frequency jitter in the receiving chip, but limited tolerance for high-frequency jitter. Once the CDR achieves lock, it filters out high-frequency jitter from the input signal, causing the recovered clock to jitter along with the measured signal. When the receiver uses this recovered clock as a reference for sampling, low-frequency jitter is not observed, and the setup and hold time for data sampling is minimally affected, thus ensuring synchronous data transmission and processing.

[0096] In the embodiment of the present application, the detection of whether the clock is locked can be applied to Figure 3 The cdr_clk_in input signal is a clock signal used to control the output result of the cache Z-1. When the clock is locked, the clock signal is more stable, so that the output result of the control cache Z-1 is more stable and the jitter is reduced.

[0097] Optionally, the filtering circuit further includes: a clock lock detection module; the clock lock detection module is configured to detect whether the clock is locked and obtain a detection result of the clock lock.

[0098] Exemplarily, the clock lock detection module is further configured to receive a first mode signal, which indicates a first mode; when detecting whether the clock is locked, the clock lock detection module is configured to detect whether the clock is locked based on the first mode indicated by the first mode signal and the target voting result.

[0099] In one possible implementation, the target voting result includes a first value or a second value, the first value indicating that the relative relationship between the clock phase and the data is that the clock phase is earlier than the data, and the second value indicating that the relative relationship between the clock phase and the data is that the clock phase is later than the data;

[0100] The clock lock detection module is configured to detect the number of consecutive first values ​​or second values ​​within a reference time period, and obtain a clock lock detection result according to the number of consecutive first values ​​or second values.

[0101] For example, the clock lock detection module further receives a lock signal and determines whether to trigger the clock lock detection based on the lock signal, wherein the value of the lock signal indicates the first mode signal or the second mode signal. Figure 3 For example, when lock_en = 1, the CDR performs lock detection. For example, the BB-PD output is detected within the lock_window range (i.e., the reference time period described above). If E or L has more than or equal to lock_filt (i.e., the number of consecutive 0s or 1s), the CDR is determined to be unlocked. Conversely, if consecutive 0s or 1s appear within the lock window, the lock signal is output as 1, indicating that the CDR is locked.

[0102] In addition, if relock_en is configured to be 0, the CDR output signal lock is set to 1. If relock_en is 1, it means that a second lock determination is required. The lock signal remains 0, and the CDR enters CDR relock mode (re-detect lock mode). Relock mode will perform a new lock determination according to the above operation. Only when lock is determined for the second time does it mean that the lock is truly locked, thus improving the reliability of lock detection.

[0103] In one possible implementation, the clock lock detection module is further configured to receive a second mode signal, the second mode signal indicating a second mode; when detecting whether the clock is locked, the clock lock detection module is configured to wait for a reference number of cycles based on the second mode indicated by the second mode signal, and then obtain a detection result indicating that the clock is locked. For example, when Lock_en = 0, no lock detection is performed, and the CDR sets the lock signal to 1 after waiting for N cycles. This embodiment of the present application does not limit the size of the reference number, i.e., N, and can be set based on the scenario.

[0104] Among them, the first mode signal is, for example, Figure 3 The cdr_mode input signal shown in FIG. 1 indicates different CDR modes. For example, when the value of the cdr_mode input signal is a first value, it indicates a first mode signal. When the value of the cdr_mode input signal is a second value, it indicates a second mode signal.

[0105] Based on the above introduction to the filtering device, combined with Figure 3 As can be seen from the principle process shown, the input data of PD includes 20-bit data and 20-bit clock phase, respectively according to the above Figure 1 Calculate 20 E and 20 L according to the truth table shown above. Figure 4 or Figure 5 The voting process shown calculates whether the target voting result corresponding to the final data is E or L.

[0106] Each calculated target voting result is multiplied by the adjustment coefficient in the multiplier and then added to the feedback coefficient in the accumulator. When the integer part of the accumulator changes, the calculated gain value is output to the PHY PMA part. The PHY updates the gain value and adjusts the subsequent data and clock phase input to the PD, thus forming a negative feedback path.

[0107] The filtering module provided in the embodiment of the present application votes based on at least two sets of input data to obtain the target voting result. When obtaining the recovery parameters required by the CDR, in addition to considering the clock adjustment parameters determined based on the target voting result, the target adjustment coefficient is also considered. The feedback coefficient of the CDR may also be further considered to make the obtained recovery parameters more accurate, thereby achieving effective suppression of noise and improving the accuracy of recovering the clock and data based on the recovery parameters.

[0108] It should be noted that, when the filtering device provided in the above embodiment realizes its function, it only uses the division of the above functional modules as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0109] Combined with the above Figure 2 The filtering device described above, the embodiment of the present application also provides a clock data recovery method, see Figure 6 The method includes steps 601 to 603.

[0110] In step 601, voting is performed based on at least two sets of input data to obtain a target voting result, where each set of input data includes a clock phase and data, and the target voting result indicates a relative relationship between the clock phase and the data.

[0111] In a possible implementation, before voting is performed based on at least two sets of input data, the method further includes: receiving a voting mode signal, the voting mode signal indicating a voting mode, different voting modes corresponding to different ways of obtaining voting results;

[0112] Voting according to at least two sets of input data includes: voting according to the voting mode indicated by the voting mode signal based on the at least two sets of input data.

[0113] In one possible implementation, voting is performed according to the voting mode indicated by the voting mode signal based on at least two sets of input data, including:

[0114] When the voting mode is the first voting mode, a first-level voting result is obtained based on every two sets of input data, and a second-level voting result is obtained based on every two first-level voting results, and the target voting result is determined based on the relationship between the value of the second-level voting result and the reference value; or

[0115] When the voting mode is the second voting mode, a first-level voting result is obtained based on every two sets of input data, and then a second-level voting result is obtained based on every two first-level voting results. A third-level voting result is obtained based on the two second-level voting results. The third-level voting results and the remaining second-level voting results are combined in pairs for voting, and the target voting result is obtained based on the voting results of the pairwise combinations.

[0116] In step 602, a clock adjustment parameter is determined according to the target voting result, and a target adjustment coefficient is obtained.

[0117] Exemplarily, obtaining the target adjustment coefficient includes: receiving a gear control signal, selecting an adjustment coefficient that matches the gear corresponding to the gear control signal, and using the adjustment coefficient that matches the gear corresponding to the gear control signal as the target adjustment coefficient.

[0118] In step 603, a recovery parameter is obtained according to the clock adjustment parameter and the target adjustment coefficient, and the recovery parameter is used to recover the clock and data.

[0119] In one possible implementation, a recovery parameter is obtained based on a clock adjustment parameter and a target adjustment coefficient, including: multiplying the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result; accumulating the first operation result and a feedback coefficient to obtain a second operation result, and obtaining the recovery parameter based on the second operation result, where the feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

[0120] In a possible implementation, the method provided in the embodiment of the present application further includes: detecting whether the clock is locked, and obtaining a detection result of clock locking.

[0121] In one possible implementation, the method further includes: receiving a first mode signal, the first mode signal indicating a first mode; detecting whether the clock is locked, including: detecting whether the clock is locked according to a target voting result based on the first mode indicated by the first mode signal.

[0122] Exemplarily, the target voting result includes a first value or a second value, the first value indicating that the relative relationship between the clock phase and the data is that the clock phase is earlier than the data, and the second value indicating that the relative relationship between the clock phase and the data is that the clock phase is later than the data;

[0123] Detecting whether the clock is locked according to the target voting result includes: detecting a continuous number of the first value or the second value within a reference time period, and obtaining a detection result of clock locking according to the continuous number of the first value or the second value.

[0124] In one possible implementation, the method further includes: receiving a second mode signal, the second mode signal indicating a second mode; detecting whether the clock is locked, including: based on the second mode indicated by the second mode signal, waiting for a reference number of cycles, and obtaining a detection result indicating that the clock is locked.

[0125] It should be noted that the method provided in the above embodiment and the filter device embodiment are of the same concept, and the specific implementation process thereof is detailed in the above filter device embodiment, which will not be repeated here.

[0126] The embodiment of the present application also provides a clock data recovery circuit, namely a CDR circuit. The clock data recovery circuit includes the above Figure 2 Any filter circuit provided in the embodiments. Optionally, the clock data recovery circuit further includes other components in addition to the filter circuit, and the embodiment of the present application does not limit the structure of the clock data recovery circuit.

[0127] For example, the clock data recovery circuit further includes a phase detector and a voltage controlled oscillator. The phase detector is connected to the filter circuit and the voltage controlled oscillator respectively. The phase detector is configured to sample the input signal through the output signal of the voltage controlled oscillator to obtain at least two sets of input data. The filter circuit is configured to use the above-mentioned Figure 6 The method shown outputs restoration parameters based on at least two sets of input data; a voltage-controlled oscillator is configured to adjust the frequency and phase of an output signal according to the restoration parameters output by a filtering circuit.

[0128] Optionally, the clock data recovery circuit further includes a charge pump configured to generate an adjustment signal based on the phase difference output by the phase detector, converting the voltage signal into a current signal for subsequent filter processing. Optionally, the clock data recovery circuit further includes a control circuit configured to control and manage the entire CDR circuit to ensure stable operation of the circuit, and to adjust the operating states of the filter and voltage-controlled oscillator based on the phase detector output signal and preset parameters.

[0129] The present application also provides a high-definition multimedia interface (HDMI) receiver, which includes the above-mentioned CDR circuit. Optionally, the HDMI receiver also includes other components in addition to the CDR circuit. The present application does not limit the structure of the HDMI receiver.

[0130] For example, an HDMI receiver includes, in addition to the CDR circuit, a receiving port, a video decoder, and an audio decoder. The receiving port receives signals sent by the transmitting device, including video and audio signals. The receiving port sends the received signal to the CDR circuit, which determines the clock frequency and recovers the data. The CDR circuit then passes the recovered clock and data signals to the video decoder and audio decoder. The video decoder decodes the received signal and parses the video data therein. The audio decoder decodes the received signal and parses the audio data therein.

[0131] It should be noted that the information, data, and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the input data, CDR mode signals, and voting mode signals involved in this application are all obtained with full authorization.

[0132] It should be understood that the terms "plurality" and "at least two" used herein refer to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0133] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A filter circuit, characterized in that: The filtering circuit includes a voting module, a selection module and a processing module; The voting module is configured to vote based on at least two sets of input data to obtain a target voting result, and send the target voting result to the selection module, wherein each set of input data includes a clock phase and data, and the target voting result indicates a relative relationship between the clock phase and the data; The selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient, and send the clock adjustment parameter and the target adjustment coefficient to the processing module; The processing module is configured to obtain a recovery parameter according to the clock adjustment parameter and the target adjustment coefficient, where the recovery parameter is used to recover clock and data.

2. The circuit according to claim 1, wherein: The voting module is further configured to receive a voting mode signal, wherein the voting mode signal indicates a voting mode, and different voting modes correspond to different ways of obtaining voting results; When voting according to at least two sets of input data, the voting module is configured to vote according to the voting mode indicated by the voting mode signal according to the at least two sets of input data.

3. The circuit according to claim 2, characterized in that The voting module is configured to, when the voting mode is the first voting mode, obtain a primary voting result based on every two sets of input data, then obtain a secondary voting result based on every two primary voting results, and determine the target voting result based on the relationship between the value of the secondary voting result and a reference value; or When the voting mode is the second voting mode, a first-level voting result is obtained based on every two groups of input data, and then a second-level voting result is obtained based on every two first-level voting results. A third-level voting result is obtained based on the two second-level voting results. The third-level voting results and the remaining second-level voting results are combined in pairs for voting, and the target voting result is obtained based on the voting results of the pairwise combinations.

4. The circuit according to claim 1, wherein: The selection module includes a first selector and a second selector; The first selector is configured to determine the clock adjustment parameter according to the target voting result and send the clock adjustment parameter to the processing module; The second selector is configured to receive a gear control signal, select an adjustment coefficient that matches the gear corresponding to the gear control signal, use the adjustment coefficient that matches the gear corresponding to the gear control signal as the target adjustment coefficient, and send the target adjustment coefficient to the processing module.

5. The circuit according to claim 1, wherein: The processing module includes a multiplier and an accumulator; The multiplier is configured to perform a multiplication operation on the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result, and send the first operation result to the accumulator; The accumulator is configured to accumulate the first operation result and the feedback coefficient to obtain a second operation result, and obtain the recovery parameter based on the second operation result. The feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

6. The circuit according to any one of claims 1 to 5, characterized in that: The filtering circuit further includes: a clock lock detection module; The clock lock detection module is configured to detect whether the clock is locked and obtain a detection result of clock lock.

7. The circuit according to claim 6, characterized in that The clock lock detection module is further configured to receive a first mode signal, wherein the first mode signal indicates a first mode; When detecting whether the clock is locked, the clock lock detection module is configured to detect whether the clock is locked according to the target voting result based on the first mode indicated by the first mode signal.

8. The circuit according to claim 7, characterized in that The target voting result includes a first value or a second value, wherein the first value indicates that the relative relationship between the clock phase and the data is that the clock phase is earlier than the data, and the second value indicates that the relative relationship between the clock phase and the data is that the clock phase is later than the data; The clock lock detection module is configured to detect a continuous number of the first value or the second value within a reference time period, and obtain a clock lock detection result according to the continuous number of the first value or the second value.

9. The circuit according to claim 6, characterized in that The clock lock detection module is further configured to receive a second mode signal, wherein the second mode signal indicates a second mode; When detecting whether the clock is locked, the clock lock detection module is configured to wait for a reference number of cycles based on the second mode indicated by the second mode signal and then obtain a detection result indicating that the clock is locked.

10. A clock data recovery method, characterized in that: The method comprises: Voting based on at least two sets of input data to obtain a target voting result, each set of input data including a clock phase and data, the target voting result indicating a relative relationship between the clock phase and the data; Determine a clock adjustment parameter according to the target voting result, and obtain a target adjustment coefficient; A recovery parameter is acquired according to the clock adjustment parameter and the target adjustment coefficient, and the recovery parameter is used to recover clock and data.

11. The method according to claim 10, characterized in that Before voting according to at least two sets of input data, the method further includes: receiving a voting mode signal, wherein the voting mode signal indicates a voting mode, and different voting modes correspond to different ways of obtaining voting results; The voting according to at least two sets of input data includes: Voting is performed according to the at least two sets of input data and the voting mode indicated by the voting mode signal.

12. The method according to claim 11, characterized in that The performing voting according to the voting mode indicated by the voting mode signal based on the at least two sets of input data includes: When the voting mode is the first voting mode, a primary voting result is obtained based on every two sets of input data, and a secondary voting result is obtained based on every two primary voting results, and the target voting result is determined based on the relationship between the value of the secondary voting result and a reference value; or When the voting mode is the second voting mode, a first-level voting result is obtained based on every two groups of input data, and then a second-level voting result is obtained based on every two first-level voting results. A third-level voting result is obtained based on the two second-level voting results. The third-level voting results and the remaining second-level voting results are combined in pairs for voting, and the target voting result is obtained based on the voting results of the pairwise combinations.

13. The method according to claim 10, characterized in that The acquiring of the recovery parameter according to the clock adjustment parameter and the target adjustment coefficient includes: Performing a multiplication operation on the clock adjustment parameter and the target adjustment coefficient to obtain a first operation result; The first operation result and the feedback coefficient are accumulated to obtain a second operation result, and the recovery parameter is obtained based on the second operation result. The feedback coefficient is the feedback coefficient of the accumulation result at the previous moment or a reference value.

14. A clock data recovery circuit, characterized in that: The clock data recovery circuit includes the filter circuit according to any one of claims 1-9.

15. A high-definition multimedia interface receiver, characterized in that: The high-definition multimedia interface receiver includes the clock data recovery circuit of claim 14 .

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