Control circuit of switching converter and switching converter

Abstract

The invention discloses a control circuit of a switching converter and the switching converter, error amplification is carried out on an output feedback signal and a reference signal to obtain a compensation signal, the compensation signal is clamped according to a peak value of a ramp signal, and when the compensation signal is greater than or equal to a clamping voltage, the compensation signal is clamped at an upper limit voltage; and generating a comparison signal according to the compensation signal, the ramp signal and the ripple signal so as to control the switching state of a main switching tube of the switching converter. The current limiting precision of the inductance peak current is high, overcurrent protection can be carried out on the inductance current, and the condition of subharmonic oscillation cannot occur in the overcurrent protection period.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and more particularly to a control circuit of a switching converter and a switching converter. Background Art

[0002] In power electronic circuits, switching converters are usually required for signal conversion. Figure 1 A switching converter is shown in FIG. 1 , taking a buck converter as an example. Figure 2 A conventional control circuit is shown. Figure 3 Indicated Figure 2 The waveforms of various signals corresponding to the control circuit. The buck converter consists of the connected upper tube Q1 (main switch tube) and lower tube Q2, inductor L1 and output capacitor C OUT One end of the inductor is connected to the switch node SW between the upper and lower tubes, and the other end of the inductor is connected to the output capacitor. The control circuit generates a switch control signal Q 1D , Q 2D They are used to control the switching states of the upper tube and the lower tube respectively, and the switching states of the upper tube and the lower tube are complementary.

[0003] The control circuit adopts the conventional fixed frequency control mode. In order to ensure the stability of the converter at 50% duty cycle, it is necessary to perform slope compensation on the compensation signal. Figure 2 , op amp 00 will output feedback signal V FB and the reference signal V REF Amplify the error to get the compensation signal V C0 The ramp signal generating circuit 01 generates a ramp signal V according to the clock pulse signal CLK. RAMP1 , the operation unit 02 will compensate the signal V C0 The difference signal V is obtained by subtracting the ramp signal C1 , comparator 03 converts the difference signal V C1 and the inductor current sampling signal V ISNS1 The comparison signal PWM is generated by the comparison, and the driving unit 03 generates a switch control signal Q according to the comparison signal PWM and the clock pulse signal CLK. 1D and Q 2D See also Figure 3 When the clock pulse signal CLK rises, the switch control signal Q 1D To flip from low level to high level to control the upper tube to turn on, the ramp signal V RAMP1 Starting from the bottom value, the difference signal V C1 Starts to drop from the peak value, when the inductor current sampling signal V ISNS1 Rising to the difference signal V C1 When the ramp signal V RAMP Reset, the comparison signal PWM generates a high level pulse to indicate the switch control signal Q1D Flip from high level to low level to control the shutdown of the upper tube.

[0004] In the prior art, to protect switching converters, overcurrent protection is implemented for the inductor peak current. Two existing overcurrent protection schemes are as follows: The first scheme clamps the compensation signal at the set threshold when the compensation signal reaches the set threshold. This scheme results in inaccurate peak current limiting and is significantly affected by the duty cycle and slope of the ramp signal. The second scheme directly shuts off the main switch when excessive inductor peak current is detected. This scheme may cause subharmonic oscillations during the overcurrent protection period. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a control circuit for a switching converter and a switching converter, so as to solve the problems in the prior art such as low current limiting accuracy of the inductor peak current and easy occurrence of subharmonic oscillation.

[0006] According to a control circuit of a switching converter of the present application, the control circuit includes: a first error amplifier, performing error amplification on the output feedback signal and the reference signal to obtain a compensation signal; A ramp signal generating circuit generates a ramp signal according to a clock pulse signal; a clamping circuit connected to the output end of the first error amplifier, configured to generate an upper limit voltage according to the peak value of the ramp signal, and to clamp the compensation signal to the upper limit voltage when the compensation signal is greater than or equal to the upper limit voltage; A comparison circuit generates a comparison signal based on the compensation signal, the ramp signal and the ripple signal, wherein the comparison signal is used to control the switching state of the main switch tube in the switching converter, and the ripple signal is in phase with the inductor current of the switching converter.

[0007] Optionally, the comparison circuit compares the difference between the compensation signal and the ramp signal with the ripple signal, and generates a valid comparison signal when the ripple signal reaches the difference to control the main switch tube to turn off.

[0008] Optionally, an average value of a switch node voltage of the switching converter is acquired to obtain the ripple signal, where the switch node voltage is a voltage at a connection terminal between a switch tube and an inductor of the switching converter.

[0009] Optionally, a sampling signal of the inductor current is acquired to obtain the ripple signal.

[0010] Optionally, the clamping circuit adds the first threshold voltage and the peak value of the ramp signal to obtain the upper limit voltage.

[0011] Optionally, the first threshold voltage is a constant voltage signal set according to an overcurrent protection threshold.

[0012] Optionally, the clamping circuit includes a threshold generating circuit for performing error amplification on a sampling signal of the inductor current and a second threshold voltage to obtain an error signal, and obtaining the first threshold voltage according to the error signal.

[0013] Optionally, the threshold generating circuit superimposes the error signal and a third threshold voltage to obtain the first threshold voltage.

[0014] Optionally, the clamping circuit includes a second error amplifier and a diode, the non-inverting input of the second error amplifier receives the clamping voltage, the inverting input of the second error amplifier is connected to the cathode of the diode, the output of the second error amplifier is connected to the anode of the diode, and the cathode of the diode is connected to the output of the first error amplifier.

[0015] Optionally, the ramp signal generating circuit includes a first current source, a first capacitor and a first switch, wherein the first capacitor and the first switch are connected in parallel. When the rising edge of the clock pulse signal triggers the first switch to turn off, the first current generated by the first current source charges the first capacitor, and the voltage of the first capacitor starts to rise from zero; When the ripple signal reaches the difference between the compensation signal and the ramp signal, the first switch is turned on and the voltage of the first capacitor is reset; The first capacitor voltage is the ramp signal.

[0016] Optionally, the device further includes a driving unit, which receives the comparison signal and the clock pulse signal and generates a switch control signal to control the switching state of the main switch tube in the switching converter; When the ripple signal reaches the difference between the compensation signal and the ramp signal, the comparison signal is valid, and the switch control signal controls the main switch tube to be turned off. When the rising edge of the clock pulse signal occurs, the switch control signal controls the main switch tube to be turned on.

[0017] The present invention further provides a switching converter, comprising a main switch tube and any one of the control circuits described above, wherein the control circuit is used to control the switching state of the main switch tube.

[0018] Compared with existing technologies, the present invention has the following advantages: It performs error amplification on the output feedback signal and the reference signal to generate a compensation signal, clamps the compensation signal based on the peak value of the ramp signal, and clamps the compensation signal to an upper voltage limit when the compensation signal is greater than or equal to the clamping voltage; and controls the switching state of the main switch of the switching converter based on the comparison result between the compensation signal and the ramp signal. The present invention can provide overcurrent protection for the inductor current, achieves high current limiting accuracy for the inductor peak current, and prevents subharmonic oscillation during current limiting / overcurrent protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a switching converter; Figure 2 It is a schematic diagram of a conventional control circuit; Figure 3 for Figure 2 Signal waveform diagram of the control circuit; Figure 4 is a schematic diagram of a control circuit of a buck converter of the present invention; Figure 5 for Figure 4 Schematic diagram of an embodiment of a clamping circuit; Figure 6 for Figure 4 A schematic diagram of an embodiment of a medium threshold voltage generating unit; Figure 7 2 is a signal waveform diagram of the control circuit of the present invention. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments and covers any substitution, modification, equivalent method and solution made within the spirit and scope of the present invention.

[0021] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can also fully understand the present invention without description of these details.

[0022] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are simplified and not to exact proportions, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0023] See also Figure 4The present invention provides a control circuit for controlling the switching state of each switching transistor in a switching converter to limit the peak value of the inductor current and provide current limiting / overcurrent protection for the inductor current. The switching converter includes a main switching transistor, which charges and stores energy in the inductor when the main switching transistor is on, and a rectifier transistor, which complements the switching state of the main switching transistor and allows the inductor to continue current when the rectifier transistor is on. The switching converter can be a buck converter, a boost converter, or a buck-boost converter, and the present invention is not limited to the structure of the switching converter.

[0024] See also Figure 4 , control circuit to control Figure 1 Take the buck converter shown in the figure as an example, the output voltage V OUT Perform voltage division sampling to obtain the output feedback signal V FB , the first error amplifier 00 will output a feedback signal V FB and the reference signal V REF Amplify the error to get the compensation signal V C0 The ramp signal generating circuit 01 generates a ramp signal V according to the clock pulse signal. RAMP . Clamping circuit 05 (see Figure 5 ) samples the peak value of the ramp signal and generates an upper limit voltage based on the peak value of the ramp signal to clamp the maximum value of the compensation signal. When the compensation signal reaches the upper limit voltage, the compensation signal is clamped at the upper limit voltage. The operation unit 02 subtracts the compensation signal from the ramp signal to obtain a difference signal V C1 , comparator 03 will represent the ripple signal V of the inductor current ISNS Sum difference signal V C1 The comparison generates a PWM signal. When the ripple signal reaches the difference signal, the PWM signal changes from invalid to valid. The ripple signal is in phase with the inductor current (the timing changes are the same / synchronous). The ripple signal is a sampling signal of the inductor current, or a signal equivalent to the inductor current obtained by filtering the voltage of the switch node SW. The drive unit 04 generates a switch control signal Q according to the PWM signal and the clock pulse signal CLK. 1D , Q 2D Respectively control the switching state of the upper tube Q1 and the lower tube Q2 in the buck converter. When the pulse of the clock pulse signal occurs, the switch control signal Q 1D Valid, switch control signal Q 2D Invalid controls the upper tube to turn on and the lower tube to turn off. When the PWM signal changes from invalid to valid, the switch control signal Q 1D Invalid, switch control signal Q 2D The ramp signal generating circuit 01 includes a current source I1, a capacitor C1 and a switch K1. The capacitor C1 and the switch K1 are connected in parallel. When the clock pulse signal CLK occurs, the switch control signal Q2D Invalid, the control switch K1 is turned off, the current source I1 charges the capacitor C1, and the capacitor voltage, i.e. the ramp signal, begins to rise. That is, the ramp starting value of the ramp signal is synchronized with the pulse generation edge of the clock pulse signal. When the PWM signal changes from invalid to valid, the switch control signal Q 2D When valid, the control switch K2 is turned on, and the capacitor voltage, that is, the ramp signal, is reset to zero.

[0025] See also Figure 5 , indicated Figure 4 The schematic diagram of the clamping circuit includes a sampling unit 501, a threshold voltage generating unit 502, an operation unit 503 and a clamping unit 504. The sampling unit 501 includes a sampling switch K2 and a holding capacitor C2. When the ripple signal V ISNS Reaching the difference signal V C1 When the PWM signal changes from invalid to valid, the instantaneous control signal PWM_SMP controls the sampling switch K2 to be turned on briefly to sample the peak value of the ramp signal, and the ramp peak signal V is obtained by holding the capacitor. R_SM , the operation unit 503 converts the slope peak signal V R_SM and the first threshold voltage V generated by the threshold voltage generating unit 502 ILIM Add up to get the upper limit voltage V CLAMP The clamping unit 504 receives the upper limit voltage V CLAMP The output end is connected to the output end of the first error amplifier 00, which is used to compensate the signal V C0 Reaching the upper limit voltage V CLAMP When the compensation signal is clamped at the upper limit voltage, the peak value of the inductor current is clamped at the current limit value. The clamping unit 504 includes a second error amplifier 505 and a diode D1. The second error amplifier 505 receives the upper limit voltage at its non-inverting input terminal, and its inverting input terminal is connected to the output terminal of the first error amplifier, i.e., the output terminal of the clamping circuit 05. Its output terminal is connected to the cathode of the diode D1, and the anode of the diode D1 is connected to the inverting input terminal of the second error amplifier. When the compensation signal V C0 Greater than the clamping voltage, the second error amplifier outputs a negative voltage, diode D1 is turned on, and the conduction voltage drop of diode D1 is ignored. The compensation signal V C0 Equal to the upper limit voltage V CLAMP (The second error amplifier 505 is equivalent to a voltage follower, and the compensation signal is clamped at the upper limit voltage). C0 Less than the upper limit voltage V CLAMP When , diode D1 is cut off and the clamping circuit does not need to clamp the compensation signal.

[0026] Optionally, the first threshold voltage V generated by the threshold voltage generating unit ILIMTo set a constant voltage signal according to the overcurrent protection threshold. When the ripple signal is an inductor current sampling signal, since the ripple signal can accurately represent the inductor current, by directly giving the first threshold voltage, a more accurate peak current limitation can be achieved, and the current limiting accuracy is high. When the ripple signal is not a signal obtained by sampling the inductor current, but a signal obtained by averaging the voltage of the switch node, or a signal obtained by calculating and constructing the inductor current, the ripple signal cannot accurately represent / is equivalent to the inductor current. If the first threshold voltage is given directly, the limitation of the inductor peak current will not be very accurate, and the current limiting accuracy is not high. Therefore, optionally, the threshold voltage generating unit obtains the first threshold voltage according to the inductor current sampling signal to achieve accurate limitation of the inductor peak current and achieve accurate current limiting protection, see. Figure 6 .

[0027] Figure 6 The schematic diagram of the embodiment of the threshold voltage generating unit 502 is shown, which includes a sampling switch K3, a holding capacitor C3, a third error amplifier 5021, a diode D2 and an adder 5022. When the upper tube Q1 is turned on, the effective switch control signal Q 1D Control sampling switch K3 to open, and keep capacitor C3 sampling signal V ISNS1 To maintain, the third error amplifier 5021 sets the second threshold voltage V ILIM2 and the inductor current sampling signal V ISNS1 The error is amplified to obtain an error signal. The cathode of the diode D2 is connected to the output end of the third error amplifier. The adder 5022 adds the output signal of the anode of the diode D2 and the third threshold voltage V ILIM3 Adding the first threshold voltage V ILIM , the third threshold voltage V ILIM3 It is a voltage signal set according to the overcurrent protection threshold (the current limit value of the inductor peak current). ISNS1 is less than the second threshold voltage V ILIM2 , the third error amplifier outputs a positive voltage, the diode D2 is cut off, and the third threshold voltage is the first threshold voltage; when the inductor current sampling signal V ISNS1 Greater than the second threshold voltage V ILIM2 , the third error amplifier outputs a negative voltage, diode D2 conducts (ignoring the diode conduction voltage drop), and the sum of the third error amplifier's output voltage and the third threshold voltage equals the first threshold voltage. This method allows for flexible adjustment of the first threshold voltage based on the inductor current. When the inductor current sampling signal is less than the second threshold voltage, the difference between the second threshold voltage and the sampling signal is superimposed on the slope peak value, resulting in more precise current limiting of the inductor peak current. This results in a more stable and accurate current limit, further improving current control accuracy.

[0028] See also Figure 7 , which illustrates the signal waveform of the control circuit of the present invention. When the pulse of the clock pulse signal CLK occurs, the switch control signal Q 1D Valid, used to control the upper tube Q1 (main switch tube) to turn on, and the ramp signal V RAMP Starting from zero, the difference signal V is obtained by subtracting the compensation signal from the ramp signal. C1 Starts to drop, representing the ripple signal V of the inductor current ISNS Starts to rise, when the ripple signal V ISNS Reach signal V C1 When the PWM signal generates pulses, the ramp signal V RAMP Reset, switch control signal Q 1D Invalid, the upper tube Q1 is turned off. When the average current signal is too large (ripple signal V ISNS The valley value is too large, and the signal V is reached in a short time. C1 ), resulting in a decrease in duty cycle, the ramp signal peak value V R_SM and the upper voltage limit (signal V C1 The peak value) is reduced accordingly, and the inductor peak current can still be kept basically constant.

[0029] The present invention samples the peak value of the ramp signal during the on-state of the main switch tube on a cycle-by-cycle basis and superimposes a preset current-limiting threshold voltage as the clamping value of the compensation signal. This ensures high current-limiting accuracy for the inductor current, minimizes the influence of the duty cycle and the ramp signal on the current-limiting value of the inductor peak current, and prevents subharmonic oscillation during the cycle-by-cycle protection process.

[0030] It should be noted that the specific implementation and corresponding illustrations given are merely a way of describing the implementation method of the present invention, and do not limit the specific structure of the implementation scheme of the present invention. Various changes or modifications can be made to these implementation schemes without departing from the principles and essence of the present invention, but these changes and modifications fall within the scope of protection of the present invention.

[0031] Although the embodiments are described and explained separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that they can be replaced and integrated between the embodiments. If there is anything not clearly recorded in one of the embodiments, reference can be made to another recorded embodiment.

[0032] The above-described embodiments do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the above-described embodiments shall be included in the scope of protection of this technical solution.

Claims

1. A control circuit for a switching converter, the control circuit comprising: a first error amplifier, performing error amplification on the output feedback signal and the reference signal to obtain a compensation signal; A ramp signal generating circuit generates a ramp signal according to a clock pulse signal; a clamping circuit connected to the output end of the first error amplifier, configured to generate an upper limit voltage according to the peak value of the ramp signal, and to clamp the compensation signal to the upper limit voltage when the compensation signal is greater than or equal to the upper limit voltage; A comparison circuit generates a comparison signal based on the compensation signal, the ramp signal and the ripple signal, wherein the comparison signal is used to control the switching state of the main switch tube in the switching converter, and the ripple signal is in phase with the inductor current of the switching converter.

2. The control circuit according to claim 1, wherein: The comparison circuit compares the difference between the compensation signal and the ramp signal with the ripple signal, and generates a valid comparison signal when the ripple signal reaches the difference to control the main switch to turn off.

3. The control circuit according to claim 1, wherein: The ripple signal is obtained by acquiring an average value of a switch node voltage of the switching converter, where the switch node voltage is a voltage at a connection end between a switch tube and an inductor of the switching converter.

4. The control circuit according to claim 1, wherein: A sampling signal of the inductor current is obtained to obtain the ripple signal.

5. The control circuit according to claim 1, wherein: The clamping circuit adds a first threshold voltage and a peak value of the ramp signal to obtain the upper limit voltage.

6. The control circuit according to claim 5, wherein: The first threshold voltage is a constant voltage signal set according to an overcurrent protection threshold.

7. The control circuit according to claim 5, wherein: The clamping circuit includes a threshold generating circuit for performing error amplification on a sampling signal of the inductor current and a second threshold voltage to obtain an error signal, and obtaining the first threshold voltage according to the error signal.

8. The control circuit according to claim 7, wherein: The threshold generating circuit superimposes the error signal and the third threshold voltage to obtain the first threshold voltage.

9. The control circuit according to claim 1, wherein: The clamping circuit includes a second error amplifier and a diode, the non-inverting input terminal of the second error amplifier receives the clamping voltage, the inverting input terminal of the second error amplifier is connected to the cathode of the diode, the output terminal of the second error amplifier is connected to the anode of the diode, and the cathode of the diode is connected to the output terminal of the first error amplifier.

10. The control circuit according to claim 1, wherein: The ramp signal generating circuit includes a first current source, a first capacitor and a first switch, wherein the first capacitor and the first switch are connected in parallel. When the rising edge of the clock pulse signal triggers the first switch to turn off, the first current generated by the first current source charges the first capacitor, and the voltage of the first capacitor starts to rise from zero; When the ripple signal reaches the difference between the compensation signal and the ramp signal, the first switch is turned on and the voltage of the first capacitor is reset; The first capacitor voltage is the ramp signal.

11. The control circuit according to claim 9, wherein: The device further comprises a driving unit, which receives the comparison signal and the clock pulse signal and generates a switch control signal to control the switch state of the main switch tube in the switching converter; When the ripple signal reaches the difference between the compensation signal and the ramp signal, the comparison signal is valid, and the switch control signal controls the main switch tube to be turned off. When the rising edge of the clock pulse signal occurs, the switch control signal controls the main switch tube to be turned on.

12. A switching converter, characterized in that: It comprises a main switch tube and the control circuit according to any one of claims 1 to 11, wherein the control circuit is used to control the switching state of the main switch tube.

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