Data sampling processing method of DSP (Digital Signal Processor) chip, computer program product and terminal equipment

Abstract

The embodiment of the invention discloses a data sampling processing method of a DSP (Digital Signal Processor) chip, a computer program product and terminal equipment. The data sampling processing method of the DSP chip comprises the following steps: controlling the DSP chip to run software to be debugged; in the running process of the to-be-debugged software, running data of the DSP chip in the multiple sampling periods are collected, and the running data in the multiple sampling periods are cached; wherein the plurality of sampling periods are sequentially arranged according to a time sequence, and the operation data of any sampling period are synchronously collected for a plurality of indexes; under the condition that the sending requirement is met, packaging the operation data in a plurality of sampling periods into a data frame, and sending the data frame to an upper computer; wherein the sending requirement comprises that the data volume of the packaged operation data in the plurality of sampling periods is smaller than or equal to the maximum effective data volume of single frame transmission corresponding to the sending mode. According to the method and the device, the technical problem that the DSP software debugging effect is affected due to the fact that the DSP chip data sampling effect is poor in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of DSP software debugging, and in particular to a data sampling and processing method for a DSP chip, a computer program product and a terminal device. Background Art

[0002] In related technologies, DSP software debugging is typically performed using methods such as JTAG (Joint Test Action Group) debugging and SWD (Serial Wire Debug). During software debugging, the frequency of data signal acquisition is low, and the synchronization of data acquisition of different signals is poor, resulting in poor data sampling performance of the DSP chip, which in turn affects the debugging effect of the DSP software.

[0003] To address the above-mentioned problems, no effective solutions have been proposed so far.

[0004] The above information disclosed in the Background section is only intended to enhance the understanding of the background technology of the technology described herein. Therefore, the Background section may contain some information that does not form the known prior art for those skilled in the art. Summary of the Invention

[0005] The embodiments of the present invention provide a data sampling and processing method for a DSP chip, a computer program product, and a terminal device, so as to at least solve the technical problem in the related art that poor data sampling effect of a DSP chip affects the debugging effect of DSP software.

[0006] According to a first aspect of an embodiment of the present invention, a data sampling and processing method for a DSP chip is provided, the method comprising: controlling the DSP chip to run software to be debugged; during the running of the software to be debugged, collecting operating data of the DSP chip within multiple sampling periods, and caching the operating data within the multiple sampling periods; wherein the multiple sampling periods are arranged in chronological order, and the operating data of any sampling period is synchronously collected for multiple indicators; and when sending requirements are met, encapsulating the operating data within the multiple sampling periods into a data frame and sending it to a host computer; wherein the sending requirements include: the amount of data after encapsulation of the operating data within the multiple sampling periods is less than or equal to the maximum effective data amount for single-frame transmission corresponding to the sending mode.

[0007] Furthermore, before encapsulating the operating data within the multiple sampling periods into a data frame and sending it to the host computer, the data sampling and processing method of the DSP chip further includes: compressing the operating data within the multiple sampling periods.

[0008] Furthermore, compressing the operating data within multiple sampling periods includes: moving the operating data from the source address to the target address, where the size of each operating data is A bits; wherein, during each moving process, the moved operating data covers the last B bits of the previously moved operating data, where B<A.

[0009] Furthermore, compressing the operating data within multiple sampling periods includes: moving the operating data from the source address to the target address, where the size of each operating data is A bits; wherein, during each moving process, the moved operating data covers the first C bits of the previously moved operating data, where C<A.

[0010] Furthermore, compressing the operating data within multiple sampling periods includes: obtaining target data for the target indicator from the operating data; and replacing the target data with a corresponding preset value based on a size relationship between at least part of the bits of the target data and a preset threshold.

[0011] Furthermore, according to the size relationship between at least part of the bits of the target data and the preset threshold, replacing the target data with the corresponding preset value includes: determining whether the target data reaches the preset threshold; if the target data reaches the preset threshold, replacing the target data with the first preset value; if the target data does not reach the preset threshold, replacing the target data with the second preset value; wherein the number of bits occupied by the first preset value and the second preset value is less than the number of bits occupied by the target data; or, dividing the target data into multiple data segments, each data segment includes multiple bits; comparing the sizes of the multiple data segments with multiple preset thresholds; if the value of any data segment reaches the preset threshold corresponding to it, replacing the data segment with the third preset value corresponding to the preset threshold; if the value of any data segment does not reach the preset threshold corresponding to it, replacing the data segment with the fourth preset value corresponding to the preset threshold; wherein each preset threshold has a third preset value and a fourth preset value corresponding to it.

[0012] Furthermore, compressing the operating data within multiple sampling periods includes: determining whether a preset condition is met; if the preset condition is met, moving the operating data that meets the preset condition from the source address to the target address; if the preset condition is not met, discarding the operating data that does not meet the preset condition.

[0013] Furthermore, before collecting the operating data of the DSP chip within multiple sampling cycles, the data sampling and processing method of the DSP chip also includes: obtaining the effective data volume M and time consumption T of a single frame transmission corresponding to the sending mode; determining the sampling cycle as T / N, and determining the upper limit of the data volume of the operating data collected within a single sampling cycle as M / N, where N is a natural number greater than 1.

[0014] Furthermore, collecting the operating data of the DSP chip within multiple sampling cycles includes: using DMA to obtain the operating data of the DSP chip within multiple sampling cycles; and / or, after encapsulating the operating data within multiple sampling cycles into a data frame and sending it to the host computer, the data sampling and processing method of the DSP chip also includes: controlling the operating data corresponding to multiple indicators to be displayed in the same time axis coordinate system.

[0015] According to a second aspect of an embodiment of the present invention, a computer program product is further provided, comprising computer instructions, which implement the above-mentioned data sampling and processing method of the DSP chip when executed by a processor.

[0016] According to a third aspect of an embodiment of the present invention, a terminal device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the data sampling and processing method of the DSP chip described above is implemented.

[0017] A data sampling and processing method for a DSP chip according to an embodiment of the present invention comprises: controlling the DSP chip to run software to be debugged; during the execution of the software to be debugged, collecting operating data of the DSP chip within multiple sampling periods and caching the operating data within the multiple sampling periods; wherein the multiple sampling periods are arranged in chronological order, and the operating data of any sampling period is collected synchronously for multiple indicators; and if transmission requirements are met, encapsulating the operating data within the multiple sampling periods into a single data frame and transmitting it to a host computer; wherein the transmission requirements include: the amount of data after encapsulation of the operating data within the multiple sampling periods is less than or equal to the maximum valid data amount for a single frame transmission corresponding to the transmission mode. Using this configuration, the data sampling method for a DSP chip divides the operating data corresponding to a single data frame sent to the host computer into data for multiple sampling periods, synchronously collecting relevant data for multiple indicators in each sampling period, and then encapsulating the cached operating data for the multiple sampling periods into a single data frame and transmitting it to the host computer. In this way, compared with a scheme of directly sending data after sampling, the situation where a large data transmission interval limits the sampling granularity can be avoided. By dividing the data into multiple sampling periods, the granularity of the sampling process can be finer, thereby improving the sampling rate. Furthermore, by synchronously collecting data for multiple indicators within each sampling cycle, the synchronization of the collected signal data can be ensured. Compared with sampling methods in related arts, the data sampling and processing method for DSP chips in the embodiments of the present invention effectively improves the sampling density and ensures the synchronization of sampling for different indicators. This allows for more accurate understanding of the status of software running within the DSP chip, facilitating software debugging, and resolving the technical problem in related arts of poor DSP chip data sampling, which affects DSP software debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0019] Figure 1 A schematic flow chart of a data sampling and processing method for a DSP chip provided in an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a device for applying the data sampling and processing method of a DSP chip according to an embodiment of the present invention;

[0021] Figure 3 for Figure 2 The structure and interaction diagram of the DSP chip in;

[0022] Figure 4 The figure is a specific flow chart of the data sampling and processing method of the DSP chip according to the embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish different objects rather than to limit a specific order.

[0025] Figure 1 is a data sampling and processing method of a DSP chip according to an embodiment of the present invention, such as Figure 1 As shown, the method includes the following steps:

[0026] Step S102, controlling the DSP chip to run the software to be debugged;

[0027] Step S104, during the operation of the software to be debugged, collecting the operation data of the DSP chip in multiple sampling periods, and caching the operation data in the multiple sampling periods;

[0028] Step S106: If the sending requirement is met, the operation data within multiple sampling periods are packaged into a data frame and sent to the host computer.

[0029] The multiple sampling periods are arranged in chronological order, and the operating data of any sampling period is collected synchronously for multiple indicators. The above-mentioned transmission requirements include: the amount of data after encapsulation of the operating data within the multiple sampling periods is less than or equal to the maximum valid data amount of a single frame transmission corresponding to the transmission method.

[0030] The data sampling method of the DSP chip using this setting divides the operating data corresponding to a single data frame sent to the host computer into data of multiple sampling periods. Each sampling period will synchronously collect relevant data for multiple indicators, and then the cached operating data of multiple sampling periods is packaged into a data frame and sent to the host computer. In this way, compared with the solution of sending data directly after sampling, the situation where the sampling granularity is limited by a large data transmission interval can be avoided. By dividing the data into multiple sampling periods, the granularity of the sampling process can be made finer, and the sampling rate can be improved. Moreover, the synchronous collection of data for multiple indicators in each sampling period can ensure the synchronization of the collected signal data. Compared with the sampling method in the related art, the data sampling and processing method of the DSP chip in the embodiment of the present invention effectively improves the sampling density and ensures the synchronization of sampling for different indicators. Therefore, the status of the software running inside the DSP chip can be more accurately known, which facilitates software debugging work and solves the technical problem in the related art that the DSP chip data sampling effect is poor and affects the DSP software debugging effect.

[0031] As mentioned above, operating data within any sampling cycle is collected synchronously for multiple indicators, each of which represents data with different labels. For example, during the overall software optimization phase of a DSP chip used in a full-bridge inverter, real-time debugging of the AC voltage signal and the PWM timing signal of MOS1 (MOS transistor number 1) is required. Within a single sampling cycle, the AC voltage signal and MOS1's PWM signal can be synchronously collected.

[0032] The above-mentioned host computer is a device used to receive the collected operation data and then display the data. For example, it can be a Windows host computer, a Linux host computer, a Mac host computer, etc.

[0033] When sending data to a host computer, various transmission methods can be used, such as CAN FD transmission, CAN XL transmission, FlexRay transmission, USB transmission, Ethernet transmission, etc. When different transmission methods are used, the maximum amount of valid data that can be transmitted in a single data frame also varies.

[0034] As some optional embodiments, before encapsulating the operating data within multiple sampling periods into a single data frame and transmitting it to the host computer, the data sampling and processing method for the DSP chip further includes: compressing the operating data within the multiple sampling periods. In this embodiment, by compressing the operating data within the multiple sampling periods, the amount of data transmitted to the host computer can be reduced, thereby improving data transmission efficiency, timely transmitting the collected data to the host computer, and facilitating more rapid monitoring of the operating status of the DSP software.

[0035] In a preferred embodiment, the DSP has a multi-core structure, and the aforementioned software to be debugged runs in a first core. Compressing the running data over multiple sampling periods includes compressing the running data using cores other than the first core. This avoids occupying the main CPU core, allowing the DSP main core to run at full speed, ensuring zero CPU overhead, and avoiding changes in the main software state, so that the sampled data better reflects the actual software runtime.

[0036] In actual implementation, there are different options for compressing the operating data within multiple sampling periods, such as:

[0037] In an optional compression method, compressing the operating data within multiple sampling periods includes: moving the operating data from the source address to the target address, and the size of each operating data is A bits; wherein, during each movement, the moved operating data covers the last B bits of the previously moved operating data, wherein B<A.

[0038] In this embodiment, when moving A bits of operational data, it overwrites the last B bits of the previous operational data, and so on. Consequently, each operational data piece ultimately retains only its first (AB) bits. While this reduces the resolution of individual operational data, it effectively reduces the data size, facilitating rapid subsequent data transmission. For example, when compressing a 32-bit signal to 16 bits, each time operational data is moved from the source address to the destination address, it is shifted forward by 16 bits, overwriting the lower 16 bits of the previous signal. The overall effect is that only the high-order byte of each 32-bit signal is used, saving signal resolution.

[0039] In the second optional compression method, the compression processing of the operating data within multiple sampling periods includes: moving the operating data from the source address to the target address, and the size of each operating data is A bits; wherein, during each movement, the moved operating data covers the first C bits of the previously moved operating data, wherein C<A.

[0040] In this embodiment, when operating data occupying A bits is transferred, it overwrites the first C bits of the previous operating data. Similarly, after each piece of operating data is transferred, only the last (AC) bits of its own data are retained. This reduces the range of the operating data, thereby reducing the data volume and facilitating subsequent data transmission. For operating data with smaller values, which often do not require a particularly large range, the compression method of this embodiment can effectively conserve the signal range, thereby effectively reducing the data size without affecting the signal.

[0041] In the third optional compression method, the compression processing of the operating data within multiple sampling periods includes: obtaining target data for the target indicator from the operating data; replacing the target data with a corresponding preset value based on the size relationship between at least part of the bits of the target data and a preset threshold.

[0042] The compression scheme in this embodiment can be implemented for specific target indicators during actual implementation. For indicators that are applicable to this compression scheme, at least part of the bits of the target data corresponding to the indicator can be compared with a preset threshold value in terms of size, and the preset value can be used to replace the target data based on the size relationship.

[0043] In a specific embodiment, replacing the target data with a corresponding preset value based on the size relationship between at least part of the bits of the target data and a preset threshold includes: determining whether the target data reaches the preset threshold; if the target data reaches the preset threshold, replacing the target data with a first preset value; if the target data does not reach the preset threshold, replacing the target data with a second preset value; wherein the number of bits occupied by the first preset value and the second preset value is less than the number of bits occupied by the target data; or, dividing the target data into multiple data segments, each data segment includes multiple bits; comparing the sizes of the multiple data segments with multiple preset thresholds; if the value of any data segment reaches the preset threshold corresponding to it, replacing the data segment with a third preset value corresponding to the preset threshold; if the value of any data segment does not reach the preset threshold corresponding to it, replacing the data segment with a fourth preset value corresponding to the preset threshold; wherein each preset threshold has a third preset value and a fourth preset value corresponding to it.

[0044] For example, in one optional implementation, the target data as a whole can be compared with a preset threshold. If the target data reaches the preset threshold, the target data is replaced by the first preset value; otherwise, the target data is replaced by the second preset value. This allows a qualitative judgment of compression to be made based on the size relationship between the target data and the preset threshold. In actual implementation, the fewer bits occupied by the first and second preset values, the more significant the compression effect. For example, if 32-bit target data is compared with the preset threshold, and the first preset value is 1 and the second preset value is 0, then after compression, the 32-bit target data can be compressed to 1 bit, effectively reducing the data size.

[0045] For another example, in another optional implementation, the target data will be divided into multiple data segments, and the multiple data segments will be compared with multiple corresponding preset thresholds. Then, based on the comparison results, each data segment will be replaced with its corresponding third preset value or fourth preset value. In this way, the resolution of the compressed data can be improved, which is conducive to better understanding the software running status and software debugging.

[0046] In the fourth optional compression method, the compression processing of the operating data within multiple sampling periods includes: determining whether the preset conditions are met; if the preset conditions are met, moving the operating data that meets the preset conditions from the source address to the target address; if the preset conditions are not met, discarding the operating data that does not meet the preset conditions.

[0047] In this embodiment, a preset condition is used as a judgment, and whether the current operating data is retained or discarded is determined based on whether the preset condition is met. For example, the data at the current moment is retained when the preset condition is met, and the data at the current moment is discarded when the preset condition is not met. In actual implementation, the preset condition can be flexibly selected according to actual conditions. For example, in a specific implementation method, an Event can be used as a trigger condition. When the Event occurs, the current operating data is pushed into the cache, otherwise the current operating data is discarded. When the cached data meets the above-mentioned sending requirements, the accumulated operating data is encapsulated into a data frame and sent to the host computer.

[0048] In a specific embodiment, before collecting the operating data of the DSP chip within multiple sampling cycles, the data sampling and processing method of the DSP chip also includes: obtaining the effective data volume M and time consumption T of a single frame transmission corresponding to the sending mode; determining the sampling cycle as T / N, and determining the upper limit of the data volume of the operating data collected within a single sampling cycle as M / N, where N is a natural number greater than 1.

[0049] For example, using the CAN FD transmission method, its maximum bit rate is 8MHz. A single frame can transmit a maximum of 64 bytes of valid data, taking approximately 125µs. In this case, M = 64 bytes and T = 125µs. In practice, by dividing the 125µs transmission period into N sampling periods, the signal sampling interval can be shortened to 125 / Nµs. Each sampling period allows for simultaneous acquisition of multiple signals using 64 / N bytes of data. The sampled data is then cached until 64 bytes have accumulated before transmission. This allows for increased signal sampling rates and simultaneous acquisition of multiple signals through the use of caching technology.

[0050] Collecting the operating data of the DSP chip within multiple sampling cycles includes: using DMA to obtain the operating data of the DSP chip within multiple sampling cycles; and / or, after encapsulating the operating data within multiple sampling cycles into a data frame and sending it to the host computer, the data sampling and processing method of the DSP chip also includes: controlling the operating data corresponding to multiple indicators to be displayed in the same time axis coordinate system.

[0051] As a preferred implementation, this embodiment uses DMA to acquire the DSP chip's operational data within each sampling period. DMA (Direct Memory Access) is a data transmission method that allows external devices to directly access a computer's memory without the intervention of the central processing unit. This avoids increasing the DSP chip's internal overhead and does not require changing the DSP's operating state when collecting operational data, making data sampling more convenient and accurate. Compared to the solution of this embodiment, debugging methods using technologies such as JTAG (Joint Test Action Group) or SWD (Serial Wire Debug) in related technologies require a CPU breakpoint to compare and analyze the logical relationships between various signals. However, this application adopts the solution of the aforementioned embodiment, which does not require a breakpoint.

[0052] In this embodiment, by controlling the display of the operating data corresponding to multiple indicators in the same time coordinate system, the correlation between the various operating data can be more intuitively reflected, the visualization level in the DSP software debugging process is improved, and horizontal and vertical comparisons are convenient, thereby better helping operators perform software debugging operations.

[0053] In a preferred embodiment, the data acquisition and processing method of the DSP chip further includes controlling the operation data received by the host computer to be stored in a target location (such as a hard disk) to facilitate subsequent recovery.

[0054] In addition, an embodiment of the present invention further provides a computer program product, including computer instructions, which implement the above-mentioned data sampling and processing method of the DSP chip when executed by a processor.

[0055] Finally, an embodiment of the present invention further provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the data sampling and processing method of the DSP chip described above is implemented.

[0056] The data sampling and processing method for a DSP chip according to an embodiment of the present invention, when applied to DSP software debugging, can overcome the following defects of the debugging methods using JTAG (Joint Test Action Group) or SWD (Serial Wire Debug) in related arts:

[0057] (a) The sampling and debugging methods in related technologies have a low signal acquisition frequency (e.g., 1 Hz) during Run debugging, and the granularity of the time dimension is large, making it difficult to debug high-speed running software (e.g., a signal update frequency of 1 MHz). However, the method of the embodiment of the present invention can divide the running data corresponding to a single data frame sent to the host computer into data of multiple sampling periods. Each sampling period will synchronously collect relevant data for multiple indicators, and then encapsulate the cached running data of multiple sampling periods into a data frame and send it to the host computer. In this way, compared with the solution of sending data directly after sampling, it can avoid the situation where the sampling granularity is limited due to a large data sending interval. By dividing the data into multiple sampling periods, the granularity of the sampling process can be finer, and the sampling rate can be increased, making it better suitable for debugging high-speed running software.

[0058] (b) The sampling and debugging methods in related technologies require CPU operation to be paused (Breakpoint) to compare and analyze the logical relationship between various signals during Run debugging. However, the method of the embodiment of the present invention can synchronously collect data for multiple indicators within each sampling cycle and display the operating data corresponding to the multiple indicators in the same time coordinate system. This can more intuitively reflect the correlation between various operating data, improve the visualization level during the DSP software debugging process, facilitate horizontal and vertical comparisons, and thus better help operators perform software debugging operations.

[0059] (c) In related art sampling and debugging methods, peripherals are typically still running when the CPU is paused, which can introduce synchronization issues and require manual insertion of code to pause the peripherals, which is cumbersome and error-prone. However, the method of the present invention can synchronously collect data for multiple indicators within each sampling cycle without pausing the CPU, ensuring the synchronization of the collected signal data.

[0060] Furthermore, the data sampling and processing method for a DSP chip according to the present invention occupies little space during DSP software debugging, eliminating the need for consuming large amounts of storage space and making it well-suited for embedded software devices. Furthermore, the data sampling and processing method for a DSP chip according to the present invention occupies little space during DSP software debugging, eliminating the need for increasing Flash storage capacity and hardware costs.

[0061] Figure 2 A schematic diagram of a device for applying the data sampling and processing method of a DSP chip according to an embodiment of the present invention; Figure 3 for Figure 2 The structure and interaction diagram of the DSP chip in; Figure 4 FIG. 1 is a specific flow chart of the data sampling and processing method of the DSP chip according to an embodiment of the present invention. Figures 2 to 4 As shown, the data sampling and processing method of the DSP chip of the present invention is described here in conjunction with a more specific embodiment:

[0062] Taking the application of a certain type of DSP chip in a full-bridge inverter as an example, during the overall software optimization phase, it is desired to perform real-time debugging on the AC voltage signal and the PWM action timing signal of MOS1 (MOS tube numbered 1).

[0063] like Figure 2 As shown in the figure, the data sampled by the DSP chip and the inverter bridge during operation are sent to the Windows host computer through the CAN FD interface and the CAN interface card, which facilitates data analysis and software debugging.

[0064] like Figure 3 As shown, in this embodiment, DMA is used to obtain the operating data of the DSP chip in each sampling period. DMA has ch1, ch2 and ch3 channels. The DSP chip includes a main core CPU and an auxiliary core CLA. The main core CPU is used to run the main software, and DMA, cache space, auxiliary core CLA, CANFD and Windows host computer are used to implement debugging functions.

[0065] The AC voltage signal sampling period is 2µs, and the sampling result is 12 bits of valid data (the chip's address alignment mechanism stores it in the 16-bit ADC_Result register). DMACh1 triggers once after each sampling cycle, moving the sampling result in the ADC_Result register to the cache. The DMACh1 operation period is 2µs.

[0066] The PWM period is fixed, while the duty cycle is dynamically controlled by the main CPU. The 16-bit PWM_AQCTLA register indicates its real-time high and low levels. DMACh2 uses a synchronous triggering method with Ch1 to synchronously move data in the PWM_AQCTLA register to the cache.

[0067] like Figure 4 Both DMA channels use a 64-count loop. After every 64 transfers, a compression algorithm task is triggered. This task is executed by the auxiliary CLA core, avoiding tying up the main CPU core and allowing the DSP to run at full speed. This ensures zero CPU overhead and avoids changes in the main software state, allowing the sampled data to better reflect actual software runtime conditions. The CLA task operates in a 128µs cycle. The auxiliary CLA task compresses the 64 AC voltage signals and 64 PWM signals.

[0068] DMACh3 is software-triggered and is triggered at the end of the auxiliary core CLA compression algorithm task. The DMACh3 operation cycle is 128us. DMACh3 moves the compressed 64-byte data to the CAN transmit register and triggers the CAN FD send action. The CAN FD send cycle is 128us.

[0069] The Windows host computer receives the CANFD data stream through the CAN card and analyzes it in real time. The AC voltage signal and the PWM real-time level signal are displayed synchronously in the form of curves on the same time axis coordinate system for visualization. The data is then stored on the computer hard drive for later playback.

[0070] The serial numbers of the embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. Moreover, the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system, such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be performed in a different order than shown here.

[0071] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0073] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0074] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0075] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc. Various media that can store program codes.

[0076] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A data sampling and processing method for a DSP chip, characterized in that: include: Control the DSP chip to run the software to be debugged; During the operation of the software to be debugged, operating data of the DSP chip in multiple sampling periods are collected and the operating data in the multiple sampling periods are cached; wherein the multiple sampling periods are arranged in chronological order, and the operating data in any one of the sampling periods is collected synchronously for multiple indicators; If the sending requirements are met, the operating data within the multiple sampling periods are encapsulated into a data frame and sent to the host computer; wherein, the sending requirements include: the amount of data after the operating data within the multiple sampling periods is encapsulated is less than or equal to the maximum effective data amount of a single frame transmission corresponding to the sending mode.

2. The data sampling and processing method of the DSP chip according to claim 1, characterized in that: Before encapsulating the operation data in the plurality of sampling periods into a data frame and sending it to the host computer, the data sampling and processing method of the DSP chip further includes: The operation data within the multiple sampling periods are compressed.

3. The data sampling and processing method of the DSP chip according to claim 2, characterized in that: The compressing of the operating data within the plurality of sampling periods includes: Moving the operating data from the source address to the target address, where the size of each operating data is A bits; In each transfer process, the transferred operation data covers the last B bits of the operation data transferred in the previous transfer, where B<A.

4. The data sampling and processing method of the DSP chip according to claim 2, characterized in that: The compressing of the operating data within the plurality of sampling periods includes: Moving the operating data from the source address to the target address, where the size of each operating data is A bits; In each transfer process, the transferred operation data covers the first C bits of the operation data transferred in the previous transfer, wherein C<A.

5. The data sampling and processing method of the DSP chip according to claim 2, characterized in that: The compressing of the operating data within the plurality of sampling periods includes: obtaining target data for a target indicator from the operating data; According to the magnitude relationship between at least part of the bits of the target data and a preset threshold, the target data is replaced with a corresponding preset value.

6. The data sampling and processing method of the DSP chip according to claim 5, characterized in that: Replacing the target data with a corresponding preset value according to a magnitude relationship between at least some bits of the target data and a preset threshold includes: determining whether the target data reaches a preset threshold; if the target data reaches the preset threshold, replacing the target data with a first preset value; if the target data does not reach the preset threshold, replacing the target data with a second preset value; wherein the number of bits occupied by the first preset value and the second preset value is less than the number of bits occupied by the target data; or, The target data is divided into multiple data segments, each of which includes multiple bits; the multiple data segments are compared with the sizes of multiple preset thresholds; when the value of any one of the data segments reaches the preset threshold corresponding to it, the third preset value corresponding to the preset threshold is used to replace the data segment; when the value of any one of the data segments does not reach the preset threshold corresponding to it, the fourth preset value corresponding to the preset threshold is used to replace the data segment; wherein, each of the preset thresholds has the third preset value and the fourth preset value corresponding to it.

7. The data sampling and processing method of the DSP chip according to claim 2, characterized in that: The compressing of the operating data within the plurality of sampling periods includes: Determine whether the preset conditions are met; When the preset condition is met, the operation data that meets the preset condition is moved from the source address to the target address; If the preset condition is not met, the operation data that does not meet the preset condition is discarded.

8. The data sampling and processing method of a DSP chip according to any one of claims 1 to 7, characterized in that: Before collecting the operating data of the DSP chip in a plurality of sampling periods, the data sampling and processing method of the DSP chip further includes: Obtain the effective data volume M and time consumption T of a single frame transmission corresponding to the sending mode; The sampling period is determined to be T / N, and the upper limit of the amount of the operating data collected in a single sampling period is determined to be M / N, where N is a natural number greater than 1.

9. The data sampling and processing method of a DSP chip according to any one of claims 1 to 7, characterized in that: Collecting the operating data of the DSP chip in a plurality of sampling periods includes: acquiring the operating data of the DSP chip in a plurality of sampling periods in a DMA manner; and / or, After encapsulating the operation data in the multiple sampling periods into a data frame and sending it to the host computer, the data sampling and processing method of the DSP chip further includes: controlling the operation data corresponding to the multiple indicators to be displayed in the same time axis coordinate system.

10. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the data sampling and processing method of the DSP chip according to any one of claims 1 to 9.

11. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data sampling and processing method for the DSP chip according to any one of claims 1 to 9 is implemented.

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