Cross-platform radio frequency data transmission method and system based on HC3080 chip

Abstract

The invention discloses a cross-platform radio frequency data transmission method and system based on an HC3080 chip, belongs to the technical field of data transmission, and constructs a multi-platform-oriented data interaction and control framework based on five concurrent execution thread tasks and three high-performance message queues. A unified cross-platform signaling protocol structural body is introduced as a semantic carrier of instruction data, so that accurate identification and processing of instructions among different platforms are ensured, and cross-platform function control and high-performance data communication of a system comprising an HC3080 chip are successfully realized; the application blank of the HC3080 chip in the aspect of communication support between multi-core heterogeneous systems is effectively filled, and the application range of the HC3080 chip in the field of high-reliability embedded communication and signal processing is remarkably expanded.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a cross-platform radio frequency data transmission method and system based on an HC3080 chip. Background Art

[0002] In the field of drone edge computing, heterogeneous computing architectures are increasingly being used. The HC3080, a high-performance domestically produced intelligent acceleration chip, significantly improves data processing capabilities by integrating a DSP with a dedicated acceleration unit. However, at the data transmission level, the HC3080 faces different interface driver implementation logic than mainstream intelligent acceleration chips, resulting in direct incompatibility with the standardized interface drivers relied upon by existing AI chips.

[0003] This compatibility issue severely restricts the application of the HC3080 chip in multi-platform collaboration scenarios, especially when high-speed data interaction with FPGA processing modules and display and control terminals is required. Traditional solutions often require the addition of an additional protocol conversion layer, which not only introduces additional memory copy overhead, but also increases transmission latency and reduces throughput. Summary of the Invention

[0004] The purpose of the present invention is to address the above-mentioned problems and provide a cross-platform radio frequency data transmission method and system based on the HC3080 chip. Based on the interface driver architecture characteristics of the HC3080 chip, an innovative and targeted cross-platform data transmission solution is proposed, thereby realizing an efficient cross-platform data communication system.

[0005] A cross-platform radio frequency data transmission method based on the HC3080 chip, the method comprising: constructing a heterogeneous communication architecture including five concurrent task modules and three message queues in the HC3080 terminal; The five concurrent task modules include a first task module, a second task module, a third task module, a fourth task module, and a fifth task module; The three message queues include a first message queue, a second message queue, and a third message queue; The first task module writes the control signaling received from the display and control system end into the first message queue or the third message queue; The second task module writes the FPGA-side data received from the display and control system side into the third message queue; The third task module reads the control signaling to be processed from the first message queue, executes the service logic according to the control signaling, and distributes the processing result to the second message queue or the third message queue; The fourth task module obtains the display control data and the return signaling from the second message queue, and returns the display control data and the return signaling to the display control system end; The fifth task module reads target data from the third message queue and sends the target data to the FPGA end; The display and control data is obtained by the HC3080 end processing the radio frequency data received from the FPGA end; The return signaling is generated by the HC3080 end and the FPGA end after executing tasks according to the control signaling.

[0006] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the display and control system is used for human-computer interaction, transmitting control signaling, HC internal data, and FPGA-side data to the HC3080 side, or receiving return signaling and display and control data from the HC3080 side, and receiving return signaling from the FPGA side through the HC3080 side. The second task module stores the received HC internal data.

[0007] The HC3080 terminal is used to receive signaling and data sent by the display and control system terminal and the FPGA terminal, and process the signaling and data based on the five concurrent task modules and three message queues; The data includes the HC internal data, FPGA end data, and display control data; The FPGA end is used to perform corresponding tasks according to the target information sent by the HC3080 end; The target information sent by the HC3080 end includes the control signaling uploaded by the display and control system end and transparently transmitted by the HC3080 end, the FPGA end data, and the control signaling generated by the HC3080 end.

[0008] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the HC3080 end interacts with the display and control system end through the GMAC interface, and the HC3080 end interacts with the FPGA end through the SRIO interface; The GMAC interface adopts a dual-channel mode: The first channel is implemented using stream sockets, and the TCP protocol is used for communication to transmit control signaling and return signaling; The second channel is used to transmit data and uses a cyclic write mechanism for cumulative verification; The communication between the first task module and the display and control system end adopts the first channel; The communication between the second task module and the display and control system end adopts the second channel; The communication between the fourth task module and the display and control system end adopts the first channel and the second channel.

[0009] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the FPGA end transmits the generated return signaling and the acquired RF data back to the HC3080 end through the SRIO interface; The HC3080 end writes the return signaling from the FPGA end into the second message queue, processes the radio frequency data, and packages the processing result and related radio frequency data into display control data and writes it into the second message queue; The return signaling and display and control data at the FPGA end of the second message queue are extracted by the fourth task module and returned to the display and control system end through the GMAC interface.

[0010] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the first message queue is used to cache control signaling transmitted through the GMAC interface and directed to the HC3080 end for subsequent processing flow scheduling; The second message queue is used to cache business data sent to the display and control system end through the GMAC interface, including return signaling from the HC3080 end, return signaling from the FPGA end, and display and control data; The third message queue is used to cache business data sent to the FPGA end through the SRIO interface, including FPGA end data and control signaling for the FPGA end.

[0011] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the method further includes defining a cross-platform signaling protocol structure, which is used to encapsulate control signaling and return signaling between the display and control system end, the FPGA end, and the HC3080 end, including: The frame header field head1 is used to mark the start of the data frame; The frame header field head21 is combined with the frame header field head1 to form a unique frame header identifier; The function code field cmdl and the function code field cmdh jointly encode a 16-bit function code to indicate the operation type; FPGA-side global registers, which store FPGA-side status parameters; HC end global register, stores the status parameters of the HC3080 end; The global register of the display and control end stores the status parameters of the display and control end; Signaling timestamp register, used to record the timestamp of signaling generation; Temporary data register, used to transfer intermediate calculation results or extended data; Checksum field, used to verify the integrity of the data frame; The tail field tail1 and the tail field tail2 are combined to mark the end of the data frame.

[0012] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, cross-platform interaction is achieved between the HC308 end, the display and control system end, and the FPGA end based on 128-byte signaling; The 128-byte signaling includes the function code field, and the interaction between the HC3080 end, the display and control system end, and the FPGA end is triggered by different function code fields.

[0013] In the above-mentioned cross-platform RF data transmission method based on the HC3080 chip, the signaling sent to the display and control system end is sent through the sRk circular buffer, and the data sent to the display and control system end is sent through the frame sending buffer; Signaling to the FPGA side is sent through the pZU circular buffer, and data to the FPGA side is sent through the SRIO send buffer and round-robin scheduling mechanism.

[0014] In the above-mentioned cross-platform radio frequency data transmission method based on the HC3080 chip, the frame transmission buffer includes multiple buffer blocks, such as four buffer blocks, and each buffer block is separated by 64MB; The SRIO send buffer includes multiple buffer blocks, such as four buffer blocks, each buffer block is 8MB apart; The sRK circular buffer has 200-300 buffer slots, each slot supports 128 bytes of data storage; The interactive modes for display and control data acquisition include active mode and single frame mode; In single-frame mode, the HC3080 interacts with the FPGA based on the control signaling sent by the display and control end to obtain RF data, and then processes the RF data and returns the display and control data to the display and control system end. In active mode, the display and control system initiates an initialization control signaling, and the HC3080 establishes a continuous communication channel with the FPGA. Signaling and data are continuously exchanged through polling or interrupt mechanisms. When the set conditions are met, such as 10 results, the display and control data is returned to the display and control system.

[0015] A cross-platform data transmission system based on the HC3080 chip, including a display and control system end, an FPGA end, and an HC3080 end; The display and control system end is connected to the HC3080 end via a GMAC interface; The FPGA end is connected to the HC3080 end via the SRIO interface; The HC3080 terminal has a heterogeneous communication architecture constructed by five concurrent task modules and three message queues; The five concurrent task modules include a first task module, a second task module, a third task module, a fourth task module, and a fifth task module; The three message queues include a first message queue, a second message queue, and a third message queue; The first task module writes the control signaling received from the display and control system end into the first message queue or the third message queue; The second task module writes the FPGA-side data received from the display and control system side into the third message queue; The third task module reads the control signaling to be processed from the first message queue, executes the service logic according to the control signaling, and distributes the processing result to the second message queue or the third message queue; The fourth task module obtains the display control data and the return signaling from the second message queue, and returns the display control data and the return signaling to the display control system end; The fifth task module reads target data from the third message queue and sends the target data to the FPGA end; The display and control data is obtained by the HC3080 end processing the radio frequency data received from the FPGA end; The return signaling is generated by the HC3080 end and the FPGA end after executing tasks according to the control signaling.

[0016] The advantages of the present invention are: The system architecture provided by this solution builds a multi-platform data interaction and control framework based on five concurrently executed thread tasks and three high-performance message queues. It also introduces a unified cross-platform signaling protocol structure as the semantic carrier of instruction data to ensure accurate identification and processing of instructions between different platforms. It successfully implements cross-platform functional control and high-performance data communication for systems containing the HC3080 chip, effectively filling the application gap of the HC3080 chip in supporting communication between multi-core heterogeneous systems and significantly expanding its application scope in the fields of high-reliability embedded communications and signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The heterogeneous communication architecture of the cross-platform data transmission method based on the HC3080 chip of the present invention; Figure 2 This is a block diagram of the cross-platform system based on HC3080 in the present invention; Figure 3 This is a data interaction flow chart for the single frame mode of the present invention; Figure 4 This is a data interaction flow chart in the active mode of the present invention Figure 5 This is a flow chart of the data processing result return in single frame mode of the present invention; Figure 6 This is a flow chart of the active mode data processing result transmission process of the present invention.

[0018] Fig. 1 shows a schematic diagram of the unmanned aerial vehicle system according to the present application. Fig. 2 shows a schematic diagram of the software system framework according to the present application. Fig. 3 shows a schematic diagram of the message queue design according to the present application. Fig. 4 shows a schematic diagram of the task module design according to the present application. Fig. 5 shows a schematic diagram of the message passing mechanism according to the present application. Fig. 6 shows a schematic diagram of the task scheduling strategy according to the present application. DETAILED DESCRIPTION

[0019] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0020] The present application is based on the HC3080 software platform to build a cross-platform radio frequency data processing system architecture. The implementation of the cross-platform system architecture includes system framework building, interface function implementation, signaling control and backhaul mechanism, data reception and transmission, data flow processing procedure, result storage and result backhaul, the data flow processing procedure includes mode configuration, data splitting and data processing.

[0021] It should be noted that the present system architecture can be used in the scenario of unmanned aerial vehicle system using HC3080 chip on the unmanned aerial vehicle side 1, as shown in Fig. 1, the unmanned aerial vehicle system mainly includes the unmanned aerial vehicle side 1 and the ground side 2, the unmanned aerial vehicle side 1 has the HC3080 end 11 and the FPGA end 12, and the ground side 2 mainly has the display and control system end 21. The present application mainly faces the efficient transmission and processing of radio frequency data between the HC3080 chip and the FPGA and the display and control system, and solves the problem of serious control signaling delay caused by the incompatibility of the HC3080 chip interface driving logic and the display and control system and the FPGA, and does not involve general image or video data, which is backhauled by another set of backhaul link and is not within the scope of the present application. Figure 1 As shown in Fig. 4, the specific implementation is as follows:

[0022] As shown in Fig. 4, the specific implementation is as follows: Figure 2 System framework building According to the task requirements, the present application proposes an innovative software system framework design, which introduces three key message queues: the first message queue, the second message queue and the third message queue; and five core concurrent task modules: the first task module 13, the second task module 14, the third task module 15, the fourth task module 16 and the fifth task module 17. Through the precisely designed message passing mechanism and task scheduling strategy, efficient cross-platform data transmission capability is realized. The present architecture significantly improves the performance throughput and scalability of the system while supporting multi-thread cooperative processing, and provides strong support for real-time interaction of radio frequency data between heterogeneous platforms.

[0023] Message queue design

[0024] ​The first message queue receives and manages control signals, including control frame indexes and command information, transmitted from the display and control system 21 to the HC3080 11 via the GMAC (Gigabit Media Access Controller) interface. It is responsible for scheduling and coordinating subsequent processing within the framework. This ensures efficient transmission and accurate routing of control signals, thereby improving the real-time and reliability of command execution.

[0025] The second message queue, serving as a high-speed data transmission channel for the GMAC interface, caches and schedules critical business data to be transmitted to the display and control system 21 via the GMAC interface. This includes return signaling generated by the HC3080 11 after executing control signaling tasks, and return signaling and display and control data generated by the FPGA 12 in response to control signaling. This ensures the real-time and reliable transmission of critical data, enabling high-bandwidth, low-latency information push scenarios.

[0026] When the FPGA end 12 needs to return a signal to the display and control system end 21, the return signal is written into the second message queue in the form of an interrupt response. The return signal of the FPGA end waits in the second message queue for the fourth task module 16 to return it to the display and control system end 21; When the system needs RF data, it similarly obtains it from FPGA 12 via an interrupt response. HC3080 11 processes the RF data and packages the processing results with some or all of the currently processed RF data as display and control data, which is then written to the second message queue. Those skilled in the art will appreciate that drones typically have RF chips, and the FPGA obtains RF data from these chips. The details are omitted here.

[0027] The third message queue carries service data sent to the high-performance processing module on the FPGA side 12 via the SRIO (Serial RapidIO) interface. This includes FPGA side 12 data, control signaling for the FPGA side 12, and FPGA side 12 data, primarily including FPGA reload data. This queue features low latency and high throughput, ensuring stable, real-time transmission of critical data even under high-load conditions, meeting the communication requirements of high-speed interconnections.

[0028] Task allocation and execution The first task module 13 is responsible for receiving control signaling from the GMAC interface, parsing the signaling content based on its function code, encapsulating it into a standardized message format, and writing it to the first or third message queue for subsequent task scheduling. This module implements the instruction entry bridge function from the physical interface to the task scheduling system.

[0029] Specifically, the control signaling received by the first task module 13 from the display and control system end 21 includes two categories. One category needs to be processed by the HC3080 itself, such as model update instructions, which are written into the first message queue; the other category needs to be processed by the FPGA, such as FPGA software upgrade instructions, which are written into the third message queue.

[0030] The second task module 14 is responsible for processing data received from the display and control system 21 via the GMAC interface. This includes internal HC data used by the HC3080 chip itself, such as model files, and data that needs to be transparently transmitted to the FPGA 12, such as FPGA reload data. After receiving the internal HC data, the HC3080 11 stores these files in a specific storage space. Data received from the FPGA 12 is written to the third message queue.

[0031] The third task module 15 is responsible for reading pending control signaling from the first message queue and executing corresponding business logic based on the function code, such as data parsing, numerical calculation, and system status update. The processing results are delivered to the second message queue (to be sent to the display and control system end 21) or the third message queue (to be sent to the FPGA end 12) according to their application scenario, completing message-driven business processing and result distribution.

[0032] The third task module 15 classifies the processing results, and stores the results that need to be sent back to the display and control system in the second message queue, and stores the results that need to be provided to the FPGA end 12 in the third message queue.

[0033] The fourth task module 16 is used to obtain display and control data and return signaling from the second message queue. The return signaling includes the return signaling of the HC3080 and the return signaling of the FPGA, and send the display and control data and return signaling to the display and control system end 21 through the GMAC interface, thereby realizing the data return and result interaction function from the drone side 1 to the host computer.

[0034] The fifth task module 17 is responsible for reading target messages from the third message queue, that is, data to be sent to the FPGA side, such as FPGA reload data, and control signaling to be transmitted to the FPGA side 12, including control signaling transparently transmitted by the display and control system side 21 through the HC3080. The information generated by the HC3080 after processing the control signaling from the display and control system side 21 can also be control signaling. The data is sent to the FPGA side 12 via the SRIO high-speed interface, realizing high-speed data communication and task collaboration with the FPGA side 12.

[0035] Interface function implementation SRIO interface function implementation, in the HC3080 system, the SRIO interface initialization process includes device identification configuration, address mapping window setting, data buffer initialization and other key operation steps, to ensure the reliability and accessibility of high-speed interconnection communication. The following is a detailed description of the HC3080 SRIO initialization process.

[0036] bslRioSetID(1,0x3333); bslRioSetIW(1,(u64)0x40000000,(u64)0x10d0000000,8); bslRioSetIW(1,(u64)0x10000000,(u64)0x1090000000,0); bslRioDBInit(1,RabDBTest); The bslRioSetID function sets the unique device ID of SRIO interface channel 1 to 0x3333, which is used for device identification and target addressing in the RapidIO network, ensuring correct routing and directional transmission of data packets in the multi-device network.

[0037] The bslRioSetIW function configures the input window mapping relationship. The local physical address range of SRIO interface 1 (0x40000000 and 0x10000000) is mapped to the remote RapidIO address space (0x10d0000000 and 0x1090000000), and the corresponding window attributes (window index 8 and 0) are specified. This step completes the establishment of the address mapping table, so that the remote node can correctly access the local memory resources through SRIO.

[0038] The bslRioDBInit function initializes the Doorbell (doorbell mechanism) buffer of SRIO interface 1 and binds the corresponding interrupt processing function or callback processing logic RabDBTest. The Doorbell mechanism is a lightweight communication mechanism in SRIO for event notification and signal transmission, ensuring that the system can efficiently respond to remote interrupt or event trigger requests.

[0039] GMAC interface function implementation, in this system, GMAC interface as the core data communication interface, undertakes the task of high-speed data interaction with the display control system. GMAC interface conforms to IEEE802.3 standard specification, located in the data link layer of OSI seven-layer model, responsible for realizing the encapsulation and decapsulation of data frame and the interactive communication with the underlying PHY (Physical Layer) device, ensuring the efficient cooperation between data link layer and physical layer.

[0040] This system is configured with two independent Socket channels based on the GMAC network port, here referred to as the first channel and the second channel, which are respectively for signaling and large-scale data transmission scenarios.

[0041] The first channel is dedicated to 128B signaling transmission. First task module 13 uses this channel to receive control signals from the display and control system. This channel, based on streaming sockets and utilizing the TCP protocol, ensures the reliable and orderly transmission of signaling commands. Signaling commands often contain critical control information, requiring extremely high real-time and accuracy. The GMAC network port, with its low latency, can quickly respond to and process these commands, ensuring stable operation of the display and control system 21.

[0042] The second channel is used for data transmission and reception. Second task module 14 uses this channel to receive internal HC data from the display and control system, as well as data from the FPGA 12. This channel uses the TCP protocol based on actual conditions. In full-duplex mode, the GMAC network port fully utilizes its high-speed transmission capabilities, supporting data transmission rates up to 1Gb FPGA, meeting the needs of rapid large-scale data transmission.

[0043] The fourth task module 16 communicates with the display and control system end 21 using both channels. Signaling is sent back to the display and control system end 21 via the first channel, and display and control data is transmitted to the display and control system end 21 via the second channel.

[0044] Signaling control and signaling return Signaling control and backhaul mechanisms form the core foundation for the coordinated operation of various functional modules in a cross-platform system. This system completes unified signaling frame structure negotiation before implementing cross-platform data transmission to ensure consistent and operable data communication between different platforms. This process defines the signaling data encapsulation format, field parsing methods, and transmission specifications, providing protocol support for efficient signaling transmission and accurate parsing.

[0045] In this system architecture, the three different platforms follow a unified data frame format definition. This format establishes logical consistency above the network layer or transport layer, ensuring interoperability, scalability, and protocol compatibility of signaling across multiple platforms. Through this mechanism, each platform can accurately identify and process signaling, achieving key functions such as signaling distribution, status synchronization, and processing result feedback. The data formats of the three platforms include: The frame header field head1 is used to mark the starting position of the data frame, helping the receiving end to quickly synchronize the frame boundary. The frame header field head12 is combined with head1 to form a unique frame header identifier, enhancing the reliability of frame synchronization. The function code field cmdl and the function code field cmdh jointly encode a 16-bit function code, which is used to indicate the specific operation type; FPGA end 12 global register, storing parameters related to the FPGA end 12 device status; HC-side global registers, used for HC3080 status management; The global register of the display and control end records the internal status of the display and control system; Signaling timestamp register, used to record the timestamp of signaling generation; Temporary data registers provide flexible data storage space for transferring intermediate calculation results or extended data; Signaling checksum, using cyclic redundancy check CRC or simple cumulative sum algorithm to ensure the integrity of data frames; The tail fields tail1 and tail2 are combined to form the frame tail to mark the end of the frame.

[0046] Signaling feedback includes signaling from the FPGA side 12 and signaling from the HC3080 side 11. Signaling from the FPGA side 12 is transparently transmitted from the HC3080 to the display and control system side 21 via the software system framework of the HC3080 side 11. The display and control system signaling from the HC3080 side 11 is transmitted based on the cmdl and cmdh function codes as follows: When the CMDL and CMDH of the 128-byte signaling are represented as 01 and 00 in hexadecimal, the HC-side global registers X6 and X7 bytes control the version number 11 of the HC3080 side that is returned to the display and control system.

[0047] When CMDL and CMDH of the 128-byte signaling are represented as 02 and 00 in hexadecimal, the HC-side global register X0: X0.0 (0: Display and control system end 21 failed to establish a connection; 1: Display and control system end 21 successfully established a connection), X0.1 (0: Disable time-frequency AI reasoning; 1: Enable time-frequency AI reasoning), X0.2 (0: No data packet has arrived from display and control system end 21; 1: Data packet is about to arrive, after the data packet arrives, the flag is set to 0 and the tasks in the task function code, including firmware upgrade, are executed), X0.3 (0: Manual mode to obtain data and execute the task; 1: Automatic mode to obtain data and execute the task), X0.4 (0: Disable watchdog; 1: Enable watchdog), X0.5 (0: Disable FHW detection; 1: Enable FHW detection), X5: Task function code (to achieve functional reconfiguration), (X5: 0x01: Enable algorithm single-frame mode; 0x04: Enable algorithm active mode), X6: Version number L, X7: Version number H.

[0048] When CMDL and CMDH of the 128-byte signaling are expressed as 03 and 00 in hexadecimal, the control display and control system terminal 21 sends data to the HC3080 terminal 11. After sending this command, the HC3080 terminal 11 sets X0.2 to 1 and returns. The display and control system terminal 21 must send data to the HC3080 terminal 11. After receiving it, the HC3080 terminal 11 replies with the 03 instruction with X0.2 set to 0.

[0049] When CMDL and CMDH of the 128-byte signaling are 04 and 00 in hexadecimal notation, the display and control system end 21 obtains the TF data AI inference result, direction finding inference result, timestamp, latitude and longitude, and FHW detection result in the active mode of the HC3080 end 11.

[0050] When CMDL and CMDH of the 128-byte signaling are 06 and 00 in hexadecimal, X0.3 controls the selection of the inference mode of HC3080 terminal 11 (0: disable active acquisition; 1: enable active acquisition).

[0051] When CMDL and CMDH of the 128-byte signaling are 07 and 00 in hexadecimal notation, the global register status of the 21HC terminal of the display and control system is transmitted back.

[0052] When CMDL and CMDH of the 128-byte signaling are 08 and 00 in hexadecimal notation, the display and control system side 21 signaling configures the HC side global register.

[0053] When CMDL and CMDH of the 128-byte signaling are 0a and 00 in hexadecimal notation, the display and control system side 21 signaling controls the HC3080 side 11Srio to rebuild the chain.

[0054] When CMDL and CMDH of the 128-byte signaling are 0b and 00 in hexadecimal notation, the display and control system side 21 signaling controls the activation of the HC3080 side 11FHW inference function.

[0055] When CMDL and CMDH of the 128-byte signaling are 0c and 00 in hexadecimal, the display and control system side 21 signaling controls the activation of the time-frequency AI inference function on the HC3080 side 11.

[0056] When CMDL and CMDH of the 128-byte signaling are 0d and 00 in hexadecimal, the display and control system end 21 signaling controls the start of the watchdog function of the HC3080 end 11.

[0057] When CMDL and CMDH of the 128-byte signaling are represented as 0d and 00 in hexadecimal, the display and control system end 21 signaling controls the HC3080 end 11Yolov7 threshold reception.

[0058] When CMDL and CMDH of the 128-byte signaling are represented by hexadecimal 0e and 00, the display and control system end 21 signaling controls the HC3080 end 11 center frequency point reception.

[0059] When CMDL and CMDH of the 128-byte signaling are represented as 1e and 00 in hexadecimal, the display and control system side 21 signaling controls the HC3080 side 11Srio initialization.

[0060] The above solves the compatibility issue of signaling interaction between heterogeneous platforms, display and control systems, HC3080, and FPGA ends, and provides reliable protocol support for real-time transmission and processing of RF data.

[0061] Data reception and transmission The 128-byte signaling received from the display and control system terminal 21 is stored at the first address of the fixed address space pointed to by the pointer IMGPKG.

[0062] The return signaling sent back by the FPGA end 12 is directly written into the memory space mapped by the SRIO interface, and the real-time and reliability of data reception are ensured through the DMA or bus direct access mechanism.

[0063] The data received from the display and control system end 21 is stored at the first address of the fixed physical address space pointed to by the IMGPKG_ pointer, thereby realizing the unified takeover of large blocks of data.

[0064] The FPGA-side 12-bit data and return signaling share the unified memory space mapped by SRIO, and adopt the address segment division strategy to achieve multiplexing and isolated access to different data types.

[0065] The 128-byte signaling sent to the display and control system end 21 uses the sRK circular buffer as the signaling sending buffer pool, which includes 255 buffer slots, each slot supports 128 bytes of data storage, and realizes multi-frame concurrent management and orderly sending based on the circular queue structure.

[0066] The 128-byte signaling sent to the FPGA end 12 is also managed by the pZU circular buffer to ensure that the control information sent to the FPGA end 12 has timing and stability.

[0067] The data sent to the display and control system end 21 is cached and managed through the frame sending buffer. Each buffer block is 64MB apart and adopts a continuous linear address division method to ensure the isolated storage and asynchronous loading of large-scale data frames.

[0068] The SRIO send buffer is used to send data to the FPGA end 12. Each buffer is arranged in steps of 8MB. The round-robin scheduling mechanism supports the concurrent push of multiple frames of data to adapt to the high-speed, low-latency link characteristics.

[0069] Data stream processing Data type classification 1) Single-channel TF data: Contains only feature data (Tensor Features, TF for short) used for AI model inference and is sent from the FPGA end 12 to the HC3080 chip end.

[0070] 2) Single-channel TF + 8-channel IQ data: Contains feature data (TF) used for neural network model inference and 8-channel complex baseband sampling data (IQ data) used by other signal processing algorithms (such as interference identification and positioning).

[0071] The interactive modes of the display and control system terminal 21 acquiring radio frequency data include active mode and single frame mode. Figure 3 As shown, the display and control system end 21 sends a data request control signaling. After receiving the request, the HC3080 end 11 interacts with the FPGA end 12 so that the FPGA end 12 obtains the RF data. After the HC3080 end 11 completes the processing of the RF data, it returns the processing result and related RF data to the display and control system end 21.

[0072] Active mode, such as Figure 4 As shown, the display and control system end 21 initiates an initialization signaling, the HC3080 end 11 and the FPGA end 12 establish a continuous communication channel, and continuously exchange signaling and data through polling or interrupt mechanism to realize data streaming processing and multi-frame parallelism.

[0073] Data splitting and data processing Data received from FPGA terminal 12 is transmitted to the HC3080 chip via the SRIO interface and directly mapped to the predefined physical address space of the system memory. The system reads the received data by accessing the SRIO mapped memory area. To extract the contents of each field in the data structure, a pointer offset method is used to locate and parse the length information, data content, and other metadata of each data field according to the agreed data format specifications (such as header structure and field alignment). The specific implementation of data length field extraction is as follows: memcpy((u8*)arr1,(u8*)0x10d0000000,52); DisTfLen=*(u32*)((u8*)arr1+16); InfTfOriLen=*(u32*)((u8*)arr1+20); InfTfLen=((InfTfOriLen+2048-1) / 2048)*2048; FhwOriLen=*(u32*)((u8*)arr1+24); FhwLen=((FhwOriLen+2048-1) / 2048)*2048; TLen=*(u32*)((u8*)arr1+28); DtTfLen=*(u32*)((u8*)arr1+44); DtIqLen=*(u32*)((u8*)arr1+48); Memcpy copies the register data of the SRIO controller to the 52-byte data frame header starting at physical address 0x10d0000000 through DMA or MMU mapping, and copies it to the local buffer arr1 through memory mapping, avoiding the security risks caused by directly operating the physical address.

[0074] Extract the data segment length field at a predefined offset from the buffer through pointer offset and forced type conversion.

[0075] Result storage and result return Corresponding to the above interaction mode, the data processing results are also divided into active mode results and single frame mode results. The active mode results are stored in a buffer containing 10 elements of cyclic inference information, which is used to cyclically store active mode result data. The single frame mode results are stored in a buffer containing 4 elements of the frame sending buffer. Each time a result is obtained, it is transmitted back to the display and control system end 21. Figure 5 、 Figure 6 It is a logic diagram of the results of the two modes.

[0076] As mentioned above, this solution realizes functional coordination and control among multiple platforms by constructing a heterogeneous system communication architecture consisting of five concurrent thread tasks and three message queues, and defines a unified cross-platform signaling protocol structure for encapsulating signaling and status data, ensuring the standardization and compatibility of signaling communications among systems.

[0077] Furthermore, this solution designs and implements a thread and message queue collaboration framework based on two high-speed communication interfaces, GMAC and SRIO, to form a data communication architecture adapted to the HC3080 chip. This architecture improves system communication efficiency and scalability through task division and asynchronous message mechanisms. Based on a deep understanding of the FPGA receiving mechanism, a large-scale data transmission logic for the HC3080 chip was designed, which uses a buffer loop write and integrity verification mechanism to effectively ensure the integrity and reliability of the data transmission process. In addition, this solution proposes a feasible and efficient data transmission and reception process implementation strategy for the GMAC and SRIO communication subsystems of the HC3080 chip, including link initialization, DMA transmission, cache management, and signaling collaboration mechanisms, to comprehensively improve the performance and robustness of the communication subsystem.

[0078] Although this document frequently uses terms such as first task module 13, second task module 14, third task module 15, fourth task module 16, fifth task module 17, first message queue, second message queue, and third message queue, the use of other terms is not excluded. These terms are used solely to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitations is contrary to the spirit of the present invention.

Claims

1. A cross-platform radio frequency data transmission method based on HC3080 chip, characterized in that: The method includes building a heterogeneous communication architecture including five concurrent task modules and three message queues in the HC3080 terminal; The five concurrent task modules include a first task module, a second task module, a third task module, a fourth task module, and a fifth task module; The three message queues include a first message queue, a second message queue, and a third message queue; The first task module writes the control signaling received from the display and control system end into the first message queue or the third message queue; The second task module writes the FPGA-side data received from the display and control system side into the third message queue; The third task module reads the control signaling to be processed from the first message queue, executes the service logic according to the control signaling, and distributes the processing result to the second message queue or the third message queue; The fourth task module obtains the display control data and the return signaling from the second message queue, and returns the display control data and the return signaling to the display control system end; The fifth task module reads target data from the third message queue and sends the target data to the FPGA end; The display and control data is obtained by the HC3080 end processing the radio frequency data received from the FPGA end; The return signaling is generated by the HC3080 end and the FPGA end after executing tasks according to the control signaling.

2. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 1, characterized in that: The display and control system is used for human-computer interaction, transmitting control signals, HC internal data, and FPGA data to the HC3080, or receiving return signals and display and control data from the HC3080, and receiving return signals from the FPGA through the HC3080. The HC3080 terminal is used to receive signaling and data sent by the display and control system terminal and the FPGA terminal, and process the signaling and data based on the five concurrent task modules and three message queues; The data includes the HC internal data, FPGA end data, and display control data; The FPGA end is used to perform corresponding tasks according to the target information sent by the HC3080 end; The target information sent by the HC3080 end includes the control signaling uploaded by the display and control system end and transparently transmitted by the HC3080 end, and the data on the FPGA end.

3. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 1, characterized in that: The HC3080 end interacts with the display and control system end via a GMAC interface, and the HC3080 end interacts with the FPGA end via an SRIO interface; The GMAC interface adopts a dual-channel mode: The first channel is implemented using stream sockets, and the TCP protocol is used for transmitting control signaling and return signaling; The second channel is used to transmit data and uses a cyclic write mechanism for cumulative verification; The communication between the first task module and the display and control system end adopts the first channel; The communication between the second task module and the display and control system end adopts the second channel; The communication between the fourth task module and the display and control system end adopts the first channel and the second channel.

4. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 3, characterized in that: The FPGA side transmits the generated return signaling and the acquired RF data back to the HC3080 side through the SRIO interface; The HC3080 end writes the return signaling from the FPGA end into the second message queue, processes the radio frequency data, and packages the processing result and related radio frequency data into display control data and writes it into the second message queue; The return signaling and display and control data at the FPGA end of the second message queue are extracted by the fourth task module and returned to the display and control system end through the GMAC interface.

5. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 1, characterized in that: The first message queue is used to cache control signaling transmitted through the GMAC interface and oriented to the HC3080 end for subsequent processing flow scheduling; The second message queue is used to cache business data sent to the display and control system end through the GMAC interface, including return signaling from the HC3080 end, return signaling from the FPGA end, and display and control data; The third message queue is used to cache business data sent to the FPGA end through the SRIO interface, including FPGA end data and control signaling for the FPGA end.

6. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 1, characterized in that: The method further includes defining a cross-platform signaling protocol structure, which is used to encapsulate control signaling and return signaling between the display and control system, the FPGA, and the HC3080, including: The frame header field head1 is used to mark the start of the data frame; The frame header field head21 is combined with the frame header field head1 to form a unique frame header identifier; The function code field cmdl and the function code field cmdh jointly encode a 16-bit function code to indicate the operation type; FPGA-side global registers, which store FPGA-side status parameters; HC end global register, stores the status parameters of the HC3080 end; The global register of the display and control end stores the status parameters of the display and control end; Signaling timestamp register, used to record the timestamp of signaling generation; Temporary data register, used to transfer intermediate calculation results or extended data; Checksum field, used to verify the integrity of the data frame; The tail field tail1 and the tail field tail2 are combined to mark the end of the data frame.

7. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 6, characterized in that: The HC308 terminal, the display and control system terminal, and the FPGA terminal implement cross-platform interaction based on 128-byte signaling; The 128-byte signaling includes the function code field, and the interaction between the HC3080 end, the display and control system end, and the FPGA end is triggered by different function code fields.

8. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 7, characterized in that: The signaling sent to the display and control system is sent through the sRk circular buffer, and the data sent to the display and control system is sent through the frame sending buffer; Signaling to the FPGA side is sent through the pZU circular buffer, and data to the FPGA side is sent through the SRIO send buffer and round-robin scheduling mechanism.

9. The cross-platform radio frequency data transmission method based on the HC3080 chip according to claim 8, characterized in that: The frame sending buffer includes multiple buffer blocks, each buffer block is 64MB apart; The SRIO send buffer includes multiple buffer blocks, each buffer block is 8MB apart; The sRK circular buffer has 200-300 buffer slots, each slot supports 128 bytes of data storage; The interactive modes for display and control data acquisition include active mode and single frame mode; In single-frame mode, the HC3080 interacts with the FPGA based on the control signaling sent by the display and control end to obtain RF data, and then processes the RF data and returns the display and control data to the display and control system end. In active mode, the display and control system initiates an initialization control signaling, and the HC3080 establishes a continuous communication channel with the FPGA. Signaling and data are continuously exchanged through polling or interrupt mechanisms, and display and control data are returned to the display and control system when the set conditions are met.

10. A cross-platform data transmission system based on HC3080 chip, characterized in that: Including display and control system end, FPGA end and HC3080 end; The display and control system end is connected to the HC3080 end via a GMAC interface; The FPGA end is connected to the HC3080 end via the SRIO interface; The HC3080 terminal has a heterogeneous communication architecture constructed by five concurrent task modules and three message queues; The five concurrent task modules include a first task module, a second task module, a third task module, a fourth task module, and a fifth task module; The three message queues include a first message queue, a second message queue, and a third message queue; The first task module writes the control signaling received from the display and control system end into the first message queue or the third message queue; The second task module writes the FPGA-side data received from the display and control system side into the third message queue; The third task module reads the control signaling to be processed from the first message queue, executes the service logic according to the control signaling, and distributes the processing result to the second message queue or the third message queue; The fourth task module obtains the display control data and the return signaling from the second message queue, and returns the display control data and the return signaling to the display control system end; The fifth task module reads target data from the third message queue and sends the target data to the FPGA end; The display and control data is obtained by the HC3080 end processing the radio frequency data received from the FPGA end; The return signaling is generated by the HC3080 end and the FPGA end after executing tasks according to the control signaling.

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