Data intelligent cache management method and device and medium

Abstract

The invention provides an intelligent data cache management method and device and a medium, and is applied to the technical field of storage software. Wherein synchronous write-in analysis and / or update frequency analysis are / is carried out on the to-be-written-in data; if the result of the synchronous write-in analysis and / or the result of the update frequency analysis meet the requirement of writing into the four-layer unit data block, writing the data to be written into the four-layer unit data block; and if the result of the synchronous write-in analysis and / or the result of the update frequency analysis meet the requirement of writing into the single-layer unit data block, writing the to-be-written data into the single-layer unit data block. Therefore, the synchronous write-in analysis and / or the update frequency analysis are dynamically performed on the to-be-written data so as to determine the write-in destination point, the full-capacity availability of the solid state disk is maintained through the four-layer unit data blocks, and the read-write performance of the solid state disk is improved through the single-layer unit data blocks; the long-term stability of the to-be-written data in the writing process is maintained, and the consistency of service quality is ensured.

Description

Technical Field

[0001] The present invention relates to the field of storage software technology, and in particular to a data intelligent cache management method, device and medium. Background Art

[0002] Each storage cell in a Quad-Level Cell (QLC) can store 4 bits of data, significantly increasing storage density. High-density storage reduces the cost per gigabyte (GB), enabling the deployment of large-capacity storage with a lower budget, making it particularly suitable for scenarios requiring cost-effectiveness. However, due to QLC's high storage density, its write operations become complex, the write speed is relatively slow, and the write lifespan is much shorter than that of a Single-Level Cell (SLC).

[0003] There are two common approaches to improving QLC write performance. The first involves some SSDs using a full-disk pseudo-single-level cell (PSLC) mode, accelerating reads and writes by switching each storage cell to SLC mode. However, this technology essentially trades capacity for performance. This means that a QLC cell that originally stores 4 bits of data only writes 1 bit, reducing the effective storage space to 1 / 4 of its original capacity. While it's possible to restore the original capacity by disabling PSLC mode, enterprise-class storage systems typically require storage media with stable configurations. Frequent dynamic capacity switching can disrupt storage pool consistency, making this solution limited in mission-critical scenarios. The second approach involves using dynamic PSLC caching, which allocates only a portion of the blocks as cache, writing data to SLC first and then to QLC. While this design mitigates capacity loss, it introduces a significant performance cliff effect: when burst write traffic exceeds the cache capacity, the inherently slow write speed of the original QLC media becomes apparent, and measured sequential write speeds can drop by more than tenfold. Such drastic fluctuations not only affect service quality, but may also cause flow control anomalies at the application layer, posing potential risks to scenarios such as databases and virtualization platforms that require stable input and output delays.

[0004] It can be seen that how to ensure the stability of the storage process while ensuring the storage capacity of the solid-state drive is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a data intelligent cache management method, device and medium, which can solve the problem of reduced capacity of the full-disk pseudo single-layer unit mode and the problem of unstable dynamic PSLC cache technology.

[0006] To solve the above technical problems, on the one hand, an embodiment of the present invention provides a data intelligent cache management method, which is applied to a solid-state drive including a plurality of four-layer unit data blocks and single-layer unit data blocks, comprising:

[0007] Perform synchronous write analysis and / or update frequency analysis on the data to be written; wherein the priority of synchronous write analysis is higher than the priority of update frequency analysis;

[0008] If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the four-layer unit data block, the data to be written is written into the four-layer unit data block;

[0009] If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the single-layer unit data block, the data to be written is written into the single-layer unit data block.

[0010] In some embodiments, the results of the synchronous write analysis and / or the results of the update frequency analysis satisfy the requirements for writing a four-layer unit data block, including:

[0011] When the result of the synchronous write analysis indicates that the data to be written is sequentially written, the data to be written is written into any four-layer unit data block;

[0012] When the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in the first / second frequency interval, the data to be written is written into any four-layer unit data block.

[0013] In some embodiments, the results of the synchronous write analysis and / or the update frequency analysis satisfy the requirements for writing a single-layer unit data block, including:

[0014] When the result of the synchronous writing analysis indicates that the data to be written is random writing, and the result of the updating frequency analysis indicates that the data to be written is data in the second / third frequency interval, the data to be written is written into any single-layer unit data block.

[0015] In some embodiments, performing synchronous write analysis on the data to be written includes:

[0016] determining a corresponding first continuous parameter based on a weight factor corresponding to the data to be written, a number of write operations within a preset time period, a logical page address corresponding to each write operation, and an indicator function;

[0017] determining a corresponding second continuous parameter based on the duration of the write operation and the total time period;

[0018] Determine a corresponding third continuous parameter based on the data amount of each to-be-written data and the average data amount in the write operation;

[0019] Obtaining a continuous parameter sum of the first continuous parameter, the second continuous parameter, and the third continuous parameter;

[0020] If the sum of the continuous parameters is not less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is sequentially written;

[0021] If the sum of the continuous parameters is less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is random write.

[0022] In some embodiments, performing update frequency analysis on the data to be written includes:

[0023] Determining a corresponding first frequency parameter based on a time-sensitive factor corresponding to the data to be written, a cumulative number of accesses to the data block under different operations, an observation time period, and the number of different operations;

[0024] Determining a corresponding second frequency parameter based on a time sensitivity factor, a decay rate parameter, a timestamp of a last access operation on the data block, and an observation time period;

[0025] Determine a corresponding third frequency parameter based on the field whose access times exceed the access threshold in the observation time period and the total field;

[0026] Obtaining a frequency parameter sum of a first frequency parameter, a second frequency parameter, and a third frequency parameter;

[0027] If the sum of the frequency parameters is not less than the first frequency parameter threshold, the result of the updated frequency analysis indicates that the data to be written is data in the third frequency interval;

[0028] If the sum of the frequency parameters is not greater than the second frequency parameter threshold, the result of the updated frequency analysis indicates that the data to be written is data in the first frequency interval;

[0029] If the sum of the frequency parameters is greater than the second frequency parameter threshold and less than the first frequency parameter threshold, the result of the updated frequency analysis indicates that the data to be written is data in the second frequency interval.

[0030] In some embodiments, further comprising:

[0031] During the garbage collection time period, any single-layer unit data block that is not fully populated is selected as a recycled single-layer unit data block;

[0032] Acquire single-layer valid data in the recovered single-layer unit data block, and determine the single-layer valid data volume corresponding to the single-layer valid data;

[0033] Any single-layer unit data block or four-layer unit data block that is not fully stored and has a remaining capacity greater than the single-layer valid data volume is selected as a migration unit data block;

[0034] The single-layer valid data in the recycled single-layer unit data block is migrated to the migration unit data block, and the data of the recycled single-layer unit data block is erased.

[0035] In some embodiments, further comprising:

[0036] Obtaining a four-layer unit data block difference between a four-layer unit data block storing data and a four-layer unit data block not storing data in the four-layer unit data block;

[0037] If the difference between the four-layer unit data blocks is lower than the migration threshold and within the garbage collection time period, any four-layer unit data block that is not full of data is selected as the recycled four-layer unit data block;

[0038] Acquire and recycle four-layer valid data in the four-layer unit data block, and determine the four-layer valid data amount corresponding to the four-layer valid data;

[0039] Any four-layer unit data block that is not fully populated and has a remaining capacity greater than the four-layer valid data volume is selected as a migration data block;

[0040] The four layers of valid data in the recycled four-layer unit data block are migrated to the migration data block, and the data of the recycled four-layer unit data block is erased.

[0041] In some embodiments, the process of migrating the single-layer valid data in the recycled single-layer unit data block to the migration unit data block further includes:

[0042] The data rate of effective data migration on a single layer is less than the maximum write bandwidth of a single layer unit data block;

[0043] The process of migrating the four-layer valid data in the recovered four-layer unit data block to the migration data block also includes:

[0044] The data rate of the effective data migration of the four layers is less than the maximum write bandwidth of the four-layer unit data block.

[0045] In another aspect, the present invention further provides an electronic device, comprising:

[0046] memory for storing computer programs;

[0047] A processor is used to execute a computer program to implement the steps of the above-mentioned data intelligent cache management method.

[0048] On the other hand, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above-mentioned data intelligent cache management method when executed by a processor.

[0049] On the other hand, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned data intelligent cache management method when executed by a processor.

[0050] It can be seen from the above technical solution that the present invention provides a data intelligent cache management method, which is applied to a solid-state hard disk including several four-layer unit data blocks and single-layer unit data blocks, including: performing synchronous write analysis and / or update frequency analysis on the data to be written; wherein, the priority of the synchronous write analysis is higher than the priority of the update frequency analysis; if the result of the synchronous write analysis and / or the result of the update frequency analysis meets the requirements for writing the four-layer unit data block, the data to be written is written into the four-layer unit data block; if the result of the synchronous write analysis and / or the result of the update frequency analysis meets the requirements for writing the single-layer unit data block, the data to be written is written into the single-layer unit data block. It can be seen that the present invention dynamically performs synchronous write analysis and / or update frequency analysis on the data to be written to determine the destination of the write, maintains the full capacity availability of the solid-state hard disk through the four-layer unit data block, improves the read and write performance of the solid-state hard disk through the single-layer unit data block, maintains the long-term stability of the data to be written during the writing process, and ensures the consistency of service quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 A flowchart of a data intelligent cache management method provided by an embodiment of the present invention;

[0053] Figure 2 A hardware structure diagram of a solid-state drive provided in an embodiment of the present invention;

[0054] Figure 3 This is a diagram of the overall architecture corresponding to the data intelligent cache management method provided by an embodiment of the present invention;

[0055] Figure 4 A complete flow chart of the data intelligent cache management method provided by an embodiment of the present invention;

[0056] Figure 5 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0058] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0059] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0060] Next, a data intelligent cache management method, device, and medium provided by an embodiment of the present invention are introduced in detail.

[0061] Figure 1 A flowchart of a data intelligent cache management method provided by an embodiment of the present invention is as follows Figure 1 As shown, the following steps are included:

[0062] S10: Perform synchronous writing analysis and / or update frequency analysis on the data to be written.

[0063] S11: If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the four-layer unit data block, the data to be written is written into the four-layer unit data block.

[0064] S12: If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the single-layer unit data block, the data to be written is written into the single-layer unit data block.

[0065] In an embodiment, Figure 2As shown, the data intelligent cache management method provided by the present invention is specifically applied to a solid-state drive (SSD) including several channels (Channel 0-Channel n). Each channel includes several quad-level cell data blocks (QLC chips) and single-level cell data blocks (SLC chips) connected to the SSD main controller. The single-level cell data blocks (SLC chips) are simulated using PSLC technology. To maximize the bandwidth of the quad-level cell data blocks (QLC chips) and reduce the path loss of the quad-level cell data blocks (QLC chips), the QLC chips can be designed closer to the SSD main controller, while the single-level cell data blocks (SLC chips) can be designed farther away from the SSD main controller.

[0066] Further, if Figure 3 As shown, the SSD interacts with the host for reading and writing. The host includes a file system and underlying drivers. The SSD includes an SSD interface unit, an SSD controller, a write arbitration control module, and several quad-level cell data blocks (QLC chips) and single-level cell data blocks (SLC chips). The SSD interface unit is responsible for communicating with the host, receiving and parsing data packets and commands from the host client to obtain the data to be written, and then sending the data to be written to the statistical classification module in the SSD controller.

[0067] The statistical classification module is responsible for monitoring data traffic. It meticulously counts and analyzes the status of different channels, providing detailed data support for system optimization. Its main function is to perform synchronous write analysis and / or update frequency analysis on the data to be written to classify the data to be written. It mainly writes different data blocks according to different types. Some of the operations of writing data blocks require the write arbitration control module to write; and the write arbitration control module also includes garbage collection, which mainly ensures that as many free data blocks as possible are retained by efficiently organizing the contents of data blocks, removing useless data (i.e., "garbage"), and migrating valid data to new data blocks. This module integrates two advanced processing mechanisms: IGC (influencer-generated content) and UGC (user-generated content).

[0068] In addition to write operations, there are also read and erase operations between the SSD master controller and the QLC / SLC chip; there are also write and read operations between the host and the SSD.

[0069] It's important to note that the physical space ratio between quad-level cell data blocks (QLC chips) and single-level cell data blocks (SLC chips) is pre-set, ensuring physical isolation between the two storage media at the hardware level. This design avoids the risk of storage pool reconstruction caused by capacity changes in traditional dynamic caching solutions.

[0070] Among them, in step S10: performing synchronous write analysis and / or update frequency analysis on the data to be written, it should be noted that synchronous write analysis and update frequency analysis are two-dimensional analyses, and there is no order of precedence. However, since synchronous write analysis includes two categories: sequential write and random write, and update frequency analysis includes three categories: hot data, cold data, and warm data, different categories of data to be written correspond to different write locations, but the write locations provided by the present invention only include four-layer unit data blocks and single-layer unit data blocks, so conflicts are likely to occur. Based on this, the present invention limits the priority of synchronous write analysis to be higher than the priority of update frequency analysis.

[0071] For example: when the result of the synchronous write analysis indicates that the data to be written is sequential write, the priority of sequential write is the highest at this time, so the data to be written is written into any four-layer unit data block; but when the result of the synchronous write analysis indicates that the data to be written is random write, the data to be written is written into any four-layer unit data block or single-layer unit data block, and based on this, the write location is further determined by updating the frequency analysis result, that is, when the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in the first / second frequency interval (cold data and warm data), the data to be written is written into any four-layer unit data block; when the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in the second / third frequency interval (warm data and hot data), the data to be written is written into any single-layer unit data block.

[0072] It can be seen from the above technical solution that the present invention provides a data intelligent cache management method, which is applied to a solid-state hard disk including several four-layer unit data blocks and single-layer unit data blocks, including: performing synchronous write analysis and / or update frequency analysis on the data to be written; wherein, the priority of the synchronous write analysis is higher than the priority of the update frequency analysis; if the result of the synchronous write analysis and / or the result of the update frequency analysis meets the requirements for writing the four-layer unit data block, the data to be written is written into the four-layer unit data block; if the result of the synchronous write analysis and / or the result of the update frequency analysis meets the requirements for writing the single-layer unit data block, the data to be written is written into the single-layer unit data block. It can be seen that the present invention dynamically performs synchronous write analysis and / or update frequency analysis on the data to be written to determine the destination of the write, maintains the full capacity availability of the solid-state hard disk through the four-layer unit data block, improves the read and write performance of the solid-state hard disk through the single-layer unit data block, maintains the long-term stability of the data to be written during the writing process, and ensures the consistency of service quality.

[0073] In some embodiments, the specific implementation method for the synchronous write analysis result and / or the update frequency analysis result to meet the requirement of writing the four-layer unit data block is:

[0074] When the result of the synchronous write analysis indicates that the data to be written is sequentially written, the data to be written is written into any four-layer unit data block;

[0075] When the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in the first / second frequency interval, the data to be written is written into any four-layer unit data block.

[0076] The specific implementation method for the synchronous writing analysis result and / or the update frequency analysis result to meet the requirement of writing a single-layer unit data block is as follows:

[0077] When the result of the synchronous writing analysis indicates that the data to be written is random writing, and the result of the updating frequency analysis indicates that the data to be written is data in the second / third frequency interval, the data to be written is written into any single-layer unit data block.

[0078] In an embodiment, synchronous write analysis includes two categories: sequential write and random write, and update frequency analysis includes three categories: hot data (data in the third frequency interval), cold data (data in the first frequency interval) and warm data (data in the second frequency interval). Therefore, the steps of performing synchronous write analysis and / or update frequency analysis on the data to be written can be understood as establishing a three-level data classification and a two-level write mode classification system: when the host issues a command, it will first be statistically classified by the statistical classification module, and analyzed using two different dimensions of write analysis and / or update frequency analysis. At this time, five situations will be obtained. The first situation is: the result of the synchronous write analysis indicates that the data to be written is sequential write; the second situation is: the result of the synchronous write analysis indicates that the data to be written is random write; the third situation: the result of the update frequency analysis indicates that the data to be written is data in the first frequency interval; the fourth situation: the result of the update frequency analysis indicates that the data to be written is data in the second frequency interval; the fifth situation: the result of the update frequency analysis indicates that the data to be written is data in the third frequency interval. However, since the present invention limits the priority of synchronous write analysis to be higher than the priority of update frequency analysis, there are four specific cases at this time. The first case: the result of the synchronous write analysis indicates that the data to be written is sequentially written. At this time, the requirement of writing four-layer unit data blocks is met, and the data to be written is written into any four-layer unit data block; the second case: when the result of the synchronous write analysis indicates that the data to be written is randomly written, and the result of the update frequency analysis indicates that the data to be written is data in the first frequency interval (cold data), the requirement of writing four-layer unit data blocks is met, and the data to be written is written into any four-layer unit data block; the third case: when the result of the synchronous write analysis indicates that the data to be written is randomly written, and the result of the update frequency analysis indicates that the data to be written is data in three frequency intervals, the requirement of writing single-layer unit data blocks is met, and the data to be written is written into any single-layer unit data block. However, the fourth case is more special. When the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in two frequency intervals, then the requirements for writing a single-layer unit data block are met, and the requirements for writing a four-layer unit data block are also met. Therefore, the data to be written is written into any four-layer unit data block or single-layer unit data block.

[0079] In this design, the specific implementation method of synchronous write analysis of the data to be written is: determine the corresponding first continuous parameter based on the weight factor corresponding to the data to be written, the number of write operations within a preset time period, the logical page address corresponding to each write operation, and the indicator function; determine the corresponding second continuous parameter based on the duration of the write operation and the total time period; determine the corresponding third continuous parameter based on the data volume of each data to be written under the write operation and the average data volume; obtain the continuous parameter sum of the first continuous parameter, the second continuous parameter and the third continuous parameter; if the continuous parameter sum is not less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is sequentially written; if the continuous parameter sum is less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is randomly written.

[0080] In the embodiment, whether it is continuous writing or random writing is mainly determined by the continuity coefficient, and the continuity coefficient formula is as follows:

[0081] ;

[0082] is the first continuous parameter, and the specific expression is as follows:

[0083] ;

[0084] Among them, 0.7 is the weight factor; is the number of write operations within a preset time period; is the logical page address corresponding to the i-th write operation, Expresses the increment of adjacent logical page addresses, It expresses the indicator function. is 1, that is, the logical page address of the write operation increases continuously, then is 1 if the value is set, otherwise it is 0.

[0085] is the second continuous parameter, and the specific expression is as follows:

[0086] ;

[0087] in, The duration of the write operation (the time period from the first detection of the continuous address write to the time when the addresses are no longer continuous); is the total time period.

[0088] is the third continuous parameter, and the specific expression is as follows:

[0089] ;

[0090] in, For the The amount of data to be written; For the The amount of data to be written; is the average data volume.

[0091] when (the sum of the continuous parameters is not less than the continuous parameter threshold), it is judged as continuous writing. In other cases, it is defaulted to random writing.

[0092] In this design, the specific implementation method of updating the frequency analysis of the data to be written is as follows: determining the corresponding first frequency parameter based on the time-sensitive factor corresponding to the data to be written, the cumulative number of accesses to the data block under different operations, the observation time period, and the number of different operations; determining the corresponding second frequency parameter based on the time-sensitive factor, the decay rate parameter, the timestamp of the last access operation of the data block, and the observation time period; determining the corresponding third frequency parameter based on the field whose access times exceed the access threshold and the total field in the observation time period; obtaining the frequency parameter sum of the first frequency parameter, the second frequency parameter, and the third frequency parameter; if the frequency parameter sum is not less than the first frequency parameter threshold, then the result of the update frequency analysis represents that the data to be written is data in the third frequency interval; if the frequency parameter sum is not greater than the second frequency parameter threshold, then the result of the update frequency analysis represents that the data to be written is data in the first frequency interval; if the frequency parameter sum is greater than the second frequency parameter threshold and less than the first frequency parameter threshold, then the result of the update frequency analysis represents that the data to be written is data in the second frequency interval.

[0093] In this embodiment, data in a first frequency interval (cold data), data in a second frequency interval (warm data), and data in a third frequency interval (hot data) are distinguished based on the access intensity of the data. The access intensity formula is as follows:

[0094] ;

[0095] is the first frequency parameter, and the specific expression is as follows:

[0096] ;

[0097] in, It is a time-sensitive factor, which can also be understood as a weight factor for dynamically adjusting access intensity and time decay. Its expression is: , For time; For data blocks in The cumulative number of visits under the operation, when When it is 1, it is a read operation. When it is 2, it is a copy operation. When it is 3, it is a write operation; ; ; ; is the observation time period; is the operation type.

[0098] is the second frequency parameter, and the specific expression is as follows:

[0099] ;

[0100] in, is the time-sensitive factor; is the decay rate parameter; is the observation time period; The timestamp of the last access operation on the data block.

[0101] is the third frequency parameter, and the specific expression is as follows:

[0102] ;

[0103] in, The field whose access times exceed the access threshold during the observation time period; For the total field.

[0104] when When (the sum of the frequency parameters is not less than the first frequency parameter threshold,), the result of the updated frequency analysis indicates that the data to be written is data in the third frequency interval (hot data); When (the sum of the frequency parameters is not greater than the second frequency parameter threshold), the result of the updated frequency analysis at this time indicates that the data to be written is data in the first frequency interval (cold data); otherwise, the result of the updated frequency analysis indicates that the data to be written is data in the second frequency interval (warm data).

[0105] Based on the above embodiment, the present invention provides a specific flow chart of a data intelligent cache management method, as shown in FIG. Figure 4 As shown, the following steps are included:

[0106] S20: The host sends a data write request.

[0107] S21: Perform synchronous writing analysis and / or update frequency analysis on the data to be written.

[0108] S22: Determine whether the synchronous write analysis indicates that the data to be written is sequentially written.

[0109] S23: If yes, write the data to be written into the four-layer unit data block.

[0110] S24: If not, determining whether the result of the update frequency analysis indicates that the data to be written is data in the first frequency range.

[0111] S25: If yes, proceed to step S23; if not, determine whether the result of the update frequency analysis indicates that the data to be written is data in the third frequency range.

[0112] S26: If yes, write the data to be written into the single-layer unit data block.

[0113] S27: If not, the data to be written is randomly written into the single-layer unit data block or the four-layer unit data block.

[0114] It should be noted that steps S20 to S27 are a summary of the above embodiments and will not be elaborated herein in the present invention.

[0115] It should also be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to only this implementation method and can be set according to user needs.

[0116] The embodiment of the present invention provides a clear write strategy. When the result of the synchronous write analysis indicates that the data to be written is a sequential write, the data to be written is written into any four-layer unit data block; when the result of the synchronous write analysis indicates that the data to be written is a random write, and the result of the update frequency analysis indicates that the data to be written is data in the first / second frequency interval, the data to be written is written into any four-layer unit data block; when the result of the synchronous write analysis indicates that the data to be written is a random write, and the result of the update frequency analysis indicates that the data to be written is data in the second / third frequency interval, the data to be written is written into any single-layer unit data block. The full capacity availability of the solid-state drive is maintained through the four-layer unit data block, the read and write performance of the solid-state drive is improved through the single-layer unit data block, the long-term stability of the data to be written during the writing process is maintained, and the consistency of the service quality is guaranteed.

[0117] While maintaining stable write performance for the foreground host, the number of single-layer unit data blocks is controlled to prevent single-layer unit data blocks from being exhausted. At this point, data in a single-layer unit data block is migrated to other single-layer unit data blocks or four-layer unit data blocks. Simultaneously, data in a four-layer unit data block is also migrated to another four-layer unit data block. However, once data is written to a four-layer unit data block, it cannot be migrated from the four-layer unit data block to a single-layer unit data block.

[0118] For the garbage collection of single-layer unit data blocks, its implementation method is as follows: within the garbage collection time period, any single-layer unit data block that is not full of data is selected as a recycled single-layer unit data block; the single-layer valid data in the recycled single-layer unit data block is obtained, and the single-layer valid data volume corresponding to the single-layer valid data is determined; any single-layer unit data block or four-layer unit data block that is not full of data and has a remaining capacity greater than the single-layer valid data volume is selected as a migration unit data block; the single-layer valid data in the recycled single-layer unit data block is migrated to the migration unit data block, and the recycled single-layer unit data block is erased.

[0119] In an embodiment, when garbage collection is performed to migrate from a single-layer unit data block to a single-layer unit data block, the single-layer valid data in the single-layer unit data block is recycled. The data that remains in the single-layer unit data block when selected is , its internal retention ratio is: When garbage collection is performed from a single-layer unit data block to a four-layer unit data block, the single-layer valid data in the single-layer unit data block is recycled. The data that is still migrated to the fourth-level unit data block when selected is , its internal retention ratio is: ; The total single-layer effective data is: , that is, the total single-layer valid data ratio is: First, assume that the average time period for garbage collection of a data block in a single-layer unit data block is , the time period includes the time for reading the single-layer valid data in the recycled single-layer unit data block and writing it into the destination data block, and erasing the recycled single-layer unit data block.

[0120] The single-layer unit data block space recovery constraint requires that the single-layer unit data block must recover the amount of data that the host side expects to write to the single-layer unit data block within the garbage time recovery cycle, which can be expressed as:

[0121] ;

[0122] in The ratio of data blocks allocated to single-layer units in the foreground host write traffic; is the total write rate; Represents the write rate of the host writing single-layer unit data blocks; Represents the invalid data space that can be freed by a single garbage collection.

[0123] Due to the migration bandwidth constraint, the data rate of the single-layer cell data block writing data and the garbage collection migration data is lower than the maximum writing bandwidth of the single-layer cell data block (that is, the data rate of the single-layer effective data migration is less than the maximum writing bandwidth of the single-layer cell data block), and the expression is:

[0124] ;

[0125] wherein, is the maximum writing bandwidth of the single-layer cell data block.

[0126] For the garbage collection of the four-layer cell data block, the implementation manner is: obtaining the four-layer cell data block difference between the four-layer cell data block storing data and the four-layer cell data block not storing data in the four-layer cell data block; if the four-layer cell data block difference is lower than the migration threshold, and within the garbage collection time period, any one data-unstored four-layer cell data block is selected as a collection four-layer cell data block; the four-layer effective data in the collection four-layer cell data block is obtained, and the four-layer effective data amount corresponding to the four-layer effective data is determined; any one data-unstored four-layer cell data block with a remaining capacity greater than the four-layer effective data amount is selected as a migration data block; the four-layer effective data in the collection four-layer cell data block is migrated to the migration data block, and the collection four-layer cell data block is subjected to data erasure.

[0127] In the embodiment, the four-layer cell data block space recovery constraint is different from the single-layer cell data block. Only when the remaining idle data block of the four-layer cell data block is lower than a certain threshold, the four-layer cell data block is required to recover the data amount expected to be written to the four-layer cell data block by the host end within the garbage collection period, that is, expressed by the formula:

[0128] ;

[0129] wherein, is the proportion of the front-end host writing flow allocated to the four-layer cell data block; is the total writing rate; represents the writing rate of the host writing the four-layer cell data block; is the four-layer effective data in the collection four-layer cell data block is the internal reserved proportion of the four-layer cell data block still migrated at the time of selection; represents the invalid data space released by a single garbage collection; is the average time period of the garbage collection of the four-layer cell data block.

[0130] The data rate of writing data and garbage collection migration of the four-layer unit data block must be lower than the maximum write bandwidth of the four-layer unit data block (it can also be understood that the data rate of the four-layer effective data migration is lower than the maximum write bandwidth of the four-layer unit data block). The specific formula is:

[0131] ;

[0132] in, It is the maximum write bandwidth of the four-layer unit data block.

[0133] Among them, the writing speed of the single-layer unit data block is much faster than that of the four-layer unit data block, while the overall capacity occupied by the single-layer unit data block is constant. , so at the beginning the proportion of host write traffic allocated to single-layer unit data blocks The maximum value of ,When the number of four-layer unit data blocks exceeds the threshold set by the partition, then:

[0134] ;

[0135] in, is the storage capacity of a single-layer unit data block; is the storage capacity of the four-layer unit data block, is the first scale parameter.

[0136] In order to avoid performance jitter drop, we The lowest value There are also requirements, then:

[0137] ;

[0138] in, is the second scale parameter.

[0139] The implicit relationship at this time is:

[0140] ;

[0141] Right now ;

[0142] After extensive testing and There is a linear relationship, ,in is the proportional coefficient.

[0143] Therefore, just ensure That's it.

[0144] and To maximize the upper limit, Figure 2 It is reflected in the design. The upper limit is determined by the physical characteristics of the front-end host interface. The lowest value Meet the conditions.

[0145] therefore, The thresholds are as follows:

[0146] ;

[0147] When the number of remaining free data blocks of the four-layer unit data block is less than the threshold set for the partition of the four-layer unit data block, there are two corresponding relationships:

[0148] ;

[0149] ;

[0150] In fact, this also implies another corresponding relationship, as follows:

[0151] ;

[0152] That is to say, only when the four-layer unit data block is below a certain threshold, will it be required to limit the four-layer unit data block to recycle the amount of data that the host side expects to write to the four-layer unit data block within the garbage collection cycle. This situation shows that the four-layer unit data block will obtain a lot of source data blocks, and in the recycling process, it is generally recycled from the data block with the smallest valid data in the source data block first, so The value will be quite low, and because , so we only need to control , the condition is met. When the remaining free data blocks of the four-layer unit data block are only below a certain threshold, The value will be quite low. Based on a lot of experiments, it can be guaranteed that the Meet the conditions.

[0153] therefore, The thresholds are as follows:

[0154] ;

[0155] It should be noted that the embodiment provided by the present invention is only one possible implementation method, but is not limited to this implementation method and can be configured according to user needs.

[0156] In addition, since the data can be migrated, in order to avoid data damage during migration, the data newly written in the migration unit data block or the migration data block needs to be compared with the migration data, if the comparison result is completely consistent, it indicates that the migration is successful, if the comparison result has difference, the migration is re-performed until the migration is successful.

[0157] Therefore, the application has the following advantages:

[0158] 1. The application pre-sets the physical space ratio of the single-layer unit data block and the multi-layer unit data block main storage area, ensures the physical isolation of the two storage media, and avoids the risk of storage pool reconstruction.

[0159] 2. The statistical classification module is used for synchronous write analysis and / or update frequency analysis on the to-be-written data, so as to determine the write destination of the to-be-written data.

[0160] 3. According to the feedback control algorithm based on the remaining capacity of the cache and the write pressure, the write ratio of the single-layer unit data block and the four-layer unit data block is dynamically and reasonably controlled within a certain range, the performance is improved, the garbage collection strategy is implemented to manage the single-layer unit data block, the single-layer unit data block is prevented from being exhausted, and the performance is guaranteed.

[0161] Figure 5 A structure diagram of an electronic device provided by the embodiment of the application is shown in FIG. 1. Figure 5 As shown in FIG. 1, the electronic device includes a memory 60 for storing a computer program.

[0162] A processor 61 is used for executing the computer program to realize the steps of the data intelligent cache management method of the above embodiment.

[0163] The electronic device provided by the embodiment can include but is not limited to a smart phone, a tablet computer, a notebook computer or a desktop computer, etc.

[0164] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing content required to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor for handling computational operations related to machine learning.

[0165] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein, after the computer program is loaded and executed by the processor 61, it can implement the relevant steps of the data intelligent cache management method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc.

[0166] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0167] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation of the electronic device, and may include more or fewer components than shown in the figure.

[0168] It can be understood that if the data intelligent cache management method in the above embodiments is implemented in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and performs all or part of the steps of the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), an electrically erasable programmable ROM, a register, a hard disk, a removable magnetic disk, a CD-ROM, a magnetic disk or an optical disk, and various media that can store program codes.

[0169] Based on this, the embodiment of the present application also provides a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps of the data intelligent cache management method as described above.

[0170] Based on this, the embodiment of the present application also provides a computer program product, which includes computer programs / instructions. The computer programs / instructions are executed by a processor to implement the steps of the data intelligent cache management method as described above.

[0171] The above describes in detail the data intelligent cache management method, device and medium provided by the embodiment of the present application. The embodiments in the specification are described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the related parts can be referred to the method part.

[0172] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solutions. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0173] The above is a detailed introduction to a data intelligent cache management method, device and medium provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified. These improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A data intelligent cache management method, characterized in that: Applicable to solid-state drives including several four-layer unit data blocks and single-layer unit data blocks, including: Performing synchronous writing analysis and / or update frequency analysis on the data to be written; wherein the priority of the synchronous writing analysis is higher than the priority of the update frequency analysis; If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the four-layer unit data block, writing the data to be written into the four-layer unit data block; If the result of the synchronous writing analysis and / or the result of the updating frequency analysis meets the requirement of writing into the single-layer unit data block, the data to be written is written into the single-layer unit data block.

2. The data intelligent cache management method according to claim 1, characterized in that: The result of the synchronous writing analysis and / or the result of the update frequency analysis meeting the requirement of writing the four-layer unit data block includes: When the result of the synchronous writing analysis indicates that the data to be written is sequentially written, writing the data to be written into any one of the four-layer unit data blocks; When the result of the synchronous write analysis indicates that the data to be written is randomly written, and the result of the update frequency analysis indicates that the data to be written is data in the first / second frequency interval, the data to be written is written into any one of the four-layer unit data blocks.

3. The data intelligent cache management method according to claim 1, characterized in that: The result of the synchronous writing analysis and / or the result of the update frequency analysis meeting the requirement of writing the single-layer unit data block includes: When the result of the synchronous write analysis indicates that the data to be written is random write, and the result of the update frequency analysis indicates that the data to be written is data in the second / third frequency interval, the data to be written is written into any one of the single-layer unit data blocks.

4. The data intelligent cache management method according to claim 1, characterized in that: Performing the synchronous write analysis on the data to be written includes: Determining a corresponding first continuous parameter based on a weight factor corresponding to the data to be written, a number of write operations within a preset time period, a logical page address corresponding to each write operation, and an indicator function; determining a corresponding second continuous parameter based on the duration and the total time period of the write operation; determining a corresponding third continuous parameter based on the data amount of each of the to-be-written data and the average data amount in the write operation; Obtaining a continuous parameter sum of the first continuous parameter, the second continuous parameter, and the third continuous parameter; If the sum of the continuous parameters is not less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is sequentially written; If the sum of the continuous parameters is less than the continuous parameter threshold, the result of the synchronous write analysis indicates that the data to be written is randomly written.

5. The data intelligent cache management method according to claim 1, characterized in that: Performing the update frequency analysis on the data to be written includes: Determining a corresponding first frequency parameter based on a time-sensitive factor corresponding to the data to be written, a cumulative number of accesses to the data block under different operations, an observation time period, and the number of different operations; Determining a corresponding second frequency parameter based on the time sensitivity factor, the decay rate parameter, the timestamp of the last access operation of the data block, and the observation time period; determining a corresponding third frequency parameter based on the field whose access times exceed the access threshold and the total field in the observation time period; Obtaining a frequency parameter sum of the first frequency parameter, the second frequency parameter, and the third frequency parameter; If the sum of the frequency parameters is not less than the first frequency parameter threshold, the result of the update frequency analysis indicates that the data to be written is data in the third frequency interval; If the sum of the frequency parameters is not greater than a second frequency parameter threshold, the result of the update frequency analysis indicates that the data to be written is data in the first frequency interval; If the sum of the frequency parameters is greater than the second frequency parameter threshold and less than the first frequency parameter threshold, the result of the update frequency analysis indicates that the data to be written is data in the second frequency interval.

6. The data intelligent cache management method according to any one of claims 1 to 5, characterized in that: Also includes: During the garbage collection time period, any single-layer unit data block that is not fully populated is selected as a recycled single-layer unit data block; Acquire the single-layer valid data in the recovered single-layer unit data block, and determine the single-layer valid data amount corresponding to the single-layer valid data; Selecting any one of the single-layer unit data blocks or the four-layer unit data blocks that is not fully stored and has a remaining capacity greater than the single-layer valid data volume as a migration unit data block; The single-layer valid data in the recycled single-layer unit data block is migrated to the migration unit data block, and data in the recycled single-layer unit data block is erased.

7. The data intelligent cache management method according to claim 6, characterized in that: Also includes: Obtaining a four-layer unit data block difference between the four-layer unit data block storing data and the four-layer unit data block not storing data in the four-layer unit data block; If the difference value of the four-layer unit data blocks is lower than the migration threshold and within the garbage collection time period, any one of the four-layer unit data blocks that is not fully stored is selected as a recycled four-layer unit data block; Acquire four layers of valid data in the recovered four-layer unit data block, and determine a four-layer valid data amount corresponding to the four layers of valid data; any one of the four-layer unit data blocks that is not fully stored and has a remaining capacity greater than the four-layer valid data volume is selected as a migration data block; The four layers of valid data in the recycled four-layer unit data block are migrated to the migration data block, and data in the recycled four-layer unit data block is erased.

8. The data intelligent cache management method according to claim 7, characterized in that: In the process of migrating the single-layer valid data in the recycled single-layer unit data block to the migration unit data block, the method further includes: The data rate of the single-layer effective data migration is less than the maximum write bandwidth of the single-layer unit data block; In the process of migrating the four layers of valid data in the recycled four-layer unit data block to the migration data block, the method further includes: The data rate of the four-layer effective data migration is less than the maximum write bandwidth of the four-layer unit data block.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the data intelligent cache management method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data intelligent cache management method according to any one of claims 1 to 8 are implemented.

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