Register sensitive instruction selection and sorting method based on tree pattern matching

Abstract

The invention discloses a register-sensitive instruction selecting and sorting method based on tree pattern matching, which is used for performing expression tree construction and optimization on instructions in a control flow diagram, and selecting and sorting the instructions in combination with a Sethi-Ullman algorithm and an iburg instruction selector. According to the method, the expression tree of the instruction is merged and optimized, so that the pressure of a register is reduced, the instruction selection and sorting efficiency is improved, and the execution performance of a program is optimized. Compared with the prior art, the method has the advantages that register resources can be utilized more effectively, register conflicts in the instruction selection and sorting process are reduced, and the execution efficiency and performance of a program are improved.

Description

Technical Field

[0001] The present invention belongs to the field of high performance computing in computer system architecture, and in particular relates to a register-sensitive instruction selection and sorting method based on tree pattern matching. Background Art

[0002] Registers are memory within the CPU used to temporarily store instructions, data, and addresses. Registers have limited storage capacity and are the fastest locations in the computer's memory hierarchy. Registers store intermediate results of calculations performed at known points in time, accelerating the execution of computer programs by providing fast access to data. When the number of active values ​​at a given point in the program exceeds the number of physical registers, an optimized program will exhibit high register pressure, forcing one or more active values ​​to overflow.

[0003] Instruction selection involves translating a program from a target-independent representation to a target-specific form by making the best use of available machine instructions. Basic instruction selection methods include macro expansion, tree pattern matching, DAG and graph coverage, and simulation. For many years, code generation systems that utilize tree pattern matching have been widely used in many compilers. These systems are often very fast and efficient, making tree pattern matching the best-known instruction selection method.

[0004] In general, register allocation and instruction scheduling are computationally complex and interdependent. Addressing instruction scheduling first tends to increase register pressure; conversely, addressing register allocation first often increases register reuse, potentially degrading instruction scheduling results. As the performance gap between CPU computation time and memory access time continues to widen, optimizing register usage is becoming increasingly important in high-performance processors. Proposing an instruction selection and sequencing method that prioritizes register pressure reduction has implications for performance optimization in high-performance processors. Summary of the Invention

[0005] The object of the present invention is to provide a register-sensitive instruction selection and sorting method based on tree pattern matching to solve the above problems.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The method for register-sensitive instruction selection and sequencing based on tree pattern matching comprises the following steps:

[0008] Step 1, initialization: set the leaf node leaves(instr) of each intermediate instruction instr expression tree in the control flow graph to an empty set, and set the expression tree queue trees to empty;

[0009] Step 2: For each instruction instr in the control flow graph, construct an expression tree for the instruction instr; for each instruction instr, check whether it is a related instruction. If so, execute step 7; if not, add the source operand of the instruction to its leaf node set leaves(instr);

[0010] Step 3, check the value and usage count of the destination operand dest of instr; if the value or usage count is greater than 1, execute step 7;

[0011] Step 4: Check whether the instruction target using dest is in the same loop as the current instruction instr; if not, go to step 7;

[0012] Step 5: Check whether there is a node in leaves(instr) with a fixed value in the path from the current instruction instr to the target instruction target; if there is such a fixed value, execute step 7;

[0013] Step 6: Merge the expression tree of instruction instr with the leaf node dest of the expression tree of instruction target, and update the leaf node set leaves(target) of instruction target to the original leaf node set plus the leaf node set leaves(instr) of the current instruction instr, and remove the target operand dest, and execute step 8;

[0014] Step 7: Let the root node of the instr expression tree be p, and then go to step 9.

[0015] Step 8: Repeat steps 2 to 7 until all the expression trees of the instructions are processed.

[0016] Step 9: For a given expression tree node p, determine whether its operator has the commutative and associative properties. If the operator does not have these two properties, recursively execute step 9 for its left and right child nodes, mark the node priority according to the Sethi-Ullman algorithm, and execute step 13.

[0017] Step 10: For each leaf node in the single-type operator tree starting from the root node p, recursively execute step 9 for each leaf node and add it to the priority queue leaves;

[0018] Step 11: Take out two leaf nodes s1 and s2 from the priority queue leaves in order and check whether there are other leaf nodes in the priority queue. If the priority queue is not empty, generate a new node whose operator is the operator of p and set s1 and s2 as the left and right child nodes of the new node. Otherwise, set s1 as the left child node of p and s2 as the right child node of p, and use the Sethi-Ullman algorithm to mark the parent node of s1.

[0019] Step 12: If there are still remaining nodes in the priority queue leaves, add the newly generated node to the priority queue leaves and execute step 10; otherwise, execute step 13.

[0020] Step 13: Put node p into the queue trees and continue from step 9.

[0021] Step 14: For all expression trees in the queue trees, use the iburg instruction selector to select instructions and generate assembly instructions.

[0022] A further improvement of the present invention is that, in step 1, the control flow graph, intermediate instructions, and expression tree are defined as follows:

[0023] Use the symbols V, O, B, and F to denote the set of program variables, the set of operators, the set of control flow operations, and the set of non-function operations, respectively; in particular, constants are also considered to be variables belonging to V;

[0024] Non-control flow instructions must be decomposed into the following simple form:

[0025] (f,x0,x1,x2,…,x n )

[0026] where f∈O∪F, x i ∈V, n is the number of source operands of f, x0 is the target operand of f, x1, x2, ..., x n is the source operand of f;

[0027] Control flow instructions must be broken down into the following simple form:

[0028] (f,x0,x1,x2,x3)

[0029] where f∈B,x i ∈V, x0, x1 are the variables to be compared by f, x2, x3 are the identifiers of the target instructions to jump to if the comparison result is true and false respectively; in particular, if f is a direct jump instruction goto, then x0, x1, x3 are invalid;

[0030] A program P consists of a directed flow graph P = (NP ,E P ,entry,exit) represents;Node set N P represents the set of basic blocks, including non-control flow instructions, control flow instructions, and the entry and exit nodes of P;Edge set E P represents non-deterministic control flow;

[0031] All control flow instructions and non-control flow instructions can be expressed as expression trees, for a certain instruction and its expression tree, there is a unique tree node t corresponding to a variable x in the instruction V,

[0032] The queue is an abstract data type, which is a first-in first-out linear list, and only insertion operation is allowed at the rear end and deletion operation is allowed at the front end.

[0033] The further improvement of the present application is that in step 2, the instructions are divided into two categories according to whether the intermediate instructions have side effects: relevant instructions and non-relevant instructions, wherein the relevant instructions represent instructions with side effects, and the non-relevant instructions represent instructions without side effects.

[0034] The further improvement of the present application is that in step 3, when the variable v is located at the left side of the assignment statement, that is, v=s(j), then s(j) is the constant value of v;When the variable v is located at the right side of the statement s(j), then v is used in the statement s(j).

[0035] The further improvement of the present application is that in step 4, the loop is a piece of code which appears only once in the program but may be executed continuously for many times.

[0036] The further improvement of the present application is that in step 9, the implementation method of the Sethi-Ullman algorithm is as follows:

[0037] A label L(eta) is assigned to each node eta of the expression tree from bottom to top:

[0038] L1.If eta is a leaf and is the left child of its parent node, then L(eta)=1;If eta is the right child, then L(eta)=0;

[0039] L2.If eta has descendants with labels l1 and l2, then for l1≠l2, L(eta)=max(l1,l2);For l1=l2, L(eta)=l1+1;

[0040] To generate code, first generate code for the subtree that needs the most registers if the subtrees need different numbers of registers.

[0041] The further improvement of the present application is that in step 10, the operator types of all non-leaf nodes of the single-type operator tree are consistent, and the operator types of the leaf nodes are different from the operator types of the non-leaf nodes.

[0042] The further improvement of the present application is that in step 11, the priority queue is that each element in the priority queue has a respective priority, and the element with the highest priority is served first; the elements with the same priority are served according to their order in the priority queue.

[0043] The further improvement of the present application is that in step 14, iburg is an instruction selector using dynamic programming at compile time; the assembly instruction is some operators and mnemonics used in the assembly language, and the assembly instruction corresponds to the machine instruction one by one.

[0044] A computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps of the method for register-sensitive instruction selection and ordering based on tree pattern matching.

[0045] Compared with the prior art, the present application has at least the following beneficial technical effects:

[0046] The method for register-sensitive instruction selection and ordering based on tree pattern matching provided by the present application constructs and optimizes the expression tree for the instructions in the control flow graph, and selects and orders the instructions in combination with the Sethi-Ullman algorithm and the iburg instruction selector. This method reduces the register pressure and improves the efficiency of instruction selection and ordering by merging and optimizing the expression tree of the instructions, thereby optimizing the execution performance of the program. Compared with the prior art, the present application can more effectively utilize the register resources, reduce the register conflicts in the instruction selection and ordering process, and improve the execution efficiency and performance of the program. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0048] Figure 1 The flowchart of the method of the present application.

[0049] Figure 2 The expression tree constructed for each instruction in the basic block of the embodiment of the present application is shown in the schematic diagram.

[0050] Figure 3 Figure for all constant and target operand with usage times no more than 1 for embodiments of the present application.

[0051] Figure 4 Figure for expression tree nodes that can be merged for embodiments of the present application.

[0052] Figure 5 Figure for merged expression tree for embodiments of the present application.

[0053] Figure 6 Figure for first expression tree for embodiments of the present application.

[0054] Figure 7 Figure for final generated expression tree for embodiments of the present application. DETAILED DESCRIPTION

[0055] In the following, only certain exemplary embodiments are simply described. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature rather than restrictive.

[0056] In the description of the present application, it is to be understood that the terms "including", "comprising", "having" and "with" as used herein indicate the presence of the stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0057] It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0058] It will be further understood that the terms "and / or", as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items, and that the term "at least one of" followed by a list of two or more items means any single one of the items from the list individually, as well as any combination of two or more of the items.

[0059] Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. These diagrams are not drawn to scale in that certain details are exaggerated for clarity and others are omitted. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only and can vary depending on the manufacturing techniques used to produce the structures and the intended application of the structures. The skilled person can design alternative regions / layers with different shapes, sizes, relative positions according to the actual needs.

[0060] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0061] The present application provides a register-sensitive instruction selection and scheduling method based on tree pattern matching, which constructs and optimizes expression trees for instructions in a control flow graph, and selects and schedules the instructions in combination with Sethi-Ullman algorithm and iburg instruction selector. The method reduces register pressure and improves the efficiency of instruction selection and scheduling by merging and optimizing the expression trees of the instructions, thereby optimizing the execution performance of the program.

[0062] Embodiment 1

[0063] Please refer to Figure 1 The present application provides a register-sensitive instruction selection and scheduling method based on tree pattern matching, which constructs and optimizes expression trees for instructions in a control flow graph, and selects and schedules the instructions in combination with Sethi-Ullman algorithm and iburg instruction selector. The method reduces register pressure and improves the efficiency of instruction selection and scheduling by merging and optimizing the expression trees of the instructions, thereby optimizing the execution performance of the program.

[0064] Step 1, initialization: set the leaf nodes of the expression trees of each intermediate instruction instr in the control flow graph leaves(instr) to be empty sets, and set the expression tree queue trees to be empty. Wherein, the control flow graph, intermediate instruction, expression tree are defined as follows:

[0065] In the compiler, the control flow graph, intermediate instruction, expression tree, etc. are used as the intermediate representation of the program, and the symbols V, O, B and F are used to represent the set of program variables, the set of operators, the set of control flow operations and the set of non-functional operations, respectively. In particular, constants are also regarded as variables belonging to V. For example,

[0066] V = {x1, x2, 21, -9, …} O = {+, -, move, …} B = {goto, ifeq, iflt, …} F = {load, store, call, …}

[0067] Non-control flow instructions must be decomposed into the following simple form:

[0068] (f, x0, x1, x2, …, xn) n )

[0069] Wherein f ∈ O ∪ F, x i ∈ V, n is the number of source operands of f, x0 is the target operand of f, and x1, x2, …, xn are the source operands of f. n

[0070] Control flow instructions must be decomposed into the following simple form:

[0071] (f, x0, x1, x2, x3)

[0072] Wherein f ∈ B, x i ​∈V, x0, x1 are the variables to be compared by f, and x2, x3 are the identifiers of the target instructions to jump to if the comparison result is true and false, respectively. In particular, if f is a direct jump instruction goto, then x0, x1, x3 are invalid.

[0073] A program P consists of a directed flow graph P = (N P ,E P ,entry,exit). Node set N P Represents the set of basic blocks, including non-control flow instructions, control flow instructions, and the entry and exit nodes of P. Edge set E P Indicates non-deterministic control flow.

[0074] We assume that all control flow instructions and non-control flow instructions can be expressed as expression trees. For a certain instruction and its expression tree, there is always a unique tree node t corresponding to a variable x∈V in the instruction.

[0075] A queue is an abstract data type, a first-in-first-out linear table that only allows insertion operations at the back end and deletion operations at the front end.

[0076] Step 2: For each instruction instr in the control flow graph, construct an expression tree for the instruction instr. For each instruction instr, check whether it is a related instruction. If so, execute step 7; if not, add the source operand of the instruction to its leaf node set leaves(instr). Related instructions are defined as instructions that can be divided into two categories based on whether the intermediate instructions have side effects: related instructions and non-related instructions. Related instructions represent instructions with side effects, and non-related instructions represent instructions without side effects. Operands are the objects of operation, that is, the objects or quantities to be operated on. Operators are enumerated values ​​used to specify the operation to be performed.

[0077] Step 3, check the fixed value and the number of times the target operand dest of instr is used. If the number of fixed values ​​or the number of times it is used is greater than 1, then execute step 7. Traversal refers to visiting each node in the tree (or graph) in turn along a certain search route. Fixed value and use are defined as follows: when the variable v is on the left side of the assignment statement, for example, v = s(j), then s(j) is the fixed value of v; when the variable v is on the right side of the statement s(j), then v is used in the statement s(j);

[0078] Step 4: Check whether the instruction target using dest is in the same loop as the current instruction instr. If not, proceed to step 7. A loop is a section of code that appears only once in a program but may be executed multiple times in succession.

[0079] Step 5, check if there is a path from the current instruction instr to the target instruction target in which some node in leaves(instr) is assigned. If such an assignment exists, perform step 7;

[0080] Step 6, merge the expression tree of instruction instr with the leaf node dest of the expression tree of instruction target, and update the leaf node set leaves(target) of instruction target to be the original leaf node set plus the leaf node set leaves(instr) of the current instruction instr and minus the target operand dest. Perform step 8;

[0081] Step 7, let p be the root node of the expression tree of instr, perform step 9;

[0082] Step 8, repeat steps 2 to 7 until all expression trees of instructions are processed;

[0083] Step 9, for a given expression tree node p, determine if its operator has the commutative and associative properties. If the operator does not have these two properties, recursively perform step 9 on its left and right child nodes, and label the priority of the node according to the Sethi-Ullman algorithm, perform step 13. The Sethi-Ullman algorithm is an algorithm that:

[0084] assigns a label L(p) to each node p of the expression tree from the bottom up:

[0085] L1. If p is a leaf and is the left child of its parent, then L(p) = 1; if p is the right child, then L(p) = 0;

[0086] L2. If p has descendants with labels 1 and 2, then L(p) = max(l, 2) for 1 ≠ 2; and L(p) = 1 + 1 for 1 = 2.

[0087] To generate code, first generate code for the subtree that requires the most registers if the subtrees require different numbers of registers;

[0088] Step 10, for each leaf node in the single-type operator tree starting from the root node p, recursively perform step 9 on each leaf node and add it to the priority queue leaves. The single-type operator tree is a tree in which the operator types of all non-leaf nodes are consistent, and the operator types of the leaf nodes are different from the operator types of the non-leaf nodes;

[0089] Step 11, in the priority queue leaves, two leaf nodes s1 and s2 are taken out in order, and it is checked whether there are other leaf nodes in the priority queue. If the priority queue is not empty, a new node is generated, the operator of the new node is the operator of p, and s1 and s2 are taken as the left and right child nodes of the new node. Otherwise, s1 is taken as the left child node of p, and s2 is taken as the right child node of p, and the Sethi-Ullman algorithm is used to mark the parent node of s1. Wherein, the priority queue is a data type, each element in the priority queue has its own priority, and the element with the highest priority is serviced first; elements with the same priority are serviced according to their order in the priority queue;

[0090] Step 12, if there are remaining nodes in the priority queue leaves, the newly generated node is added to the priority queue leaves, and step 10 is executed, otherwise step 13 is executed;

[0091] Step 13, the node p is put into the queue trees, and the step of entering step 9 is continued to execute.

[0092] Step 14, for all expression trees in the queue trees, instruction selection is performed using the iburg instruction selector, to generate assembly instructions. Wherein, iburg is an instruction selector using dynamic programming at compile time; the assembly instruction is some operator and mnemonic used in assembly language, and the assembly instruction corresponds to the machine instruction one by one.

[0093] After the above steps are completed, the register-sensitive machine assembly instructions are obtained, and subsequent instruction scheduling and register allocation can be performed according to the assembly instructions. Thus, the method of register-sensitive instruction selection and ordering based on tree pattern matching is ended.

[0094] Embodiment 2

[0095] The following is an example of a control flow graph with only one basic block:

[0096]

[0097] The expression tree constructed for each instruction in this basic block is shown as Figure 2 .

[0098] All constant values and target operands with a usage count of no more than 1 have been marked in Figure 3 .

[0099] Since there is no cycle in the control flow graph, and for the marked target operand, there is also no path from the corresponding instruction instr to the target instruction target, the merging of the expression trees is done directly. The expression tree nodes that can be merged are indicated in Figure 4 .

[0100] The merged expression trees are shown in Figure 5 .

[0101] The steps from step 7 onwards are performed for the first expression tree in Figure 6 , as shown in Figure 5 . The label L(η) of each node η is indicated below it; the resulting expression tree is shown in Figure 7 .

[0102] The expression trees are then instruction selected using the iburg instruction selector, resulting in assembly instructions (ARM assembly).

[0103]

[0104] The present application has the advantage over the conventional method that it reduces the time needed for compilation while achieving similar effects of reducing register pressure as the conventional method. For example, in the control flow graph with only one basic block and 7 intermediate instructions, the conventional method needs to perform 7! = 5040 operations in the worst case, while the present application only needs to perform 7 x 5 x 4 x 3! = 840 operations at most. The execution time in the worst case is only

[0105] Embodiment 3

[0106] The present application provides a computer readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the method for register-sensitive instruction selection and ordering based on tree pattern matching.

[0107] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage media, etc.) containing computer-usable program code.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of the methods, systems, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or boxes.

[0109] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0111] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, from all points of view, the embodiments should be regarded as illustrative and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and range of equivalents of the claims are included in the present invention. Any reference signs in the claims should not be construed as limiting the claim to which they relate.

[0112] In addition, it should be understood that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This description is for clarity only. Those skilled in the art should consider the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for the purpose of illustrating the technical concept of the present invention and cannot be used to limit the scope of protection of the present invention. Any changes made based on the technical solution in accordance with the technical concept proposed by the present invention fall within the scope of protection of the claims of the present invention.

Claims

1. A method for register-sensitive instruction selection and sequencing based on tree pattern matching, characterized in that: The following steps are involved: Step 1, initialization: set the leaf node leaves(instr) of each intermediate instruction instr expression tree in the control flow graph to an empty set, and set the expression tree queue trees to empty; Step 2: For each instruction instr in the control flow graph, construct an expression tree for the instruction instr; For each instruction instr, check whether it is a related instruction. If so, execute step 7; if not, add the source operand of the instruction to its leaf node set leaves(instr); Step 3, check the value and usage count of the destination operand dest of instr; if the value or usage count is greater than 1, execute step 7; Step 4, check whether the instruction target using dest is in the same loop as the current instruction instr; If not in the same loop, go to step 7; Step 5: Check whether there is a node in leaves(instr) with a fixed value in the path from the current instruction instr to the target instruction target; if there is such a fixed value, execute step 7; Step 6: Merge the expression tree of instruction instr with the leaf node dest of the expression tree of instruction target, and update the leaf node set leaves(target) of instruction target to the original leaf node set plus the leaf node set leaves(instr) of the current instruction instr, and remove the target operand dest, and execute step 8; Step 7: Let the root node of the instr expression tree be p, and then go to step 9. Step 8: Repeat steps 2 to 7 until all the expression trees of the instructions are processed. Step 9: For a given expression tree node p, determine whether its operator has the commutative and associative properties. If the operator does not have these two properties, recursively execute step 9 for its left and right child nodes, mark the node priority according to the Sethi-Ullman algorithm, and execute step 13. Step 10: For each leaf node in the single-type operator tree starting from the root node p, recursively execute step 9 for each leaf node and add it to the priority queue leaves; Step 11: Take out two leaf nodes s1 and s2 from the priority queue leaves in order and check whether there are other leaf nodes in the priority queue. If the priority queue is not empty, generate a new node whose operator is the operator of p and set s1 and s2 as the left and right child nodes of the new node. Otherwise, set s1 as the left child node of p and s2 as the right child node of p, and use the Sethi-Ullman algorithm to mark the parent node of s1. Step 12: If there are still remaining nodes in the priority queue leaves, add the newly generated node to the priority queue leaves and execute step 10; otherwise, execute step 13. Step 13: Put node p into the queue trees and continue from step 9. Step 14: For all expression trees in the queue trees, use the iburg instruction selector to select instructions and generate assembly instructions.

2. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, characterized in that: In step 1, the control flow graph, intermediate instructions, and expression tree are defined as follows: Use the symbols V, O, B, and F to denote the set of program variables, the set of operators, the set of control flow operations, and the set of non-function operations, respectively; in particular, constants are also considered to be variables belonging to V; Non-control flow instructions must be decomposed into the following simple form: (f,x0,x1,x2,…,x n ) where f∈O∪F, x i ∈V, n is the number of source operands of f, x0 is the target operand of f, x1, x2, ..., x n is the source operand of f; Control flow instructions must be broken down into the following simple form: (f,x0,x1,x2,x3) where f∈B,x i ∈V, x0, x1 are the variables to be compared by f, x2, x3 are the identifiers of the target instructions to jump to if the comparison result is true and false respectively; in particular, if f is a direct jump instruction goto, then x0, x1, x3 are invalid; A program P consists of a directed flow graph P = (N P ,E P ,entry,exit) represents; node set N P Represents the set of basic blocks, including non-control flow instructions, control flow instructions, and the entry and exit nodes of P; the edge set E P Represents non-deterministic control flow; All control flow instructions and non-control flow instructions can be expressed as expression trees. For a certain instruction and its expression tree, there is always a unique tree node t corresponding to a variable x∈V in the instruction. A queue is an abstract data type, a first-in-first-out linear table that only allows insertion operations at the back end and deletion operations at the front end.

3. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, characterized in that: In step 2, instructions are divided into two categories according to whether the intermediate instructions have side effects: dependent instructions and non-dependent instructions, wherein dependent instructions represent instructions with side effects, and non-dependent instructions represent instructions without side effects.

4. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, characterized in that: In step 3, when the variable v is on the left side of the assignment statement, that is, v = s(j), then s(j) is the fixed value of v; when the variable v is on the right side of the statement s(j), then v is used in the statement s(j).

5. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, characterized in that: In step 4, a loop is a section of code that appears only once in a program but may be executed multiple times in succession.

6. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, wherein: In step 9, the Sethi-Ullman algorithm is implemented as follows: Assign a label L(η) to each node η of the expression tree from the bottom up: L1. If η is a leaf and is the left child of its parent, then L(η) = 1; if η is the right child, then L(η) = 0; L2. If η has descendants with labels l1 and l2, then for l1≠l2, L(η)=max(l1,l2); for l1=l2, L(η)=l1+1; To generate code, if the subtrees require different numbers of registers, generate code for the subtree that requires the most registers first.

7. The method for register-sensitive instruction selection and sorting based on tree pattern matching according to claim 1, characterized in that: In step 10, the operator types of all non-leaf nodes of the single-type operator tree are consistent, while the operator type of the leaf node is different from the operator type of the non-leaf nodes.

8. The method for register-sensitive instruction selection and sequencing based on tree pattern matching according to claim 1, characterized in that: In step 11, the priority queue is such that each element in the priority queue has its own priority, and the element with the highest priority is served first; elements with the same priority are served according to the order in which they are in the priority queue.

9. The method for register-sensitive instruction selection and sequencing based on tree pattern matching according to claim 1, wherein: In step 14, iburg is an instruction selector that uses dynamic programming during compilation; assembly instructions are some operators and mnemonics used in assembly language, and assembly instructions correspond one-to-one to machine instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for register-sensitive instruction selection and sequencing based on tree pattern matching according to any one of claims 1 to 9.

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