System on chip and operation method of system on chip

Abstract

A system-on-chip and an operation method of the system-on-chip are provided. The system-on-chip (SoC) includes a first processor including a first performance monitor configured to perform monitoring on a plurality of first performance parameters including the first performance parameters. The SoC further includes a power prediction circuit configured to predict power consumption of the first processor based on a count value of the first performance parameter collected by the first performance monitor; and a power management unit configured to manage power supplied to the first processor based on a prediction result of the power prediction circuit.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0048083, filed on April 9, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0112334, filed on August 21, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. TECHNICAL FIELD

[0002] The disclosure relates to a system on chip (SoC) and an operating method of a system on chip. BACKGROUND

[0003] An SoC corresponding to a computer or an electronic system component integrated in an integrated circuit is a system including devices having various functions on a chip. For example, the SoC can include main semiconductor devices such as an operating device (such as a processor), a memory device, and a digital signal processing device.

[0004] A processor can execute various applications to perform various operations. The processor requires a power supply to perform the operations, and the required power (for example, power) varies according to the operations of the processor, and thus a power management technology that appropriately supplies the power required for the processor to operate is proposed. SUMMARY

[0005] Embodiments provide a system on chip (SoC) and an operating method of a system on chip (SoC) that selectively uses a count value of an effective performance parameter among a plurality of performance parameters supported by a processor in order to accurately predict power consumption of the processor without a separate hardware logic for measuring power consumption of the processor.

[0006] According to one aspect of the disclosure, a system on chip (SoC) includes a first processor including a first performance monitor configured to perform monitoring on a plurality of first performance parameters including a first performance parameter, a power prediction circuit configured to predict power consumption of the first processor based on first count values of the first performance parameters collected through the first performance monitor, and a power management circuit configured to manage power supplied to the first processor based on a prediction result of the power prediction circuit.

[0007] According to one aspect disclosed, a method of operating a computing device for generating a neural network model that predicts power consumption of a processor includes performing a first counting operation on a plurality of performance parameters of the processor and performing a first measuring operation on power consumption of the processor in a first time period during which a plurality of benchmark applications are executed through the processor, selecting a first performance parameter from among the plurality of performance parameters based on a first result of the first counting operation and based on a second result of the first measuring operation, performing a second counting operation on the first performance parameter of the processor and performing a second measuring operation on the power consumption of the processor in a second time period during which a plurality of user applications are executed through the processor, and training the neural network model based on a third result of the second counting operation and based on a fourth result of the second measuring operation.

[0008] According to one aspect disclosed, a method of operating a system on chip (SOC) for managing power supplied to a processor includes collecting a counting value of a performance parameter among a plurality of performance parameters of the processor, predicting power consumption of the processor based on the counting value and a neural network model, and controlling power supplied to the processor based on a prediction result. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and / or other aspects will become apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 FIG. 1 is a block diagram schematically illustrating a system on chip (SoC) according to an embodiment.

[0011] Figure 2A and Figure 2B FIG. 2 is a flowchart for describing a method of predicting power consumption of a processor of an SoC according to an embodiment.

[0012] Figure 3A and Figure 3B FIG. 3 is a block diagram for describing an operation of a power prediction circuit according to an embodiment.

[0013] Figure 4 FIG. 4 is a flowchart illustrating a method of predicting power consumption of a processor of an SoC according to an embodiment.

[0014] Figure 5 FIG. 5 is a block diagram for describing an operation of a power prediction circuit according to an embodiment.

[0015] Figure 6 FIG. 6 is a diagram for describing a method of operating an SoC according to an embodiment.

[0016] Figure 7A and Figure 7B FIG. 7 is a block diagram of a processor according to an embodiment.

[0017] FIG. 8 is a block diagram of a processor according to an embodiment.Figure 8 is a block diagram illustrating a processor according to an embodiment.

[0018] Figure 9 is a flowchart illustrating a method of operating an apparatus (e.g., a computing apparatus) that constructs a neural network model for predicting power consumption of a processor according to an embodiment.

[0019] Figure 10 is a flowchart for describing a specific embodiment of operation S300 of Figure 9

[0020] Figure 11 is a flowchart for describing a specific embodiment of operation S306 of Figure 10

[0021] Figure 12 is a diagram for describing a method of selecting an effective performance parameter according to an embodiment.

[0022] Figure 13 is a flowchart for describing a specific embodiment of operation S310 of Figure 9

[0023] Figure 14 is a flowchart for describing a specific embodiment of operation S320 of Figure 9

[0024] Figure 15 is a block diagram illustrating an SoC according to an embodiment.

[0025] Figure 16 is a block diagram illustrating an electronic device according to an embodiment. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram schematically illustrating a system on chip (SoC) 10 according to an embodiment.

[0027] Referring to Figure 1 , the SoC 10 can be included in a mobile phone, a smart phone, a tablet personal computer (PC), a digital camera, a handheld game console, or a handheld device such as an electronic book or a wearable device as an electronic device. Embodiments described below focus on the configuration of the SoC 10, but the embodiments are not limited thereto, and it is well understood that the disclosure can be applied to various electronic devices including a computing apparatus such as a processor.

[0028] In one embodiment, the SoC 10 can include a power prediction circuit 100, a power management unit 110 (also referred to as a power management circuit), a processor 120, and a bus 130. In addition to the SoC 10, the power prediction circuit 100, the power management unit 110, the processor 120, and the bus 130 can be included in an electronic device such as a mobile phone, a smart phone, a tablet PC, a digital camera, a handheld game console, or a handheld device such as an electronic book or a wearable device. Figure 1 ​​​​In addition to the components shown in FIG. 1, the SoC 10 can also include additional components. In some embodiments, a power management integrated circuit (PMIC) supporting the functions of the power management unit 110 can be implemented outside of the SoC 10, in place of the power management unit 110.

[0029] In one embodiment, the processor 120 can process or execute programs and / or data, and can be various types of operating devices such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), or an image signal processor (ISP). Also, the processor 120 can be implemented as a multi-core processor. The multi-core processor is a single computing component having two or more independent substantial cores, and each core can execute a program to perform an operation. Here, the program and the application as a target of execution by the processor 120 can be interchangeable. The performance monitor 121 can be implemented by a circuit and / or software of the processor 120.

[0030] In one embodiment, the power management unit 110 can perform an operation of managing power required to drive the components of the SoC 10. As one specific example, the power management unit 110 can supply power required for the processor 120 to process or execute programs and / or data to the processor 120. The power management unit 110 can be implemented with a CPU, a GPU, an NPU, an ISP, custom hardware, and / or software.

[0031] In one embodiment, the power management unit 110 can adjust power based on the power consumption of the processor 120 predicted by the power prediction circuit 100, and supply the adjusted power to the processor 120. For example, the power management unit 110 can adjust the power supplied to the processor 120 by adjusting at least one of an operating voltage, an operating frequency, and a current applied to the processor 120. In some embodiments, the operating frequency applied to the processor 120 can be adjusted by a clock management unit.

[0032] Hereinafter, a method of predicting power consumption of the processor 120 by the power prediction circuit 100 will be described. Before the description, the processor 120 can include a performance monitor 121, and the performance monitor 121 can monitor performance or operational problems of the processor 120. Specifically, the performance monitor 121 can perform a counting operation (or monitoring) on a plurality of performance parameters of the processor 120 by using registers to collect hardware events (or count values) corresponding to the plurality of performance parameters of the processor 120. The count values of the plurality of performance parameters collected in the registers can indicate performance of the processor 120 in various aspects. For example, the plurality of performance parameters can include a parameter on the number of memory accesses, a parameter on the number of instructions executed, a parameter on the number of clock cycles, etc. On the other hand, the number of registers supported by the performance monitor 121 can be limited, and thus, the number of performance parameters counted and collected in the registers at the same time among the plurality of performance parameters can match the number of registers.

[0033] In one embodiment, the power prediction circuit 100 can predict power consumption of the processor 120 based on count values of effective performance parameters among the plurality of performance parameters targeted by the performance monitor 121 to monitor. Here, the effective performance parameters can be previously selected from the plurality of performance parameters so that the power prediction circuit 100 is used to predict power consumption of the processor 120. Accordingly, in some embodiments, the effective performance parameters are pre-selected performance parameters for power consumption prediction, and can be simply referred to as performance parameters.

[0034] In some embodiments, the performance monitor 121 can include a measurement circuit to measure at least one of an operating frequency, an operating voltage, and a temperature of the processor 120 by the measurement circuit, and the power prediction circuit 100 can also predict power consumption of the processor 120 based on a measurement result of the performance monitor 121. However, this is only an embodiment, and the measurement circuit can be implemented as hardware separate from the performance monitor 121. Specific embodiments in this regard will be described below.

[0035] In one embodiment, the number of effective performance parameters can be based on the number of registers supported by the performance monitor 121. For example, when the number of registers supported by the performance monitor 121 is "A" (where A is an integer greater than or equal to 2), the number of effective performance parameters can be less than or equal to "A". Further, as one embodiment, the effective performance parameters can have a correlation degree less than a first threshold value, and have a correlation degree with power consumption of the processor 120 greater than or equal to a second threshold value. Specific embodiments of selecting the effective performance parameters will be described below.

[0036] In one embodiment, the performance monitor 121 can perform a counting operation on an effective performance parameter of the processor 120 through a register to collect a count value of the effective performance parameter, and the power prediction circuit 100 can obtain the count value of the effective performance parameter from the register of the performance monitor 121. In some embodiments, the power prediction circuit 100 can also obtain at least one of an operating frequency, an operating voltage, and a temperature of the processor 120 measured by the performance monitor 121. The power prediction circuit 100 can predict the power consumption of the processor 120 based on the information obtained from the performance monitor 121.

[0037] As one embodiment, the power prediction circuit 100 includes a neural network model 101, and can predict the power consumption of the processor 120 by using the neural network model 101. For example, the power prediction circuit 100 can input the count value of the effective performance parameter to the neural network model 101, and predict the power consumption of the processor 120 based on a value output from the neural network model 101. As one specific example, the output of the neural network model 101 can indicate the predicted power consumption of the processor 120, and the power prediction circuit 100 can confirm the predicted power consumption of the processor 120 through the output of the neural network model 101. The neural network model 101 can be implemented using a CPU, a GPU, an NPU, an ISP, a custom hardware, and / or software.

[0038] In one embodiment, the power prediction circuit 100 can provide information about the predicted power consumption of the processor 120 to the power management unit 110. The power management unit 110 can manage the power supplied to the processor 120 based on the information provided from the power prediction circuit 100.

[0039] Further, as one embodiment, the power prediction circuit 100 can predict a next count value based on the count value of the effective performance parameter, and predict a next power consumption of the processor 120 based on the predicted next count value. As one embodiment, the power management unit 110 can prepare the power to be supplied to the processor 120 based on the power consumption predicted by the power prediction circuit 100. The preparation of the power generally indicates scheduling power, scheduling a restriction of power, or planning power management. Specific embodiments in this regard will be described below.

[0040] Hereinafter, an embodiment in which the effective performance parameter is selected from a plurality of performance parameters is schematically described. In this embodiment, it is assumed that the configuration of the processor 120 is performed in a mass production stage of the SoC 10.

[0041] To monitor the performance of the processor 120, the performance monitor 121 can perform a counting operation on a plurality of performance parameters to generate a count value and store the count value in a register. However, because the number of registers of the performance monitor 121 is limited, the counting operation on a part of the plurality of performance parameters can be simultaneously performed.

[0042] In one embodiment, the number of effective performance parameters can be selected based on the number of registers of the performance monitor 121. That is, for accurate operation of the power prediction circuit 100, it can be important to select the effective performance parameters considering the number of performance parameters that can be simultaneously monitored by the performance monitor 121. In one embodiment, the number of effective performance parameters can correspond to the number of performance parameters that are simultaneously monitored by the performance monitor 121.

[0043] In one embodiment, to select the effective performance parameters, the processor 120 can be controlled by a device. Further, the device can be used to build the neural network model 101. The device can control a plurality of benchmark applications prepared to be sequentially executed by the processor 120, and collect test count values of a plurality of performance parameters generated by the performance monitor 121 in a period in which the plurality of benchmark applications are executed. That is, the effective performance parameters can be selected from among the plurality of performance parameters based on the test count values of the plurality of performance parameters generated by the performance monitor 121 by executing the plurality of benchmark applications through the processor 120. The device can also collect power consumption values of the processor 120 corresponding to the test count values of the plurality of performance parameters. For example, hardware logic for measuring the power consumption of the processor 120 can be provided only in a mass production stage, and the actual power consumption of the processor 120 corresponding to the test count values of the plurality of performance parameters can be measured by the hardware logic. The hardware logic can also be used to build the neural network model 101. In some embodiments, the hardware logic can be removed from the processor 120 or the SoC 10 after the mass production stage.

[0044] Here, the benchmark application can be defined as an application made to allow the processor 120 to repeatedly execute a specific operation in order to confirm a specific performance of the processor 120. For example, the benchmark application can be a dedicated application that confirms any one of an arithmetic and logic unit (ALU) related performance, a memory access related performance, and a comprehensive performance of the processor 120. Further, as one embodiment, the benchmark application can support an execution fixing function. The execution fixing function is applicable even when the processor 120 includes a plurality of cores, and a detailed description thereof will be given below.

[0045] As one embodiment, the device can select an effective performance parameter based on test count values of a plurality of performance parameters (and / or power consumption of the processor 120) obtained from the performance monitor 121. First, the device can generate first information indicating correlation degrees between the plurality of performance parameters based on the test count values. Specifically, the device can generate the first information by analyzing increasing / decreasing patterns of the test count values of the plurality of performance parameters. Thereafter, the device can perform a first filtering on performance parameters having a correlation degree less than a first threshold among the plurality of performance parameters based on the first information. In some embodiments, the device can also confirm the correlation degrees between the plurality of performance parameters using at least one of an operating voltage, an operating frequency, and a temperature of the processor 120 measured by the performance monitor 121.

[0046] In one embodiment, the device can generate second information indicating correlation degrees between count values of the first filtered performance parameters and power consumptions of the processor 120 corresponding to the count values of the first filtered performance parameters. Specifically, the device can generate the second information by analyzing increasing / decreasing patterns of the count values of the first filtered performance parameters and increasing / decreasing patterns of actually measured power consumption values of the processor 120. Thereafter, the device can perform a second filtering on performance parameters each having a correlation degree equal to or greater than a second threshold with the power consumptions of the processor 120 among the first filtered performance parameters based on the second information. The device can select the second filtered performance parameters as effective performance parameters.

[0047] As described above, the effective performance parameters have low mutual correlation degrees and high correlation degrees with the power consumptions of the processor 120, and thus, accuracy of the power consumption prediction operation of the power prediction circuit 100 can be improved.

[0048] Hereinafter, an embodiment in which the neural network model 101 is trained is schematically described. In this embodiment, it is assumed that training is performed for construction of the neural network model 101 in a mass production stage of the SoC 10.

[0049] In one embodiment, the processor 120 can be controlled by an apparatus for constructing the neural network model 101. The apparatus can control a plurality of user applications prepared to be sequentially executed by the processor 120, and collect training count values of a plurality of effective performance parameters generated by the performance monitor 121 in a period in which the plurality of user applications are executed, and use the training count values in training of the neural network model 101. In addition, the apparatus can further collect power consumption values of the processor 120 corresponding to the collected training count values. In one example, the apparatus can train the neural network model 101 based on the training count values and the power consumption values. The power consumption of the processor 120 can be directly measured through the hardware logic described above. In some embodiments, the apparatus can further collect training measurement values of at least one of an operating voltage, an operating frequency, and a temperature of the processor 120 corresponding to the collected training count values, and use the values in training of the neural network model 101. Here, the user application can be defined as an application that can be executed by the user's need after the SoC 10 is mass-produced and mounted on an electronic device.

[0050] In one embodiment, the apparatus can perform first training to generate a preliminarily constructed neural network model 101 based on the collected training count values, the collected power consumption values, and a first loss function. For example, the first loss function can include a mean square error loss function. Thereafter, the apparatus can finally construct the neural network model 101 by performing second training on the neural network model 101 based on a second loss function according to characteristics of the processor 120 in a low power period and / or a high power period. For example, the second loss function can include a system loss function. The second loss function can be a function defined to compensate for a first prediction error occurring based on use of the first loss function in a low power period of the processor 120 and / or a second prediction error occurring based on use of the first loss function in a high power period. Specifically, the first prediction error can be related to the preliminarily constructed neural network model 101 predicting the power consumption of the processor 120 as a negative value in the low power period, and the second prediction error can be related to an amount of training data collected in the high power period of the processor 120 being less than a threshold amount. For example, the mean square error loss function can be defined as [Equation 1], and the system loss function can be defined as [Equation 2].

[0051] [Equation 1] .

[0052] represents a target value, and represents a value of the neural network model 101, and The value can be generated in the first training through an operation of [Equation 1]. For example, J can represent the number of the collected training count values.

[0053] [Equation 2] .

[0054] may be an operation for compensating for the second prediction error in the high-power period, and may be an operation for compensating for the first prediction error in the low-power period. 、 and may be a preset value for effectively compensating for the first prediction error and the second prediction error. Specifically, the second loss function can compensate for a large number of occurrences of the second prediction error in the high-power period, and compensate for the first prediction error in the low-power period due to the predicted power consumption having a negative value. may be a preset value for effectively compensating for the first prediction error and the second prediction error. Specifically, the second loss function can compensate for a large number of occurrences of the second prediction error in the high-power period, and compensate for the first prediction error in the low-power period due to the predicted power consumption having a negative value. denotes a target value, and denotes a value of the neural network model 101, and is used to adjust an artificial intelligence parameter of the neural network model 101 The value can be generated in the second training through the operation of [Equation 2].

[0055] As one embodiment, the finally constructed neural network model 101 can be stored in a memory of the SoC 10, and the neural network model 101 can be driven by the power prediction circuit 100. The neural network model 101 can be used by the power prediction circuit 100 to predict the power consumption of the processor 120.

[0056] The SoC 10 according to the embodiment can accurately predict the power consumption of the processor 120 by using the count value of the effective performance parameter selected from the plurality of performance parameters, without separate hardware logic for measuring the power consumption of the processor 120. Accordingly, since there is no hardware logic for measuring the power consumption, the design space of the processor 120 can be further secured, and the circuit design flexibility of the processor 120 can be improved.

[0057] The SoC 10 according to the embodiment can accurately predict the power consumption of the processor 120 by using the neural network model 101 trained based on the effective performance parameter optimally selected to predict the power consumption of the processor 120 and the loss function considering the characteristics of the processor 120 in the low-power period and / or the high-power period. Based on the prediction result, appropriate power (e.g., power) can be supplied to the processor 120, so that the operating performance of the processor 120 can be improved.

[0058] ​Further, the SoC 10 according to embodiments can determine the power (e.g., power) required for the processor 120 in advance by predicting the next count value based on the count value of the effective performance parameter and predicting the next power consumption of the processor 120 in advance based on the predicted next count value. This can contribute to the overall power management of the SoC 10.

[0059] Figure 2A and Figure 2B is a flowchart for describing a method of predicting the power consumption of a processor of a SoC according to embodiments.

[0060] Referring to Figure 2A In operation S100A, a performance monitor of a processor can perform a counting operation on an effective performance parameter among a plurality of performance parameters of the processor. For example, the performance monitor can simultaneously perform a counting operation on the effective performance parameters by using registers matching the number of the effective performance parameters and store count values generated by the counting operation in the registers. For example, the registers can be assigned to the effective performance parameters one-to-one to store count values of the effective performance parameters assigned to the registers. In some embodiments, at least one of the registers can not be assigned an effective performance parameter and can dynamically store count values of performance parameters requested by any component in the SoC.

[0061] In operation S110A, a power prediction circuit can input the count values of the effective performance parameters to a neural network model. For example, the power prediction circuit can pre-process the count values of the effective performance parameters to conform to an input format of the neural network model. The neural network model of operation S110A can be constructed by training based on training count values of the effective performance parameters.

[0062] In operation S120A, a power management unit can control power supplied to the processor based on an output of the neural network model. For example, the power prediction circuit can transmit the output of the neural network model to the power management unit.

[0063] Further referring to Figure 2B In operation S100B, a performance monitor of a processor can perform a counting operation on an effective performance parameter among a plurality of performance parameters of the processor and perform a measurement operation on the processor. For example, the performance monitor can measure at least one of an operating frequency, an operating voltage, and a temperature of the processor.

[0064] In operation S110B, a power prediction circuit can input the count values of the effective performance parameters and the measurement values to a neural network model. The neural network model in operation S110B can be constructed by training based on training count values of the effective performance parameters, power consumptions of the processor corresponding to the training count values of the effective performance parameters, and training measurement values of at least one of an operating frequency, an operating voltage, and a temperature of the processor.

[0065] In operation S120B, the power management unit can control the power supplied to the processor based on the output of the neural network model.

[0066] Figure 3A and Figure 3B is a block diagram for describing an operation of the power prediction circuit 100 according to an embodiment.

[0067] Referring to Figure 3A , the power prediction circuit 100 can input the count values V_11 to V_K1 of the "K" effective performance parameters VPP_1 to VPP_K as input signals IN to the neural network model 101. The power prediction circuit 100 can predict the power consumption of the processor based on the output signal OUT of the neural network model 101.

[0068] Further referring to Figure 3B , the power prediction circuit 100 can input the count values V_11 to V_K1 of the "K" effective performance parameters VPP_1 to VPP_K and the "N" measurement values V_12 to V_N2 as input signals IN to the neural network model 101. For example, the "N" measurement values V_12 to V_N2 can include measurement values of at least one of an operating frequency, an operating voltage, and a temperature of the processor. The power prediction circuit 100 can predict the power consumption of the processor based on the output signal OUT of the neural network model 101.

[0069] Figure 4 is a flowchart illustrating a method of predicting power consumption of a processor of an SoC according to an embodiment.

[0070] Referring to Figure 4 , in operation S200, a performance monitor of the processor can perform a counting operation on an effective performance parameter among a plurality of performance parameters of the processor.

[0071] In operation S210, a power prediction circuit can input a count value of the effective performance parameter to a first neural network model. Here, the first neural network model denotes a neural network model constructed to predict power consumption of the processor.

[0072] In operation S220, a power management unit can control power supplied to the processor based on a first output of the first neural network model.

[0073] Operation S230 and operation S240 can be performed in parallel with operation S210 and operation S220.

[0074] In operation S230, the power prediction circuit can predict a next count value by inputting the count value of the effective performance parameter to a second neural network model. Here, the second neural network model denotes a neural network model constructed to predict the next count value based on the count value of the effective performance parameter.

[0075] In operation S240, the power prediction circuit can prepare for next power control by inputting the predicted count value (e.g., predicted next count value) to the first neural network model. For example, the power prediction circuit can provide the second output of the first neural network model to the power management unit in response to the input of the predicted count value. The power management unit can prepare to supply power to the processor by previously identifying power (e.g., power) predicted to be required for the processor based on the provided second output. For example, the power management unit can plan power management regarding power to be supplied to the processor based on the predicted next count value.

[0076] Figure 5 is a block diagram for describing an operation of a power prediction circuit 200 according to an embodiment.

[0077] Referring to Figure 5 , the power prediction circuit 200 can input count values V_11 to V_K1 of "K" effective performance parameters VPP_1 to VPP_K as a first input signal IN1 to each of the first neural network model 201 and the second neural network model 202.

[0078] The first neural network model 201 can output a first output signal OUT1 in response to the count values V_11 to V_K1, and the power prediction circuit 200 can predict a current power consumption of the processor based on the first output signal OUT1.

[0079] The second neural network model 202 can output predicted count values EV_11 to EV_K1 of the "K" effective performance parameters VPP_1 to VPP_K in response to the count values V_11 to V_K1. The predicted count values EV_11 to EV_K1 can be input as a second input signal IN2 to the first neural network model 201.

[0080] The first neural network model 201 can output a second output signal OUT2 in response to the predicted count values EV_11 to EV_K1, and the power prediction circuit 200 can predict a next power consumption of the processor based on the second output signal OUT2.

[0081] The power prediction circuit 200 can continuously predict the power consumption of the processor by inputting the predicted count values EV_11 to EV_K1 to the second neural network model 202, further generating future predicted count values, and inputting the future predicted count values to the first neural network model 201.

[0082] Figure 6 is a diagram for describing a method of operating an SoC according to an embodiment. To help understanding Figure 6 , further described with reference to Figure 5 ​Figure 6 .

[0083] Referring Figure 6 , the power prediction circuit 200 can predict the power consumption of the processor in the first power control period based on the first count value of the effective performance parameter generated through the first count operation at the "T1" time. For example, the power prediction circuit 200 can continuously generate the predicted count value for predicting the power consumption of the processor in the first power control period by using the first count value and the second neural network model 202. As one specific example, the power prediction circuit 200 can predict the power consumption of the processor in the first power control period by generating other predicted count values with predicted count values by re-inputting the output of the second neural network model 202 into the second neural network model 202. In the first power control period corresponding to the first count operation, the power management unit can receive information about the power consumption of the processor predicted by the power prediction circuit 200 and manage the power supplied to the processor.

[0084] The power prediction circuit 200 can predict the power consumption of the processor in the second power control period based on the second count value of the effective performance parameter generated through the second count operation at the "T2" time. In some embodiments, the power prediction circuit 200 can compare the count value last predicted in the first power control period with the second count value and adjust the length of the second power control period based on the comparison result. For example, the power prediction circuit 200 can continuously generate the predicted count value for predicting the power consumption of the processor in the second power control period by using the second count value and the second neural network model 202. In the second power control period corresponding to the second count operation, the power management unit can receive information about the power consumption of the processor predicted by the power prediction circuit 200 and manage the power supplied to the processor.

[0085] The power prediction circuit 200 can predict the power consumption of the processor in the third power control period based on the third count value of the effective performance parameter generated through the third count operation at the "T3" time. In some embodiments, the power prediction circuit 200 can compare the count value last predicted in the second power control period with the third count value and adjust the length of the third power control period based on the comparison result. For example, the power prediction circuit 200 can continuously generate the predicted count value for predicting the power consumption of the processor in the third power control period by using the third count value and the second neural network model 202. In the third power control period corresponding to the third count operation, the power management unit can receive information about the power consumption of the processor predicted by the power prediction circuit 200 and manage the power supplied to the processor.

[0086] Figure 7A and Figure 7Bis a block diagram illustrating a processor 300 according to an embodiment.

[0087] Referring to Figure 7A The processor 300 can include a first core cluster 310_1 and a performance monitor 320. The first core cluster 310_1 can include first through Mth cores 310_11 through 310_1M (where M is an integer of 2 or more). The performance monitor 320 can include first performance monitoring circuitry 321 including first through Mth performance monitoring counters 321_1 through 321_M. For example, the first and Mth performance monitoring counters 321_1 and 321_M can each include "L" registers REG_11 through REG_L1 and REG_1M through REG_LM. Each of the second through M-1th performance monitoring counters 321_2 through 321_M-1 can also include "L" registers. The first through Mth cores 310_11 through 310_1M can correspond one-to-one with the first through Mth performance monitoring counters 321_1 through 321_M.

[0088] In one embodiment, power can be managed in units of core clusters, and thus, an effective performance parameter can be selected in units of core clusters. That is, a first effective performance parameter can be selected from among a plurality of performance parameters in order to predict power consumption of the first core cluster 310_1. However, embodiments are not limited thereto, and the disclosure can be applied even in a condition that power is managed in units of cores and an effective performance parameter is selected in units of cores.

[0089] In one embodiment, in order to predict power consumption of the first core cluster 310_1, the first performance monitoring counter 321_1 can perform a counting operation on the first effective performance parameter of the first core 310_11. The first performance monitoring counter 321_1 can store a count value of the first effective performance parameter of the first core 310_11 in the "L" registers REG_11 through REG_L1 at a time. As such, the second through Mth performance monitoring counters 321_2 through 321_M can perform counting operations on the first effective performance parameters of the second through Mth cores 310_12 through 310_1M. In one embodiment, the count values stored in the first through Mth performance monitoring counters 321_1 through 321_M can be provided to a power prediction circuit, and the power prediction circuit can predict power consumption of the first core cluster 310_1 based on the provided count values. For example, the power prediction circuit can sum or average (or perform a neural network operation) the count values provided from the first through Mth performance monitoring counters 321_1 through 321_M, and predict power consumption of the first core cluster 310_1 based on the calculation result.

[0090] In one embodiment, the first performance monitoring counters 321_1 to the Mth performance monitoring counters 321_M can be used to select the first effective performance parameter in a mass production phase of the SoC and can be used to build a neural network model for predicting the power consumption of the first core cluster 310_1.

[0091] With further reference to Figure 7B , the first performance monitoring circuit 321 can further include a measurement circuit 321_(M+1) for measuring at least one of an operating frequency, an operating voltage, and a temperature of the first core cluster 310_1. In some embodiments, the measurement circuit 321_(M+1) can be implemented as hardware separate from the performance monitor 320.

[0092] As one embodiment, the measurement values generated by the measurement circuit 321_(M+1) can be additionally used to predict the power consumption of the first core cluster 310_1. Further, in one embodiment, the measurement values generated by the measurement circuit 321_(M+1) can be additionally used to select the first effective performance parameter in a mass production phase of the SoC and can be additionally used to build a neural network model for predicting the power consumption of the first core cluster 310_1.

[0093] Figure 8 is a block diagram illustrating a processor 400 according to an embodiment.

[0094] With reference to Figure 8 , the processor 400 can include first to third core clusters 410_1 to 410_3 and a performance monitor 420. The performance monitor 420 can include first to third performance monitoring circuits 421 to 423. The first performance monitoring circuit 421 can be a circuit for monitoring performance of the first core cluster 410_1, the second performance monitoring circuit 422 can be a circuit for monitoring performance of the second core cluster 410_2, and the third performance monitoring circuit 423 can be a circuit for monitoring performance of the third core cluster 410_3.

[0095] In one embodiment, a first effective performance parameter can be selected for predicting the power consumption of the first core cluster 410_1, a second effective performance parameter can be selected for predicting the power consumption of the second core cluster 410_2, and a third effective performance parameter can be selected for predicting the power consumption of the third core cluster 410_3.

[0096] In one embodiment, the first performance monitoring circuit 421 can perform a counting operation on the first effective performance parameter of the first core cluster 410_1 to generate a count value of the first effective performance parameter, and the power prediction circuit can predict the power consumption of the first core cluster 410_1 based on the count value of the first effective performance parameter.

[0097] In one embodiment, the second performance monitoring circuit 422 can perform a counting operation on the second effective performance parameter of the second core cluster 410_2 to generate a count value of the second effective performance parameter, and the power prediction circuit can predict the power consumption of the second core cluster 410_2 based on the count value of the second effective performance parameter.

[0098] In addition, in one embodiment, the third performance monitoring circuit 423 can perform a counting operation on the third effective performance parameter of the third core cluster 410_3 to generate a count value of the third effective performance parameter, and the power prediction circuit can predict the power consumption of the third core cluster 410_3 based on the count value of the third effective performance parameter.

[0099] In one embodiment, the first core cluster 410_1 to the third core cluster 410_3 can be designed to have different data processing speeds (or performance parameters). For example, the first core cluster 410_1 can be designed as a large core cluster, the second core cluster 410_2 can be designed as a medium core cluster, and the third core cluster 410_3 can be designed as a small core cluster. In this case, the first effective performance parameter to the third effective performance parameter can be different from each other. Specifically, because the first core cluster 410_1 to the third core cluster 410_3 are designed differently, the best effective performance parameter for predicting the power consumption of the first core cluster 410_1 to the third core cluster 410_3 can be different. Accordingly, at least one of the first effective performance parameter can be different from any one of the second effective performance parameter and any one of the third effective performance parameter. However, this is only an embodiment, and is not limited thereto, and the second effective performance parameter of the second core cluster 410_2 and the third effective performance parameter of the third core cluster 410_3 can be selected with respect to the first core cluster 410_1, and thus, the first effective performance parameter to the third effective performance parameter can be the same.

[0100] Figure 9 is a flowchart illustrating a method of an apparatus of operating to construct a neural network model for predicting power consumption of a processor according to an embodiment.

[0101] Referring to Figure 9 In operation S300, the apparatus can select an effective performance parameter from a plurality of performance parameters of a processor. For example, the apparatus can construct a preliminary data set including operating frequencies, operating voltages, temperatures, and power consumptions of the processor and count values of the plurality of performance parameters in a period in which the processor executes a plurality of benchmark applications. The apparatus can select an effective performance parameter having a low cross-correlation and a high correlation with the power consumption of the processor based on the preliminary data set.

[0102] In operation S310, the device can construct a data set matching the effective performance parameter selected in operation S300. For example, the device can construct a data set including the training count values of the effective performance parameter in the period in which the processor executes the plurality of user programs. In some embodiments, the device can include the measured values of at least one of the operating frequency, operating voltage, and temperature of the processor in the data set in the period in which the processor executes the plurality of user programs.

[0103] In operation S320, the device can train the neural network model based on the training count values of the data set constructed in operation S310 and the characteristics of the processor in the low-power period and / or the high-power period. In some embodiments, the device can also train the neural network model using the measured values of at least one of the operating frequency, operating voltage, and temperature of the processor.

[0104] Figure 10 is a flowchart for describing a specific embodiment of operation S300 of Figure 9 .

[0105] Referring to Figure 10 , in operation S301, the device can start the operation of selecting the effective performance parameter by setting "W" to 1.

[0106] In operation S302, the device can execute the Wth reference application through the processor.

[0107] In operation S303, the device can periodically collect the training count values of the plurality of performance parameters by using the performance monitor of the processor and periodically collect the power consumption values of the processor by using the hardware logic in the period in which the Wth reference application is executed through the processor. As described above, the hardware logic is limitedly used in the mass production stage of the SoC for selecting the effective performance parameter and training the neural network model, and can be removed from the processor in the future.

[0108] In operation S304, the device can determine whether "W" reaches "X" (where X is an integer greater than or equal to 1). "X" can represent the total number of reference applications for selecting the effective performance parameter.

[0109] When operation S304 is "No", operation S305 follows, and the device can count up "W" and repeat operations S302 to S304.

[0110] When operation S304 is "Yes", operation S306 follows, and the device can select the effective performance parameter from among the plurality of performance parameters based on the collected training count values and power consumption values.

[0111] Figure 11 is a flowchart for describing a specific embodiment of operation S300 of Figure 10a flowchart of a specific embodiment of operation S306.

[0112] Referring to Figure 11 In operation S306_1, the device can perform a first filtering operation on the plurality of performance parameters based on a correlation between the plurality of performance parameters. For example, the device can generate first information indicating a degree of correlation between the performance parameters by analyzing the training count values of the plurality of performance parameters. The device can perform the first filtering operation based on the generated first information, such that only performance parameters having a degree of cross-correlation less than a first threshold value among the plurality of performance parameters are retained.

[0113] In operation S306_2, the device can perform a second filtering operation on the plurality of performance parameters based on a correlation between the first filtered performance parameters and power consumption. For example, the device can generate second information indicating a degree of correlation between the first filtered performance parameters and power consumption of the processors corresponding to the first filtered performance parameters. The device can perform the second filtering operation based on the generated second information, such that only performance parameters each having a degree of correlation with power consumption greater than or equal to a second threshold value among the first filtered performance parameters are retained. Thereafter, the device can select the second filtered performance parameters as effective performance parameters.

[0114] Figure 12 is a diagram for describing a method of selecting effective performance parameters according to an embodiment. In Figure 12 In operation S306_1, the device can perform a first filtering operation on the plurality of performance parameters based on a correlation between the plurality of performance parameters. For example, the device can generate first information indicating a degree of correlation between the performance parameters by analyzing the training count values of the plurality of performance parameters. The device can perform the first filtering operation based on the generated first information, such that only performance parameters having a degree of cross-correlation less than a first threshold value among the plurality of performance parameters are retained.

[0115] Referring to Figure 12As a first step STEP 1, the apparatus can periodically collect count values of a plurality of performance parameters PP of the first core to the fourth core from the first performance monitoring circuit to the fourth performance monitoring circuit of the first core to the fourth core during a period of time from "T11" time to "TG1" time (e.g., a period of time during which a plurality of benchmark applications are executed by the processor), collect measurement values of a measurement parameter MP of the core cluster from the measurement circuit during the period of time from "T11" time to "TG1" time, and generate a first table TB_C1 to a fourth table TB_C4 in the period of time during which the plurality of benchmark applications are executed by the processor. The first table TB_C1 to the fourth table TB_C4 can be the preliminary data set described above. For example, the plurality of performance parameters PP can include a first performance parameter PP_1 to a Qth performance parameter PP_Q (where Q is an integer of 2 or more). Also, for example, the measurement parameter MP can include a first parameter F, a second parameter V, and a third parameter T related to an operating frequency, an operating voltage, and a temperature, and a fourth parameter PO related to power consumption. In some embodiments, the first parameter F, the second parameter V, and the third parameter T can be omitted from the first table TB_C1 to the fourth table TB_C4. As described above, the plurality of benchmark applications can support execution of a fixed function with respect to the first core to the fourth core. For example, a benchmark application can be fixed to the first core and executed, and thus, execution of the benchmark application can be completed in the first core.

[0116] As one embodiment, as a second step STEP 2, the apparatus can use a 'Pearson' correlation coefficient method as a method of obtaining a correlation degree (or a correlation value) to clearly identify a correlation degree between the plurality of performance parameters PP. The apparatus can convert the first table TB_C1 to the fourth table TB_C4 into first data p indicating a correlation degree between the plurality of performance parameters PP of each core based on the 'Pearson' correlation coefficient method.

[0117] In one embodiment, as a third step STEP 3, the apparatus can convert the first data p into second data h based on a 'Fisher' conversion method. Specifically, because correlation coefficients of performance parameters of all cores need to be considered to select an effective performance parameter, values of the correlation coefficients listed in three dimensions can be converted into two dimensions through an arithmetic operation. In order to perform an arithmetic operation on the values of the correlation coefficients, although the values need to follow a normal distribution, because the values of the correlation coefficients do not follow a normal distribution, it can be necessary to convert into the second data h using the 'Fisher' conversion method to perform an averaging operation on the values of different correlation coefficients.

[0118] In one embodiment, as a fourth step STEP4, the device can convert the second data h into third data h_avg by performing an "Element-wise" average operation. The device can convert the third data h_avg into fourth data based on a "Reverse Fisher" conversion method. The fourth data can correspond to the first information described above for the first screening. In one example, the first information can be generated based on a "Pearson" correlation coefficient method and a "Fisher" conversion method.

[0119] In one embodiment, as a fifth step STEP5, the device can remove the performance parameter having a correlation degree greater than or equal to a first threshold. For example, when the first threshold is set to "0.8", the device can remove the first performance parameter PP_1 having a correlation degree of "0.9" with each of the second performance parameter PP_2 and the third performance parameter PP_3. As such, by repeating the removal operation, only the performance parameters having a cross-correlation degree less than the first threshold can be retained. In this regard, the retained performance parameters can be referred to as the first-screened performance parameters PP'.

[0120] In one embodiment, as a sixth step STEP6, the device can generate fifth data by extracting a portion corresponding to the first-screened performance parameters PP' from the first table TB_C1 to the fourth table TB_C4.

[0121] In one embodiment, as a seventh step STEP7, the device can generate sixth data by summing (or averaging) the count values for each of the cores CORE based on the fifth data for each of the times TIME and for each of the first-screened performance parameters PP' and merging the summed (or averaged) results with the measured values of the measured parameters MP of the first table TB_C1 to the fourth table TB_C4 for each of the times TIME.

[0122] In one embodiment, as an eighth operation STEP8, the device can generate seventh data in which the correlation degrees between the first-screened performance parameters PP' and the power consumption of the processor are arranged in order of magnitude based on the sixth data. The device can retain only the performance parameters each having a correlation degree with the power consumption greater than or equal to a second threshold among the first-screened performance parameters PP' based on the seventh data. The retained performance parameters can be referred to as second-screened performance parameters or valid performance parameters VPP. The seventh data can correspond to the second information described above for the second screening.

[0123] In one embodiment, as a ninth step STEP9, the device can construct a data set for training a neural network model based on the valid performance parameters VPP.

[0124] Figure 13 is a flowchart for describing a specific embodiment of operation S310 of Figure 9

[0125] Referring to Figure 13 , in operation S311, the device can start the operation of constructing the dataset by setting "Y" to 1.

[0126] In operation S312, the device can execute the Yth user application. In operation S313, the device can periodically collect the training count value of the effective performance parameter by using the performance monitor of the processor and periodically collect the power consumption value of the processor by using the hardware logic in a period in which the Yth user application is executed by the processor.

[0127] In operation S314, the device can determine whether "Y" reaches "Z" (where Z is an integer greater than or equal to 1). "Z" can represent the total number of user applications for constructing the neural network model.

[0128] When operation S314 is "No", operation S315 follows, and the device can count up "Y" and repeat operations S312 to S314.

[0129] When operation S314 is "Yes", operation S316 follows, and the device can complete the construction of the dataset. The device can train the neural network model based on the training count value of the effective performance parameter included in the dataset and the power consumption value of the processor corresponding to the training count value of the effective performance parameter.

[0130] Figure 14 is a flowchart for describing a specific embodiment of operation S320 of Figure 9

[0131] Referring to Figure 14 , in operation S321, the device can perform first training of the neural network model based on a first loss function. For example, the device can perform the first training of the neural network model by using the dataset constructed in operation S310 and the first loss function. As a result of performing the first training, the neural network model can be initially constructed. Figure 13

[0132] In operation S322, the device can perform second training of the neural network model based on a second loss function for compensating for a prediction error of the initially constructed neural network model in a low-power period and / or a high-power period. As a result of performing the second training, the neural network model can be finally constructed.

[0133] Figure 15 is a block diagram illustrating an SoC 1000 according to an embodiment. ​​​

[0134] Referring to Figure 15 The SoC 1000 can include a power prediction circuit 1010, a power management unit 1020, a CPU 1030, an NPU 1040, a GPU 1050, a timer 1060, an internal memory 1070, a memory controller 1080, a display controller 1090, a clock management unit 1100, and a bus 1110.

[0135] In one embodiment, the CPU 1030 can include a performance monitor 1031, and can process or execute programs and / or data stored in an external memory 1081 through the memory controller 1080.

[0136] As one embodiment, the NPU 1040 includes a performance monitor 1041, and can efficiently process large-scale operations using a neural network. The NPU 1040 can perform deep learning by supporting simultaneous matrix operations.

[0137] In one embodiment, the GPU 1050 includes a performance monitor 1051, and can convert data read from the external memory 1081 through the memory controller 1080 into a signal suitable for a display device 1091. In some embodiments, the GPU 1050 can also support simultaneous matrix operations for deep learning.

[0138] In one embodiment, the power prediction circuit 1010 can predict power consumptions of the CPU 1030, the NPU 1040, and the GPU 1050. As one specific example, the power prediction circuit 1010 can receive a count value of a first effective performance parameter from the performance monitor 1031 of the CPU 1030, and predict a power consumption of the CPU 1030 based on the received count value and a neural network model 1011. The power prediction circuit 1010 can receive a count value of a second effective performance parameter from the performance monitor 1041 of the NPU 1040, and predict a power consumption of the NPU 1040 based on the received count value and the neural network model 1011. In addition, the power prediction circuit 1010 can receive a count value of a third effective performance parameter from the performance monitor 1051 of the GPU 1050, and can predict a power consumption of the GPU 1050 based on the received count value and the neural network model 1011.

[0139] In one embodiment, the CPU 1030, the NPU 1040, and the GPU 1050 can have different design approaches and different supported performance parameters due to different purposes and operations. Accordingly, the first to third effective performance parameters can be different from each other. As one specific example, at least one of the first effective performance parameters of the CPU 1030 can be different from any one of the second effective performance parameters of the NPU 1040 and any one of the third effective performance parameters of the GPU 1050.

[0140] Further, the neural network model 1011 can include first to third sub-neural network models trained and constructed for each of the CPU 1030, the NPU 1040, and the GPU 1050. As one specific example, the first sub-neural network model can be used to predict power consumption of the CPU 1030, the second sub-neural network model can be used to predict power consumption of the NPU 1040, and the third sub-neural network model can be used to predict power consumption of the GPU 1050.

[0141] The timer 1060 can output a value indicating time based on an operation clock signal output from the clock management unit 1100.

[0142] The display device 1091 can display an image signal output from the display controller 1090. For example, the display device 1091 can be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, or a flexible display. The display controller 1090 can control an operation of the display device 1091.

[0143] The internal memory 1070 can include a random access memory (RAM) that temporarily stores programs (or applications), data, or instructions.

[0144] The memory controller 1080 can communicate with the external memory 1081 through an interface. The memory controller 1080 can control overall operation of the external memory 1081 and control exchange of data between any one of the CPU 1030, the NPU 1040, and the GPU 1050 and the external memory 1081.

[0145] The clock management unit 1100 can generate an operation clock signal and provide the operation clock signal to any one of the CPU 1030, the NPU 1040, and the GPU 1050. The clock management unit 1100 can include a clock signal generation device such as a phase-locked loop, a delay-locked loop, or a crystal oscillator.

[0146] The power management unit 1020, the CPU 1030, the NPU 1040, the GPU 1050, the timer 1060, the internal memory 1070, the memory controller 1080, the display controller 1090, and the clock management unit 1100 can communicate with each other via a bus 1110.

[0147] Figure 16 is a block diagram illustrating an electronic device according to an embodiment.

[0148] Referring to Figure 16 , the electronic device can include a SoC 2000, a camera module 2100, a display 2200, a power supply 2300, an input / output (I / O) port 2400, a memory 2500, a storage 2600, an external memory 2700, and a network device 2800.

[0149] As one embodiment, the SoC 2000 can predict power consumption of a processor based on a count value of an effective performance parameter of the processor included in the SoC 2000. Furthermore, the SoC 2000 can predict the power consumption of the processor by using a neural network model optimized for predicting the power consumption of the processor.

[0150] The camera module 2100 represents a module capable of converting a light image into an electric image. Accordingly, the electric image output from the camera module 2100 can be stored in the storage 2600, the memory 2500, or the external memory 2700. Furthermore, the electric image output from the camera module 2100 can be displayed through the display 2200.

[0151] The display 2200 can display data output from the storage 2600, the memory 2500, the I / O port 2400, the external memory 2700, or the network device 2800.

[0152] The power supply 2300 can supply an operating voltage to at least one of the components. The power supply 2300 can be controlled by the power management unit 110 shown in Figure 1

[0153] The I / O port 2400 represents a port capable of transmitting data to or from an external device. For example, the I / O port 2400 can be a port for connecting a pointing device such as a computer mouse, a port for connecting a printer, or a port for connecting a USB drive.

[0154] ​The memory 2500 can be implemented as a volatile memory or a non-volatile memory. According to an embodiment, a memory controller capable of controlling data access operations (e.g., read operations, write operations (or program operations), or erase operations) of the memory 2500 can be integrated into or embedded in the SoC 2000. According to another embodiment, the memory controller can be implemented between the SoC 2000 and the memory 2500.

[0155] The storage 2600 can be implemented as a hard disk drive or a solid state drive (SSD).

[0156] The external memory 2700 can be implemented as a secure digital (SD) card or a multimedia card (MMC). According to an embodiment, the external memory 2700 can be a subscriber identity module (SIM) card or a universal subscriber identity module (USIM) card.

[0157] The network device 2800 represents a device capable of connecting an electronic device to a wired network or a wireless network.

[0158] While the embodiments have been particularly shown and described, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A system on a chip, comprising: a first processor comprising a first performance monitor configured to perform monitoring of a plurality of first performance parameters including a first performance parameter; a power prediction circuit configured to predict the power consumption of the first processor based on a first count value of the first performance parameter collected by the first performance monitor; as well as The power management circuit is configured to manage power supplied to the first processor based on a prediction result of the power prediction circuit.

2. The system on chip according to claim 1, wherein: The number of the first performance parameters is based on a number of registers supported by the first performance monitor.

3. The system on chip according to claim 1, wherein: The first performance parameter has a mutual correlation less than a first threshold and has a correlation with the power consumption of the first processor greater than or equal to a second threshold.

4. The system on chip according to claim 1, wherein: The first performance parameter is selected from among the plurality of first performance parameters based on test count values ​​of the plurality of first performance parameters, the test count values ​​of the plurality of first performance parameters being generated by a first performance monitor by executing a plurality of benchmark applications via a first processor.

5. The system on chip according to claim 4, wherein: The first performance parameter is selected by performing a first screening on the plurality of first performance parameters based on first information indicating a first correlation between the plurality of first performance parameters generated based on a test count value, and performing a second screening on the plurality of first performance parameters after the first screening based on second information indicating a second correlation between the test count values ​​of the plurality of first performance parameters after the first screening and the power consumption of the first processor.

6. The system on chip according to claim 5, wherein: The first information is generated based on the Pearson correlation coefficient method and the Fisher transformation method.

7. The system on chip according to claim 1, wherein: The first performance monitor is further configured to measure at least one of an operating frequency, an operating voltage, and a temperature of the first processor, and The power prediction circuit is further configured to predict the power consumption of the first processor based on the measurement result of the first performance monitor.

8. The system on chip according to claim 1, wherein: The power prediction circuit is configured to predict the power consumption of the first processor based on a value output from the first neural network model by inputting the first count value of the first performance parameter to the first neural network model.

9. The system on chip according to claim 8, wherein: The first neural network model is trained based on second count values ​​of the first performance parameter, and the second count values ​​are generated by the first performance monitor by executing a plurality of user applications via the first processor.

10. The system on chip according to claim 9, wherein: The first neural network model is constructed by sequentially performing a first training operation based on a first loss function and a second training operation based on a second loss function according to characteristics of the first processor in a low power period and / or a high power period.

11. The system on chip according to claim 10, wherein: The first loss function includes a mean square error loss function, and The second loss function includes a system loss function.

12. The system on chip according to claim 1, wherein: The power prediction circuit is further configured to: predict a next count value based on the first count value of the first performance parameter, and predict a next power consumption of the first processor based on the predicted next count value, and The power management circuit is further configured to plan power management regarding power to be supplied to the first processor based on a prediction result of the power prediction circuit regarding next power consumption.

13. The system on chip according to claim 12, wherein: The power prediction circuit is configured to predict next power consumption of the first processor based on a value output from the first neural network model by inputting the predicted next count value to the first neural network model.

14. The system on chip according to claim 1, wherein: The first processor includes a first core cluster, the first core cluster includes a plurality of first cores, The first performance monitor includes a plurality of first performance monitoring counters, the plurality of first performance monitoring counters being configured to monitor first-first performance parameters of the plurality of first cores, and The first count value of the first performance parameter includes first-first count values ​​of the first-first performance parameter corresponding to the plurality of first cores.

15. The system on chip according to claim 14, wherein: The first processor also includes a second core cluster, the second core cluster includes a plurality of second cores, The first performance monitor further includes a plurality of second performance monitoring counters, wherein the plurality of second performance monitoring counters are configured to monitor the second-first performance parameters of the plurality of second cores, and The first count value of the first performance parameter further includes a second-first count value of a second-first performance parameter corresponding to the plurality of second cores.

16. The system on chip according to claim 15, wherein: The first core cluster includes a different core cluster than the second core cluster, and At least one of the first-first performance parameters corresponding to the plurality of first cores is different from any one of the second-first performance parameters corresponding to the plurality of second cores.

17. The system on chip according to claim 1, further comprising: a second processor, the second processor including a second performance monitor configured to monitor a plurality of second performance parameters including a second performance parameter, The power prediction circuit is further configured to predict a second power consumption of the second processor based on a second count value of the second performance parameter collected by a second performance monitor, and The power management circuit is further configured to manage power supplied to the second processor based on a prediction result of the power prediction circuit on the second processor.

18. The system on chip according to claim 17, wherein: The first processor is different from the second processor, and Wherein, at least one of the first performance parameters is different from any one of the second performance parameters.

19. A method of operating a computing device for generating a neural network model for predicting power consumption of a processor, the method comprising: performing a first counting operation on a plurality of performance parameters of the processor and a first measuring operation on power consumption of the processor during a first time period, wherein a plurality of benchmark applications are executed by the processor; selecting a first performance parameter from among the plurality of performance parameters based on a first result of the first counting operation and based on a second result of the first measuring operation; performing a second counting operation on the first performance parameter of the processor and a second measuring operation on the power consumption of the processor in a second time period, wherein a plurality of user applications are executed by the processor; as well as The neural network model is trained based on the third result of the second counting operation and based on the fourth result of the second measuring operation.

20. A method of operating a system on chip for managing power supplied to a processor, the method comprising: collecting count values ​​of performance parameters among a plurality of performance parameters of the processor; Predicting processor power consumption based on count values ​​and neural network models; as well as Power supplied to the processor is controlled based on the prediction result.

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