A high-speed high-precision timing generator
By integrating internal memory and a two-stage delay adjustment structure, a high-speed, high-precision timing generator is developed, which solves the problems of signal stability and power consumption in high-frequency, high-precision testing, and achieves stable transmission of high-speed signals and low-power design.
Patent Information
- Application Number
- CN202511360999.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2045-09-23
AI Technical Summary
Existing technologies struggle to achieve stable high-speed signal transmission in high-frequency and high-precision semiconductor testing, and there is a trade-off between power consumption and design complexity, with communication interface bandwidth limiting the operating speed.
It employs a high-speed, high-precision timing generator, integrates internal memory to pre-store vector data, adjusts edge positioning in real time through a digital control module, and combines coarse and fine adjustment delay units to achieve picosecond-level time resolution. An edge merging circuit is introduced for efficient merging output.
It achieves stable transmission of high-speed signals, reduces design complexity and energy consumption, meets high-precision testing requirements, and improves output vector rate and system compatibility.
Smart Images
Figure CN120850915B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a high-speed, high-precision timing generator. Background Technology
[0002] Timing generators are a core module of automated test equipment, primarily used to provide high-precision timing stimuli and measurement benchmarks for the chip under test (DUT), performing memory testing (such as DDR and LPDDR), system-on-a-chip (SoC) testing, and functional testing of general-purpose logic chips. With the continuous evolution of semiconductor processes, chip operating frequencies are constantly increasing, interface standards are becoming increasingly complex, and the requirements for test accuracy are also rising. This necessitates that timing generators not only achieve gigahertz (GHz) level vector output rates but also possess sub-nanosecond or even picosecond level edge resolution capabilities to ensure the accuracy and reliability of test results. Therefore, the development of high-speed, high-precision timing generators has become particularly important.
[0003] Currently, many test systems still rely on general-purpose FPGAs for timing control and edge generation, replacing dedicated timing generators. While this approach offers significant advantages in flexibility and development cost, its operating speed, edge accuracy, and jitter performance are often limited by the logic delays and clock management capabilities within the FPGA, making it difficult to meet the stringent requirements of high-speed interface or precision circuit testing. Therefore, as semiconductor testing enters a phase of higher bandwidth and smaller time resolution, the demand for dedicated timing generator chips is becoming increasingly urgent. However, the research and development of dedicated timing generator chips faces several technical challenges. First, achieving picosecond-level time resolution makes circuit design extremely sensitive to device mismatch, temperature drift, and power supply noise. Key units, under deep submicron processes, are limited by process fluctuations, non-ideal effects, and power consumption constraints, making it difficult to balance high accuracy and low power consumption. Second, while finely adjusting resolution, it is necessary to ensure the stability of high-speed signal transmission and reduce signal attenuation and jitter degradation, which often exacerbates overhead in terms of power consumption, area, and design complexity. Furthermore, timing generator operation requires a large amount of control data, which must be transmitted in real-time via a communication interface, and its operating speed is strictly limited by the communication interface data rate. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides a high-speed, high-precision timing generator that can improve the output vector rate while effectively reducing circuit design complexity and energy consumption, achieving a balance between high speed and low power consumption.
[0005] The present invention provides a high-speed, high-precision timing generator, comprising:
[0006] The communication interface receives external data DATA at its first input terminal and outputs synchronization data D through its first output terminal. SYNThe second output terminal of the synchronization module outputs vector data D. PAT The calibration data D is output to the transmitter's memory and the third output terminal. CAL The second input terminal reads data D from the receiver's memory, which is then sent to the calibration memory. SAMP ;
[0007] The clock generation module multiplies the input reference signal REF and provides the clock signal CLK to the digital control module, the transmitting edge positioning module, and the receiving edge positioning module.
[0008] The synchronization module receives the externally input clock signal SYN and synchronizes the data D. SYN Under the control of [the system], a start signal SU is generated during a specified counting period;
[0009] The digital control module receives a start signal SU from the synchronization module at its first input terminal, a clock signal CLK from the clock generation module at its second input terminal, and vector information M from the first output terminal of the transmitting end memory at its third input terminal. PAT The fourth input terminal receives the edge information M sent by the second output terminal of the transmitting end memory. Period The fifth input terminal receives calibration information M sent by the calibrator. CAL The sixth input terminal receives the D signal sent by the sampling circuit. CMP The sampling signal M is sent through the first output terminal. SAMP The second output terminal sends the period control word CW to the receiver's memory. PE The period control word CW is transmitted from the first input terminal and the third output terminal of the transmitting edge positioning module. SE The data control word CW is transmitted from the first input terminal and the fourth output terminal of the edge positioning module at the receiving end. DATA The first input terminals of the transmitting end edge combining module and the receiving end edge combining module are respectively connected to the first input terminal of the transmitting end edge combining module;
[0010] The transmitting edge positioning module, in the periodic control word CW PE Under its influence, the input clock signal CLK is delayed accordingly, and the PE signal is output to the edge merging module at the transmitting end.
[0011] The transmitting edge combining module, based on PE and CW DATA Generate high-speed vector PAT;
[0012] The receiver edge positioning module, in the periodic control word CW SE Under its influence, the input clock signal CLK is delayed accordingly, and the SE signal is output to the edge merging module at the receiving end.
[0013] The receiver edge combining module, based on SE and CW DATAGenerate a sampling clock SAMP to control the sampling circuit to sample the externally input comparison signal CMP;
[0014] The sampling circuit will sample the result D. CMP The sampled signal M is sent to the digital control module; the digital control module then processes the sampled signal M. SAMP Stored in the receiver's memory.
[0015] Furthermore, the digital control module includes,
[0016] The counter counts based on the received start signal SU and clock signal CLK, and sends the counting result CNT to the state machine;
[0017] The state machine has its first output terminal R / D connected to the first input terminal for storage read / write, and its second output terminal PG connected to the first input terminal for periodic synthesis.
[0018] Storage read / write, which reads edge information M from the transmitter's memory. Period Vector information M PAT and sampling results D CMP Generate vector data control word CW DATA CW MEM and sampling information M SAMP ;
[0019] Periodic synthesis generates the periodic control word CW used for delays in the transmitting and receiving edge positioning modules. PE and CW SE The signal PE or SE is a multiple of the synthesis period reference clock CLK.
[0020] Furthermore, both the transmitting end edge positioning module and the receiving end edge positioning module are composed of m identical edge positioning units. The first input terminals of the m edge positioning units are interconnected, serving as clock input terminals CLK; the i-th edge positioning unit is based on the CW output by the digital control module. PE or CW SE The clock signal CLK is delayed, and the output signal PE or SE is generated, where 1 ≤ i ≤ m.
[0021] Furthermore, the edge positioning unit includes a delay coarse adjustment module and a delay fine adjustment module, wherein,
[0022] The first input terminal of the delay coarse adjustment module is connected to the clock input CLK of the edge positioning unit, and the second input terminal is connected to CW. PE or CW SE Its output is connected to the first input DA,DB of the delay fine-tuning module;
[0023] The second input of the delay fine-tuning module is connected to the digital control signal CW. PE or CW SE The output terminal is connected to the output PE or SE of the edge positioning unit.
[0024] Furthermore, the delay coarse adjustment module includes a delay-locked loop, X identical delay coarse adjustment units, and a multiplexer (MUX);
[0025] The input of the delay-locked loop is connected to the clock signal CLK, and the first input of the first coarse adjustment unit is connected to the CLK signal; the output of each coarse adjustment unit is connected to the first input of the next coarse adjustment unit, and the second input of each coarse adjustment unit is connected to the clock Vc of the delay-locked loop at the same frequency.
[0026] The input of the multiplexer MUX receives the outputs P0~P from the delay coarse adjustment module. X-1 And input CW PE or CW SE The output signals DA and DB are of the same frequency but different phases.
[0027] Furthermore, the delay fine-tuning module includes n DA delay fine-tuning units and n DB delay fine-tuning units; the DA delay fine-tuning units and the DB delay fine-tuning units have the same structure;
[0028] The delay fine-tuning unit includes PMOS transistors M1, M3, M4, M2, M5, and M6, and an output capacitor C.
[0029] Among them, the gate of M1 is connected to the gates of M2 and M5, serving as the control input terminal of the delay fine-tuning unit; the source of M1 is connected to the power supply VDD, the drain of M1 is connected to the drain of M2 and the gate of M4, and the source of M2 is connected to the ground line.
[0030] The gate of M3 is connected to the gate of M6 and serves as the input terminal of the delay fine-tuning unit, connected to the signal DA or DB; the source of M3 is connected to the power supply VDD, and the drain of M3 is connected to the source of M4.
[0031] The source of M5 is connected to the drain of M6, and the source of M6 is connected to ground.
[0032] The upper plate of capacitor C is connected to the drains of M4 and M5, serving as the output terminal PE or SE of the delay fine-tuning unit. The other end of capacitor C is connected to ground.
[0033] Furthermore, both the transmitting-end edge combining module and the receiving-end edge combining module consist of m data combining units and a total XOR gate. SUM The structure includes: each data merging unit comprises an XOR gate and a D flip-flop; the first input of the XOR gate is CW. DATAConnect the output terminal of the digital control module, connect the second input terminal to the Q output terminal IN of the D flip-flop, and connect the output terminal of the XOR gate to the D input terminal of the D flip-flop, with the input determined according to CW. DATA The signal obtained by XORing IN; the CLK input PE of the D flip-flop is connected to the output of the transmitting edge positioning module, and its output IN is connected to the input of the total XOR gate; the output of the total XOR gate is the combined high-speed vector PAT or the sampling clock SAMP.
[0034] The beneficial effects of this invention are as follows:
[0035] 1) This invention integrates a high-speed memory and pre-stores vector data inside the timing generator, which is then called in real time by the digital control module to achieve dynamic adjustment of edge positioning. This effectively avoids the limitation of the operating speed caused by insufficient bandwidth of the external communication interface, enabling the system to maintain stable data loading and transmission capabilities even under high-speed operation, thereby improving the overall compatibility and reliability.
[0036] 2) By adopting a two-stage timing adjustment structure composed of coarse and fine timing delay units, this invention achieves picosecond-level timing resolution adjustment accuracy, which not only meets the high-precision requirements of high-speed automatic testing equipment for timing control, but also significantly reduces the contradiction between adjustment range and resolution that exists in traditional single-stage delay adjustment architecture.
[0037] 3) This invention introduces a parallel-to-serial conversion scheme based on edge merging circuits, which efficiently merges and serially outputs multiple parallel vectors while ensuring phase accuracy and amplitude stability, greatly improving the output vector rate. At the same time, it effectively reduces the design complexity and energy consumption of the front-end edge positioning circuit, achieving a balance between high speed and low power consumption.
[0038] 4) The overall architecture of this invention maintains the advantages of timing accuracy and speed while having good scalability and portability. It can be widely applied to high-speed vector drive and high-precision timing control in various automatic test systems, and has significant engineering application value and industrial promotion prospects. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the overall circuit of the present invention;
[0040] Figure 2 This is a schematic diagram of the digital control module structure;
[0041] Figure 3 This is a structural diagram of the edge positioning module and a schematic diagram of the edge positioning unit.
[0042] Figure 4 This is a schematic diagram of the internal unit circuit of the delay coarse adjustment module;
[0043] Figure 5 This is a schematic diagram of the structure of the delay coarse adjustment unit;
[0044] Figure 6 This is a schematic diagram of the internal unit circuit of the delay fine-tuning module;
[0045] Figure 7 This is a schematic diagram of the internal unit circuit of the edge merging module;
[0046] Figure 8 The simulation waveform diagram of the digital control module;
[0047] Figure 9 The simulation waveform diagram is for the delay coarse adjustment module;
[0048] Figure 10 The simulation waveform diagram for the delay fine-tuning module;
[0049] Figure 11 The simulation waveform diagram is shown for the data merging unit in the edge merging module.
[0050] Figure 12 The simulation waveform of the total XOR gate in the merging module is shown below.
[0051] Figure 13 The simulation results of generating high-speed time-series vectors using this invention are shown in the figure.
[0052] Figure 14 The simulation results are shown in the figure. The time series vectors are generated using a traditional time series generator. Detailed Implementation
[0053] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0054] like Figure 1 As shown, the high-speed, high-precision timing generator of the present invention includes a communication interface, a transmitting end memory, a receiving end memory, a calibration memory, a synchronization module, a clock generation module, a digital control module, a transmitting end edge positioning module, a receiving end edge positioning module, a transmitting end edge merging module, a receiving end edge merging module, and a sampling circuit.
[0055] The communication interface has a first input terminal DATA and a second input terminal D. SAMP Connected to the output terminal of the receiver's memory, the first output terminal D SYN Connect to the second input terminal and the second output terminal D of the synchronization module. PAT The third output terminal D is connected to the input terminal of the transmitter's memory. CAL Connect to the input terminal of the calibration memory;
[0056] The synchronization module receives the externally input clock signal SYN and synchronizes the data D. SYN Under the control of [the system], a start signal SU is generated during a specified counting period;
[0057] The digital control module has its first input terminal SU connected to the output terminal of the synchronization module, its second input terminal CLK connected to the output terminal of the clock generation module, and its third input terminal M. PAT Connected to the first output terminal and the fourth input terminal M of the transmitter's memory Period The second output and fifth input M are connected to the transmitter's memory. CAL Connected to the output of the calibration memory, sixth input terminal D CMP Connected to the output terminal of the sampling circuit, the first output terminal M SAMP Connect to the input terminal of the receiver's memory, and the second output terminal CW. PE The first input terminal and the third output terminal CW are connected to the edge positioning module of the transmitting end. SE Connected to the first input terminal and the fourth output terminal CW of the receiver edge positioning module. DATA They are respectively connected to the first input terminal of the transmitting end edge combining module and the first input terminal of the receiving end edge combining module;
[0058] The clock generation module has REF as its input terminal and CLK as its output terminal, which is also connected to the second input terminal of the transmitting edge positioning module and the second input terminal of the receiving edge positioning module, respectively.
[0059] The first input terminal PE of the transmitting end edge merging module is connected to the output terminal of the transmitting end edge positioning module, and the output terminal is PAT.
[0060] The first input terminal SE of the receiving edge merging module is connected to the output terminal of the receiving edge positioning module.
[0061] The sampling circuit has its first input terminal SAMP connected to the output terminal of the receiving edge merging module, and its second input terminal CMP.
[0062] When the system is working, it first receives external data DATA through the communication interface and then synchronizes the data D. SYN Send the vector data D to the synchronization module. PAT The calibration data D is sent to the transmitter's memory. CAL The data is fed into the calibration memory; subsequently, the synchronization module sends a start signal SU to the digital control module, and the digital control module begins reading vector information M from the transmitter memory. PAT and edge information M Period And read calibration information M from the calibration memory. CALThe clock generation module contains a phase-locked loop (PLL) that multiplies the input reference signal REF and provides a clock signal to the digital control module, the transmitting edge positioning module, and the receiving edge positioning module. The transmitting edge positioning module uses the control word CW... PE Under the action of [unclear], the input clock signal CLK is delayed accordingly, and the PE signal is output to the input of the transmitting edge combining module. Finally, the transmitting edge combining module determines the input based on PE and CW. DATA Generate and output the test vector PAT; the receiver edge positioning module in the control word CW SE Under the action of [unclear], the input clock signal CLK is delayed accordingly, and the SE signal is output to the input of the receiving edge combining module; the receiving edge combining module [unclear] determines the delay based on SE and CW. DATA A sampling clock SAMP is generated to control the sampling circuit to sample the externally input comparison signal CMP. The sampling circuit then converts the sampled result D... CMP The sampled information M is sent to the digital control module; finally, the digital control module will input the sampled information M. SAMP It is stored in the receiver's memory and output through the communication interface.
[0063] like Figure 2 As shown, the digital control module includes a counter, a state machine, a storage read / write mechanism, and a periodic synthesizer. The counter has a first input terminal SU, a second input terminal CLK, and its output terminal CNT connected to the input terminal of the state machine. The state machine has its input terminal CNT connected to the output terminal of the counter, its first output terminal outputting a read / write control signal R / D to the first input terminal of the storage read / write module, and its second output terminal outputting the data PG required for periodic synthesis to the first input terminal of the periodic synthesizer. The storage read / write mechanism has a second input terminal M... PAT Its third input terminal is M Period Its fourth input terminal is D SAMP Its first output terminal CW MEM Connected to the second input of the periodic synthesizer, its second output is M. SAMP Its third output is CW DATA The periodic synthesis has a third input terminal M. CAL The first output terminal is CW. PE Its second output is CW SE .
[0064] like Figure 3 As shown, the transmitting end edge positioning module and the receiving end edge positioning module are composed of m identical edge positioning units; the i-th edge positioning unit is based on the digitally controlled output signal CW. iThe clock-generated output signal CLK is delayed, and its output signal is PE or SE; 1≤i≤m, where m is a positive integer; wherein, the edge positioning unit consists of a coarse delay adjustment and a fine delay adjustment; the first input terminal of the coarse delay adjustment is connected to the clock input CLK of the edge positioning unit, the second input terminal is connected to the digital control signal CW, and its output terminal is connected to the input terminals DA,DB of the fine delay adjustment; the first input terminal of the fine delay adjustment is connected to the output terminals DA,DB of the coarse delay adjustment, the second input terminal is connected to the digital control signal CW, and its output terminal is connected to the output of the edge positioning unit.
[0065] like Figure 4 As shown, the delay coarse adjustment module consists of a delay-locked loop, X (X is a positive integer) identical coarse adjustment units, and a multiplexer MUX. The input of the delay-locked loop is connected to the input CLK of the delay coarse adjustment module, and its output is connected to the input Vc of the X delay coarse adjustment units. The first input of the first delay coarse adjustment unit is connected to the input CLK of the delay coarse adjustment module, the second input is connected to the output Vc of the delay-locked loop, and its output is connected to the input P1 of the second delay coarse adjustment unit. The first input of the second delay coarse adjustment unit is connected to the output P1 of the first delay coarse adjustment unit, the second input is connected to the output Vc of the delay-locked loop, and its output is connected to the input P2 of the third delay coarse adjustment unit. The connections for the third to Xth delay units are similar. The input of the multiplexer MUX is the input CLK (P0) of the delay coarse adjustment module and the outputs P1 to P2 of each delay coarse adjustment unit. X-1 The input CW is the delay coarse adjustment module, and its output is the delay coarse adjustment module's output DA,DB.
[0066] like Figure 5 As shown, the delay coarse adjustment unit consists of a PMOS transistor M1, a resistor R1, and a voltage-controlled current source IBIAS; wherein, the gate of M1 serves as the first input terminal P of the delay coarse adjustment unit. y (y is a positive integer ranging from 0 to x-2); the drain of M1 is connected to one end of resistor R1, serving as the output terminal P of the delay coarse adjustment unit. y+1 (y+1 is a positive integer ranging from 1 to x-1), the other end of the resistor is connected to the power supply VDD; the source of M1 is connected to one end of the voltage-controlled current source, the control terminal of the voltage-controlled current source is used as the second input terminal Vc of the delay coarse adjustment unit, and the other end of the voltage-controlled current source is connected to the ground wire.
[0067] like Figure 6As shown, the delay fine-tuning module includes n DA delay fine-tuning units and n DB delay fine-tuning units; the DA delay fine-tuning units and DB delay fine-tuning units have the same structure. Each delay fine-tuning unit includes PMOS transistors M1, M3, M4, M2, M5, and M6, and an output capacitor C; wherein, the gate of M1 is connected to the gates of M2 and M5, serving as the control input terminal of the delay fine-tuning unit; the source of M1 is connected to the power supply VDD, the drain of M1 is connected to the drain of M2 and the gate of M4, and the source of M2 is connected to ground; the gate of M3 is connected to the gate of M6, serving as the input terminal of the delay fine-tuning unit connected to the signal DA or DB; the source of M3 is connected to the power supply VDD, and the drain of M3 is connected to the source of M4; the source of M5 is connected to the drain of M6, and the source of M6 is connected to ground; the upper plate of capacitor C is connected to the drains of M4 and M5, serving as the output terminal PE or SE of the delay fine-tuning unit, and the other end of capacitor C is connected to ground.
[0068] like Figure 7 As shown, both the transmitting-end edge combining module and the receiving-end edge combining module consist of m data combining units and a total XOR gate. Each data combining unit includes an XOR gate and a D flip-flop. Taking the i-th data combining unit as an example (i is a positive integer ranging from 1 to m), the first input terminal CW of the XOR gate... DATAi The output of the digital control module is connected, the second input INi is connected to the Q output of the D flip-flop, and the output of the XOR gate is connected to the D input of the D flip-flop, with its input determined according to CW. DATAi The signal obtained by XORing IN1 and INi; the CLK input PEi of the D flip-flop is connected to the output of the transmitting edge positioning module, and its output INi is connected to the input of the total XOR gate; the output signal of the total XOR gate is based on IN1~IN1. m The PAT obtained by XORing.
[0069] This invention uses Cadence software, based on a 40nm CMOS process platform, employs an 800MHz LVDS protocol, has an external reference frequency REF of 100MHz, and a clock generation module that multiplies the CLK to 2GHz. The timing vector generated by the timing generator is verified according to the PRBS code pattern (pseudo-random binary sequence) pre-stored in memory.
[0070] The high-speed, high-precision timing generator described in this invention has the following simulation waveform diagram: Figures 7-11 As shown.
[0071] like Figure 8As shown, the main functions of the digital control module include counting, memory read / write, and cycle synthesis control. Specifically, the counter starts counting based on the start signal SU and the clock signal CLK, and sends the counting result CNT to the state machine. The memory read / write function reads the cycle information M from the memory. Period and vector data information M PAT Generate vector data control word CW DATA The periodic synthesis function generates the delay control word (CW) for the edge positioning module. DE and CW SE The signal PE is a multiple of the synthesis period of the reference clock CLK. For example, if the period T of the PE1 signal is required... PE1 1.1T CLK Since the CLK clock frequency is 2GHz and its period is 500ps, T PE1 =550ps, based on the characteristics of the delay fine-tuning module, one CW PE The control word can generate a delay of 0.98 ps, therefore the control word CW should be used in this case. PE Set to 50.
[0072] like Figure 9 As shown, the delay coarse adjustment unit of the edge positioning module receives its input clock signal CLK(P0) from the clock generation module. X identical delay coarse adjustment units, under the control of a delay-locked loop, precisely delay the input clock signal, generating X-1 clock signals with different phases. The output CW of the unit digital control module is connected to the input of the multiplexer MUX. The multiplexer selects the output P of the Nth delay unit according to the control word CW=N. N As the output DA of the delay coarse adjustment unit, the output P of the (N+1)th delay unit is selected. N+1 The output DB serves as the delay coarse adjustment unit.
[0073] like Figure 10 As shown, the delay fine-tuning unit of the edge positioning module has input signals DA and DB, its control input terminal is CW, and its output signal is PE obtained by interpolation of DA and DB. Taking 7-bit delay fine-tuning as an example, the interval between input signals DA and DB is 90°. The control input terminal CW, according to the control word CW=50, causes the output terminal PE to generate an output signal PE that is delayed by 50 LSBs (i.e., delayed by 49ps) from the input signal DA. The control input terminal CW, according to the control word CW=100, causes the output terminal PE to generate an output signal PE that is delayed by 100 LSBs (i.e., delayed by 98ps) from the input signal DA.
[0074] like Figure 11 As shown, the data merging unit's first input signal is the output signal CW from the digital control module. DATAmThe second input signal is the output signal PE from the transmitting edge positioning module. m The output signal is the input signal IN of the total XOR gate. m Taking the first data merging unit as an example, the output signal PE1 of the transmitting end edge positioning module is a square wave with a 50% duty cycle, and the output signal CW of the digital control module... DATA1 For the control code of the edge merging module, according to CW DATA1 The control word controls the output signal IN1 to flip.
[0075] like Figure 12 As shown, the total XOR gate of the data merging unit has the first input signal as the output signal IN1 of the first data merging unit, the second input signal as the output signal IN2 of the second data merging unit, and so on for the third to mth input signals. The total XOR gate outputs the m data merging units' output signals IN1 to IN2. m Perform an XOR operation and output the result PAT.
[0076] Using the method described in this invention, the specific process of generating high-speed vectors is as follows: the digital control module reads the vector data information M from the transmitter's memory. PAT and vector periodic information M Period Generate vector data control word CW DATA and cycle control word CW PE The delay coarse adjustment module in the transmitting end edge positioning unit selects the outputs DA and DB of two adjacent delay coarse adjustment units according to the control word CW; the delay fine adjustment module in the transmitting end edge positioning unit generates a signal PE with a specified delay according to the control word CW and DA and DB; the data merging unit selects the outputs DA and DB of two adjacent delay coarse adjustment units according to CW. DATA The control word and PE signal first generate multiple low-speed vector information of a specified mode, then the multiple vectors are combined by a total XOR gate to finally generate an 8Gbps high-speed vector PAT, such as... Figure 13 As shown.
[0077] Simulations using traditional timing generators, such as Figure 14 As shown, when using the 800MHz LVDS protocol and the chip's internal clock frequency of 2GHz, due to the 800MHz limitation of LVDS communication and the absence of edge combining technology, even with PRBS code transmitted via LVDS communication, a timing vector of up to 2Gbps can only be generated in certain time periods, making it impossible to achieve PRBS flipping in every 2GHz clock cycle. Compared to traditional methods, this invention employs a method of first storing the data on-chip and then generating high-speed timing vectors through an internal clock, which has significant technical advantages and good application value in high-speed vector generation applications of ATE test machines.
[0078] The above description is merely a preferred embodiment of the present invention and is not intended to further limit the present invention. All equivalent changes made based on the description and drawings of the present invention are within the protection scope of the present invention.
Claims
1. A high-speed, high-precision timing generator, characterized in that, include, The communication interface receives external data DATA at its first input terminal and outputs synchronization data D through its first output terminal. SYN The second output terminal of the synchronization module outputs vector data D. PAT The calibration data D is output to the transmitter's memory and the third output terminal. CAL The second input terminal reads data D from the receiver's memory, which is then sent to the calibration memory. SAMP ; The clock generation module multiplies the input reference signal REF and provides the clock signal CLK to the digital control module, the transmitting edge positioning module, and the receiving edge positioning module. The synchronization module receives the externally input clock signal SYN and synchronizes the data D. SYN Under the control of [the system], a start signal SU is generated during a specified counting period; The digital control module receives a start signal SU from the synchronization module at its first input terminal, a clock signal CLK from the clock generation module at its second input terminal, and vector information M from the first output terminal of the transmitting end memory at its third input terminal. PAT The fourth input terminal receives the edge information M sent by the second output terminal of the transmitting end memory. Period The fifth input terminal receives calibration information M sent by the calibrator. CAL The sixth input terminal receives the D signal sent by the sampling circuit. CMP ; The sampling signal M is sent through the first output terminal. SAMP The second output terminal sends the period control word CW to the receiver's memory. PE The period control word CW is transmitted from the first input terminal and the third output terminal of the transmitting edge positioning module. SE The data control word CW is transmitted from the first input terminal and the fourth output terminal of the edge positioning module at the receiving end. DATA The first input terminals of the transmitting end edge combining module and the receiving end edge combining module are respectively connected to the first input terminal of the transmitting end edge combining module; The transmitting edge positioning module, in the periodic control word CW PE Under its influence, the input clock signal CLK is delayed accordingly, and the PE signal is output to the edge merging module at the transmitting end. The transmitting edge combining module, based on PE and CW DATA Generate high-speed vector PAT; The receiver edge positioning module, in the periodic control word CW SE Under its influence, the input clock signal CLK is delayed accordingly, and the SE signal is output to the edge merging module at the receiving end. The receiver edge combining module, based on SE and CW DATA Generate a sampling clock SAMP to control the sampling circuit to sample the externally input comparison signal CMP; The sampling circuit will sample the result D. CMP Send to the digital control module; The digital control module will sample the signal M. SAMP Stored in the receiver's memory.
2. The high-speed, high-precision timing generator according to claim 1, characterized in that, The digital control module includes, The counter counts based on the received start signal SU and clock signal CLK, and sends the counting result CNT to the state machine; The state machine has its first output terminal R / D connected to the first input terminal for storage read / write, and its second output terminal PG connected to the first input terminal for periodic synthesis. Storage read / write, which reads edge information M from the transmitter's memory. Period Vector information M PAT and sampling results D CMP Generate vector data control word CW DATA CW MEM and sampling information M SAMP ; Periodic synthesis generates the periodic control word CW used for delays in the transmitting and receiving edge positioning modules. PE and CW SE .
3. The high-speed, high-precision timing generator according to claim 1, characterized in that, Both the transmitting end edge positioning module and the receiving end edge positioning module are composed of m identical edge positioning units. The first input terminals of the m edge positioning units are connected to each other as clock input terminals CLK. The i-th edge positioning unit is based on the CW output by the digital control module. PE or CW SE The clock signal CLK is delayed, and the output signal PE or SE is generated, where 1 ≤ i ≤ m.
4. A high-speed, high-precision timing generator according to claim 3, characterized in that, The edge positioning unit includes a coarse delay adjustment module and a fine delay adjustment module, wherein, The first input terminal of the delay coarse adjustment module is connected to the clock input CLK of the edge positioning unit, and the second input terminal is connected to CW. PE or CW SE Its output is connected to the first input DA,DB of the delay fine-tuning module; The second input of the delay fine-tuning module is connected to CW. PE or CW SE The output terminal is connected to the output PE or SE of the edge positioning unit.
5. A high-speed, high-precision timing generator according to claim 4, characterized in that, The delay coarse adjustment module includes a delay-locked loop, X identical delay coarse adjustment units, and a multiplexer (MUX). The input of the delay-locked loop is connected to the clock signal CLK, and the first input of the first coarse adjustment unit is connected to the CLK signal; the output of each coarse adjustment unit is connected to the first input of the next coarse adjustment unit, and the second input of each coarse adjustment unit is connected to the clock Vc of the delay-locked loop at the same frequency. The input of the multiplexer MUX receives the outputs P0~P from the delay coarse adjustment module. X-1 And input CW PE or CW SE The output signals DA and DB are of the same frequency but different phases.
6. A high-speed, high-precision timing generator according to claim 4, characterized in that, The delay fine-tuning module includes n DA delay fine-tuning units and n DB delay fine-tuning units; the DA delay fine-tuning units and the DB delay fine-tuning units have the same structure; The delay fine-tuning unit includes PMOS transistors M1, M3, M4, M2, M5, and M6, and an output capacitor C. Among them, the gate of M1 is connected to the gates of M2 and M5, serving as the control input terminal of the delay fine-tuning unit; the source of M1 is connected to the power supply VDD, the drain of M1 is connected to the drain of M2 and the gate of M4, and the source of M2 is connected to the ground line. The gate of M3 is connected to the gate of M6 and serves as the input terminal of the delay fine-tuning unit, connected to the signal DA or DB; the source of M3 is connected to the power supply VDD, and the drain of M3 is connected to the source of M4. The source of M5 is connected to the drain of M6, and the source of M6 is connected to ground. The upper plate of capacitor C is connected to the drains of M4 and M5, serving as the output terminal PE or SE of the delay fine-tuning unit. The other end of capacitor C is connected to ground.
7. A high-speed, high-precision timing generator according to claim 1, characterized in that, Both the transmitting end edge merging module and the receiving end edge merging module consist of m data merging units and a total XOR gate. SUM constitute; Each data merging unit includes an XOR gate and a D flip-flop; the first input of the XOR gate is CW. DATA Connect the output terminal of the digital control module, connect the second input terminal to the Q output terminal IN of the D flip-flop, and connect the output terminal of the XOR gate to the D input terminal of the D flip-flop, with the input determined according to CW. DATA The signal obtained by XORing IN; the CLK input PE of the D flip-flop is connected to the output of the transmitting edge positioning module, and its output IN is connected to the input of the total XOR gate; The high-speed vector PAT or sampling clock SAMP is generated by combining the outputs of the total XOR gate.
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