Data communication method and electronic device

Abstract

The application discloses a data communication method and an electronic device, which are applied to a target centralized management controller constructed based on a logic device in a multi-node server, and relate to the technical field of data communication, and the method comprises the following steps: obtaining and analyzing a target data packet of a local area network switch through the logic device in a communication time period, and saving the target data packet into a register of the logic device; if it is monitored that the logic device or the local area network switch is reset or firmware is upgraded before the analysis is completed, the register is cleared, the target data packet is re-obtained and analyzed, and until the target data packet is completely analyzed and saved into the register, the analyzed data is sent to a node management controller to adjust the network port state of the corresponding node. In the communication time period, data is obtained and analyzed through the logic device, and the register is cleared when the logic device or the local area network switch is reset or firmware is upgraded, so that the control logic can be ensured to normally operate while the error data is emptied, and data analysis confusion is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data communication, and in particular to a data communication method and an electronic device. BACKGROUND

[0002] With the continuous improvement of CPU (Central Processing Unit) performance, in order to adapt to the needs of different customers, multi-node design is applied in server design, 2 / 4 independent nodes are integrated in a single chassis, each node contains a dedicated BMC (Baseboard Management Controller) and CPLD (Complex Programmable Logic Device), and a CMC (Centralized Management Controller) management board controls public resources (such as LAN SW (lan switch), shared power supply, etc.) through the CPLD. Among them, the commonly used LAN SW chip repeatedly sends out the connection state and rate of the network port in a serial communication mode, and then the CPLD in the CMC board directly analyzes the LAN SW chip serial data packet and transmits the data to the BMC of the multi-node mainboard. In this process, when the CPLD or LAN SW is reset or firmware upgrade causes reloading, which happens to be in the CPLD and LAN SW serial communication process, the problem of data analysis confusion will occur. SUMMARY

[0003] The present application provides a data communication method and an electronic device. In a communication time period, if the logic device or the LAN switch is reset / firmware upgrade, the data parsed in the register is cleared, which clears the error data and ensures the normal operation of the control logic, avoiding data analysis confusion.

[0004] The present application provides a data communication method, which is applied to a target centralized management controller based on a logic device in a multi-node server, comprising:

[0005] In a communication time period of a target communication cycle, the logic device acquires and parses a target data packet sent by the LAN switch, and saves the parsed data to a register of the logic device; the communication time period is a preset communication time period between the logic device and the LAN switch;

[0006] If a target event is monitored before the target data packet is parsed, the register is cleared at the end of the target event, and the next time cycle is determined as a new target communication cycle; the target event is reset or firmware upgrade of the logic device or the LAN switch.

[0007] The process jumps back to the step of acquiring and parsing the target data packet sent by the LAN switch through the logic device during the communication period of the target communication cycle, until the data in the target data packet is completely parsed and saved to the register;

[0008] The parsed data in the register is sent to the node management controller to adjust the network port status of the corresponding node based on the parsed data.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described data communication methods.

[0010] This application can acquire and parse target data packets sent by a LAN switch through a logic device during the communication time period of the target communication cycle, and save the data in the target data packets to the register of the logic device. If a target event that performs a reset operation or firmware upgrade operation on the logic device or LAN switch is detected before the parsing operation is completed, the register is cleared at the end of the target event, the next time period is determined as the new target communication cycle, and the process jumps back to the step of acquiring and parsing the target data packets sent by the LAN switch through the logic device during the communication time period of the target communication cycle. This process continues until the data in the target data packets is completely parsed and saved to the register, and then the parsed data is sent to the node management controller to adjust the network port status of the corresponding node.

[0011] According to the technical solution of this application, in the design of a multi-node server, if the target centralized management controller acquires and parses the target data packet through the logic device during the communication period of the target communication cycle, and at this time the logic device or LAN switch has a corresponding reset operation or firmware upgrade operation, then the current data in the register is cleared, and the data packet is acquired again for parsing. In this way, only the register is reset, which can clear the erroneous data while ensuring the normal operation of the control logic, avoiding affecting the control function of the logic device on other components, and not affecting the overall system function. This avoids the current problem of data parsing chaos caused by the reset / firmware upgrade of the logic device or LAN switch. Moreover, by clearing the register, the reset can be completed quickly, avoiding missing the data transmission of the LAN switch during the reset process, and ensuring the timeliness and continuity of communication. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A data communication method flow chart provided for the embodiment of the present application;

[0014] Figure 2 A serial communication schematic diagram provided for the embodiment of the present application;

[0015] Figure 3 A data communication flow chart when CPLD is reset or reloaded provided for the embodiment of the present application;

[0016] Figure 4 A data communication flow chart when LAN SW is reset or reloaded provided for the embodiment of the present application;

[0017] Figure 5 A data communication device structure schematic diagram provided for the embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0019] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0020] In the server multi-node design, the LAN SW chip repeatedly sends the connection state and rate of the network port in a serial communication mode, and then the CPLD in the CMC board directly analyzes the serial data packet of the LAN SW chip and transmits the data to the BMC of the multi-node mainboard. In this process, when the CPLD or the LAN SW is reset or firmware upgrade causes reloading, which happens to be in the CPLD and LAN SW serial communication process, the problem of data analysis confusion will occur. When the target data packet is obtained and analyzed, the current data in the register is cleared and the data packet is re-acquired and analyzed if the CPLD or the LAN SW is reset or firmware upgrade causes reloading. Only the register is reset, the control logic can run normally while the error data is cleared, and the problem of data analysis confusion is avoided.

[0021] In order to enable the person skilled in the art to better understand the scheme of the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0022] As shown in Figure 1 The embodiment of the present application provides a data communication method applied to a target centralized management controller constructed based on a logic device in a multi-node server. Next, the execution process of the data communication method is described in detail, including:

[0023] Step S11, in the communication time period in the target communication period, the logic device acquires and analyzes the target data packet sent by the local area network switch, and saves the analyzed data to the register of the logic device; the communication time period is the preset communication time period between the logic device and the local area network switch.

[0024] The multi-node server in the embodiment integrates 2 / 4 independent nodes, each node contains a dedicated BMC and CPLD, and in the communication time period of the target communication cycle, the target centralized management controller CMC can obtain the target data packet sent by the local area network switch LAN SW through the logic device CPLD, and trigger the analysis operation of the target data packet, so as to analyze the target in the target data packet into the register of the logic device CPLD. The communication time period is the communication time period between the pre-configured logic device CPLD and the local area network switch LAN SW. Therefore, first of all, the target communication cycle of the target centralized management controller obtaining the target data packet sent by the local area network switch can be determined. The above-mentioned target communication cycle includes a communication time period and a communication idle time period, and the communication idle time period is the remaining time period in the target communication cycle except the communication time period, wherein the duration corresponding to the communication time period is less than the duration corresponding to the communication idle time period. It should be pointed out that in the communication idle time period, the clock signal CLK in the target centralized management controller remains low, and the data signal DATA remains high. It can be understood that each server node in the embodiment has a dedicated CPLD, which is used in cooperation with the BMC of the node to serve the needs of a single node; the CPLD associated with the CMC management board is a dedicated CPLD for centralized control of public resources by the CMC, which is used for public resources of the whole chassis.

[0025] For example, as shown in Figure 2 The LAN SW chip repeatedly sends the connection state and rate of the network port in a serial communication mode. The sending mode of the serial data is to send about 2.59us serial data packet (including connection state / rate information, CLK T is 108ns, a total of 24T) to the outside every 16ms. Except for the communication time, it is in the communication idle state (CLK remains low, DATA remains high), that is, the communication time of LAN SW and CPLD is 2.59us, and the communication idle time is 15.997ms.

[0026] Step S12, if the target event is monitored before the target data packet is parsed, the register is cleared at the end of the target event, and the next time period is determined as a new target communication cycle; the target event is to perform reset or firmware upgrade on the logic device or the local area network switch.

[0027] In the embodiment, it can be determined whether the target event is monitored before the analysis operation for the target data packet is completed, the register is cleared at the end of the target event, and the next time period is determined as a new target communication period, so as to reacquire the target data packet in the new target communication period. The target event is an event of performing a target operation on the logic device or the LAN switch, and the target operation is a reset operation or a firmware upgrade operation. It can be understood that since it is in the data communication period at this time, the detected target event also occurs in the communication period of the CPLD and the LAN SW.

[0028] Specifically, if the clock signal is low and the data signal is high at the end of the target event, the timer in the logic device is started, the first time length during which the clock signal remains low is determined by using the timer, and the preset reset operation of the register is performed based on the first time length to clear the data in the register. That is, compared with the current CPLD analyzing the LAN SW serial data, the embodiment adds a reset mechanism after the CPLD analyzes the LAN SW serial data, and needs to ensure that the reset time point is in the communication gap, so as to ensure that there is only one reset action, thereby avoiding the problem that the reset time point coincides with the data sampling time point due to continuous repeated communication. Therefore, since the communication idle state CLK remains low and DATA remains high, the CPLD internal high-precision timer can be started when CLK=0 and DATA=1 in the communication gap.

[0029] And when the preset reset operation of the register is performed based on the first time length to clear the data in the register, it is necessary to judge whether the first time length meets the preset condition, and perform the preset reset operation of the register to clear the data in the register when the first time length meets the preset condition; wherein, the preset condition is that the first time length is not less than the second time length, the second time length is not less than half of the time length corresponding to the communication idle time period, and is not greater than the time length corresponding to the communication idle time period. For example, in order to avoid multiple resets of the register, the first time length can also be set to 75% of the second time length in the embodiment, that is, when CLK continuous low level ≥ 16ms x 0.75 = critical value 12ms, trigger event, it can be understood that if the detection of CLK continuous low level is selected to be short, such as 1ms, it will lead to more resets of LAN SW and CPLD communication idle period, and the CPLD register will be continuously reset; if the detection of CLK continuous low level is selected to be long, such as 17ms, it will lead to that if the CPLD is upgraded and reloaded by the firmware at the T1 time point of the current communication period, but the register of the CPLD will be reset at the T2 time point of the next time period, which will lead to that the CPLD will misplace the first segment of LAN SW serial data and the second segment of serial data, the network port state information will be wrong, and the subsequent information will be continuously misaligned and reported to the BMC, so that the misalignment of serial data analysis cannot be solved due to improper reset time selection. And, the above-mentioned CPLD register reset time is about 20ns (1 CLK high pulse of 50M clock), that is, the CPLD register can be reset, and only the data analysis register group is reset, and the CPLD control logic is retained, so that for incomplete data, the reset action is used to clear, and the second data is not combined to cause information misjudgment, that is, the intelligent soft reset of the register is realized, which is helpful to solve the problem of communication data analysis abnormality caused by CPLD or common component firmware upgrade.

[0030] And it can be understood that if the target event is monitored in the communication idle time period, the timer in the logic device is prohibited to be started. This is because if the CPLD reset is completed without encountering LAN SW serial data, the data analysis is correct, and if the LAN SW is reset or upgraded during serial communication idle period, it will not affect the CPLD register, so it is not necessary to start the timer in the logic device to time, and it is not necessary to reset the register.

[0031] It also needs to be pointed out that in the process of clearing the data in the register at the end of the target event, the target flag bit in the logic device needs to be kept as the first target value; wherein the target flag bit is a flag bit used to represent whether the data in the target data packet is completely parsed and saved to the register, and the first target value is a value used to represent that the data in the target data packet is completely parsed and saved to the register. Correspondingly, before the parsed data saved in the register is sent to the node management controller in the multi-node server, the target flag bit in the logic device can be updated to a second target value; wherein the second target value is a value used to represent that the data in the target data packet is not completely parsed and saved to the register. In this way, by taking the target flag bit as a data completion flag bit, the CPLD can judge whether the LAN SW serial data packet is parsed completely, which helps to confirm the data parsing integrity. Specifically, in normal parsing, after the CPLD completely parses a serial data packet sent by the LAN SW, the data completion flag bit is set to 1, representing that the parsing is completed, and the data can be transmitted to the BMC; in abnormal parsing, such as LAN SW / CPLD reset, if the CPLD does not completely receive a data packet and only parses part of the data, the data completion flag bit will not be set to 1, at this time the CPLD will recognize that the data is incomplete, and subsequently the remaining data is emptied through the soft reset of the register.

[0032] Step S13, re-jump to the step of acquiring and parsing the target data packet sent by the local area network switch through the logic device in the communication time period in the target communication cycle until the data in the target data packet is completely parsed and saved to the register.

[0033] If the target event is monitored in the embodiment, the step of obtaining and analyzing the target data packet sent by the LAN switch through the logic device is re-jumped until the data in the target data packet is completely analyzed and saved to the register. In the process of re-jumping to the step of obtaining and analyzing the target data packet sent by the LAN switch through the logic device until the data in the target data packet is completely analyzed and saved to the register, the preset check bit in the target data packet can also be checked. If the preset check bit passes the check, it is determined that the data in the target data packet is completely analyzed and saved to the register; if the preset check bit fails the check, the step of obtaining and analyzing the target data packet sent by the LAN switch through the logic device is re-jumped. That is, the data packet sent by the LAN SW can also be adjusted in the embodiment, for example, a parity check bit or a CRC check code is added after 24-bit data. The check bit is verified when the CPLD analyzes. If the check passes, the data is normally updated; if the check fails, the data error is marked, and the LAN SW re-sends the current data packet. When the check fails for a plurality of times, the CPLD directly triggers a soft reset to clear the error data and reports a fault alarm to the BMC. In this way, the data correctness check is helpful to avoid errors caused by signal interference, and whether the data is correctly transmitted can be judged, further improving the reliability of serial communication.

[0034] In step S14, the analyzed data in the register is sent to the node management controller, so as to adjust the network port state of the corresponding node according to the analyzed data.

[0035] In the embodiment, the analyzed data saved in the register is sent to the node management controller of each node in the multi-node server, so that each node adjusts the local network port state, such as network port connection state and network port data transmission rate, according to the analyzed data by using the node management controller. It should be noted that the embodiment is not only applicable to the application of CMC board and public component LAN SW, but also can be extended to other public components, such as power components and fan components, and is also applicable to other serial communication with repeated data transmission but without data check, so as to ensure correct, effective and zero-error data analysis.

[0036] The embodiment can acquire the target data packet sent by the LAN SW through the CPLD of the CMC in the communication time period of the target communication period, trigger the parsing operation for the target data packet to parse the data in the target data packet into the registers of the CPLD, and if the event of performing the reset operation or the firmware upgrade operation on the logic device or the local area network switch is monitored before the parsing operation is completed, the timer is monitored at the end of the target event, the data in the registers is cleared when the CLK is continuously low and is not less than the critical value 12 ms, the next time period is determined as a new target communication period, and the target data packet is reacquired until the data in the target data packet is completely parsed and saved to the registers, and then the parsed data is sent to the BMC of each node in the multi-node server to adjust the local network port state. In this way, in the multi-node server design, if the target centralized management controller acquires the target data packet through the logic device and parses the target data packet in the communication time period of the target communication period, and at this time, the logic device or the local area network switch has a corresponding reset operation or firmware upgrade operation, the current data in the registers is cleared, and the data packet is reacquired for parsing. In this way, only the reset registers can empty the error data while ensuring the normal operation of the control logic, avoiding the failure rate of 0.1% of the LAN SW and the CPLD, realizing zero error of the LAN SW and the CPLD communication data parsing data, avoiding affecting the control function of the logic device on other components, not affecting the overall system function, avoiding the problem of data parsing confusion caused by the reset / firmware upgrade of the logic device or the local area network switch, and quickly completing the reset by clearing the registers. Only the CPLD code modification can avoid the data parsing problem, the change is small, and the monitoring stability of the BMC to the network state is greatly improved, avoiding missing the data sending of the local area network switch in the reset process, and ensuring the stability and continuity of the communication.

[0037] Based on the above technical solution, the embodiment is aimed at the communication gap of serial communication data, for example, the communication gap time of 15.997 ms of the LAN SW and the CPLD communication, according to the principle of T*0.75, there is only one reset, and when it is detected that the CLK has a low level greater than or equal to 12 ms, the CPLD soft reset is triggered, and the registers in the original parsing of the CPLD are zeroed after the reset.

[0038] In a specific embodiment, as Figure 3As shown, if the CPLD is reset or the firmware is upgraded, at this time all the registers in the CPLD will be reset to the original value, the parsing data is zeroed, and the data parsing completion flag is set to 0. If no LAN SW serial data is encountered when the reset is completed, the first pen data is parsed and parsed correctly; if the LAN SW is sending data when the reset is completed, the CPLD starts to parse the first pen data, but since the data is incomplete, the data parsing completion flag will not be set to 1, and after the first pen data transmission is completed, the serial communication bus data CLK is continuously low, at this time the CPLD detects that the CLK has more than 12ms low level, and the CPLD register is reset once, that is, the first pen parsed data is set to zero and the CLK low pulse is re-timed, at this time, since there is only 15.997ms low pulse in total, the following 3.977ms low pulse is not enough to support the second CPLD register reset, the LAN SW sends the second pen data, the CPLD re-parses the data and sets the data completion flag to 1, and the data is transmitted to the multi-node BMC.

[0039] In another specific embodiment, as shown in Figure 4 The LAN SW is reset or upgraded. If the LAN SW is reset or upgraded during the serial communication idle period, it will not affect the CPLD register; if the LAN SW is reset or the firmware is upgraded when the serial communication occurs, it will cause the CPLD parsing state machine to be forced to interrupt, the new state flag of the CPLD is still 0, the original parsed data will not be overwritten, and at the same time, the CPLD continuously detects that the LAN SW CLK is low for more than 12ms, and starts to reset the CPLD state flag and the serial data that has not been parsed. After the LAN SW re-sends new data, the CPLD parses the new data and sets the completion flag to 1, and updates the network state information to notify the BMC.

[0040] As shown in Figure 5 The embodiment of the application also provides a data communication device applied to a target centralized management controller constructed based on a logic device in a multi-node server, which comprises:

[0041] A first data parsing module 11 is configured to acquire and parse a target data packet sent by a LAN switch through the logic device in a communication time period of a target communication period, and save the parsed data into a register of the logic device; the communication time period is a preset communication time period between the logic device and the LAN switch;

[0042] A data zeroing module 12 is configured to zero the register at the end of a target event, and determine a next time period as a new target communication period if the target event is monitored before the target data packet is parsed; the target event is a reset or firmware upgrade performed on the logic device or the LAN switch.

[0043] The second data analysis module 13 is configured to re-jump to the step of obtaining and analyzing the target data packet sent by the LAN switch through the logic device during the communication time period in the target communication period until the data in the target data packet is completely analyzed and saved to the register.

[0044] The data forwarding module 14 is configured to send the analyzed data in the register to the node management controller to adjust the network port state of the corresponding node according to the analyzed data.

[0045] In some embodiments, the data communication device further comprises:

[0046] The period determination module is configured to determine a target communication period in which the target centralized management controller performs serial communication when obtaining the target data packet sent by the LAN switch; the target communication period comprises a communication time period and a communication idle time period; the communication idle time period is a remaining time period in the target communication period except for the communication time period; and the length of the communication time period is less than the length of the communication idle time period.

[0047] In addition, during the communication idle time period, the clock signal in the target centralized management controller remains at a low level, and the data signal remains at a high level.

[0048] In some embodiments, the data clearing module 12 specifically comprises:

[0049] The timer starting sub-module is configured to start the timer in the logic device if the clock signal is monitored to be at a low level and the data signal is monitored to be at a high level at the end of the target event.

[0050] The data clearing sub-module is configured to determine the first length of time during which the clock signal remains at a low level by using the timer, and perform the preset reset operation of the register based on the first length of time to clear the data in the register.

[0051] In some embodiments, the data clearing sub-module specifically comprises:

[0052] The data clearing unit is configured to determine whether the first length of time meets a preset condition, and perform the preset reset operation of the register to clear the data in the register when the first length of time meets the preset condition; wherein the preset condition is that the first length of time is not less than a second length of time, the second length of time is not less than one-half of the length of the communication idle time period, and is not greater than the length of the communication idle time period.

[0053] In some embodiments, the data clearing sub-module is further configured to prohibit starting the timer in the logic device if the target event is monitored during the communication idle time period.

[0054] In some embodiments, the data clearing module 12 specifically includes:

[0055] The flag maintaining unit is configured to maintain the target flag in the logic device as a first target value, wherein the target flag is a flag used to represent whether the data in the target data packet is completely parsed and saved to the register, and the first target value is a value used to represent that the data in the target data packet is completely parsed and saved to the register.

[0056] In some embodiments, the data communication device further includes:

[0057] The parameter updating module is configured to update the target flag in the logic device as a second target value, wherein the second target value is a value used to represent that the data in the target data packet is not completely parsed and saved to the register.

[0058] In some embodiments, the data forwarding module 14 further includes:

[0059] The data checking unit is configured to check the preset checking bit in the target data packet, and if the preset checking bit passes the check, it is determined that the data in the target data packet is completely parsed and saved to the register, and if the preset checking bit fails the check, the step of obtaining and parsing the target data packet sent by the LAN switch through the logic device in the communication time period of the target communication period is performed again.

[0060] The features of the above-mentioned data communication device corresponding embodiments can be referred to the related descriptions of the data communication method corresponding embodiments, which will not be repeated here.

[0061] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above-mentioned embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0062] The embodiments of the present application also provide an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned data communication method embodiments.

[0063] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above-mentioned data communication method embodiments when running.

[0064] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0065] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program, when executed by a processor, implements the steps in any of the data communication method embodiments described above.

[0066] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps in any of the data communication method embodiments described above.

[0067] The skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0068] The above describes in detail a data communication method and an electronic device provided by the present application. The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above description of the examples is only applicable to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data communication method, characterized in that, A target centralized management controller based on logic devices, applied in multi-node servers, including: During the communication period of the target communication cycle, the logic device acquires and parses the target data packet sent by the local area network switch, and saves the parsed data to the register of the logic device; the communication period is a preset communication period between the logic device and the local area network switch. If a target event is detected before the target data packet is parsed, the register is cleared when the target event ends, and the next time period is determined as the new target communication period; the target event is a reset or firmware upgrade of the logic device or the LAN switch. The process then jumps back to the step of acquiring and parsing the target data packet sent by the LAN switch through the logic device during the communication time period of the target communication cycle, until the data in the target data packet is completely parsed and saved to the register; The parsed data in the register is sent to the node management controller to adjust the network port status of the corresponding node according to the parsed data; The step of clearing the register at the end of the target event includes: If a clock signal is detected to be low and a data signal to be high when the target event ends, then the timer in the logic device is started. The timer is used to determine the first duration for which the clock signal remains low, and a preset reset operation of the register is performed based on the first duration to clear the data in the register; Furthermore, the step of performing a preset reset operation on the register based on the first duration to clear the data in the register includes: Determine whether the first duration meets the preset condition, and if the first duration meets the preset condition, execute the preset reset operation of the register to clear the data in the register; The preset condition is that the first duration is not less than the second duration, the second duration is not less than half of the duration corresponding to the communication idle time period, and is not greater than the duration corresponding to the communication idle time period.

2. The data communication method according to claim 1, characterized in that, Also includes: When the target centralized management controller obtains the target data packet sent by the local area network switch, the target communication period for serial communication is determined; the target communication period includes the communication time period and the communication idle time period, and the communication idle time period is the remaining time period in the target communication period excluding the communication time period; The duration of the communication time period is shorter than the duration of the communication idle time period.

3. The data communication method according to claim 2, characterized in that, Also includes: During the communication idle period, the clock signal in the target centralized management controller remains at a low level, and the data signal remains at a high level.

4. The data communication method according to claim 3, characterized in that, Also includes: If the target event is detected during the communication idle period, the timer in the logic device is prevented from starting.

5. The data communication method according to any one of claims 1 to 4, characterized in that, The process of clearing the register at the end of the target event includes: The target flag in the logic device is kept at the first target value; The target flag is a flag used to indicate whether the data in the target data packet has been completely parsed and saved to the register, and the first target value is a value used to indicate that the data in the target data packet has been completely parsed and saved to the register.

6. The data communication method according to claim 5, characterized in that, Before sending the parsed data in the register to the node management controller, the process further includes: Update the target flag bit in the logic device to the second target value; The second target value is used to characterize that the data in the target data packet has not been fully parsed and saved to the register.

7. The data communication method according to claim 1, characterized in that, The step of re-jumping to the step of acquiring and parsing the target data packet sent by the LAN switch through the logic device during the communication time period of the target communication cycle, until the data in the target data packet is completely parsed and saved to the register, further includes: The preset checksum in the target data packet is checked; If the preset check bit verification passes, it is determined that the data in the target data packet has been completely parsed and saved to the register; If the preset check bit verification fails, the process jumps back to the step of acquiring and parsing the target data packet sent by the LAN switch through the logic device during the communication time period of the target communication cycle.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data communication method as described in any one of claims 1 to 7.

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