Method, system and device for processing function block diagram, medium and program product
By using a graphical function block diagram processing method, the function block diagram is compiled into an instruction stream and reassembled using the FPGA core, which solves the problems of low development efficiency and insufficient flexibility in FPGA development. It realizes deep collaboration and dynamic configuration between the function block diagram and the FPGA hardware, and improves the system's flexibility and scalability.
Patent Information
- Application Number
- CN202511078683.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-11-07
AI Technical Summary
In existing technologies, function block diagrams in FPGA development suffer from low development efficiency, complex design, and insufficient flexibility, making it difficult to achieve deep collaboration between function block diagrams and FPGA hardware and efficient, dynamic hardware configuration.
A method for processing function block diagrams is provided. By obtaining graphical function modules, compiling them into instruction streams based on execution order, recombining them using the number of processing cores in the FPGA, generating a target function block chain, and realizing the parsing and execution of function modules through instruction stream broadcasting, the method supports dynamic updates of function modules.
It lowers the development threshold, improves development efficiency and system flexibility and scalability, realizes deep collaboration between function block diagrams and FPGA hardware, supports efficient and dynamic hardware configuration and execution, and simplifies system maintenance.
Smart Images
Figure CN120909570A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of FPGA (Field Programmable Gate Array), and particularly relates to a processing method, system, device, medium and program product of function block diagram. BACKGROUND
[0002] With the continuous development of automation technology, PLC (Programmable Logic Controller) and DCS (Distributed Control System) have been widely used in industrial control, process control and production automation fields. In these systems, FBD (Function Block Diagram) as a standard graphical programming language, because of its intuitive and easy-to-use characteristics, has become a common tool for engineers to design control logic. FBD abstracts complex control logic into basic function modules, and realizes the function of the control system by connecting these function modules, greatly facilitating the design and maintenance of the control system.
[0003] However, the existing FBD programming method can usually only be compiled to the CPU (Central Processing Unit) of PLC or DCS for execution. In FPGA development, FBD is usually converted into hardware description language code, such as VHDL (Very High Speed Integrated Circuit Hardware Description Language) and Verilog HDL (a hardware description language), and further compiled and synthesized to generate FPGA hardware logic. However, this process is usually a simple translation process, which requires developers to manually write hardware description language code. This method has a high learning threshold for non-professional developers, reduces development efficiency, and has certain complexity in large-scale system design. It has not effectively realized the deep cooperation between FBD and FPGA hardware, and it is difficult to realize efficient and dynamic hardware configuration and execution. Each time the function is changed, the code needs to be compiled and synthesized by the FPGA design tool, and the flexibility is insufficient. SUMMARY
[0004] The technical problem to be solved by the present disclosure is to overcome the defects of low development efficiency, complex design, insufficient flexibility and the like in the prior art, and to provide a processing method, system, device, medium and program product of function block diagram.
[0005] The present disclosure solves the above technical problems by the following technical solutions:
[0006] The present disclosure provides a processing method of function block diagram, the processing method comprising:
[0007] obtaining a function block diagram;
[0008] The function block diagram includes a plurality of graphical function modules for implementing preset functions based on data.
[0009] The function block diagram is compiled based on the execution sequence of the function modules to obtain an instruction stream.
[0010] The instruction stream includes a plurality of instruction codes corresponding to the function modules and / or data addresses corresponding to the data arranged in sequence.
[0011] Optionally, the step of compiling the function block diagram based on the execution sequence of the function modules to obtain an instruction stream includes:
[0012] A target function block chain corresponding to the function block diagram is obtained based on the execution sequence of the function modules.
[0013] The target function block chain includes a plurality of function modules arranged in sequence.
[0014] The target function block chain is compiled to obtain the instruction stream.
[0015] Optionally, the step of obtaining the target function block chain corresponding to the function block diagram based on the execution sequence of the function modules includes:
[0016] A terminal module and a starting module are determined based on the execution sequence of the function modules.
[0017] The terminal module is the last function module to be executed, and the starting module is the first function module to be executed.
[0018] An initial function block chain corresponding to the function block diagram is obtained by sequentially backtracking from the terminal module to the starting module based on the connection relationship between the function modules.
[0019] The function modules in the initial function block chain are reversely arranged to obtain the target function block chain.
[0020] Optionally, the step of compiling the target function block chain to obtain the instruction stream includes:
[0021] The target function block chain is reorganized based on the number of cores of operation cores in an FPGA.
[0022] The target function block chain after the reorganization operation is compiled to obtain the instruction stream.
[0023] Optionally, the step of reorganizing the target function block chain based on the number of cores of operation cores in an FPGA includes:
[0024] in response to the core number being greater than a chain number of the target function block chain, splitting the target function block chain;
[0025] in response to the core number being less than the chain number, merging the target function block chain;
[0026] wherein a chain number of the target function block chain after being merged or split is equal to the core number.
[0027] Optionally, after the step of compiling the function block graph based on the execution order of the function modules to obtain an instruction stream, the method further comprises:
[0028] broadcasting the instruction stream to all the function modules, so that the function modules parse the instruction stream to obtain a current instruction;
[0029] scheduling a function module whose instruction code matches the current instruction to execute.
[0030] The present disclosure also provides a processing system of a function block graph, the processing system comprising:
[0031] a function block graph obtaining module configured to obtain a function block graph;
[0032] wherein the function block graph comprises a plurality of graphical function modules, and the function modules are configured to implement a preset function based on data;
[0033] a function block graph compiling module configured to compile the function block graph based on an execution order of the function modules to obtain an instruction stream;
[0034] wherein the instruction stream comprises a plurality of instruction codes corresponding to the function modules and / or data addresses corresponding to the data arranged in sequence.
[0035] Optionally, the function block graph compiling module comprises:
[0036] a target chain obtaining unit configured to obtain a target function block chain corresponding to the function block graph based on the execution order of the function modules;
[0037] wherein the target function block chain comprises a plurality of the function modules arranged in sequence.
[0038] a target chain compiling unit configured to compile the target function block chain to obtain the instruction stream.
[0039] Optionally, the target chain obtaining unit comprises:
[0040] a module determining subunit configured to determine a terminal module and a starting module based on the execution order of the function modules;
[0041] The end point module is the last executed function module, and the start point module is the first executed function module.
[0042] An initial chain obtaining subunit is configured to obtain an initial function block chain corresponding to the function block graph by tracing back from the end point module to the start point module in sequence based on the connection relationship between the function modules.
[0043] A target chain obtaining subunit is configured to obtain the target function block chain by inversely arranging the function modules in the initial function block chain.
[0044] Optionally, the target chain compiling unit comprises:
[0045] A recombination subunit is configured to perform a recombination operation on the target function block chain based on the number of cores of operation cores in the FPGA.
[0046] A compiling subunit is configured to compile the target function block chain after the recombination operation to obtain the instruction stream.
[0047] Optionally, the recombination subunit is further configured to split the target function block chain in response to the number of cores being greater than the number of chains of the target function block chain.
[0048] In response to the number of cores being less than the number of chains, the target function block chain is merged.
[0049] The number of chains of the target function block chain after the merging or splitting is equal to the number of cores.
[0050] Optionally, the processing system further comprises:
[0051] An instruction obtaining module is configured to broadcast the instruction stream to all the function modules, so that the function modules parse the instruction stream to obtain a current instruction.
[0052] A scheduling module is configured to schedule a function module whose instruction code matches the current instruction to execute.
[0053] The present disclosure further provides an electronic device comprising a memory, a processor, and a computer program stored on the memory and configured to run on the processor, wherein the processor implements the function block graph processing method described above when executing the computer program.
[0054] The present disclosure further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the function block graph processing method described above.
[0055] The present disclosure also provides a computer program product comprising a computer program which, when executed by a processor, implements the processing method of the functional block diagram as described above.
[0056] On the basis of common sense in the art, the above-mentioned preferred conditions can be combined arbitrarily, i.e. to obtain each preferred example of the present disclosure.
[0057] The positive progress effect of the present disclosure is that:
[0058] The present disclosure enables non-professional developers to easily design and configure complex control systems through the graphical functional block diagram design, reduces the development threshold, and improves the development efficiency; by compiling the functional block diagram into a functional module-based instruction stream, the compilation and execution of the functional block diagram to FPGA hardware are solved, the flexibility, scalability and real-time performance of FPGA hardware design are significantly improved, the deep cooperation between the functional block diagram and FPGA hardware is effectively realized, efficient and dynamic hardware configuration and execution are realized; by modifying the functional module in real time, the function can be changed without modifying the FPGA code, which makes the system maintenance more convenient, further improves the development efficiency and the scalability of the system, and is suitable for industrial automation, embedded control system and other scenarios. BRIEF DESCRIPTION OF DRAWINGS
[0059] Figure 1 The first flowchart of the processing method of the functional block diagram of Embodiment 1 of the present disclosure;
[0060] Figure 2 The structure and generation schematic diagram of the instruction stream of Embodiment 1 of the present disclosure;
[0061] Figure 3 The flowchart of step S12 in the processing method of the functional block diagram of Embodiment 1 of the present disclosure;
[0062] Figure 4 The flowchart of step S121 in the processing method of the functional block diagram of Embodiment 1 of the present disclosure;
[0063] Figure 5 The structure schematic diagram of the functional block diagram of Embodiment 1 of the present disclosure;
[0064] Figure 6 The flowchart of step S122 in the processing method of the functional block diagram of Embodiment 1 of the present disclosure;
[0065] Figure 7 The second flowchart of the processing method of the functional block diagram of Embodiment 1 of the present disclosure;
[0066] Figure 8 The reconstruction schematic diagram of the functional block diagram of Embodiment 1 of the present disclosure;
[0067] Figure 9 A functional block diagram for the execution of the embodiment 1 of the present disclosure in an FPGA is shown in FIG. 1.
[0068] Figure 10 A first module of a processing system for the functional block diagram of the embodiment 2 of the present disclosure is shown in FIG. 2.
[0069] Figure 11 A second module of a processing system for the functional block diagram of the embodiment 2 of the present disclosure is shown in FIG. 3.
[0070] Figure 12 A structure of an electronic device of the embodiment 3 of the present disclosure is shown in FIG. 4. DETAILED DESCRIPTION
[0071] The present disclosure is further illustrated by the following embodiments, but the present disclosure is not limited in the scope of the embodiments.
[0072] In the embodiments of the present disclosure, the prefix words such as "first", "second" are used only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of ordinal words such as ordinal words in the embodiments of the present disclosure does not constitute a limitation on the described objects, and the description of the described objects should be referred to the description of the context in the embodiments, and should not constitute an unnecessary limitation because of the use of such prefix words. In addition, in the description of the embodiments, unless otherwise specified, the meaning of "a plurality of" is two or more.
[0073] Embodiment 1
[0074] The present embodiment provides a processing method of a functional block diagram, as shown in FIG. 1, the processing method comprises: Figure 1
[0075] S11, obtaining a functional block diagram;
[0076] The functional block diagram comprises a plurality of graphical functional modules, and the functional modules are used to implement a preset function based on data.
[0077] S12, compiling the functional block diagram based on the execution order of the functional modules to obtain an instruction stream;
[0078] The instruction stream comprises a plurality of instruction codes corresponding to the functional modules and / or data addresses corresponding to the data arranged in sequence.
[0079] Specifically, in the function block diagram design, the function modules realize the control logic and data processing in a graphical way. The function block diagram design usually uses some standard function modules to build the control program, which includes logic control function blocks, timing and counting function blocks, comparison function blocks, mathematical operation function blocks, delay and storage function blocks, reset function blocks, etc.
[0080] The logic control function blocks include AND, OR, NOT, XOR, NAND, NOR, EQ, and NEQ.
[0081] AND (AND): the output is true only when all inputs are true.
[0082] OR (OR): the output is true when any input is true.
[0083] NOT (NOT): the input is negated.
[0084] XOR (XOR): the output is true when the input signals are different, i.e., one is true and the other is false.
[0085] NAND (NAND): the output is false when all inputs are true.
[0086] NOR (NOR): the output is false when any input is true.
[0087] EQ (EQ): the output is true when the two input values are equal.
[0088] NEQ (NEQ): the output is true when the two input values are not equal.
[0089] The timing and counting function blocks include timers and counters.
[0090] The timers include TON, TOF, and TP.
[0091] TON (time-on timer): the timing starts when the input is true, and the output is true when the time reaches.
[0092] TOF (time-off timer): the timing starts when the input is false, and the output is true when the time reaches.
[0093] TP (pulse timer): a fixed-length pulse output is generated when the input is true.
[0094] The counters include CTU and CTD.
[0095] CTU (up counter): the counter increments every time the input signal is true, and the output is true when the predetermined value is reached.
[0096] CTD (Countdown Timer): The counter is decremented whenever the input signal is true, and the output is true when the predetermined value is reached.
[0097] Comparison function blocks include greater than, less than, equal to, not equal to, greater than or equal to, less than or equal to.
[0098] Greater Than (GT): Determines if the first input is greater than the second input, and outputs true if true.
[0099] Less Than (LT): Determines if the first input is less than the second input, and outputs true if true.
[0100] Equal To (EQ): Determines if the two inputs are equal, and outputs true if true.
[0101] Not Equal To (NEQ): Determines if the two inputs are not equal, and outputs true if true.
[0102] Greater Than or Equal To (GEQ): Determines if the first input is greater than or equal to the second input, and outputs true if true.
[0103] Less Than or Equal To (LEQ): Determines if the first input is less than or equal to the second input, and outputs true if true.
[0104] Mathematical operation function blocks include addition, subtraction, multiplication, division, modulus, square root, maximum, minimum.
[0105] Addition (ADD): Performs an addition operation on two input values.
[0106] Subtraction (SUB): Performs a subtraction operation on two input values.
[0107] Multiplication (MUL): Performs a multiplication operation on two input values.
[0108] Division (DIV): Performs a division operation on two input values.
[0109] Modulus (MOD): Performs a modulus operation on two input values.
[0110] Square Root (SQRT): Calculates the square root of an input value.
[0111] Maximum (MAX): Returns the larger of the input values.
[0112] Minimum (MIN): Returns the smaller of the input values.
[0113] Delay and storage function blocks include delay, data storage, data recovery.
[0114] Delay (DELAY): Provides a predetermined delay for an input signal.
[0115] Data store (STORE): save data to a specified memory location.
[0116] Data recover (RECOVER): recover data from memory.
[0117] Reset function block: reset a certain timer, counter or other functional module.
[0118] The functional modules can intuitively realize the logic of the control system in the functional block diagram through graphical programming. The graphical functional block diagram is converted into a low-level instruction stream executable on hardware such as FPGA.
[0119] All functional modules define an instruction code. Each functional module is assigned a unique function code. Each functional module corresponds to an instruction, and the instruction is encoded to obtain the instruction code. As shown in the following table, the functional module In is defined as 0x00, the functional module func0 is defined as 0x01, the functional module func1 is defined as 0x02, the functional module func2 is defined as 0x03, and the functional module Out is defined as 0x04. Figure 2
[0120] The outputs of all functional modules are mapped to a unified virtual data space. Figure 2 In the following table, the outputs of all functional modules are mapped to a virtual data space including 7 data addresses from 0 to 6.
[0121] The inputs of all functional modules are data read from the virtual data space. Figure 2 In the following table, func0 reads data from addresses 0 and 1 of the virtual data space, func1 reads data from addresses 4 and 3 of the virtual data space, func2 reads data from addresses 5 and 3 of the virtual data space, and Out reads data from address 6.
[0122] All functional modules can be configured with attribute fields, and different functional modules can be configured with different attribute fields. For example, the functional module func2 is configured with an attribute value.
[0123] According to the execution order of the functional modules, i.e. the direction of the data flow of all data, a structured instruction stream is generated, and the previous functional modules act first to ensure the correctness of logical data processing.
[0124] The instruction stream includes a plurality of instructions, and each instruction includes an instruction code (Opcode), a data address, and an attribute field value. The instruction code corresponds to a functional module, the data address includes an input address (InAddr) and an output address (OutAddr), and the attribute field value includes an attribute value corresponding to the attribute field (Attr) of the functional module and an attribute length of the functional module. The attribute length is used to represent the number of attribute values of the functional module.
[0125] In the scheme, through the graphical function block diagram design, non-professional developers can also easily design and configure complex control systems, reduce the development threshold, and improve the development efficiency; by compiling the function block diagram into a function module-based instruction stream and using an address space mapping mechanism, virtual connection between function modules is realized, the compilation and execution of the function block diagram to FPGA hardware are solved, the flexibility, scalability and real-time performance of FPGA hardware design are significantly improved, deep cooperation between the function block diagram and FPGA hardware is effectively realized, efficient and dynamic hardware configuration and execution are realized; by modifying the function module in real time, function changes can be realized without modifying the FPGA code, making system maintenance more convenient, further improving the development efficiency and scalability of the system, and being suitable for industrial automation, embedded control systems and other scenarios.
[0126] In an implementable scheme, as shown in Figure 3 Step S12 includes:
[0127] S121, based on the execution order of the function module, obtaining a target function block chain corresponding to the function block diagram;
[0128] The target function block chain includes a plurality of function modules arranged in order.
[0129] S122, compiling the target function block chain to obtain an instruction stream.
[0130] Specifically, the target function block chain can be one or more. The target function block chain is converted into a linear instruction stream according to the data dependency order. If there are multiple parallel target function block chains, each target function block chain generates an independent instruction stream, which is executed by different operation cores of the FPGA.
[0131] In the scheme, the target function block chain is obtained based on the execution order of the function module, and then the instruction stream is obtained, the same function module is not executed repeatedly, and the correctness and reliability of the execution order of the function module are guaranteed.
[0132] In an implementable scheme, as shown in Figure 4 Step S121 includes:
[0133] S1211, based on the execution order of the function module, determining the terminal module and the starting module;
[0134] The terminal module is the last function module executed, and the starting module is the first function module executed.
[0135] S1212, based on the connection relationship between the functional modules, the initial functional block chain corresponding to the functional block diagram is obtained by backtracking from the end module to the start module in sequence;
[0136] S1213, the functional modules in the initial functional block chain are arranged in reverse to obtain the target functional block chain.
[0137] Specifically, to improve the execution efficiency of the functional block diagram in the FPGA, according to the data flow relationship of the functional block diagram, the path analysis mechanism of the backtracking layering method is adopted to trace all dependent start modules from the end module, and the target functional block chain is constructed layer by layer to determine the execution order of the functional modules.
[0138] The data dependency path is established based on the connection relationship between the functional modules by backtracking from the end module to the start module. The end module can be an output module, and the start module can be an input module.
[0139] Each path represents a functional block chain, which starts from the end module and backtracks to the start module in sequence to construct a functional module block set arranged in execution order, that is, the initial functional block chain.
[0140] As shown in Figure 5 For the two paths in the diagram:
[0141] Path A1: func2 -> func1 -> func0 -> func3;
[0142] Path B1: func5 -> func1 -> func4 -> func0 -> func3 -> func3.
[0143] Path A1 and Path B1 are the initial functional block chain.
[0144] The order chain is formed by reverse sorting from the tail to the head, and the repeated functional modules are removed to obtain:
[0145] Chain A2: func3 -> func0 -> func1 -> func2;
[0146] Chain B2: func3 -> func0 -> func4 -> func1 -> func5.
[0147] Chain A2 and Chain B2 are the target functional block chain.
[0148] In the scheme, the initial function block chain corresponding to the function block diagram is obtained by backtracking from the terminal module to the starting module according to the connection relationship between the function modules, and the target function block chain is obtained by reverse arrangement, which prevents the same function module from being executed multiple times in one execution cycle, ensures the execution of the function modules in the data dependency order, and ensures the correctness and reliability of the execution of the function modules.
[0149] In an implementable scheme, as shown in Figure 6 Step S122 includes:
[0150] S1221, recombining the target function block chain based on the number of operation cores in the FPGA;
[0151] S1222, compiling the target function block chain after the recombination operation to obtain an instruction stream.
[0152] Specifically, the recombination operation includes splitting and merging.
[0153] After generating multiple target function block chains according to the function block diagram, the number of computing resources in the FPGA, i.e., the number of operation cores, needs to be considered, and the target function block chain needs to be recombined to optimize the scheduling of the instruction stream.
[0154] In the scheme, the target function block chain is recombined according to the number of parallel operation cores of the FPGA, which facilitates the maximum parallel processing of instruction stream scheduling, can greatly reduce the total delay of the system, and improves the real-time processing capability.
[0155] In an implementable scheme, step S1221 includes:
[0156] In response to the number of cores being greater than the number of chain links of the target function block chain, the target function block chain is split;
[0157] In response to the number of cores being less than the number of chain links, the target function block chain is merged;
[0158] The number of chain links of the target function block chain after merging or splitting is equal to the number of cores.
[0159] Specifically, the function block diagram is divided into multiple function block chains, and the number of operation cores in the FPGA is used to merge and split the chain links of the multiple function block chains to realize parallel execution.
[0160] If there is only one operation core in the FPGA, all target function block chains need to be merged to generate a serial link without repeated function modules.
[0161] For example, given multiple chain links, i.e., target function block chains:
[0162] Chain 1: 1-2-3-4-5;
[0163] Chain 2: 2-3-4-5-6;
[0164] Chain 3: 3-4-5-6-7;
[0165] Chain 4: 4-5-6-7-8;
[0166] Chain 5: 5-6-7-8-9;
[0167] Chain 6: 6-7-8-9-10;
[0168] The chains can be optimized and combined as follows:
[0169] Chain 7: 1-2-3-4-5-6-7-8-9-10. Each functional module in Chain 7 is executed in sequence and without repetition.
[0170] If the FPGA has multiple parallel operation cores, the target functional block chain can be split into link groups that can be executed in parallel according to the dependency relationship.
[0171] Splitting rules:
[0172] Ensure that there is no repeated functional block within each link;
[0173] Functional blocks can be cross-multiplexed between different links, but not repeated;
[0174] Preferably, the links with high path overlap are combined to maximize parallel effects.
[0175] For example, if the FPGA has 2 operation cores, it can be optimized as follows:
[0176] Link 8: 1-2-3-4-5-6-7;
[0177] Link 9: 4-5-6-7-8-9-10.
[0178] Link 8 and Link 9 can be executed in parallel, and the entire execution time is saved multiple functional module processing cycles.
[0179] In this scheme, according to the size relationship between the number of cores and the number of chains of the target functional block chain, the target functional block chain is split or combined, which can save multiple functional module processing cycles, maximize parallel processing effects, greatly reduce system total delay, and improve real-time processing capability.
[0180] In an implementable scheme, as shown in FIG. 13, after step S12, the method further includes: Figure 7
[0181] S13, broadcasting the instruction stream to all functional modules, so that the functional modules parse the instruction stream to obtain the current instruction;
[0182] S14, the function module matching the scheduling instruction code and the current instruction is executed.
[0183] Specifically, the FPGA parses and executes the instruction stream of the pre-generated function block diagram through the built-in instruction interpreter, realizing efficient mapping and running of the function block diagram to the FPGA platform. The FPGA reads the instruction stream in a sequential or parallel manner, and the execution function includes receiving input data and mapping to a virtual data space, executing the preset function of the function module, configuring the attributes of the function module, and outputting processing. The instruction stream is received on the FPGA platform, the hit function module is activated through the instruction interpreter, and the related operation is executed.
[0184] Receiving input data and mapping to a virtual data space:
[0185] Receive input 1 and write to address 0x00;
[0186] Receive input 2 and write to address 0x01;
[0187] Receive input 3 and write to address 0x02;
[0188] Receive input 4 and write to address 0x03.
[0189] Executing the preset function of the function module:
[0190] Read data from addresses 0x00 and 0x01 as two inputs of func0;
[0191] func0 performs calculation and writes the result to address 0x04;
[0192] Read data from addresses 0x04 and 0x02 as two inputs of func1;
[0193] func1 performs calculation and writes the result to address 0x05;
[0194] Read data from addresses 0x03 and 0x05 as two inputs of func2;
[0195] func2 performs calculation and writes the result to address 0x06.
[0196] Configuring the attributes of the function module:
[0197] If a function module such as func2 has an attribute field, it is initialized and configured according to the attribute value carried in the instruction before or during execution. The attribute field is used to configure the specific behavior parameters of each function module, realizing customized control of the function module.
[0198] For example, the func2 configuration attribute value is 0xXX, which can affect its internal calculation logic or behavior mode; the func2 configuration attribute length is 0x01, indicating that func2 has one attribute value.
[0199] Output processing:
[0200] Finally, the FPGA reads the output data of func2 from address 0x06 as the overall output of the function block diagram, for use by the external system or to continue participating in subsequent data link processing.
[0201] The virtual data space driven by registers or BRAM (bipolar random access memory) is used for data read and write;
[0202] The instruction interpreter drives instruction execution by cycle;
[0203] The attribute field mechanism enhances the configurability and flexibility of the function module;
[0204] The entire execution process does not require re-synthesis of the FPGA, and only dynamic instruction flow distribution can replace the control logic.
[0205] The complete execution sequence is as follows:
[0206] Receive input 1 and write to address 0x00;
[0207] Receive input 2 and write to address 0x01;
[0208] Take the data at address 0x00 to the first input of func0;
[0209] Take the data at address 0x01 to the second input of func0;
[0210] Write the output result of func0 to address 0x04;
[0211] Receive input 3 and write to address 0x02;
[0212] Take the data at address 0x04 to the first input of func1;
[0213] Take the data at address 0x02 to the second input of func1;
[0214] Write the output result of func1 to address 0x05;
[0215] Receive input 4 and write to address 0x03;
[0216] Take the data at address 0x03 to the first input of func2;
[0217] Take the data at address 0x05 to the second input of func2;
[0218] Write the output result of func2 to address 0x06;
[0219] func2 has a property with configuration value 0xxx;
[0220] Read address 0x06 as output.
[0221] Through the instruction stream of each analysis, the FPGA on the input and output of the function module is unified data mapping management. The output result of each function module is written to the specified virtual address space, and the subsequent function module is realized by reading the corresponding address data acquisition. The mechanism will reconstruct the function block diagram in FPGA through the virtual address connection, build a virtual connection network without physical connection, effectively simplify the connection relationship management between function modules, realize the running and updating of logical function. As Figure 8 shown, the logical connection and data flow between the function modules are realized through the writing and reading of the address space, and the complete function module execution link is formed. Four function modules In write data to space 0, space 1, space 2, space 3, the output of func0 is written to space 4, the output of func1 is written to space 5, and the output of func2 is written to space 6.
[0222] As Figure 9 shown, the function block diagram is executed in FPGA through an operation core. The whole system realizes the scheduling and execution of function modules in an efficient instruction driven way, and the specific execution process includes: instruction stream broadcast and function module selection, data access and logical operation.
[0223] Instruction stream broadcast and function module selection:
[0224] The instruction stream is broadcast to all function modules in the form of bus, and each function module has an independent instruction parsing unit (Decoder) built-in. When the instruction parsing unit detects that the current instruction hits the instruction code corresponding to the function module, the function module is activated, and the function module that does not hit remains idle and does not participate in this round of execution. The instructions in the instruction stream include instruction code, input address, output address, property field value, etc.
[0225] Data access and logical operation:
[0226] The activated function module reads the corresponding input data from the shared data cache space according to the address information in the instruction, and sends it to the function logic unit inside the function module for processing. After calculation, the result is written back to the specified address space for subsequent function modules.
[0227] Each function module has a fixed hardware circuit implementation in the FPGA, has exclusive data path and control logic, and ensures high-performance parallel execution capability.
[0228] The instruction stream is connected to all function modules through a unified instruction bus, and there is no need for physical point-to-point connection between function modules, which has good scalability. The addition of new function modules or the deletion of existing function modules does not affect the instruction bus structure, facilitating dynamic upgrading and maintenance of the function block diagram.
[0229] When the function block diagram is divided into multiple parallel execution links, the system can distribute the instruction stream to different operation cores for parallel scheduling and execution according to the number of operation cores in the FPGA, thereby improving the running efficiency and response speed of the overall system.
[0230] In this scheme, the instruction stream is broadcast to all function modules through a bus, and the FPGA operation core automatically activates the related function module through instruction analysis to realize data reading, operation and result writing, supports attribute configuration and dynamic update of the function module, avoids frequent recompilation of FPGA logic, supports multi-operation core parallel execution function block chain, improves processing performance, reduces development threshold, and is suitable for industrial automation, embedded control and other scenarios, breaking through the limitation of traditional FBD only applicable to PLC, and expanding the application range of function block diagram in FPGA platform.
[0231] In this embodiment, the graphical function block diagram design enables non-professional developers to easily design and configure complex control systems, reduces the development threshold, and improves the development efficiency; by compiling the function block diagram into an instruction stream based on function modules, the compilation and execution of the function block diagram to FPGA hardware are solved, the flexibility, scalability and real-time performance of FPGA hardware design are significantly improved, the deep cooperation between the function block diagram and the FPGA hardware is effectively realized, efficient and dynamic hardware configuration and execution are realized; by modifying the function module in real time, the function change can be realized without modifying the FPGA code, which makes the system maintenance more convenient, further improves the development efficiency and the scalability of the system, and is suitable for industrial automation, embedded control system and other scenarios.
[0232] Embodiment 2
[0233] Corresponding to the foregoing function block diagram processing method embodiment, the disclosure also provides an embodiment of a function block diagram processing system.
[0234] As shown in Figure 10 , the processing system comprises:
[0235] a function block diagram acquisition module 1, configured to acquire a function block diagram;
[0236] The function block diagram includes a plurality of graphical function modules, and the function modules are used to implement preset functions based on data.
[0237] The function block diagram compiling module 2 is configured to compile the function block diagram based on the execution sequence of the function modules to obtain an instruction stream.
[0238] The instruction stream includes a plurality of instruction codes corresponding to the function modules and / or data addresses corresponding to the data arranged in sequence.
[0239] In an implementable scheme, as shown in the figure, Figure 11 The function block diagram compiling module 2 includes:
[0240] The target chain obtaining unit 21 is configured to obtain a target function block chain corresponding to the function block diagram based on the execution sequence of the function modules.
[0241] The target function block chain includes a plurality of function modules arranged in sequence.
[0242] The target chain compiling unit 22 is configured to compile the target function block chain to obtain the instruction stream.
[0243] In an implementable scheme, the target chain obtaining unit 21 includes:
[0244] The module determining subunit 211 is configured to determine a terminal module and a starting module based on the execution sequence of the function modules.
[0245] The terminal module is the last executed function module, and the starting module is the first executed function module.
[0246] The initial chain obtaining subunit 212 is configured to backtrack from the terminal module to the starting module in sequence based on the connection relationship between the function modules to obtain an initial function block chain corresponding to the function block diagram.
[0247] The target chain obtaining subunit 213 is configured to reversely arrange the function modules in the initial function block chain to obtain the target function block chain.
[0248] In an implementable scheme, the target chain compiling unit 22 includes:
[0249] The recombination subunit 222 is configured to perform a recombination operation on the target function block chain based on the number of cores of the operation cores in the FPGA.
[0250] The compiling subunit 223 is configured to compile the target function block chain after the recombination operation to obtain the instruction stream.
[0251] In an implementable scheme, the recombination subunit is further configured to split the target function block chain in response to the number of cores being greater than the number of chains of the target function block chain.
[0252] In response to the number of cores being less than the number of chains, merging the target function block chains;
[0253] The number of chains of the merged or split target function block chains is equal to the number of cores.
[0254] Optionally, the processing system further comprises:
[0255] An instruction obtaining module 3 is configured to broadcast the instruction stream to all the function modules, so that the function modules parse the instruction stream to obtain the current instruction.
[0256] A scheduling module 4 is configured to schedule the function modules whose instruction codes match the current instruction to execute.
[0257] In this embodiment,
[0258] For the system embodiment, since it basically corresponds to the method embodiment, the relevant parts are described in the method embodiment. The above-described system embodiment is only illustrative, and the units described as separate components can or can not be physically separated, and the components of the unit can or can not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present disclosure.
[0259] Embodiment 3
[0260] Figure 12 A structural schematic diagram of an electronic device is shown for an example embodiment of the present disclosure, which includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and the processor implements the processing method of the function block diagram of any of the above embodiments when executing the computer program. Figure 12 The electronic device 90 shown is only an example and should not limit the functions and use range of the embodiments of the present disclosure.
[0261] As Figure 12 shown, the electronic device 90 can be in the form of a general computing device, for example, it can be a server device. The components of the electronic device 90 can include but are not limited to: the above-mentioned at least one processor 91, the above-mentioned at least one memory 92, a bus 93 connecting different system components including the memory 92 and the processor 91.
[0262] The bus 93 includes a data bus, an address bus, and a control bus.
[0263] The memory 92 can include volatile memory, such as random access memory (RAM) 921 and / or cache memory 922, and can further include read-only memory (ROM) 923.
[0264] The memory 92 can also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such as an operating system, one or more application programs, other program modules, and program data, and each of such examples or some combination thereof, can include implementation of a network environment.
[0265] The processor 91 performs various function applications and data processing by running the computer program stored in the memory 92, such as the processing method of the function block diagram provided by any of the above embodiments.
[0266] The electronic device 90 can also communicate with one or more external devices 94 such as a keyboard or a pointing device, by way of an input / output (I / O) interface 95. Furthermore, the electronic device 90 can communicate with one or more networks, such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet, by way of a network adapter 96. As illustrated, the network adapter 96 communicates with the other modules of the electronic device 90 by way of the bus 93. It should be appreciated that other hardware and / or software modules can be used in conjunction with the electronic device 90, such as a microcode, a device driver, a redundant processing unit, external disk drive arrays, a RAID system, a tape drive, and data archival storage system, etc.
[0267] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the foregoing detailed description, such division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules for embodiment.
[0268] Embodiment 4
[0269] The embodiments of the present disclosure further provide a computer readable storage medium, having stored thereon a computer program, which when executed by a processor, implements the processing method of the function block diagram provided by any of the above embodiments.
[0270] More specifically, the readable storage medium can include, but is not limited to, a portable disc, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.
[0271] Embodiment 5
[0272] The embodiments of the present disclosure also provide a computer program product comprising a computer program, which, when executed by a processor, implements the processing method of the function block diagram of any one of the above.
[0273] The program code of the computer program product for executing the present disclosure can be written in any combination of one or more programming languages, and can be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on a remote device.
[0274] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an illustration, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A method of processing a functional block diagram, characterized by, The processing method comprises: acquiring a function block diagram; wherein the function block diagram comprises a plurality of graphical function modules, and the function modules are used to implement a preset function based on data; compiling the function block diagram based on an execution sequence of the function modules to obtain an instruction stream; wherein the instruction stream comprises a plurality of instruction codes corresponding to the function modules and / or data addresses corresponding to the data arranged in sequence.
2. The processing method of a function block diagram according to claim 1, characterized by, The step of compiling the function block diagram based on the execution sequence of the function modules to obtain an instruction stream comprises: obtaining a target function block chain corresponding to the function block diagram based on the execution sequence of the function modules; wherein the target function block chain comprises a plurality of function modules arranged in sequence; compiling the target function block chain to obtain the instruction stream.
3. The processing method of a function block diagram according to claim 2, wherein, The step of obtaining the target function block chain corresponding to the function block diagram based on the execution sequence of the function modules comprises: determining a terminal module and a starting module based on the execution sequence of the function modules; wherein the terminal module is the last executed function module, and the starting module is the first executed function module; backtracking from the terminal module to the starting module based on a connection relationship between the function modules to obtain an initial function block chain corresponding to the function block diagram; reversely arranging the function modules in the initial function block chain to obtain the target function block chain.
4. The processing method of a function block diagram according to claim 2, wherein, The step of compiling the target function block chain to obtain the instruction stream comprises: reorganizing the target function block chain based on a number of cores of operation cores in an FPGA; compiling the reorganized target function block chain to obtain the instruction stream.
5. The processing method of a function block diagram according to claim 4, wherein, The step of reorganizing the target function block chain based on the number of cores of operation cores in an FPGA comprises: in response to the number of cores being greater than a number of chains of the target function block chain, splitting the target function block chain; in response to the number of cores being less than the number of chains, merging the target function block chain; wherein the number of chains of the target function block chain after merging or splitting is equal to the number of cores.
6. The processing method of a function block diagram according to any one of claims 1 to 5, characterized by, After the step of compiling the function block diagram based on the execution sequence of the function modules to obtain an instruction stream, the method further comprises: broadcasting the instruction stream to all the function modules, so that the function modules parse the instruction stream to obtain a current instruction; scheduling a function module whose instruction code matches the current instruction to execute.
7. A processing system of a function block diagram, characterized by The processing system comprises: a function block diagram acquisition module, configured to acquire a function block diagram; wherein the function block diagram comprises a plurality of graphical function modules, and the function modules are used to implement a preset function based on data; a function block diagram compiling module, configured to compile the function block diagram based on an execution sequence of the function modules to obtain an instruction stream; wherein the instruction stream comprises a plurality of instruction codes corresponding to the function modules and / or data addresses corresponding to the data arranged in sequence.
8. An electronic device comprising a memory, a processor, and a computer program stored on the memory for running on the processor, characterized in that, The processor implements the function block diagram processing method of any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the processing method of the functional block diagram of any one of claims 1 to 6.
10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the processing method of the functional block diagram of any one of claims 1 to 6.