Broadband-gap electron selective contact structure and method applied to crystalline silicon solar cell

Abstract

The invention discloses a wide-band-gap electron selective contact structure and method applied to a crystalline silicon solar cell. The wide-band-gap electron selective contact structure comprises an ultra-thin passivation layer and an electron transmission layer deposited on the ultra-thin passivation layer. The ultrathin passivation layer is composed of one layer or a laminated structure of titanium oxide, silicon oxide or an intrinsic amorphous silicon material; the electron transport layer is a ZnO / Mg / ZnO nano laminated layer; an effective transparent electron selective passivation contact structure is provided through a simple technology, the structure has the advantages of small parasitic absorption, good passivation contact performance, no pollution to the environment in the technological process and the like, carrier recombination loss at the metal crystal silicon contact position can be effectively reduced, parasitic optical absorption can be reduced, and the service life of the device is prolonged. The excellent electron extraction and transportation performance can be realized, and meanwhile, the potential of preparing a double-sided battery is realized; according to the structure, the performance of the material is regulated and controlled through the mixing effect of Mg and ZnO, high light transmittance is guaranteed, meanwhile, a good electron selectivity function is achieved, a low-temperature process is adopted, and damage of high temperature to the silicon material is avoided.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of new energy materials, in particular to a wide-bandgap electron-selective contact structure and method applied to crystalline silicon solar cells. BACKGROUND

[0002] The development of silicon-based solar cell technology has always aimed to achieve high energy conversion efficiency with low-cost materials and simple processes. Since the mid-20th century, when Bell Laboratories pioneered the concept of silicon-based photovoltaic devices and the first crystalline silicon solar cell was introduced, this field has continued to break through under the driving force of energy crises and policies. Currently, the technology of doped thin-film silicon passivated contact has become the mainstream of the industry, significantly promoting the development of crystalline silicon cell conversion efficiency. Tunnel oxide passivated contact (TOPCon) and amorphous silicon heterojunction (HJT) passivated contact are two typical doped thin-film passivated contact technologies. Among them, TOPCon technology uses a composite structure of silicon oxide dielectric layer and heavily doped polysilicon, while HJT technology uses a design of doped / intrinsic hydrogenated amorphous silicon stack, both of which have very good passivated contact performance (low dark saturation current density and low contact resistance). However, the preparation process of TOPCon technology is relatively complex; HJT technology faces high equipment costs due to the use of thin-film silicon deposition equipment (such as plasma-enhanced chemical vapor deposition PECVD). More importantly, these two types of technology usually rely on phosphorus or boron-doped amorphous silicon or polysilicon layers to achieve selective transport of carriers, which can cause significant parasitic absorption. In addition, the preparation process requires the use of silane, methane, phosphine, borane, etc. as doping sources, which are hazardous chemicals with high toxicity, flammability and explosiveness, posing environmental risks during manufacturing.

[0003] In summary, it is crucial to remove the doping process and explore non-silicon thin-film passivated contacts with small parasitic absorption and simple deposition process. Therefore, the academic and industrial communities have shifted to using wide-bandgap materials to achieve selective transport of carriers and interface passivation. This approach has the advantages of abundant resources, green and pollution-free, low cost, and simple preparation process (vacuum thermal evaporation, atomic layer deposition, spin coating, magnetron sputtering, etc.). However, most of the currently developed wide-bandgap electron-selective passivated contacts rely on a low-work-function metal cover layer, which makes them not transparent.

[0004] To address the problems in the related art, no effective solutions have been proposed so far.

[0005] Therefore, in order to solve the above problems, the application provides a wide-bandgap electron-selective contact structure and method applied to crystalline silicon solar cells. SUMMARY

[0006] In order to overcome the above technical problems, the present application aims to provide a wide band gap electron selective contact structure and method applied to crystalline silicon solar cells.

[0007] The object of the present application can be achieved by the following technical solutions:

[0008] A wide band gap electron selective contact structure, comprising an ultrathin passivation layer and an electron transport layer deposited above the ultrathin passivation layer.

[0009] The ultrathin passivation layer is composed of one layer or a stacked structure of TiO2, SiO2 or intrinsic amorphous silicon material.

[0010] The electron transport layer is a ZnO / Mg / ZnO nano stack.

[0011] As a preferred technical solution of the present application, the thickness of the ultrathin passivation layer is 0.5-5nm.

[0012] As a preferred technical solution of the present application, the thickness of the electron transport layer is 11-22nm, wherein the thickness of the bottom layer ZnO is 1-2nm, the thickness of the middle layer Mg is 5-10nm, and the thickness of the top layer ZnO is 5-10nm.

[0013] A preparation method of the wide band gap electron selective contact structure as described above, the specific steps are as follows:

[0014] S1: the preparation method of the ultrathin passivation layer comprises: ultrasonic cleaning the crystalline silicon substrate, putting the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in air atmosphere, forming a SiO2 oxide layer, thereby forming the ultrathin passivation layer.

[0015] S2: the preparation method of the electron transport layer comprises: using a high vacuum resistance evaporation coating machine to prepare the electron transport layer on the surface of the ultrathin passivation layer, first evaporating ZnO powder on the crystalline silicon substrate, then evaporating metal Mg particles on the ZnO layer, and then evaporating a layer of ZnO powder on the metal Mg particle layer to form a ZnO / Mg / ZnO structure, due to Mg diffusion, the stacked structure can be well combined into a ZnMg x O y mixture, thus forming the electron transport layer.

[0016] As a preferred technical scheme of the present application, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as an initial substrate, performing standard RCA cleaning, placing the treated silicon substrate into a box-type annealing furnace for thermal oxygen oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by a spin coating method, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0017] As a preferred technical scheme of the present application, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as an initial substrate, performing standard RCA cleaning, placing the treated silicon substrate into a box-type annealing furnace for thermal oxygen oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by a spin coating method, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0018] As a preferred technical scheme of the present application, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as an initial substrate, performing standard RCA cleaning, placing the treated silicon substrate into a box-type annealing furnace for thermal oxygen oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by a spin coating method, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0019] The application of the wide-bandgap electron-selective contact structure in the production of crystalline silicon solar cells uses the wide-bandgap electron-selective contact structure and the preparation method.

[0020] Compared with the prior art, the present application has the following beneficial effects:

[0021] 1. The present application provides an effective transparent electron-selective passivation contact structure, which has the advantages of small parasitic absorption, good passivation contact performance, and environmentally friendly process flow, can effectively reduce the carrier recombination loss at the metal crystalline silicon contact, reduce parasitic optical absorption, achieve excellent electron extraction and transport performance, and has the potential to prepare a bifacial cell.

[0022] 2. In the present application, the structure uses the mixing effect of Mg and ZnO to regulate the material performance, ensures high light transmittance, has good electron-selective function, adopts a low-temperature process to avoid damage to the silicon material caused by high temperature, and further uses the TiO2 prepared by a solution method to optimize the passivation performance of the ultra-thin passivation layer. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings belong to the scope of protection of the present application.

[0024] Figure 1 A schematic diagram of depositing an electron transport layer mixture thin film structure on a crystalline silicon substrate according to the present application;

[0025] Figure 2 A schematic diagram of depositing ZnMg x O y A graph of transmittance (T) and absorption (A) of the mixture thin film as a function of wavelength according to the present application;

[0026] Figure 3 A schematic diagram of a solar cell structure according to the present application;

[0027] Figure 4 A J-V curve of a solar cell according to the present application;

[0028] Figure 5 A J-V curve of a solar cell without the electron transport layer according to the present application.

[0029] Reference signs:

[0030] Substrate 1; Ag grid line 2; SiN x Antireflection layer 3; Al2O3 passivation layer 4; p + Emitting electrode 5; ultrathin passivation layer 6; electron transport layer 7; tin-doped indium oxide (ITO) antireflection layer 8; Ag electrode 9. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. Based on the embodiments described in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0032] In the following description of the present specification, the term "and / or" is used to describe the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the cases of A alone, B alone and A and B together. Wherein, A, B can be singular or plural; the symbol " / " represents the meaning of "or".

[0033] In the following description of the specification, the term "at least one" means one or more, and the term "multiple" means two or more. "At least one of the following" or similar expressions means any combination of the items, including any combination of single or multiple items. For example, "at least one of A, B or C", or "at least one of A, B and C", can mean any one of A, B, C, or A+B, or A+C, or B+C, or A+B+C, where A, B, C can be single or multiple.

[0034] In the following description of the specification, the order of the serial numbers does not mean the order of execution, and part or all of the steps can be executed in parallel or in sequence. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the execution process of the embodiment.

[0035] In the following description of the specification, the numerical range should be understood to also specifically disclose each intermediate value between the upper limit and the lower limit of the range. Any stated value or intermediate value in the stated range, as well as any other stated value or intermediate value in the stated range, is also included in the embodiment, and the upper limit and lower limit of the smaller range can be independently included or excluded from the range.

[0036] Unless otherwise specified, the technical / scientific terms used in the specification have the meanings commonly understood by those skilled in the art. Although only preferred materials and methods are described in the specification, any method and material similar or equivalent to those described in the specific examples or test examples can also be used. All documents mentioned in the specification are incorporated by reference to disclose and describe the methods and / or materials related to the documents. In the event of any conflict between the content of the specification and any incorporated document, the content of the specification shall prevail.

[0037] A wide band gap electron selective contact structure, comprising an ultrathin passivation layer and an electron transport layer deposited above the ultrathin passivation layer;

[0038] The ultrathin passivation layer is composed of one or a stacked structure of TiO2, SiO2 or intrinsic amorphous silicon material;

[0039] The electron transport layer is a ZnO / Mg / ZnO nanolaminate.

[0040] Specifically, the thickness of the ultrathin passivation layer is 0.5-5nm.

[0041] Specifically, the thickness of the electron transport layer is 11-22nm, wherein the thickness of the bottom layer ZnO is 1-2nm, the thickness of the middle layer Mg is 5-10nm, and the thickness of the top layer ZnO is 5-10nm.

[0042] A preparation method of a wide band gap electron selective contact structure, the specific steps are as follows: A preparation method of a wide band gap electron selective contact structure, the specific steps are as follows:

[0043] S1: The preparation method of the ultra-thin passivation layer comprises: ultrasonic cleaning the crystalline silicon substrate, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, thereby forming the ultra-thin passivation layer.

[0044] S2: The preparation method of the electron transport layer comprises: using a high-vacuum resistance evaporation coating machine to prepare the electron transport layer on the surface of the ultra-thin passivation layer, first evaporating ZnO powder on the crystalline silicon substrate, then evaporating metal Mg particles on the ZnO layer, and then evaporating a layer of ZnO powder on the metal Mg particle layer to form a ZnO / Mg / ZnO structure. Due to the diffusion of Mg, the stacked structure can be well combined into a ZnMg x O y mixture, thereby forming the electron transport layer.

[0045] Specifically, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the crystalline silicon substrate on a glue spreader to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0046] Specifically, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning, then placing the crystalline silicon substrate on a glue spreader to prepare a TiO2 oxide layer on the surface of the substrate by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0047] Specifically, the preparation method of the ultra-thin passivation layer further comprises: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning after texturing the surface, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the crystalline silicon substrate on a glue spreader to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

[0048] The application of a wide-bandgap electron-selective contact structure in the production of crystalline silicon solar cells uses the wide-bandgap electron-selective contact structure and the preparation method described above.

[0049] Example 1:

[0050] The electron transport layer is deposited on the crystalline silicon substrate, and a ZnO / Mg / ZnO stacked film is sequentially deposited to form ZnMgx O y Mixture, deposition of ZnMg on crystalline silicon substrate x O y Mixture thin film structure schematic diagram as shown in the accompanying Figure 1 The specific preparation method is as follows:

[0051] S1, ultrasonic cleaning of glass substrate for 30 min;

[0052] S2, using high vacuum resistance evaporation coating machine to prepare electron transport layer on the surface of crystalline silicon substrate, the evaporation rate of ZnO powder and metal Mg particles is The layer structure is composed of 1 nm ZnO, 7 nm Mg, and 7 nm ZnO (ZnO / Mg / ZnO structure). Due to the diffusion of Mg, the stack structure can be well combined into a layer of ZnMg x O y Mixture.

[0053] At this point, the electron transport layer is formed, and the transmittance (T) and absorption (A) of the ZnMg xO y mixture thin film deposited on the crystalline silicon substrate as a function of wavelength are shown in the accompanying Figure 2 As shown, in the 600-1200 nm waveband, the structure has good light transmittance and low absorption. Compared with the sum of the absorption rates of Mg and ZnO layers alone, the ZnO / Mg / ZnO stack structure has lower light absorption, indicating that the stack film diffuses and reacts to form ZnMg x O y Mixture. Through X-ray photoelectron spectroscopy, it can be found that the composition of the mixed film is complex, such as Mg element, which has both oxidized Mg and metallic Mg.

[0054] Example 2:

[0055] The ultrathin passivation layer, electron transport layer, tin-doped indium oxide (ITO) antireflection layer, and silver (Ag) electrode are deposited on the N-type crystalline silicon substrate, and the contact resistance of the wide-bandgap electron selective contact structure is measured by the transfer length method (TLM). The specific preparation method is as follows:

[0056] S1, using N-type single crystal silicon wafer as the initial substrate, performing standard RCA cleaning;

[0057] S2, placing the treated sample into a box-type annealing furnace for thermal oxidation, heating at 300℃ in air atmosphere and maintaining oxidation for 30 min to form a layer of SiO2 oxide layer, thereby forming an ultrathin tunneling passivation layer;

[0058] S3, cover the surface of the ultra-thin tunneling passivation layer with a TLM mask, and then prepare an electron transport layer on the surface thereof, the process being completely identical to the preparation method in Embodiment 1;

[0059] S4, deposit a tin-doped indium oxide (ITO) anti-reflection layer as a cover layer on the surface of the electron transport layer by magnetron sputtering, the tin-doped indium oxide (ITO) target (In2O3: SnO2= 98:2 wt%, purity 99.99%) reaching 7x10 -5 Pa before sputtering;

[0060] S5, prepare a silver (Ag) electrode on the surface of the tin-doped indium oxide (ITO) anti-reflection layer by magnetron sputtering.

[0061] The contact resistance of the contact structure of the embodiment is 0.96 mΩ·cm 2 , which exhibits a low contact resistance on the surface of crystalline silicon and embodies the ZnMg x O y The electron transport layer has good electron selection performance.

[0062] Embodiment 3:

[0063] An ultra-thin passivation layer, an electron transport layer, a tin-doped indium oxide (ITO) anti-reflection layer and a silver (Ag) electrode are deposited on an N-type crystalline silicon substrate, and the contact resistance of the wide-bandgap electron-selective contact structure is determined by the transfer length method (TLM), and the specific preparation method is as follows:

[0064] S1, use an N-type single-crystal silicon wafer as the initial substrate, perform texturing on the surface, and then perform standard RCA cleaning;

[0065] S2, place the treated sample in a box-type annealing furnace for thermal oxidation, heat at 200°C in an air atmosphere for 30 min of oxidation, form a SiO2 oxide layer, then place the sample on a spin coater, prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by spin coating, the volume of the TiO2 solution is 50 μL, the rotation speed is 4000 rpm / min, the spin coating time is 30 s, the heating annealing temperature is 300°C, and the heating annealing time is 8 min, thereby forming an ultra-thin tunneling passivation layer;

[0066] S3, cover the surface of the ultra-thin tunneling passivation layer with a TLM mask, and then prepare an electron transport layer, a tin-doped indium oxide (ITO) anti-reflection layer and a silver (Ag) electrode on the surface thereof, the process being completely identical to the preparation method in Embodiments 1 and 2.

[0067] The contact resistance of the structure of the embodiment is 19.7 mΩ·cm measured by a transfer length method (TLM) 2 The structure exhibits a low contact resistance on the surface of crystalline silicon, and embodies ZnMg x O y The electron transport layer has good electron selection performance.

[0068] Embodiment 4:

[0069] An ultrathin passivation layer, an electron transport layer, an indium tin oxide (ITO) antireflection layer, and a silver (Ag) electrode are deposited on an N-type crystalline silicon substrate, and the contact resistance of the wide-bandgap electron selective contact structure is measured by a transfer length method (TLM). The specific preparation method is as follows:

[0070] S1, an N-type monocrystalline silicon wafer is used as an initial substrate, and standard RCA cleaning is performed;

[0071] S2, the treated sample is placed in a box-type annealing furnace for thermal oxidation, heated to 200℃ in an air atmosphere, and kept for oxidation for 30 min to form a SiO2 oxide layer, thereby forming an ultrathin tunneling passivation layer;

[0072] S3, a TLM mask plate is covered on the surface of the ultrathin tunneling passivation layer, and an electron transport layer is prepared on the surface thereof by using a high-vacuum resistance evaporation coating machine. The evaporation rates of ZnO powder and metal Mg particles are both The layer structure is composed of 1 nm ZnO, 10 nm Mg, and 10 nm ZnO (ZnO / Mg / ZnO structure). Due to Mg diffusion, the stacked structure can be well combined into a ZnMg x O y mixture.

[0073] S4, an indium tin oxide (ITO) antireflection layer and a silver (Ag) electrode are prepared on the surface of the electron transport layer by using a magnetron sputtering, and the process is completely the same as the preparation method in Embodiment 2.

[0074] The contact resistance of the structure of the embodiment is 0.2 mΩ·cm measured by a transfer length method (TLM) 2 The structure exhibits a low contact resistance on the surface of crystalline silicon, and embodies ZnMg x O y The electron transport layer has good electron selection performance.

[0075] Embodiment 5:

[0076] A super-thin passivation layer, an electron transport layer, an ITO anti-reflective layer and a silver electrode are deposited on an N-type silicon substrate, and the contact resistance of the wide-bandgap electron selective contact structure is determined by a transfer length method (TLM) as follows:

[0077] S1, an N-type monocrystalline silicon wafer is used as an initial substrate, and standard RCA cleaning is performed;

[0078] S2, the treated sample is placed in a box-type annealing furnace for thermal oxidation, heated to 200°C in an air atmosphere, and kept for 30 min for oxidation to form a SiO2 oxide layer, thereby forming a super-thin tunneling passivation layer;

[0079] S3, a TLM mask plate is covered on the surface of the super-thin tunneling passivation layer, and an electron transport layer is prepared on the surface by using a high-vacuum resistance evaporation coating machine, and the evaporation rates of ZnO powder and metal Mg particles are The layer structure is composed of 1 nm ZnO, 5 nm Mg and 5 nm ZnO (ZnO / Mg / ZnO structure), and due to Mg diffusion, the stack structure can be well combined into a ZnMg x O y mixture.

[0080] S4, an ITO anti-reflective layer and a silver electrode are prepared on the surface of the electron transport layer by using a magnetron sputtering, and the process is the same as the preparation method in Example 2.

[0081] The contact resistance of the structure of the present embodiment is 7.8 mΩ·cm 2 , which shows that the ZnMg x O y electron transport layer has good electron selection performance.

[0082] Example 6:

[0083] A super-thin passivation layer, an electron transport layer, an ITO anti-reflective layer and a silver electrode are deposited on an N-type silicon substrate, and the contact resistance of the wide-bandgap electron selective contact structure is determined by a transfer length method (TLM) as follows:

[0084] S1, an N-type monocrystalline silicon wafer is used as an initial substrate, and standard RCA cleaning is performed;

[0085] S2. The treated sample is placed in a box annealing furnace for thermal oxidation. It is heated to 200℃ in an air atmosphere and maintained for 30 min to form a SiO2 oxide layer. Then, the sample is placed on a spin coater, and a TiO2 oxide layer is prepared on the surface of the SiO2 oxide layer by spin coating. The volume of TiO2 solution is 50 μL, the rotation speed is 4000 rpm / min, the spin coating time is 30 s, the heating annealing temperature is 300℃, and the heating annealing time is 8 min, thus forming an ultrathin tunneling passivation layer.

[0086] S3. Cover the surface of the ultrathin tunneling passivation layer with a TLM mask, and then prepare an electron transport layer on its surface. The process is exactly the same as the preparation method in Example 1.

[0087] S4. An aluminum-doped zinc oxide (AZO) antireflection layer was prepared by magnetron sputtering and deposited on the surface of the electron transport layer as a capping layer. The aluminum-doped zinc oxide (AZO) target (ZnO:Al2O3 = 98:2wt%, purity 99.99%) was sputtered after the background vacuum reached 7×10-5Pa.

[0088] S5. A silver (Ag) electrode was prepared on the surface of an aluminum-doped zinc oxide (AZO) antireflection layer by magnetron sputtering.

[0089] The contact resistance of the structure in this embodiment was measured to be 12.81 mΩ·cm using the transfer length method (TLM). 2 This structure exhibits low contact resistance on the crystalline silicon surface, reflecting the properties of ZnMg. x O y The electron transport layer has good electron selectivity.

[0090] Example 7:

[0091] A wide-bandgap electron-selective contact structure is applied to a solar cell, the structure of which is shown in the attached figure. Figure 3 As shown, it includes: a base 1, and p are sequentially provided on one side of the base 1. + Emitter 5, Al2O3 passivation layer 4, SiN x An antireflection layer 3 and an Ag gate line 2 are sequentially disposed on the other side of the substrate 1, along with an ultrathin passivation layer 6, an electron transport layer 7, a tin-doped indium oxide (ITO) antireflection layer 8, and an Ag electrode 9. The fabrication method is as follows:

[0092] S1. Using an N-type single-crystal silicon wafer as the initial substrate, texturing and cleaning are performed.

[0093] S2. A 6 nm thick P layer is prepared on one side of the N-type substrate 1 using a boron diffusion process. + Emitter 5;

[0094] S3, using atomic layer deposition (ALD) technology to deposit a 7 nm thick Al2O3 passivation layer 4 on the p+emitter 5; + A 7 nm thick Al2O3 passivation layer 4 is deposited on the p+emitter 5 using atomic layer deposition (ALD) technology;

[0095] S4, a 70 nm SiN x anti-reflection layer 3 is deposited on the Al2O3 passivation layer 4 using plasma enhanced chemical vapor deposition (PECVD) technology;

[0096] S5, Ag grid lines 2 are prepared on the surface of the SiN x anti-reflection layer 3 by screen printing using silver paste, the thickness of the Ag grid lines 2 is 250 nm, and the distance between adjacent Ag grid lines 2 is 0.2 mm;

[0097] S6, the other side of the substrate 1 is placed above an HF solution, and cleaning is performed using the volatile gas thereof for about 2 minutes to remove the naturally grown oxide layer;

[0098] S7, the treated sample is placed in a box-type annealing furnace for thermal oxidation, heated to 300°C in an air atmosphere and maintained for 30 minutes of oxidation to form a SiO2oxide layer. Subsequently, the sample is placed on a spin coater, and a TiO2oxide layer is prepared on the surface of the SiO2oxide layer by spin coating, the volume of the TiO2solution is 50 μL, the rotation speed is 4000 rpm / min, the spin coating time is 30 seconds, the heating annealing temperature is 300°C, and the heating annealing time is 8 minutes. Thus, an ultrathin passivation layer 6 is formed;

[0099] S8, the process for preparing the electron transport layer 7 and the tin-doped indium oxide (ITO) anti-reflection layer 8 on the surface of the ultrathin passivation layer 6 is exactly the same as the preparation method in Examples 1 and 2;

[0100] S9, a silver (Ag) electrode 9 is prepared on the surface of the tin-doped indium oxide (ITO) anti-reflection layer 8 by magnetron sputtering.

[0101] The open-circuit voltage of the solar cell of this example is 0.64 V, the short-circuit current density is 40.3 mA / cm 2 , the fill factor is 83.83%, and the photoelectric conversion efficiency is 21.5%. The J-V curve of this example is shown in FIG. 4. Figure 4

[0102] Comparative Example 1

[0103] In this comparative example, a wide-bandgap electron-selective contact structure is applied to a solar cell. The structure of the cell device includes, from top to bottom, a substrate 1, a p+emitter 5, an Al2O3 passivation layer 4, a SiN x ​The substrate consists of an antireflection layer 3, Ag gate lines 2, and on the other side, an ultrathin passivation layer 6, an ITO antireflection layer 8, and an Ag electrode 9, arranged sequentially. The fabrication method is as follows:

[0104] S1. Using an N-type single-crystal silicon wafer as the initial substrate, texturing and cleaning are performed.

[0105] S2. A 6 nm thick P+ emitter 5 is prepared on one side of the N-type substrate 1 using a boron diffusion process.

[0106] S3. A 7 nm thick Al2O3 passivation layer 4 is deposited on the p+ emitter 5 using atomic layer deposition (ALD) technology;

[0107] S4. A 70 nm SiNx antireflection layer 3 is deposited on the Al2O3 passivation layer 4 using plasma-enhanced chemical vapor deposition (PECVD) technology.

[0108] S5. Applying silver paste to SiN via screen printing. x Ag gate lines 2 are fabricated on the surface of the anti-reflection layer 3. The thickness of the Ag gate lines 2 is 250 nm, and the distance between adjacent Ag gate lines 2 is 0.2 mm.

[0109] S6. Place the other side of substrate 1 above the HF solution and clean it using its volatile gases for about 2 minutes to remove the naturally grown oxide layer.

[0110] S7. The treated sample is placed in a box annealing furnace for thermal oxidation. It is heated to 300°C in air atmosphere and kept oxidized for 30 minutes to form a SiO2 oxide layer, thereby forming an ultrathin passivation layer 6.

[0111] S8. A tin-doped indium oxide (ITO) antireflection layer 8 is prepared on the surface of the ultrathin passivation layer 6, and the process is exactly the same as the preparation method in Example 2.

[0112] S9. An Ag electrode 9 is prepared on the surface of a tin-doped indium oxide (ITO) antireflection layer 8 by magnetron sputtering.

[0113] The solar cell prepared in this comparative example has an open-circuit voltage of 0.525V and a short-circuit current density of 27.8mA / cm². 2 The fill factor is 38.6%, and the photoelectric conversion efficiency is 5.8%. The JV curve for this comparative example is shown below. Figure 5 As shown.

[0114] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0115] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some or all of the technical features thereof can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present application.

Claims

1. A wide bandgap electronic selective contact structure, characterized by: The ultra-thin passivation layer and an electron transport layer deposited above the ultra-thin passivation layer; The ultra-thin passivation layer is composed of one layer or a stack structure of TiO2, SiO2 or intrinsic amorphous silicon material; The electron transport layer is a ZnO / Mg / ZnO nano stack.

2. The wide bandgap electronic selective contact structure of claim 1, wherein: The thickness of the ultra-thin passivation layer is 0.5-5nm.

3. The wide bandgap electronic selective contact structure of claim 1, wherein: The thickness of the electron transport layer is 11-22nm, wherein the thickness of the bottom layer ZnO is 1-2nm, the thickness of the middle layer Mg is 5-10nm, and the thickness of the top layer ZnO is 5-10nm.

4. A method of producing a wide bandgap electronically selective contact structure as claimed in any one of claims 1 to 3, characterised by: The specific steps are as follows: S1: The preparation method of the ultra-thin passivation layer includes: ultrasonic cleaning the crystalline silicon substrate, performing standard RCA cleaning, removing the oxide layer in the HF solution, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, thereby forming the ultra-thin passivation layer; S2: the preparation method of the electron transport layer comprises the following steps: using a high-vacuum resistance evaporation coating machine to prepare an electron transport layer on the surface of the ultra-thin passivation layer, first evaporating ZnO powder on the crystalline silicon substrate, then evaporating metal Mg particles on the ZnO layer, and then evaporating a layer of ZnO powder on the metal Mg particle layer to form a ZnO / Mg / ZnO structure, and due to Mg diffusion, the laminated structure can be well combined into a layer of ZnMg x O y mixture, thus forming an electron transport layer.

5. The method of claim 4, wherein: The preparation method of the ultra-thin passivation layer further includes: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning, removing the oxide layer in the HF solution, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the crystalline silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

6. The method of claim 4, wherein: The preparation method of the ultra-thin passivation layer further includes: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning, removing the oxide layer in the HF solution, then placing the crystalline silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the substrate by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

7. The method of claim 4, wherein: The preparation method of the ultra-thin passivation layer further includes: taking an N-type monocrystalline silicon wafer as the initial substrate, performing standard RCA cleaning after texturing the surface, placing the treated crystalline silicon substrate into a box-type annealing furnace for thermal oxidation, heating and maintaining oxidation in an air atmosphere, forming a SiO2 oxide layer, then placing the crystalline silicon substrate on a spin coater to prepare a TiO2 oxide layer on the surface of the SiO2 oxide layer by spin coating, and then performing heating annealing treatment, thereby forming the ultra-thin passivation layer.

8. The use of the wide-bandgap electron-selective contact structure according to any one of claims 1-3 in the production of crystalline silicon solar cells.

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