Shift register, gate drive circuit and display panel

Abstract

The invention discloses a shift register, a gate drive circuit and a display panel. A first pull-down control module and a first pull-down maintenance module are electrically connected with a second node, so that a second control signal is transmitted to the second node through the first pull-down control module according to a reset control signal; the first pull-down maintaining module is connected with a current path between the first node and the second power supply end, so that a signal of the first node is ineffective level, an output transistor electrically connected with the first node can be turned off in time under the action of the signal of the first node, the duration of forward bias stress borne by the output transistor is shortened, and the reliability of the output transistor is improved. The threshold voltage drift of the output transistor is improved, and the reliability of the shift register is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register, a gate drive circuit and a display panel. BACKGROUND

[0002] If the node electrically connected to the control end of the output transistor in the shift register is not pulled down in time, the output transistor will be subjected to a long positive bias stress, which will affect the volt-ampere characteristic of the output transistor, cause the threshold voltage of the output transistor to drift, and then affect the reliability of the shift register. SUMMARY

[0003] The present application provides a shift register, a gate drive circuit and a display panel, which are used to improve the problem of low working reliability of the shift register.

[0004] The present application provides a shift register, which comprises a first control module, a first pull-down maintaining module, a first pull-down control module and an output module. The first control module is electrically connected with a first node and a first power supply end, and is configured to connect the current path between the first node and the first power supply end according to a first control signal, so that the signal of the first node has a corresponding effective level. The first pull-down maintaining module is electrically connected with the first node, a second node and a second power supply end, and is configured to control the electrical connection between the first node and the second power supply end according to the signal of the second node. The first pull-down control module is electrically connected with the second node, and is configured to transmit a second control signal to the second node according to a reset control signal, so as to connect the current path between the first node and the second power supply end through the first pull-down maintaining module, so that the signal of the first node is an invalid level. The output module comprises an output transistor, the control end of the output transistor is electrically connected with the first node, and the output module is configured to control the electrical connection between the clock line and the signal output end of the shift register according to the signal of the first node.

[0005] The present application also provides a gate drive circuit comprising a plurality of any of the above-mentioned shift registers. When the first control module is configured to transmit the signal supplied by the first power supply end to the first node according to the first control signal, so that the signal of the first node has a corresponding effective level, the first control signal corresponding to the first m shift registers in the plurality of shift registers is a start signal, the first control signal corresponding to the n-level shift register in the plurality of shift registers is a signal output by the n-m-level shift register, 1≤m<n, n-m≥1. Alternatively, when the first control module is configured to transmit the signal supplied by the first power supply end to the first node according to the first control signal, so that the signal of the first node has a corresponding invalid level, the first control signal corresponding to the x-level shift register is a signal output by the x+y-level shift register, x≥1, y≥1.

[0006] The application further provides a display panel comprising any of the above-mentioned gate drive circuits. In a first scanning mode of the display panel, the first control module of each shift register is configured to connect the first node and the first power supply end in electrical connection according to the effective level of the first control signal, so that the signal of the first node has the corresponding effective level; in a second scanning mode of the display panel, the first control module of each shift register is configured to connect the first node and the first power supply end in electrical connection according to the effective level of the first control signal, so that the signal of the first node has the invalid level.

[0007] The application further provides another display panel comprising any of the above-mentioned gate drive circuits. In the display panel, the first control module of each shift register is configured to connect the first node and the first power supply end in electrical connection according to the effective level of the first control signal, so that the signal of the first node has the corresponding effective level. The first pull-down control module of the last m shift registers in the plurality of shift registers is configured to transmit the second control signal to the second node according to the reset control signal, so that the first pull-down maintenance module connects the first node and the second power supply end in electrical connection, and the first node of the last m shift registers has the invalid level.

[0008] The above technical solution connects the first pull-down control module and the second node in electrical connection in the shift register, and connects the first pull-down maintenance module and the second node in electrical connection, so that the first pull-down control module transmits the second control signal to the second node according to the reset control signal, so that the first pull-down maintenance module connects the first node and the second power supply end in electrical connection, so that the signal of the first node is invalid, and then the output transistor connected with the first node can be turned off in time under the action of the signal of the first node, the time length of the forward bias stress suffered by the output transistor is shortened, the threshold voltage drift of the output transistor is improved, and the reliability of the shift register is improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained according to the structures shown in the drawings without creative labor.

[0010] Figures 1A-1B It is a principle block diagram of the shift register of the embodiment of the application;

[0011] Figures 2A-2D It is a circuit structure schematic diagram of the shift register of the embodiment of the application;

[0012] Figures 3A-3B A timing diagram corresponding to the shift register of the embodiment of the present application;

[0013] Figures 4A-4D A structural schematic diagram of the gate drive circuit of the embodiment of the present application;

[0014] Figures 5A-5B A timing diagram corresponding to the gate drive circuit of the embodiment of the present application;

[0015] Figures 6A-6B A structural schematic diagram of the display panel of the embodiment of the present application;

[0016] Figures 7A-7D A simulation timing diagram of the first scanning mode and the second scanning mode corresponding to the gate drive circuit of the embodiment of the present application.

[0017] Figure 8 A structural schematic diagram of the display panel before and after cutting of the embodiment of the present application;

[0018] Figure 9 A structural schematic diagram of another display panel of the embodiment of the present application;

[0019] Figures 10A-10B A simulation comparison timing diagram of the signal of the first node of the embodiment of the present application.

[0020] The implementation, functional features and advantages of the embodiments of the present application will be further described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0022] In addition, the description such as "first", "second" and the like in the embodiments of the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that the technical solutions can be realized by those skilled in the art. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope claimed by the present application.

[0023] Figures 1A-1B is a principle block diagram of a shift register of an embodiment of the present application. The present application provides a shift register GA, comprising a first control module 101, a first pull-down maintaining module 201, a first pull-down control module 301 and an output module 401.

[0024] The first control module 101 is electrically connected with the first node No1 and the first power terminal Vs1, and the first control module 101 is configured to connect the current path between the first node No1 and the first power terminal Vs1 according to the first control signal Sc1, so that the signal of the first node No1 has a corresponding active level.

[0025] In some embodiments, the first control module 101 is configured to connect the electrical connection between the first node No1 and the first power terminal Vs1 according to the active level of the first control signal Sc1, and the first control module 101 is configured to disconnect the electrical connection between the first node No1 and the first power terminal Vs1 according to the inactive level of the first control signal Sc1.

[0026] It should be noted that the active level of the signal can refer to the level that makes the device controlled by the signal conduct or start, and the inactive level of the signal can refer to the level that makes the device controlled by the signal cut off or close.

[0027] In some embodiments, the active level of the signal can refer to one of the high level and the low level, and the inactive level of the signal can refer to the other of the high level and the low level.

[0028] Optionally, the first power terminal Vs1 can be a constant voltage terminal. In some embodiments, the first power terminal Vs1 can be an output terminal of a power driving chip.

[0029] Optionally, the first power terminal Vs1 can be a low voltage terminal or a high voltage terminal.

[0030] Please continue to refer to Figures 1A-1B The first pull-down maintaining module 201 is electrically connected with the first node No1, the second node No2 and the second power terminal VssQ, and the first pull-down maintaining module 201 is configured to control the electrical connection between the first node No1 and the second power terminal VssQ according to the signal of the second node No2.

[0031] In some embodiments, the first pull-down maintaining module 201 is configured to connect the electrical connection between the first node No1 and the second power terminal VssQ according to the active level of the signal of the second node No2, and the first pull-down maintaining module 201 is configured to disconnect the electrical connection between the first node No1 and the second power terminal VssQ according to the inactive level of the signal of the second node No2.

[0032] Optionally, the second power supply end VssQ can be a constant voltage end. The second power supply end VssQ can be a low voltage end or a high voltage end.

[0033] In some embodiments, when the effective level used by the device controlled by the signal of the first node No1 is a high level, the second power supply end VssQ can be a low voltage end to make the signal of the first node No1 have an invalid level by using the second power supply end VssQ.

[0034] Please continue to refer to Figures 1A-1B The first pull-down control module 301 is electrically connected with the second node No2, and the first pull-down control module 301 is configured to transmit the second control signal LC1 to the second node No2 according to the reset control signal Res, so as to connect the current path between the first node No1 and the second power supply end VssQ through the first pull-down maintenance module 201, so that the signal of the first node No1 is an invalid level.

[0035] In some embodiments, the first pull-down control module 301 is configured to connect the electrical connection between the first signal line for transmitting the second control signal LC1 and the second node No2 according to the effective level of the reset control signal Res, so as to transmit the second control signal LC1 to the second node No2. The first pull-down control module 301 is configured to disconnect the electrical connection between the first signal line for transmitting the second control signal LC1 and the second node No2 according to the invalid level of the reset control signal Res.

[0036] Please continue to refer to Figures 1A-1B The output module 401 includes an output transistor To1, and the control end of the output transistor To1 is electrically connected with the first node No1. The output module 401 is configured to control the electrical connection between the clock line CL and the signal output end OUT1 of the shift register GA according to the signal of the first node No1. The signal output end OUT1 can be configured as a gate control signal Scan.

[0037] In some embodiments, the output module 401 is configured to connect the electrical connection between the clock line CL and the signal output end OUT1 according to the effective level of the signal of the first node No1, and the output module 401 is configured to disconnect the electrical connection between the clock line CL and the signal output end OUT1 according to the invalid level of the signal of the first node No1.

[0038] Optionally, the output transistor To1 can be a silicon transistor or an oxide transistor. The silicon transistor can include monocrystalline silicon, polycrystalline silicon or amorphous silicon material. The oxide transistor can include indium gallium zinc oxide or indium zinc oxide material.

[0039] Optionally, the output transistor To1 can be a P-type transistor or an N-type transistor.

[0040] It can be understood that when the output transistor To1 is a P-type transistor, the active level of the signal of the first node No1 corresponds to a low level, and the inactive level of the signal of the first node No1 corresponds to a high level. When the output transistor To1 is an N-type transistor, the active level of the signal of the first node No1 corresponds to a high level, and the inactive level of the signal of the first node No1 corresponds to a low level.

[0041] By setting the first pull-down control module 301 in the shift register GA, the first pull-down control module 301 is used to control the first pull-down maintenance module 201 to connect the current path between the first node No1 and the second power supply end VssQ, so that the signal of the first node No1 has an inactive level, so that the output transistor To1 electrically connected to the first node No1 can be turned off in time under the action of the signal of the first node No1, the duration of the forward bias stress suffered by the output transistor To1 is shortened, the threshold voltage drift of the output transistor To1 is improved, and the reliability of the shift register GA is improved.

[0042] Optionally, in order to speed up the speed of the signal of the first node No1 jumping from the active level to the inactive level, the shift register GA can further include a reset module 500, as shown in Figures 1A-1B .

[0043] The reset module 500 is electrically connected to the first node No1 and the second power supply end VssQ, and the reset module 500 is configured to control the electrical connection between the first node No1 and the second power supply end VssQ according to the reset control signal Res.

[0044] In some embodiments, the reset module 500 is configured to connect the electrical connection between the first node No1 and the second power supply end VssQ according to the active level of the reset control signal Res, so as to cooperate with the first pull-down control module 301 and the first pull-down maintenance module 201 to commonly connect the electrical connection between the first node No1 and the second power supply end VssQ, thereby speeding up the speed of the electrical signal supplied by the first power supply end Vs1 to the first node No1, and then speeding up the speed of the signal of the first node No1 jumping from the active level to the inactive level.

[0045] Optionally, in order to shorten the duration of the forward bias stress suffered by the output transistor To1 while reducing the working duration of the first pull-down control module 301 and the first pull-down maintenance module 201, so that the first pull-down control module 301 and the first pull-down maintenance module 201 have better performance, the shift register GA can further include a second pull-down maintenance module 202 and a second pull-down control module 302, as shown in Figure 1B .

[0046] The second pull-down maintaining module 202 is electrically connected with the first node No1, the third node No3 and the second power supply end VssQ, and is configured to control the electrical connection between the first node No1 and the second power supply end VssQ according to the signal of the third node No3.

[0047] The second pull-down control module 302 is electrically connected with the third node No3, and is configured to transmit the third control signal LC2 to the third node No3 according to the reset control signal Res, so as to control the second pull-down maintaining module 202 to connect the electrical connection between the first node No1 and the second power supply end VssQ. Wherein, the phase of the second control signal LC1 and the phase of the third control signal LC2 are opposite.

[0048] By setting the second pull-down control module 302 and the second pull-down maintaining module 202, and making the phase of the second control signal LC1 and the phase of the third control signal LC2 opposite, the second pull-down control module 302 and the second pull-down maintaining module 202 can be alternately operated with the first pull-down control module 301 and the first pull-down maintaining module 201, so as to shorten the working time of the first pull-down control module 301 and the first pull-down maintaining module 201, and facilitate the first pull-down control module 301 and the first pull-down maintaining module 201 to have excellent working performance.

[0049] In some embodiments, the second pull-down maintaining module 202 is configured to connect the electrical connection between the first node No1 and the second power supply end VssQ according to the effective level of the signal of the third node No3. The second pull-down maintaining module 202 is configured to disconnect the electrical connection between the first node No1 and the second power supply end VssQ according to the invalid level of the signal of the third node No3.

[0050] In some embodiments, the second pull-down control module 302 is configured to connect the electrical connection between the second signal line for transmitting the third control signal LC2 and the second node No2 according to the effective level of the reset control signal Res, so as to transmit the third control signal LC2 to the second node No2. The second pull-down control module 302 is configured to disconnect the electrical connection between the second signal line for transmitting the third control signal LC2 and the second node No2 according to the invalid level of the reset control signal Res.

[0051] Although the signal of the first node No1 can be controlled to have the valid level or the invalid level by using the first control signal Sc1, the second control signal LC1 and the reset control signal Res in combination with the first control module 101, the first pull-down maintaining module 201 and the first pull-down control module 301, in order to reduce the probability that the first node No1 is connected to the high voltage end and the low voltage end at the same time, the shift register GA can further include at least one of the first inverting module 601 and the second inverting module 602, as shown in Figures 1A-1B

[0052] The first inverting module 601 is electrically connected to the second node No2, and the first inverting module 601 is configured to control the signal of the second node No2 to have the invalid level according to the second control signal LC1 and the fourth control signal ScA during the period in which the signal of the first node No1 has the corresponding valid level.

[0053] The second inverting module 602 is electrically connected to the third node No3, and the second inverting module 602 is configured to control the signal of the third node No3 to have the invalid level according to the third control signal LC2 and the fourth control signal ScA during the period in which the signal of the first node No1 has the corresponding valid level.

[0054] By setting the first inverting module 601, the signal of the first node No1 can have the valid level, and the signal of the second node No2 can have the invalid level, so that the first pull-down maintaining module 201 can disconnect the electrical connection between the second power supply end VssQ and the first node No1, thereby reducing the probability that the first node No1 is connected to the high voltage end and the low voltage end at the same time.

[0055] By making the first inverting module 601 share the second control signal LC1 with the first pull-down control module 301, the number of control signals applied by the shift register GA can be reduced, and the power consumption of the shift register GA can be reduced. Moreover, by setting the second control signal LC1 and the third control signal LC2 to be inverted, the first inverting module 601 and the first pull-down maintaining module 201 can correspond to the same working period, and the first inverting module 601 and the first pull-down maintaining module 201 can work alternately with the second inverting module 602 and the second pull-down maintaining module 202, which is conducive to shortening the working time of the first inverting module 601 and the first pull-down maintaining module 201.

[0056] Similarly, by setting the second inverting module 602, the signal of the third node No3 can have the invalid level during the period in which the signal of the first node No1 has the valid level, so that the second pull-down maintaining module 202 can disconnect the electrical connection between the second power supply end VssQ and the first node No1, thereby reducing the probability that the first node No1 is connected to the high voltage end and the low voltage end at the same time. ​

[0057] By sharing the third control signal LC2 between the second inverting module 602 and the second pull-down control module 302, the number of control signals applied to the shift register GA can be reduced, and the power consumption of the shift register GA can be reduced. In addition, by setting the second control signal LC1 and the third control signal LC2 to be inverted, the second inverting module 602 and the second pull-down maintenance module 202 can correspond to the same working period, so that the second inverting module 602 and the second pull-down maintenance module 202 can work alternately with the first inverting module 601 and the first pull-down maintenance module 201, and the working time of the second inverting module 602 and the second pull-down maintenance module 202 can be shortened.

[0058] Optionally, the shift register GA can further include a stage transmission module 402, the stage transmission module 402 is electrically connected with the first node No1, and the stage transmission module 402 is configured to control the electrical connection between the corresponding clock line CL and the stage transmission output end OUT2 of the shift register GA according to the signal of the first node No1. The stage transmission output end OUT2 is configured to output the stage transmission signal Stn.

[0059] By setting the stage transmission module 402 and the output module 401, the stage transmission module 402 and the output module 401 can be controlled by the first node No1, so that the shift register GA can output the gate control signal Scan and the stage transmission signal Stn at the same time, and the setting of the shift register GA outputting multiple signals can be realized.

[0060] Optionally, the clock line connected with the stage transmission module 402 and the clock line connected with the output module 401 can be the same or different. In some embodiments, the clock line connected with the stage transmission module 402 and the clock line connected with the output module 401 are the same, so that the stage transmission signal Stn and the gate control signal Scan are the same. In other embodiments, the clock line connected with the stage transmission module 402 and the clock line connected with the output module 401 are different, so that the stage transmission signal Stn and the gate control signal Scan are the same or different.

[0061] Optionally, at least one of the first pull-down maintenance module 201 and the second pull-down maintenance module 202 can be used to make the signal output by at least one of the signal output end OUT1 and the stage transmission output end OUT2 have a stable invalid level state.

[0062] Please continue to refer to Figures 1A-1BAt least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 is electrically connected with the stage transmission output terminal OUT2. The first pull-down maintaining module 201 is configured to control the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the signal of the second node No2. The second pull-down maintaining module 202 is configured to control the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the signal of the third node No3.

[0063] In some embodiments, the first pull-down maintaining module 201 is configured to connect the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the active level of the signal of the second node No2, and disconnect the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the inactive level of the signal of the second node No2. The second pull-down maintaining module 202 is configured to connect the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the active level of the signal of the third node No3, and disconnect the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ according to the inactive level of the signal of the third node No3.

[0064] By electrically connecting at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 with the stage transmission output terminal OUT2, the electrical connection between the stage transmission output terminal OUT2 and the second power supply terminal VssQ can be connected by at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202, so that the stage transmission signal Stn output by the stage transmission output terminal OUT2 has a stable inactive level state.

[0065] Please continue to refer to Figures 1A-1B At least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 is electrically connected with the signal output terminal OUT1 and the third power supply terminal VssG.

[0066] In some embodiments, the first pull-down maintaining module 201 is configured to control the electrical connection between the signal output terminal OUT1 and the third power supply terminal VssG according to the signal of the second node No2.

[0067] In some embodiments, the second pull-down maintaining module 202 is configured to control the electrical connection between the signal output terminal OUT1 and the third power supply terminal VssG according to the signal of the third node No3.

[0068] In some embodiments, the first pull-down maintaining module 201 is configured to control the electrical connection between the signal output terminal OUT1 and the third power terminal VssG according to the active level of the signal of the second node No2, and control the electrical connection between the signal output terminal OUT1 and the third power terminal VssG according to the inactive level of the signal of the second node No2.

[0069] In some embodiments, the second pull-down maintaining module 202 is configured to control the electrical connection between the signal output terminal OUT1 and the third power terminal VssG according to the active level of the signal of the third node No3, and control the electrical connection between the signal output terminal OUT1 and the third power terminal VssG according to the inactive level of the signal of the third node No3.

[0070] By electrically connecting at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 with the signal output terminal OUT1, the electrical connection between the signal output terminal OUT1 and the third power terminal VssG can be controlled by at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202, so that the gate control signal Scan output by the signal output terminal OUT1 has a stable inactive level state.

[0071] Optionally, the shift register GA can further include a second control module 102, as shown in Figures 1A-1B The second control module 102 is electrically connected with the first node No1 and the fourth power terminal Vs2, and the second control module 102 is configured to control the electrical connection between the first node No1 and the fourth power terminal Vs2 according to the fifth control signal Sc2. Wherein, the phase of the electrical signal supplied by the first power terminal Vs1 and the phase of the electrical signal supplied by the fourth power terminal Vs2 are opposite, so that one of the first control module 101 and the second control module 102 is configured to control the first node No1 to have an active level, and the other of the first control module 101 and the second control module 102 is configured to control the first node No1 to have an inactive level.

[0072] In some embodiments, the first control module 101 is configured to connect the current path between the first node No1 and the first power terminal Vs1 according to the active level of the first control signal Sc1, so that the signal of the first node No1 has an active level. The second control module 102 is configured to control the electrical connection between the first node No1 and the fourth power terminal Vs2 according to the active level of the fifth control signal Sc2, so that the signal of the first node No1 has an inactive level.

[0073] For example, in some embodiments, the first control module 101 is configured to connect the current path between the first node No1 and the first power terminal Vs1 according to the active level of the first control signal Sc1, so that the signal of the first node No1 has an inactive level. The second control module 102 is configured to control the electrical connection between the first node No1 and the fourth power terminal Vs2 according to the active level of the fifth control signal Sc2, so that the signal of the first node No1 has an active level.

[0074] To avoid the first node No1 being connected to the high voltage terminal and the low voltage terminal at the same time, the time period of the active pulse of the first control signal Sc1 and the time period of the active pulse of the fifth control signal Sc2 can not overlap.

[0075] Optionally, the first power terminal Vs1 can be one of the low voltage terminal and the high voltage terminal. The fourth power terminal Vs2 can be the other one of the low voltage terminal and the high voltage terminal.

[0076] For example, in some embodiments, the first power terminal Vs1 can be the low voltage terminal, and the fourth power terminal Vs2 can be the high voltage terminal. Accordingly, when the active level used by the device controlled by the signal of the first node No1 is the high level, the first control module 101 connects the current path between the first node No1 and the first power terminal Vs1 according to the first control signal Sc1, so that the signal of the first node No1 has an inactive level. The second control module 102 connects the current path between the first node No1 and the fourth power terminal Vs2 according to the fifth control signal Sc2, so that the signal of the first node No1 has an active level. When the active level used by the device controlled by the signal of the first node No1 is the low level, the first control module 101 connects the current path between the first node No1 and the first power terminal Vs1 according to the first control signal Sc1, so that the signal of the first node No1 has an active level. The second control module 102 connects the current path between the first node No1 and the fourth power terminal Vs2 according to the fifth control signal Sc2, so that the signal of the first node No1 has an inactive level.

[0077] In other embodiments, the first power supply terminal Vs1 can be a high-voltage terminal, and the fourth power supply terminal Vs2 can be a low-voltage terminal. Correspondingly, when the effective level used by the device controlling the signal of the first node No1 is high, the first control module 101 can make the signal of the first node No1 have an effective level by connecting the current path between the first node No1 and the first power supply terminal Vs1 according to the first control signal Sc1; the second control module 102 can make the signal of the first node No1 have an ineffective level by connecting the current path between the first node No1 and the fourth power supply terminal Vs2 according to the fifth control signal Sc2. Conversely, when the effective level used by the device controlling the signal of the first node No1 is low, the first control module 101 can make the signal of the first node No1 have an ineffective level by connecting the current path between the first node No1 and the first power supply terminal Vs1 according to the first control signal Sc1; the second control module 102 can make the signal of the first node No1 have an effective level by connecting the current path between the first node No1 and the fourth power supply terminal Vs2 according to the fifth control signal Sc2.

[0078] It should be noted that the reset module 500, the first inverting module 601, the second inverting module 602, and the cascading module 402 can be selectively configured in the shift register GA. The first pull-down control module 301 and the first pull-down sustaining module 201, the second pull-down control module 302 and the second pull-down sustaining module 202 can be selectively configured in the shift register GA or both can be configured in the shift register GA.

[0079] Figures 2A-2D This is a schematic diagram of the circuit structure of the shift register according to an embodiment of this application. For ease of understanding the shift register GA of this application, [the diagram is shown]. Figures 2A-2D The structure of the shift register GA shown is used as an example for explanation.

[0080] The first pull-down control module 301 may include a first pull-down transistor Td1. The control terminal of the first pull-down transistor Td1 is configured to receive a reset control signal Res. The first source-drain terminal of the first pull-down transistor Td1 is configured to receive a second control signal LC1. The second source-drain terminal of the first pull-down transistor Td1 is electrically connected to the second node No2.

[0081] Optionally, the shift register GA includes a second pull-down control module 302, such as Figures 2C-2D As shown. The second pull-down control module 302 includes a second pull-down transistor Td2. The control terminal of the second pull-down transistor Td2 is configured to receive a reset control signal Res. The first source-drain terminal of the second pull-down transistor Td2 is configured to receive a third control signal LC2. The second source-drain terminal of the second pull-down transistor Td2 is electrically connected to the third node No3.

[0082] Please continue reading.Figures 2A-2D The reset module 500 includes a reset transistor Tr, a control end of the reset transistor Tr is configured to receive a reset control signal Res, a first source-drain end of the reset transistor Tr is electrically connected with the second power end VssQ, and a second source-drain end of the reset transistor Tr is electrically connected with the first node No1.

[0083] Optionally, at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 includes a first switch transistor Ts1, a first source-drain end of the first switch transistor Ts1 is electrically connected with the second power end VssQ, and a second source-drain end of the first switch transistor Ts1 is electrically connected with the first node No1. In the first pull-down maintaining module 201, a control end of the first switch transistor Ts1 is electrically connected with the second node No2, as shown in FIG. 2B. Figures 2A-2D In the second pull-down maintaining module 202, a control end of the first switch transistor Ts1 is electrically connected with the third node No3, as shown in FIG. 2C. Figures 2C-2D

[0084] Optionally, at least one of the first pull-down maintaining module 201 and the second pull-down maintaining module 202 includes a second switch transistor Ts2 and a third switch transistor Ts3, a first source-drain end of the second switch transistor Ts2 is electrically connected with the second power end VssQ, a second source-drain end of the second switch transistor Ts2 is electrically connected with the stage transmission output end OUT2, a first source-drain end of the third switch transistor Ts3 is electrically connected with the third power end VssG, and a second source-drain end of the third switch transistor Ts3 is electrically connected with the signal output end OUT1. In the first pull-down maintaining module 201, a control end of the second switch transistor Ts2 and a control end of the third switch transistor Ts3 are electrically connected with the second node No2, as shown in FIG. 2B. In the second pull-down maintaining module 202, a control end of the second switch transistor Ts2 and a control end of the third switch transistor Ts3 are electrically connected with the third node No3, as shown in FIG. 2C. Figures 2A-2D Figures 2C-2D

[0085] Optionally, the shift register GA can include at least one of a first inverting module 601 and a second inverting module 602, as shown in FIG. 3A. Figures 2A-2D ​​​As shown, the fourth control signal ScA can include a first sub-control signal Sa1. At least one of the first inverting module 601 and the second inverting module 602 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, a second source-drain terminal of the first transistor T1 is electrically connected with a control terminal of the second transistor T2 and a second source-drain terminal of the third transistor T3, the control terminal of the third transistor T3 and a control terminal of the fourth transistor T4 are configured to receive the first sub-control signal Sa1, a first source-drain terminal of the third transistor T3 and a first source-drain terminal of the fourth transistor T4 are electrically connected with the second power supply terminal VssQ.

[0086] In the first inverting module 601, a control terminal of the first transistor T1, a first source-drain terminal of the first transistor T1, and a first source-drain terminal of the second transistor T2 are configured to receive the second control signal LC1, a second source-drain terminal of the second transistor T2 and a second source-drain terminal of the fourth transistor T4 are electrically connected with the second node No2, and a control terminal of the second transistor T2 is electrically connected with the fourth node No4, as shown. Figures 2A-2D In the second inverting module 602, a control terminal of the first transistor T1, a first source-drain terminal of the first transistor T1, and a first source-drain terminal of the second transistor T2 are configured to receive the third control signal LC2, a second source-drain terminal of the second transistor T2 and a second source-drain terminal of the fourth transistor T4 are electrically connected with the third node No3, and a control terminal of the second transistor T2 is electrically connected with the fifth node No5, as shown. Figures 2C-2D

[0087] In some embodiments, the first sub-control signal Sa1 can be the same as the control signal that makes the signal of the first node No1 have a valid level, so as to make the signal of the second node No2 have an invalid level when the signal of the first node No1 has the valid level. For example, the first sub-control signal Sa1 can be the same as the first control signal Sc1 when the first control module 101 connects the first power supply terminal Vs1 and the first node No1 according to the first control signal Sc1 to make the first node No1 have the valid level. For another example, the first sub-control signal Sa1 can be the same as the fifth control signal Sc2 when the second control module 102 connects the fourth power supply terminal Vs2 and the first node No1 according to the fifth control signal Sc2 to make the first node No1 have the valid level.

[0088] In some embodiments, the first sub-control signal Sa1 can be the same as the signal of the first node No1, so as to reduce the number of signals used by the shift register GA and reduce the power consumption of the shift register GA.

[0089] ​In some embodiments, the first sub-control signal Sa1 and the signal of the first node No1 have the same frequency, and the start time of the active pulse of the first sub-control signal Sa1 is ahead of the start time of the active pulse of the first control signal Sc1, so that at least one of the second node No2 and the third node No3 is controlled to have an inactive level in advance before the signal of the first node No1 has an active level, thereby breaking the electrical connection between the first node No1 and the second power supply end VssQ in advance before the signal of the first node No1 has an active level.

[0090] Optionally, the fourth control signal ScA can include a second sub-control signal Sa2. At least one of the first inverting module 601 and the second inverting module 602 includes a fifth transistor T5 and a sixth transistor T6, the control end of the fifth transistor T5 and the control end of the sixth transistor T6 are configured to receive the second sub-control signal Sa2, the first source-drain end of the fifth transistor T5 and the first source-drain end of the sixth transistor T6 are electrically connected with the second power supply end VssQ, and the second source-drain end of the fifth transistor T5 is electrically connected with the control end of the corresponding second transistor T2.

[0091] In the first inverting module 601, the second source-drain end of the sixth transistor T6 is electrically connected with the second node No2, as shown in Figures 2A-2D In the second inverting module 602, the second source-drain end of the sixth transistor T6 is electrically connected with the third node No3, as shown in Figures 2C-2D .

[0092] In some embodiments, the second sub-control signal Sa2 can be the same as the control signal that makes the signal of the first node No1 have an active level, so as to make the signal of the second node No2 have an inactive level when the signal of the first node No1 has an active level. For example, the second sub-control signal Sa2 can be the same as the first control signal Sc1 when the first control module 101 connects the first power supply end Vs1 and the first node No1 according to the first control signal Sc1 to make the first node No1 have an active level. For another example, the second sub-control signal Sa2 can be the same as the fifth control signal Sc2 when the second control module 102 connects the fourth power supply end Vs2 and the first node No1 according to the fifth control signal Sc2 to make the first node No1 have an active level.

[0093] In some embodiments, the second sub-control signal Sa2 is the same as the signal of the first node No1, so as to reduce the number of signals used by the shift register GA and reduce the power consumption of the shift register GA.

[0094] In some embodiments, the second sub-control signal Sa2 and the signal of the first node No1 have the same frequency, and the start time of the active pulse of the second sub-control signal Sa2 lags behind the start time of the active pulse of the first control signal Sc1, so as to cooperate with the first sub-control signal Sa1 to make the second node No2 have a stable inactive level state, thereby reducing the leakage of the first node No1 to the second power terminal VssQ.

[0095] Alternatively, to avoid the second node No2 simultaneously accessing the signal supplied by the second control signal LC1 and the second power terminal VssQ, the end time of the active pulse of the second sub-control signal Sa2 can be ahead of the start time of the active pulse of the reset control signal Res, so that the period during which the second control signal LC1 is transmitted to the second node No2 and the period during which the second node No2 is electrically connected to the second power terminal VssQ do not overlap, thereby making the second node No2 not simultaneously access the signals supplied by the second control signal LC1 and the second power terminal VssQ.

[0096] Similarly, to avoid the third node No3 simultaneously accessing the signal supplied by the third control signal LC2 and the second power terminal VssQ, the end time of the active pulse of the second sub-control signal Sa2 is ahead of the start time of the active pulse of the reset control signal Res, so that the period during which the third control signal LC2 is transmitted to the third node No3 and the period during which the third node No3 is electrically connected to the second power terminal VssQ do not overlap, thereby making the third node No3 not simultaneously access the signals supplied by the third control signal LC2 and the second power terminal VssQ.

[0097] Please continue to refer to Figures 2A-2D The first control module 101 can include a seventh transistor T7, the control end of the seventh transistor T7 is configured to receive the first control signal Sc1, the first source-drain end of the seventh transistor T7 is electrically connected to the first power terminal Vs1, and the second source-drain end of the seventh transistor T7 is electrically connected to the first node No1.

[0098] The output module 401 includes a capacitor Cb, the capacitor Cb is electrically connected between the first node No1 and the signal output terminal OUT1, the first source-drain end of the output transistor To1 is electrically connected to the corresponding clock line CL, and the second source-drain end of the output transistor To1 is electrically connected to the signal output terminal OUT1.

[0099] Alternatively, the shift register GA can include a second control module 102, the second control module 102 includes an eighth transistor T8, the control end of the eighth transistor T8 is configured to receive the fifth control signal Sc2, the first source-drain end of the eighth transistor T8 is electrically connected to the fourth power terminal Vs2, and the second source-drain end of the eighth transistor T8 is electrically connected to the first node No1.

[0100] Optionally, the shift register GA can include a stage transmission module 402, the stage transmission module 402 including a stage transmission transistor To2, a control terminal of the stage transmission transistor To2 being electrically connected with the first node No1, a first source-drain terminal of the stage transmission transistor To2 being electrically connected with the corresponding clock line CL, and a second source-drain terminal of the stage transmission transistor To2 being electrically connected with a stage transmission output terminal OUT2.

[0101] In some embodiments, the first power supply terminal Vs1 can correspond to a high voltage terminal (abbreviated as VGH), and the fourth power supply terminal Vs2 can correspond to a low voltage terminal (abbreviated as VGL), as shown in FIG. 4A and FIG. 4B. Figure 2A Figure 2C In other embodiments, the fourth power supply terminal Vs2 can correspond to a high voltage terminal (abbreviated as VGH), and the first power supply terminal Vs1 can correspond to a low voltage terminal (abbreviated as VGL), as shown in FIG. 5A and FIG. 5B. Figure 2B Figure 2D

[0102] It should be noted that the transistors included in the shift register GA can be P-type transistors or N-type transistors. The control terminal of the transistor can be the gate of the transistor, the first source-drain terminal of the transistor can be one of the source and the drain of the transistor, and the second source-drain terminal of the transistor can be the other of the source and the drain of the transistor.

[0103] It should be understood that, Figures 2A-2D only the combination of transistors and capacitors is taken as an example for illustration. In some embodiments, each module can also be implemented in a more complex connection form or with more types or quantities of components. The components can be at least one of transistors and capacitors.

[0104] Figures 3A-3B FIG. 6 is a timing diagram corresponding to the shift register according to the embodiments of the present application. Taking each transistor included in the shift register GA as an N-type transistor, the first sub-control signal Sa1 and the second sub-control signal Sa2 included in the fourth control signal ScA being the same as the signal of the first node No1, and the stage transmission module 402 and the output module 401 being connected with the same clock line CL as an example, the working principle of the shift register GA shown in FIG. 6 is described. Figure 2A

[0105] Please continue to refer to Figure 3A In the first working mode, the first power supply terminal Vs1 can be a high voltage terminal, and the second power supply terminal VssQ can be a low voltage terminal.

[0106] ​​​​In the first stage t1, the first control signal Sc1 and the second control signal LC1 are high level, the third control signal LC2, the reset control signal Res and the clock signal CK transmitted by the clock line CL corresponding to the electrical connection of the shift register GA are low level. The seventh transistor T7 is turned on, the first power supply end Vs1 is electrically connected with the first node No1, the output transistor To1, the stage transmission transistor To2, the third transistor T3 to the sixth transistor T6 are turned on, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the reset transistor Tr, the first pull-down transistor Td1 and the second pull-down transistor Td2 are cut off. The gate control signal Scan and the stage transmission signal Stn output by the shift register GA have low level.

[0107] In the second stage t2, the clock signal CK and the second control signal LC1 are high level, the first control signal Sc1, the third control signal LC2 and the reset control signal Res are low level. The output transistor To1, the stage transmission transistor To2, the third transistor T3 to the sixth transistor T6 are turned on, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the reset transistor Tr, the first pull-down transistor Td1 and the second pull-down transistor Td2 are cut off. The gate control signal Scan and the stage transmission signal Stn output by the shift register GA have high level.

[0108] In the third stage t3, the reset control signal Res and the second control signal LC1 are high level, the clock signal CK, the first control signal Sc1 and the third control signal LC2 are low level. The reset transistor Tr, the first pull-down transistor Td1, the second pull-down transistor Td2, the first switch transistor Ts1, the second switch transistor Ts2 and the third switch transistor Ts3 are turned on, the second power supply end VssQ is electrically connected with the first node No1, the output transistor To1, the stage transmission transistor To2, the third transistor T3 to the sixth transistor T6 are cut off, and the gate control signal Scan and the stage transmission signal Stn output by the shift register GA have low level.

[0109] In the first working mode, the fourth power supply end Vs2 can be a low voltage end. When the fifth control signal Sc2 has an effective level, the eighth transistor T8 is turned on, the fourth power supply end Vs2 is electrically connected with the first node No1, so that the first node No1 has an invalid level. When the fifth control signal Sc2 has an invalid level, the eighth transistor T8 is cut off, and the electrical connection between the fourth power supply end Vs2 and the first node No1 is disconnected. In some embodiments, when the shift register GA simultaneously sets at least one of the first pull-down control module 301 and the second pull-down control module 302 and the second control module 102, the effective pulse of the fifth control signal Sc2 can be ahead of the effective pulse of the reset control signal Res, as shown in the following table. Figure 3BAs shown.

[0110] In the second operating mode, the first power supply terminal Vs1 and the second power supply terminal VssQ can be low-voltage terminals, and the fourth power supply terminal Vs2 can be a high-voltage terminal. (Refer to...) Figure 3A Regarding the explanation of the first working mode, Figure 3A The first control signal Sc1 is adjusted to the fifth control signal Sc2. Figure 3B By swapping the first control signal Sc1 and the fifth control signal Sc2, the working principle of the second working mode can be obtained.

[0111] Understandably, referring to the working principle of the shift register GA when the first sub-control signal Sa1 and the second sub-control signal Sa2 are the same as the signal of the first node No1, we can obtain the working principle corresponding to the case where the first sub-control signal Sa1 and the second sub-control signal Sa2 are set to be the same as the first control signal Sc1, or the first sub-control signal Sa1 and the second sub-control signal Sa2 have the same frequency as the signal of the first node No1, but the effective pulses of the first sub-control signal Sa1 and the second sub-control signal Sa2 do not overlap with the effective pulses of the signal of the first node No1.

[0112] Figures 4A-4D This is a schematic diagram of the gate drive circuit according to an embodiment of this application. This application also provides a gate drive circuit GDC, including multiple shift registers GA as described above, with the multiple shift registers GA cascaded together.

[0113] Optionally, multiple shift registers (GAs) can multiplex clock signals transmitted from multiple clock lines. For example, multiple shift registers (GAs) can multiplex clock signals transmitted from Z clock lines. Z clock lines transmit Z clock signals with phase differences, and the clock signal received by the ZK+Rth stage shift register (GA) corresponds to the clock signal transmitted from the Lth clock line. Where Z ≥ 2; K ≥ 0, and K is a positive integer; 1 ≤ R ≤ Z; when R ≤ Z / 2, L = Z / 2 + R; when R > Z / 2, L = RZ / 2.

[0114] For example, when Z=12, in the direction from top to bottom (i.e. corresponding to the second direction Dr2 described below), the clock signal received by the 12K+1th shift register GA(12K+1) corresponds to the seventh clock signal CK7 transmitted by the seventh clock line, the clock signal received by the 12K+2th shift register GA(12K+2) corresponds to the eighth clock signal CK8 transmitted by the eighth clock line, the clock signal received by the 12K+3th shift register GA(12K+3) corresponds to the ninth clock signal CK9 transmitted by the ninth clock line, the clock signal received by the 12K+4th shift register GA(12K+4) corresponds to the tenth clock signal CK10 transmitted by the tenth clock line, the clock signal received by the 12K+5th shift register GA(12K+5) corresponds to the eleventh clock signal CK11 transmitted by the eleventh clock line, the clock signal received by the 12K+6th shift register GA(12K+6) corresponds to the twelfth clock signal CK12 transmitted by the twelfth clock line, the clock signal received by the 12K+7th shift register GA(12K+7) corresponds to the first clock signal CK1 transmitted by the first clock line, the clock signal received by the 12K+8th shift register GA(12K+8) corresponds to the second clock signal CK2 transmitted by the second clock line, the clock signal received by the 12K+9th shift register GA(12K+9) corresponds to the third clock signal CK3 transmitted by the third clock line, the clock signal received by the 12K+10th shift register GA(12K+10) corresponds to the fourth clock signal CK4 transmitted by the fourth clock line, the clock signal received by the 12K+11th shift register GA(12K+11) corresponds to the fifth clock signal CK5 transmitted by the fifth clock line, and the clock signal received by the 12K+12th shift register GA(12K+12) corresponds to the sixth clock signal CK6 transmitted by the sixth clock line.

[0115] Similarly, when Z=4, 6 or 8, the shift registers GA and clock lines can also be arranged as described above.

[0116] Optionally, in order to reduce the number of signal lines used by the gate drive circuit GDC, save the layout space used by the gate drive circuit GDC, and reduce the power consumption of the gate drive circuit GDC, the plurality of shift registers GA included in the gate drive circuit GDC can share the same reset control signal Res and the second control signal LC1.

[0117] For example, when Z=12, in the direction from top to bottom (i.e. corresponding to the second direction Dr2 described below), the clock signal received by the 12K+1th shift register GA(12K+1) corresponds to the seventh clock signal CK7 transmitted by the seventh clock line, the clock signal received by the 12K+2th shift register GA(12K+2) corresponds to the eighth clock signal CK8 transmitted by the eighth clock line, the clock signal received by the 12K+3th shift register GA(12K+3) corresponds to the ninth clock signal CK9 transmitted by the ninth clock line, the clock signal received by the 12K+4th shift register GA(12K+4) corresponds to the tenth clock signal CK10 transmitted by the tenth clock line, the clock signal received by the 12K+5th shift register GA(12K+5) corresponds to the eleventh clock signal CK11 transmitted by the eleventh clock line, the clock signal received by the 12K+6th shift register GA(12K+6) corresponds to the twelfth clock signal CK12 transmitted by the twelfth clock line, the clock signal received by the 12K+7th shift register GA(12K+7) corresponds to the first clock signal CK1 transmitted by the first clock line, the clock signal received by the 12K+8th shift register GA(12K+8) corresponds to the second clock signal CK2 transmitted by the second clock line, the clock signal received by the 12K+9th shift register GA(12K+9) corresponds to the third clock signal CK3 transmitted by the third clock line, the clock signal received by the 12K+10th shift register GA(12K+10) corresponds to the fourth clock signal CK4 transmitted by the fourth clock line, the clock signal received by the 12K+11th shift register GA(12K+11) corresponds to the fifth clock signal CK5 transmitted by the fifth clock line, and the clock signal received by the 12K+12th shift register GA(12K+12) corresponds to the sixth clock signal CK6 transmitted by the sixth clock line. Figures 4A-4DThe gate drive circuit GDC includes a first signal line Sl1 and a reset control line RL. The first signal line Sl1 is configured to transmit a second control signal LC1. The reset control line RL is configured to transmit a reset control signal Res. The plurality of shift registers GA are electrically connected to the same first signal line Sl1 and the same reset control line RL, so that the first pull-down control modules 301 of the plurality of shift registers GA share the same second control signal LC1 and the first pull-down control modules 301 of the plurality of shift registers GA share the same reset control signal Res.

[0118] Optionally, to reduce the number of signal lines applied by the gate drive circuit GDC, save the layout space used by the gate drive circuit GDC, and reduce the power consumption of the gate drive circuit GDC, the plurality of shift registers GA included in the gate drive circuit GDC can share the same third control signal LC2.

[0119] As will be further described Figure 4B and Figure 4D The gate drive circuit GDC includes a second signal line Sl2. The second signal line Sl2 is configured to transmit a third control signal LC2. The plurality of shift registers GA are electrically connected to the same second signal line Sl2, so that the second pull-down control modules 302 of the plurality of shift registers GA share the same third control signal LC2.

[0120] When the plurality of gate control signals Scan share the same reset control signal Res, the first nodes No1 of the plurality of shift registers GA are simultaneously connected or disconnected from the second power supply end VssQ. However, in some embodiments, the time when the first nodes No1 of the plurality of shift registers GA are electrically connected to the second power supply end VssQ is sequentially delayed, so as to realize the cascade arrangement of the plurality of gate drive circuits GDC. Therefore, in the gate drive circuit GDC, each shift register GA can simultaneously include at least one of the first pull-down control module 301 and the second pull-down control module 302 and the second control module 102.

[0121] Optionally, the first control module 101 is configured to transmit a signal supplied by the first power supply end Vs1 to the first node No1 according to the first control signal Sc1, so that when the signal of the first node No1 has a corresponding active level, the first control module 101 can be used as a pull-up control module, and the input end of the shift register GA corresponding to receiving the first control signal Sc1 is formed as a pull-up input end PU. Correspondingly, the second control module 102 is configured to transmit a signal supplied by the fourth power supply end Vs2 to the first node No1 according to the fifth control signal Sc2, so that when the signal of the first node No1 has a corresponding inactive level, the second control module 102 can be used as a third pull-down control module, and the input end of the shift register GA corresponding to receiving the fifth control signal Sc2 is formed as a pull-down input end PD.

[0122] Optionally, the first control module 101 is configured to transmit a signal supplied by the first power supply end Vs1 to the first node No1 according to the first control signal Sc1, so that when the signal of the first node No1 has a corresponding active level, the first control module 101 can be used as a pull-up control module, and the input end of the shift register GA corresponding to receiving the first control signal Sc1 is formed as a pull-up input end PU. Correspondingly, the second control module 102 is configured to transmit a signal supplied by the fourth power supply end Vs2 to the first node No1 according to the fifth control signal Sc2, so that when the signal of the first node No1 has a corresponding inactive level, the second control module 102 can be used as a third pull-down control module, and the input end of the shift register GA corresponding to receiving the fifth control signal Sc2 is formed as a pull-down input end PD.

[0123] Optionally, the first control module 101 is configured to transmit a signal supplied by the first power supply end Vs1 to the first node No1 according to the first control signal Sc1, so that when the signal of the first node No1 has a corresponding active level, the first control module 101 can be used as a pull-up control module, and the input end of the shift register GA corresponding to receiving the first control signal Sc1 is formed as a pull-up input end PU. Correspondingly, the second control module 102 is configured to transmit a signal supplied by the fourth power supply end Vs2 to the first node No1 according to the fifth control signal Sc2, so that when the signal of the first node No1 has a corresponding inactive level, the second control module 102 can be used as a third pull-down control module, and the input end of the shift register GA corresponding to receiving the fifth control signal Sc2 is formed as a pull-down input end PD.

[0124] As please continue to refer to Figures 4A-4BFor example, when m=y=6, in the first direction Dr1 from bottom to top, the first shift register GA in the plurality of shift registers GA is located at the bottom, and the last shift register GA in the plurality of shift registers GA is located at the top. The first control signal Sc1 corresponding to the first 6 shift registers GA in the plurality of shift registers GA is a start signal, the first control signal Sc1 corresponding to the nth shift register GA(n) is an (n-6)th stage transfer signal Stn(n-6) or an (n-6)th gate control signal Scan(n-6) output by an (n-6)th shift register GA(n-6), thus the pull-up input PU corresponding to the nth shift register GA(n) receives the (n-6)th stage transfer signal Stn(n-6) or the (n-6)th gate control signal Scan(n-6). The first control signal Sc1 corresponding to the xth shift register GA(x) is an (x+6)th stage transfer signal Stn(x+6) or an (x+6)th gate control signal Scan(x+6) output by an (x+6)th shift register GA(x+6), thus the pull-down input PD corresponding to the xth shift register GA(x) receives the (x+6)th stage transfer signal Stn(x+6) or the (x+6)th gate control signal Scan(x+6). The plurality of shift registers GA output the gate control signal Scan or the transfer signal Stn with the effective pulse in the first direction Dr1 in turn.

[0125] It should be understood that m can be equal to or different from y to realize symmetric or asymmetric design of the potential pull-up and pull-down of the first node No1.

[0126] Optionally, the first control module 101 is configured to transmit the signal supplied by the first power supply end Vs1 to the first node No1 according to the first control signal Sc1, so that when the signal of the first node No1 has the corresponding invalid level, the first control module 101 can be used as a third pull-down control module, and the input end of the shift register GA corresponding to the received first control signal Sc1 is formed as a pull-down input end PD. Correspondingly, the second control module 102 is configured to transmit the signal supplied by the fourth power supply end Vs2 to the first node No1 according to the fifth control signal Sc2, so that when the signal of the first node No1 has the corresponding invalid level, the second control module 102 can be used as a pull-up control module, and the input end of the shift register GA corresponding to the received fifth control signal Sc2 is formed as a pull-up input end PU.

[0127] In the embodiment, the first control module 101 is configured to transmit the signal supplied by the first power supply end Vs1 to the first node No1 according to the first control signal Sc1, so that when the signal of the first node No1 has the corresponding invalid level, the first control signal Sc1 corresponding to the xth shift register GA(x) is the signal output by the (x+y)th shift register GA(x+y), x≥1, y≥1.

[0128] The second control module 102 is configured to transmit the signal supplied by the fourth power supply end Vs2 to the first node No1 according to the fifth control signal Sc2, so that when the signal of the first node No1 has the corresponding active level, the corresponding fifth control signal Sc2 of the first m shift registers GA in the plurality of shift registers GA is the start signal, the corresponding fifth control signal Sc2 of the nth shift register GA(n) in the plurality of shift registers GA is the signal output by the n-mth shift register GA(n-m), 1≤m<n, n-m≥1.

[0129] As will be described below Figures 4C-4D Taking m=y=6 as an example, in the second direction Dr2 from top to bottom, the first shift register GA in the plurality of shift registers GA is located at the topmost, and the last shift register GA in the plurality of shift registers GA is located at the bottommost. The corresponding fifth control signal Sc2 of the first 6 shift registers GA in the plurality of shift registers GA is the start signal, the corresponding fifth control signal Sc2 of the nth shift register GA(n) is the n-6th stage transfer signal Stn(n-6) or the n-6th gate control signal Scan(n-6) output by the n-6th shift register GA(n-6), so that the pull-up input end PU corresponding to the nth shift register GA(n) receives the n-6th stage transfer signal Stn(n-6) or the n-6th gate control signal Scan(n-6). The first control signal Sc1 corresponding to the xth shift register GA(x) is the x+6th stage transfer signal Stn(x+6) or the x+6th gate control signal Scan(x+6) output by the x+6th shift register GA(x+6), so that the pull-down input end PD corresponding to the xth shift register GA(x) receives the x+6th stage transfer signal Stn(x+6) or the x+6th gate control signal Scan(x+6). The plurality of shift registers GA output the gate control signal Scan or the stage transfer signal Stn with active pulses in the second direction Dr2 in turn.

[0130] It should be understood that when m is equal to y, because the first control module 101 and the second control module 102 can alternately act as the pull-up control module and the third pull-down control module, when the first control module 101 acts as the pull-up module, the n-mth shift register GA(n-m) corresponding to the nth shift register GA(n) is the same shift register GA as the n+yth shift register GA(n+y) corresponding to the nth shift register GA(n) when the first control module 101 acts as the pull-down module.

[0131] As still taking m=y=6 as an example, along the first direction Dr1, the first control module 101 as a pull-up module, the nth-stage shift register GA(n) corresponding pull-up input end PU receives the nth-6-stage stage transfer signal Stn(n-6) or the nth-6-stage gate control signal Scan(n-6) output by the n-6-stage shift register GA(n-6). Along the second direction Dr2, the first control module 101 as a pull-down module, the nth-stage shift register GA(n) corresponding pull-down input end PD receives the nth+6-stage stage transfer signal Stn(n+6) or the nth+6-stage gate control signal Scan(n+6) output by the n+6-stage shift register GA(n+6). The n-6-stage shift register GA(n-6) corresponding along the first direction Dr1 can be the same shift register GA as the n+6-stage shift register GA(n+6) corresponding along the second direction Dr2.

[0132] Correspondingly, Figures 5A-5B is a timing diagram of the clock signal corresponding to the gate drive circuit GDC of the embodiment of the present application. Wherein, Figures 5A-5B Only taking Z=12 as an example for illustration, but not used to limit that Z can only equal to 12. The effective pulse of the nth-6-stage stage transfer signal Stn(n-6) or the nth-6-stage gate control signal Scan(n-6) output by the n-6-stage shift register GA(n-6) corresponding along the first direction Dr1 or the second direction Dr2 leads the effective pulse of the nth-stage stage transfer signal Stn(n) or the nth-stage gate control signal Scan(n) output by the nth-stage shift register GA(n), and the effective pulse of the nth+6-stage stage transfer signal Stn(n+6) or the nth+6-stage gate control signal Scan(n+6) output by the n+6-stage shift register GA(n+6) lags behind the effective pulse of the nth-stage stage transfer signal Stn(n) or the nth-stage gate control signal Scan(n) output by the nth-stage shift register GA(n). Thus, corresponding to the first direction Dr1, the clock signals transmitted by the first clock line to the Zth clock line have effective pulses with phase lag in turn, as shown in Figure 5A . Corresponding to the second direction Dr2, the clock signals transmitted by the first clock line to the Zth clock line have effective pulses with phase lag in turn, as shown in Figure 5B . Therefore, the clock line connected with the n-6-stage shift register GA(n-6) corresponding along the first direction Dr1 and the n+6-stage shift register GA(n+6) corresponding along the second direction Dr2 can be the same clock line. By adjusting the timing of the clock signals transmitted by the plurality of clock lines, the adjustment of the layout and wiring of the gate drive circuit GDC can be reduced, and the preparation cost of the gate drive circuit GDC can be reduced.

[0133] Optionally, the active pulse of the reset control signal Res does not overlap with the active pulse of the signal output by any stage of the shift register GA in the gate drive circuit GDC, so that the active pulse of the signal output by the multiple shift registers GA can be completely output when the reset control signal Res is shared.

[0134] It should be understood that, since the first control module 101 and the second control module 102 can alternatively serve as the pull-up control module and the third pull-down control module, the simultaneous setting of the first control module 101 and the second control module 102 can enable the same phase difference between the active pulses of the gate control signals Scan output by the multiple shift registers GA while achieving the stage transmission function of the gate drive circuit GDC.

[0135] Optionally, the shift register GA can further include at least one of a first inversion module 601 and a second inversion module 602.

[0136] In some embodiments, the first inversion module 601 is electrically connected to the second node No2 of the current stage of the shift register GA, and the first inversion module 601 is configured to control the time-sharing transmission of the second control signal LC1 and the signal supplied by the second power supply terminal VssQ to the second node No2 according to the second control signal LC1 and the first sub-control signal Sa1.

[0137] In some embodiments, the first inversion module 601 is further configured to control the time-sharing transmission of the second control signal LC1 and the signal supplied by the second power supply terminal VssQ to the second node No2 according to the second control signal LC1 and the second sub-control signal Sa2.

[0138] In some embodiments, the second inversion module 602 is electrically connected to the third node No3 of the current stage of the shift register GA, and the second inversion module 602 is configured to control the time-sharing transmission of the second control signal LC1 and the signal supplied by the second power supply terminal VssQ to the third node No3 according to the third control signal LC2 and the first sub-control signal Sa1.

[0139] In some embodiments, the second inversion module 602 is further configured to control the time-sharing transmission of the third control signal LC2 and the signal supplied by the second power supply terminal VssQ to the third node No3 according to the second control signal LC1 and the second sub-control signal Sa2.

[0140] Optionally, the first sub-control signal Sa1 corresponding to the nth stage of the shift register GA(n) is the signal of the first node in the nth-u stage of the shift register GA(n-u), and u < m. The second sub-control signal Sa2 corresponding to the nth stage of the shift register GA(n) is the signal of the first node in the nth+v stage of the shift register GA(n+v), and v < m.

[0141] As u=v=2, the first sub-control signal Sa1 corresponding to the nth-stage shift register GA(n) is the signal of the first node in the (n-2)th-stage shift register GA(n-2), and the second sub-control signal Sa2 corresponding to the nth-stage shift register GA(n) is the signal of the first node in the (n+2)th-stage shift register GA(n+2), so as to connect the second node No2 and the third node No3 of the nth-stage shift register GA(n) with the second power supply end VssQ before the first node of the nth-stage shift register GA(n) is electrically connected with the high-voltage end, to disconnect the electrical connection between the second power supply end VssQ and the first node No1 in the nth-stage shift register GA(n), and to reduce the leakage current between the first node No1 in the nth-stage shift register GA(n) and the second power supply end VssQ.

[0142] It should be understood that, in the design that the gate driving circuit alternately adopts the first direction Dr1 and the second direction Dr2, the first sub-control signal Sa1 and the second sub-control signal Sa2 are also switched with the design of the first direction Dr1 and the second direction Dr2. That is, the (n-2)th-stage shift register GA(n-2) corresponding to the first direction Dr1 can be the same shift register GA as the (n+2)th-stage shift register GA(n+2) corresponding to the second direction Dr2.

[0143] In some embodiments, when the plurality of shift registers GA are applied to the gate driving circuit GDC, the gate control signal Scan output by the signal output end OUT1 of the plurality of shift registers GA can be used to realize the stage transmission function of the gate driving circuit GDC. However, in some embodiments, the load required to be driven by the gate driving control signal output by the signal output end OUT1 is large, and further using the gate control signal Scan to realize the stage transmission function of the gate driving circuit GDC will further increase the number of loads required to be driven by the gate driving control signal, resulting in a further increase in the requirement for the gate control signal Scan. Therefore, in order to reduce the number of loads required to be driven by the gate driving control signal and reduce the requirement for the gate control signal Scan when the plurality of shift registers GA are applied to the gate driving circuit GDC, the shift register GA can include a stage transmission module 402 to realize the stage transmission function by using the stage transmission output end OUT2 of the shift register GA.

[0144] It should be understood that, in the design that the gate driving circuit alternately adopts the first direction Dr1 and the second direction Dr2, the first sub-control signal Sa1 and the second sub-control signal Sa2 are also switched with the design of the first direction Dr1 and the second direction Dr2. That is, the (n-2)th-stage shift register GA(n-2) corresponding to the first direction Dr1 can be the same shift register GA as the (n+2)th-stage shift register GA(n+2) corresponding to the second direction Dr2. Figures 4A-4D and Figures 5A-5B It should be understood that the present application is only illustrative and is not intended to limit the present application. Those skilled in the art can change the values of m, y, Z, u, and v according to actual design requirements, which are allowed and included in the present application.

[0145] It should be understood that the working principle of each shift register GA in the gate driving circuit GDC can be referred toFigure 3A The working principle of the shift register GA shown is obtained, and will not be described here.

[0146] As Figures 6A-6B For the structural schematic diagram of the display panel of the embodiments of the present application, the present application further provides a display panel, which comprises any of the above-mentioned gate drive circuits GDC.

[0147] Optionally, the display panel can be a passive light-emitting display panel or a self-luminous display panel. The passive light-emitting display panel includes a liquid crystal display panel, etc., and the self-luminous display panel includes a display panel with a light-emitting device as a sub-pixel SPX. The light-emitting device can include at least one of an organic light-emitting diode, a sub-millimeter light-emitting diode, and a micro light-emitting diode.

[0148] Please continue to refer to Figures 6A-6B The display panel further comprises a plurality of sub-pixels SPX, and the plurality of sub-pixels SPX are electrically connected with the gate drive circuit GDC. The gate drive circuit GDC is configured to transmit a gate control signal Scan to the plurality of sub-pixels SPX, and the plurality of sub-pixels SPX are configured to realize the display function of the display panel according to the received gate control signal Scan and data signal.

[0149] Optionally, the gate drive circuit GDC comprises T shift registers GA, the plurality of sub-pixels SPX are electrically connected with the pth shift register GA(p) to the T-qth shift register GA(T-q), and the plurality of sub-pixels SPX are configured to receive the gate control signal Scan output by the pth shift register GA(p) to the T-qth shift register GA(T-q). The control signal generated by the shift register located before the pth shift register GA(p) is only used as a signal received by the pull-up input end PU of the pth shift register GA(p) and part of the shift registers cascaded after the pth shift register GA(p), and is not transmitted to the sub-pixels SPX of the display panel. The control signal generated by the T-q+1th shift register GA(T-q+1) to the Tth shift register GA(T) is only used as a signal received by the pull-down input end PD of part of the shift registers GA located before the T-q+1th shift register GA(T-q+1), and is not transmitted to the sub-pixels SPX of the display panel. Therefore, in some embodiments, the shift registers located before the pth shift register GA(p) and the T-q+1th shift register GA(T-q+1) to the Tth shift register GA(T) can be referred to as virtual shift registers GA. In this design form, it is beneficial to use the existing preparation process of the display panel, and there is no obvious difference in the position, line width, and line spacing of each shift register GA. Wherein, p≥1, q≥1, T>p and T>q.

[0150] In some embodiments, q = m, so that the number of the T-q+1th shift register GA(T-q+1) to the Tth shift register GA(T) is equal to m, so that the potential of the first node No1 of the T shift registers GA can be pulled down by the signal output by the corresponding shift register GA, so that the phase difference between the jump of the plurality of gate control signals Scan transmitted to the display panel from the effective level to the invalid level corresponding to the jump moment is the same, so that the display panel can realize uniform scanning setting.

[0151] Optionally, because the gate drive circuit GDC can control the plurality of shift registers GA to output the gate control signal Scan with the effective pulse in the first direction Dr1 or the second direction Dr2 in turn, therefore, the display panel corresponding to the gate drive circuit GDC can include two scanning modes, as shown in Figures 6A-6B . The two scanning modes include a first scanning mode and a second scanning mode.

[0152] In the first scanning mode of the display panel, the first control module 101 of each shift register GA is configured to connect the first node No1 and the first power supply end Vs1 in electrical connection according to the effective level of the first control signal Sc1, so that the signal of the first node No1 has the corresponding effective level. Correspondingly, the second control unit of each shift register GA can be configured to connect the first node No1 and the fourth power supply end Vs2 in electrical connection according to the effective level of the fifth control signal Sc2, so that the signal of the first node No1 has the corresponding invalid level.

[0153] In the second scanning mode of the display panel, the first control module 101 of each shift register GA is configured to connect the first node No1 and the first power supply end Vs1 in electrical connection according to the effective level of the first control signal Sc1, so that the signal of the first node No1 has the invalid level. Correspondingly, the second control unit of each shift register GA can be configured to connect the first node No1 and the fourth power supply end Vs2 in electrical connection according to the effective level of the fifth control signal Sc2, so that the signal of the first node No1 has the corresponding effective level.

[0154] Optionally, in the first scanning mode, the gate drive circuit GDC can correspondingly adopt the design in the first direction Dr1, as shown in Figure 6A . In the second scanning mode, the gate drive circuit GDC can correspondingly adopt the design in the second direction Dr2, as shown in Figure 6B .

[0155] The display panel provided by the embodiments of the present application has two scanning modes, so that the display panel can realize forward and reverse scanning design.

[0156] Optionally, the start signal STV can be a frame start signal. The second control signal LC1 and the third control signal LC2 can have a switch between an active level and an inactive level in a vertical blanking interval.

[0157] Optionally, the active pulse of the reset control signal Res can be ahead of the active pulse of the frame start signal, so as to reset the potential of the first node No1 by using at least one of the reset module 500, the first pull-down control module 301 and the second pull-down control module 302, so as to eliminate the residual charge of the first node No1.

[0158] Optionally, the start time of the active pulse of the reset control signal Res can be behind the end time of the active pulse of the gate control signal Scan output by the last stage shift register GA in the gate driving circuit GDC, so that the active pulse of the gate control signal Scan output by the last stage shift register GA can be completely output.

[0159] Optionally, in the case of power failure or other unexpected situations of the display panel, the charge of the first node No1 can be eliminated by the reset module 500.

[0160] It can be understood that the display panel can further include a plurality of data lines and other unshown parts.

[0161] Optionally, the display panel can be electrically connected with at least one of a display driving chip, a timing controller and the like. The display driving chip can be used to provide the required start signal and reset control signal Res to the gate driving circuit GDC, and the timing controller can be used to provide the required clock signal to the gate driving circuit GDC. In some embodiments, at least one of the display driving chip, the timing controller and the like can be connected with the gate driving circuit GDC in the form of at least one of a flip chip, a flexible circuit board and the like.

[0162] In some embodiments, at least one of a display driving chip, a timing controller, etc. is disposed on the circuit board 700, and the circuit board 700 is disposed on one side of the display panel. The first direction Dr1 can be a direction from the first side of the display panel close to the circuit board 700 to the second side of the display panel away from the circuit board. The second direction Dr2 can be a direction from the second side to the first side. The first side and the second side are oppositely disposed. The gate driving circuit GDC is disposed on at least one of the third side and the fourth side of the display panel. The third side and the fourth side are oppositely disposed and connected between the first side and the second side. When the gate driving circuit GDC is designed in the first direction Dr1, the distance from the first-stage shift register GA(1) in the gate driving circuit GDC to the circuit board 700 is less than the distance from the remaining shift registers to the circuit board 700. When the gate driving circuit GDC is designed in the second direction Dr2, the distance from the first-stage shift register GA(1) in the gate driving circuit GDC to the circuit board 700 is greater than the distance from the remaining shift registers to the circuit board 700.

[0163] Figures 7A-7D is a simulation timing diagram of the gate driving circuit of the embodiments of the present application corresponding to the first scanning mode and the second scanning mode. Wherein, Figure 7A is a timing diagram of the first node No1, the second node No2, the third node No3, the fourth node No4, the fifth node No5, the stage transmission signal Stn, and the gate control signal Scan corresponding to the first scanning mode of a single shift register GA, Figure 7B is a timing diagram of a plurality of gate control signals Scan output by a plurality of shift registers GA corresponding to the first scanning mode. Figure 7C is a timing diagram of the first node No1, the second node No2, the third node No3, the fourth node No4, the fifth node No5, the stage transmission signal Stn, and the gate control signal Scan corresponding to the second scanning mode of a single shift register GA, Figure 7D is a timing diagram of a plurality of gate control signals Scan output by a plurality of shift registers GA corresponding to the second scanning mode.

[0164] In order to verify that the shift register GA provided in the present application can be used in the design of the display panel to realize the first scanning mode and the second scanning mode, the inventors have carried out reliability simulation experiments on the working state of the gate driving circuit GDC in the display panel in a high temperature and high humidity environment corresponding to the first scanning mode and the second scanning mode. According to the simulation results, after at least one of the first pull-down control module 301 and the second pull-down control module 302 is provided, the plurality of gate control signals Scan output by the gate driving circuit GDC can still have effective pulses in sequence, and the output function and reliability of the gate driving circuit GDC can still meet a higher standard.

[0165] It should be understood that the display panel provided by the present application includes any of the above-mentioned gate drive circuit GDC or any of the above-mentioned shift register GA, and thus the present application also has all the beneficial effects of the above-mentioned gate drive circuit GDC or shift register GA, which will not be described here.

[0166] As Figure 8 is a schematic diagram of the structure of the display panel before and after cutting. Among them, Figure 8 GDC1 in indicates a gate drive circuit including a shift register without a first pull-down control module 301 and a second pull-down control module 302. In some embodiments, in order to control the manufacturing cost, the re-cutting technology can be used to obtain the required size of the strip screen for the large size display panel. That is, the cutting line shown in Figure 8 is cut to obtain the required size of the strip screen. However, the strip screen obtained by the re-cutting technology will cut off part of the shift register in the gate drive circuit during cutting. Therefore, when the first pull-down control module 301 and the second pull-down control module 302 are not arranged in the shift register, the last stage shift register included in the gate drive circuit of the strip screen away from the circuit board 700 side does not have a corresponding control signal for making the signal of the first node in the last stage shift register jump from the effective level to the invalid level, so that the output transistor of the last stage shift register in the strip screen will be in the on state for a long time, the output transistor is subjected to the bias stress for a long time, which affects the volt-ampere characteristic of the output transistor, causes the threshold voltage of the output transistor to drift more seriously, and the reliability of the shift register becomes weaker. Therefore, in order to meet the reliability requirements of the shift register, when the first pull-down control module and the second pull-down control module are not arranged in the shift register, a control signal for making the signal of the first node of the last stage shift register invalid is connected to the last stage shift register by using the laser process, as shown in the laser point position in Figure 8 , so as to realize the control of the signal of the first node in the last stage shift register jumping from the effective level to the invalid level. However, the introduction of the laser process will reduce the product capacity and yield, and increase the product cost.

[0167] In the present application, at least one of the first pull-down control module 301 and the second pull-down control module 302 is arranged in the shift register GA, so that when the large-size display panel is cut to obtain the required size of the strip screen by using the cutting technology, the last shift register GA in the gate drive circuit GDC can realize the control of the signal of the first node No1 in the last shift register GA from the active level jump to the invalid level through at least one of the first pull-down control module 301 and the second pull-down control module 302, without introducing the laser process again. Therefore, the reliability of the shift register GA can be improved, and the preparation cost of the display panel can be reduced, and the product capacity and yield can be improved.

[0168] As shown in Figure 9 The structure of another display panel of the present application is shown in the figure. Among them, Figure 9 The display panel shown in the figure can be Figures 6A-6B The display panel shown in the figure is obtained by cutting the display panel. In Figure 9 In the display panel shown in the figure, at least one of the first pull-down control module 301 and the second pull-down control module 302 is arranged in the shift register GA included in the gate drive circuit GDC.

[0169] The first control module 101 of each shift register GA is configured to connect the current path between the first node No1 and the first power supply end Vs1 according to the active level of the corresponding first control signal Sc1, so that the signal of the first node No1 has the corresponding active level. The second control module 102 of at least part of the shift register GA is configured to connect the current path between the first node No1 and the second power supply end VssQ according to the active level of the corresponding fifth control signal Sc2, so that the signal of the first node No1 has the corresponding invalid level.

[0170] The first pull-down control module 301 of the last m shift registers GA in the plurality of shift registers GA is configured to transmit the second control signal LC1 to the second node No2 according to the reset control signal Res, so as to connect the current path between the first node No1 and the second power supply end VssQ through the first pull-down maintenance module 201, so that the first node No1 of the last m shift registers GA has the invalid level.

[0171] Because the re-cutting technology cuts part of the shift register, the second control module of the last m shift registers in the gate drive circuit without the first pull-down control module 301 and the second pull-down control module 302 cannot jump from the effective level to the invalid level due to the lack of the corresponding fifth control signal for controlling the second control module, so that the output transistor of the last m shift registers is always in the on state. In the present application, the first pull-down control module 301 is provided to control the electrical connection between the first node No1 and the second power supply end VssQ by using the reset control signal Res and the first pull-down control module 301, so that the potential of the first node No1 of the last m shift registers GA can jump from the effective level to the invalid level, which is beneficial to shorten the on time of the output transistor To1 in the last m shift registers GA, thereby reducing the time length of the bias stress suffered by the output transistor To1 in the last m shift registers GA, improving the threshold voltage drift of the output transistor To1 in the last m shift registers GA, and thereby improving the reliability of the shift register GA.

[0172] Optionally, when the shift register GA includes the second pull-down control module 302, the second pull-down control module 302 of the last m shift registers GA in the plurality of shift registers GA is configured to transmit the third control signal LC2 to the third node No3 according to the reset control signal Res, so as to connect the current path between the first node No1 and the second power supply end VssQ through the second pull-down maintenance module 202, so that the first node No1 of the last m shift registers GA has the invalid level, thereby improving the reliability of the shift register GA.

[0173] For the convenience of understanding the present application, the display panel obtained by using the re-cutting technology is described by taking m=6 as an example.

[0174] In the gate drive circuit GDC, the shift register GA can be obtained by Figures 2A-2BThe structure shown. Gate drive circuit GDC includes T shift registers GA, the first stage shift register GA(1) ~ T-6 stage shift register GA(T-6), the fifth control signal Sc2 corresponding to the i stage shift register GA(i) is the i+6 stage shift register GA(i+6) output or the i+6 stage gate control signal Scan(i+6). Where, 1≤i≤T-6. Because the shift register GA providing the fifth control signal Sc2 to the T-5 stage shift register GA(T-5) ~ T stage shift register GA(T) is cut off in the re-cutting technology, the fifth control signal Sc2 corresponding to the T-5 stage shift register GA(T-5) ~ T stage shift register GA(T) no longer exists. Because at least one of the first pull-down control module 301 and the second pull-down control module 302 is arranged in the shift register GA, the first node No1 in the T-5 stage shift register GA(T-5) ~ T stage shift register GA(T) can be controlled to jump from the effective level to the invalid level by at least one of the first pull-down control module 301 and the second pull-down control module 302 cooperating with the reset control signal Res. That is, in the T-5 stage shift register GA(T-5) ~ T stage shift register GA(T), the first pull-down control module 301 can transmit the second control signal LC1 to the second node No2 when the reset control signal Res has an effective level, so that the signal of the second node No2 has an effective level, so that the transistor included in the first pull-down maintenance module 201 can be opened to connect the electrical connection between the first node No1 and the second power supply end VssQ. At the same time, under the influence of the signal of the first node No1 jumping from the effective level to the invalid level, the third transistor T3~the sixth transistor T6 in the first inverting module 601 are cut off, the potential of the second node No2 is further raised, and the potential of the first node No1 is further reduced until the potential of the first node No1 is equal to the potential corresponding to the second power supply end VssQ. The potential of the first node No1 stops further reduction. Similarly, in the T-5 stage shift register GA(T-5) ~ T stage shift register GA(T), the second pull-down control module 302 can transmit the third control signal LC2 to the third node No3 when the reset control signal Res has an effective level, so that the signal of the third node No3 has an effective level, so that the transistor included in the second pull-down maintenance module 202 can be opened to connect the electrical connection between the first node No1 and the second power supply end VssQ.Meanwhile, under the influence of the signal of the first node No1 jumping from the effective level to the invalid level, the third transistor T3 to the sixth transistor T6 in the second inverting module 602 are turned off, the potential of the third node No3 is further raised, and the potential of the first node No1 is further lowered until the potential of the first node No1 is equal to the potential corresponding to the second power supply end VssQ, and the potential of the first node No1 stops further lowering.

[0175] Therefore, in the display panel shown in the present application Figure 9 In the display panel shown in the present application, the signal of the first node No1 of the last-stage shift register GA in the gate drive circuit GDC can no longer be controlled to jump from the effective level to the invalid level by using the laser process, which is beneficial to reduce the cost and improve the product yield and rate.

[0176] In addition, at least one of the first pull-down control module 301 and the second pull-down control module 302 can be arranged in each shift register GA, and the first pull-down control module 301 and the second pull-down control module 302 are controlled by the reset control signal Res. Therefore, the display panel obtained by using the re-cutting technology can realize the control of the signal of the first node No1 of the last-stage shift register GA jumping from the effective level to the invalid level without being affected by the cut shift register GA.

[0177] Figures 10A-10B The simulation comparison timing diagram of the signal of the first node of the embodiment of the present application. Among them, Figure 10A The timing diagram corresponding to the shift register applied in the display panel does not include the first pull-down control module 301 and the second pull-down control module 302, Figure 10B The timing diagram corresponding to the shift register GA applied in the display panel includes the first pull-down control module 301 and the second pull-down control module 302.

[0178] In order to verify that the shift register GA of the present application can be applied to the display panel obtained by using the re-cutting technology to realize the switching control of the signal of the first node No1 of the last-stage shift register GA from the effective level to the invalid level, the inventors applied the shift register GA provided in the embodiment of the present application to the display panel obtained by using the re-cutting technology and performed reliability simulation verification.

[0179] In the simulation verification, the first control module 101 of each shift register GA is configured to connect the current path between the first node No1 and the first power supply terminal Vs1 according to the effective level of the first control signal Sc1, so that the signal of the first node No1 has the corresponding effective level, and the second control module 102 of at least part of the shift register GA is configured to connect the current path between the first node No1 and the second power supply terminal VssQ according to the effective level of the fifth control signal Sc2, so that the signal of the first node No1 has the corresponding invalid level. The control end of the eighth transistor T8 included in the second control module 102 of the last m shift registers GA in the plurality of shift registers GA is continuously applied with an invalid level (for example, the eighth transistor T8 is an N-type transistor, and a low level is continuously applied), so as to simulate that the last m shift registers GA in the display panel obtained by using the re-slicing technology do not have the corresponding fifth control signal Sc2 to control the signal of the first node No1 to jump from the effective level to the invalid level. The simulation result is shown in Table 1 and Figures 10A-10B

[0180]

[0181] wherein, as shown in Table 1, T0 represents a process center piece and does not undergo high-temperature and high-humidity action, and T0+3V represents a process limit piece and does not undergo high-temperature and high-humidity action. The transistors included in the process limit piece are caused to be positively offset by 3V due to process deviation. RA represents a process center piece, and after being produced, is put into a high-temperature and high-humidity furnace (60℃+90%RH) for 500 hours in a lighting state. RA+3V represents a process limit piece, and after being produced, is put into a high-temperature and high-humidity furnace (60℃+90%RH) for 500 hours in a lighting state.

[0182] According to the simulation result, when the first pull-down control module 301 and the second pull-down control module 302 are not included in the shift register, the transition time tA of the signal of the first node of the last shift register in the gate driving circuit from the effective level to the invalid level is relatively long, as shown in Table 2. Figure 10A When the first pull-down control module 301 and the second pull-down control module 302 are included in the shift register GA, the transition time of the signal of the first node No1 of the last shift register GA in the gate driving circuit GDC from the effective level to the invalid level is obviously shortened, as shown in Table 3. Figure 10B Therefore, the shift register GA provided in the embodiment of the present application is applied to the display panel obtained by using the re-slicing technology, and can meet the pull-down of the signal of the first node No1 of the last shift register GA, and the design of the shift register GA meets the design expectation.

[0183] ​Optionally, in the display panel obtained by the re-cutting technology, the display panel is electrically connected with at least one of a display driving chip, a timing controller, etc., the display driving chip can be configured to provide a required start signal and a reset control signal Res to the gate driving circuit GDC, and the timing controller can be configured to provide a required clock signal to the gate driving circuit GDC. At least one of the display driving chip, the timing controller, etc. can be connected with the gate driving circuit GDC in at least one of a form of a chip on film (COF), a flexible printed circuit board (FPCB), etc.

[0184] In some embodiments, in the display panel obtained by the re-cutting technology, the gate driving circuit GDC outputs a plurality of gate control signals Scan having effective pulses in turn along a first direction Dr1. The first direction Dr1 can be a direction from a first side of the display panel close to the circuit board 700 to a second side of the display panel away from the circuit board 700. In this way, the gate driving circuit GDC can still have a corresponding start signal without introducing a laser process, so that the gate driving circuit GDC can be started and output a plurality of gate control signals Scan under the action of the start signal. Moreover, the signal of the first node No1 in the last-stage shift register GA in the gate driving circuit GDC can be controlled to jump from an effective level to an ineffective level by at least one of the first pull-down control module 301 and the second pull-down control module 302, so as to improve the reliability of the gate driving circuit GDC, reduce the production cost of the display panel, and improve the product capacity and product yield.

[0185] It should be understood that the display panel provided by the embodiments of the present application includes any of the above-mentioned shift registers GA or any of the above-mentioned gate driving circuits GDC, and therefore has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0186] The present application can also provide a display device, which can include any of the above-mentioned display panels, any of the above-mentioned shift registers GA, or any of the above-mentioned gate driving circuits GDC.

[0187] Optionally, the display device can include the above-mentioned display driving chip and timing controller.

[0188] Optionally, the display device can be a mobile phone, a computer, a virtual reality display, an augmented reality display, or the like. The display device can be a device for realizing a display function applied to the fields of education, entertainment, transportation, medical treatment, national defense, etc.

[0189] It should be understood that the display device includes any of the above display panels, any of the above shift registers GA, or any of the above gate drive circuits GDC. Therefore, the display device has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0190] The above is only optional embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or directly / indirectly applied to other related technical fields within the inventive concept of the present application is included in the patent protection scope of the present application.

Claims

1. A shift register, characterized in that, include: The first control module is electrically connected to the first node and the first power supply terminal, and is configured to connect the current path between the first node and the first power supply terminal according to the first control signal, so that the signal of the first node has a corresponding effective level. The first pull-down sustaining module is electrically connected to the first node, the second node, and the second power supply terminal, and is configured to control the electrical connection between the first node and the second power supply terminal according to the signal of the second node. The first pull-down control module is electrically connected to the second node and is configured to transmit a second control signal to the second node according to a reset control signal, so as to connect the current path between the first node and the second power supply terminal through the first pull-down sustaining module, so that the signal of the first node is invalid. as well as An output module includes an output transistor, the control terminal of which is electrically connected to the first node, and the output module is configured to control the electrical connection between the clock line and the signal output terminal of the shift register according to the signal of the first node.

2. The shift register according to claim 1, characterized in that, Also includes: A reset module, electrically connected to the first node and the second power supply terminal, is configured to control the electrical connection between the first node and the second power supply terminal according to the reset control signal.

3. The shift register according to claim 2, characterized in that, The reset module includes: A reset transistor, wherein the control terminal of the reset transistor is configured to receive the reset control signal, the first source-drain terminal of the reset transistor is electrically connected to the second power supply terminal, and the second source-drain terminal of the reset transistor is electrically connected to the first node.

4. The shift register according to any one of claims 1 to 3, characterized in that, The first pull-down control module includes a first pull-down transistor, the control terminal of the first pull-down transistor is configured to receive the reset control signal, the first source-drain terminal of the first pull-down transistor is configured to receive the second control signal, and the second source-drain terminal of the first pull-down transistor is electrically connected to the second node.

5. The shift register according to claim 1, characterized in that, Also includes: The second pull-down sustaining module is electrically connected to the first node, the third node, and the second power supply terminal, and is configured to control the electrical connection between the first node and the second power supply terminal according to the signal of the third node. as well as The second pull-down control module is electrically connected to the third node and is configured to transmit a third control signal to the third node according to the reset control signal, so as to control the second pull-down maintenance module to connect the electrical connection between the first node and the second power supply terminal. The phase of the second control signal is opposite to the phase of the third control signal.

6. The shift register according to claim 5, characterized in that, The second pull-down control module includes a second pull-down transistor, the control terminal of the second pull-down transistor is configured to receive the reset control signal, the first source-drain terminal of the second pull-down transistor is configured to receive the third control signal, and the second source-drain terminal of the second pull-down transistor is electrically connected to the third node.

7. The shift register according to claim 5, characterized in that, At least one of the first pull-down sustaining module and the second pull-down sustaining module includes a first switching transistor, the first source-drain terminal of the first switching transistor is electrically connected to the second power supply terminal, and the second source-drain terminal of the first switching transistor is electrically connected to the first node. In the first pull-down sustaining module, the control terminal of the first switching transistor is electrically connected to the second node; in the second pull-down sustaining module, the control terminal of the first switching transistor is electrically connected to the third node.

8. The shift register according to claim 5, characterized in that, Also includes: A first inverting module, electrically connected to the second node, is configured to control the signal of the second node to have an invalid level during the period when the signal of the first node has a corresponding valid level, according to the second control signal and the fourth control signal; and / or, The second inverting module, electrically connected to the third node, is configured to control the signal of the third node to have an invalid level according to the third control signal and the fourth control signal during the period when the signal of the first node has a corresponding valid level.

9. The shift register according to claim 8, characterized in that, The fourth control signal includes the first sub-control signal; The first sub-control signal is the same as the first control signal; or, The first sub-control signal and the signal of the first node have the same frequency, and the start time of the effective pulse of the first sub-control signal precedes the start time of the effective pulse of the first control signal. At least one of the first inverting module and the second inverting module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second source-drain terminal of the first transistor is electrically connected to the control terminal of the second transistor and the second source-drain terminal of the third transistor. The control terminals of the third transistor and the fourth transistor are configured to receive the first sub-control signal. The first source-drain terminal of the third transistor and the first source-drain terminal of the fourth transistor are electrically connected to the second power supply terminal. In the first inverting module, the control terminal of the first transistor, the first source-drain terminal of the first transistor, and the first source-drain terminal of the second transistor are configured to receive the second control signal, and the second source-drain terminal of the second transistor and the second source-drain terminal of the fourth transistor are electrically connected to the second node; in the second inverting module, the control terminal of the first transistor, the first source-drain terminal of the first transistor, and the first source-drain terminal of the second transistor are configured to receive the third control signal, and the second source-drain terminal of the second transistor and the second source-drain terminal of the fourth transistor are electrically connected to the third node.

10. The shift register according to claim 9, characterized in that, The fourth control signal includes the second sub-control signal; The second sub-control signal is the same as the first control signal; or, The second sub-control signal and the signal of the first node have the same frequency. The start time of the effective pulse of the second sub-control signal lags behind the start time of the effective pulse of the first control signal, and the end time of the effective pulse of the second sub-control signal precedes the start time of the effective pulse of the reset control signal. At least one of the first inverting module and the second inverting module includes a fifth transistor and a sixth transistor. The control terminals of the fifth transistor and the sixth transistor are configured to receive the second sub-control signal. The first source-drain terminals of the fifth transistor and the first source-drain terminals of the sixth transistor are electrically connected to the second power supply terminal. The second source-drain terminal of the fifth transistor is electrically connected to the control terminal of the corresponding second transistor. In the first inverting module, the second source-drain terminal of the sixth transistor is electrically connected to the second node; in the second inverting module, the second source-drain terminal of the sixth transistor is electrically connected to the third node.

11. The shift register according to claim 5, characterized in that, The shift register also includes: The cascade module, electrically connected to the first node, is configured to control the electrical connection between the clock line and the cascade output terminal of the shift register according to the signal from the first node.

12. The shift register according to claim 11, characterized in that, At least one of the first pull-down sustaining module and the second pull-down sustaining module is electrically connected to the stage transmission output terminal, the signal output terminal and the third power supply terminal; Wherein, the first pull-down sustaining module is configured to control the electrical connection between the stage transmission output terminal and the second power supply terminal according to the signal from the second node, and to control the electrical connection between the signal output terminal and the third power supply terminal according to the signal from the second node; and / or, The second pull-down sustaining module is configured to control the electrical connection between the stage transmission output terminal and the second power supply terminal according to the signal of the third node, and to control the electrical connection between the signal output terminal and the third power supply terminal according to the signal of the third node.

13. The shift register according to claim 12, characterized in that, At least one of the first pull-down sustaining module and the second pull-down sustaining module includes a second switching transistor and a third switching transistor. The first source-drain terminal of the second switching transistor is electrically connected to the second power supply terminal, the second source-drain terminal of the second switching transistor is electrically connected to the stage transmission output terminal, the first source-drain terminal of the third switching transistor is electrically connected to the third power supply terminal, and the second source-drain terminal of the third switching transistor is electrically connected to the signal output terminal. In the first pull-down sustaining module, the control terminals of the second and third switching transistors are electrically connected to the second node; and / or, In the second pull-down sustaining module, the control terminals of the second and third switching transistors are electrically connected to the third node.

14. The shift register according to claim 1 or 2, characterized in that, The first control module includes a seventh transistor, the control terminal of the seventh transistor is configured to receive the first control signal, the first source-drain terminal of the seventh transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the seventh transistor is electrically connected to the first node. The output module includes a capacitor electrically connected between the first node and the signal output terminal. The first source-drain terminal of the output transistor is electrically connected to the clock line, and the second source-drain terminal of the output transistor is electrically connected to the signal output terminal.

15. The shift register according to claim 1 or 2, characterized in that, Also includes: The second control module, electrically connected to the first node and the fourth power supply terminal, is configured to control the electrical connection between the first node and the fourth power supply terminal according to the fifth control signal. The phase of the electrical signal supplied by the first power supply terminal is opposite to the phase of the electrical signal supplied by the fourth power supply terminal, and the time period during which the first control signal has an effective pulse does not overlap with the time period during which the fifth control signal has an effective pulse.

16. The shift register according to claim 15, characterized in that, The second control module includes: The eighth transistor has a control terminal configured to receive the fifth control signal, a first source-drain terminal electrically connected to the fourth power supply terminal, and a second source-drain terminal electrically connected to the first node.

17. A gate driving circuit, characterized in that, include: Multiple shift registers as described in any one of claims 1 to 16; When the first control module is configured to transmit the signal supplied by the first power supply to the first node according to the first control signal, so that the signal of the first node has a corresponding effective level, the first control signal corresponding to the first m shift registers in the plurality of shift registers is the start signal, and the first control signal corresponding to the nth level shift register in the plurality of shift registers is the signal output by the nmth level shift register, 1≤m <n,n-m≥1; or, When the first control module is configured to transmit the signal supplied by the first power supply to the first node according to the first control signal, so that the signal of the first node has a corresponding invalid level, the first control signal corresponding to the x-th stage shift register is the signal output by the x+y-th stage shift register, where x≥1 and y≥1.

18. The gate driving circuit according to claim 17, characterized in that, The shift register includes: The first inverting module is electrically connected to the second node of the shift register at this stage and is configured to control the second control signal and the signal supplied by the second power supply terminal to be transmitted to the second node in a time-division manner according to the second control signal and the first sub-control signal. Wherein, the first sub-control signal corresponding to the nth level shift register is the signal of the first node in the null level shift register, u < m.

19. The gate driving circuit according to claim 17, characterized in that, The shift register includes: The first inverting module is electrically connected to the second node of the shift register at this stage and is configured to control the second control signal and the signal supplied by the second power supply terminal to be transmitted to the second node in a time-division manner according to the second control signal and the second sub-control signal. Wherein, the second sub-control signal corresponding to the nth stage shift register is the signal of the first node in the (n+v)th stage shift register, where v < m.

20. A display panel, characterized in that, include: The gate drive circuit as described in any one of claims 17 to 19; In the first scanning mode of the display panel, the first control module of each shift register is configured to connect the first node and the first power supply terminal according to the effective level corresponding to the first control signal, so that the signal of the first node has the corresponding effective level. In the second scanning mode of the display panel, the first control module of each shift register is configured to connect the electrical connection between the first node and the first power supply terminal according to the effective level of the first control signal, so that the signal of the first node has an invalid level.

21. A display panel, characterized in that, include: The gate drive circuit as described in any one of claims 17 to 19; The first control module of each shift register is configured to connect the current path between the first node and the first power supply terminal according to the effective level corresponding to the first control signal, so that the signal of the first node has the corresponding effective level. The first pull-down control module of the last m shift registers in the plurality of shift registers is configured to transmit the second control signal to the second node according to the reset control signal, so as to connect the current path between the first node and the second power supply terminal through the first pull-down sustaining module, so that the first node of the last m shift registers has an invalid level.

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