Signal sampling method and system for dynamic frequency optimization

Abstract

The invention belongs to the technical field of data acquisition, and particularly relates to a signal sampling method and system for dynamic frequency optimization. The method comprises the following steps: presetting a basic sampling frequency based on target signal characteristics, sampling an analog signal at a frequency f1 through an analog-to-digital converter (ADC) to generate a first digital signal sequence, executing a feature extraction algorithm on the first digital signal sequence in an MCU to obtain an actual signal feature value, and calculating a difference value between the actual feature value and a preset target feature value, according to the method, signal features are extracted in real time, the sampling frequency is adjusted in a closed-loop mode through PI D, power consumption and resource occupation are reduced, meanwhile, it is ensured that transient events are completely captured, the power consumption is reduced in a self-adaptive mode along with signal complexity, the capture rate of the transient events is high, and the method is suitable for large-scale popularization and application. Missing acquisition of a traditional fixed low-frequency scheme is avoided; the method is suitable for wearable, industrial monitoring, automotive electronics and other scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data acquisition, in particular to a signal sampling method and system with dynamic frequency optimization. BACKGROUND

[0002] In the field of digital signal processing, the frequency of a digital signal is a very important concept. In existing technologies, analog signal sampling is mostly in the form of fixed frequency. Generally, the higher the frequency, the more information of the analog signal can be covered. However, as the frequency of data increases, the power consumption of the device also increases, and the time required for algorithm operation also increases, resulting in waste of resources. When the sampling frequency is too low, the result after the algorithm cannot reach the desired accuracy, and the details of the signal are missed.

[0003] In a digital signal processing system, the selection of the sampling frequency fs directly determines the signal reconstruction quality, the algorithm operation amount and the system power consumption. Existing solutions mostly use fixed sampling frequency, which has the following contradictions:

[0004] Although a high sampling rate can capture signal details, it leads to linear increase of ADC, MCU operation resources and power consumption;

[0005] Although a low sampling rate reduces power consumption, it may lose key transient characteristics, affecting the accuracy of subsequent diagnosis, recognition or control.

[0006] Therefore, how to adaptively adjust the sampling frequency according to the "signal content" has become a technical problem that needs to be solved in the field, and therefore we propose a signal sampling method with dynamic frequency optimization to solve the above problems. SUMMARY

[0007] (I) Technical problems solved

[0008] In view of the deficiencies of the prior art, the present application aims to provide an analog signal sampling method and system with dynamic frequency, which minimizes system power consumption P and resource occupation under the premise of ensuring complete capture of key characteristics (such as heart rate period, rotation period, instantaneous impact, etc.), solving the problems raised in the background art.

[0009] (II) Technical solutions

[0010] The present application specifically adopts the following technical solutions to achieve the above-mentioned purposes:

[0011] A signal sampling method with dynamic frequency optimization, comprising the following steps:

[0012] S1, system initialization stage, presetting a basic sampling frequency f1 based on the characteristics of the target signal;

[0013] S2. Sample the analog signal at a frequency f1 through an analog-to-digital converter (ADC) to generate a first digital signal sequence;

[0014] S3. Execute a feature extraction algorithm on the first digital signal sequence in the MCU to obtain the actual signal feature value F_actual;

[0015] S4. Calculate the difference value between the actual feature value F_actual and the preset target feature value F_target: e = |F_actual - F_target|;

[0016] S5. Input the difference value e into a PID controller to generate a frequency adjustment amount Δf through the following formula:

[0017] Δf = Kp·e + Ki·∫e·dt + Kd·de / dt;

[0018] where Kp, Ki, and Kd are preset proportional, integral, and differential coefficients;

[0019] S6. Calculate the second sampling frequency f2 = f1 + α·Δf according to the adjustment amount Δf, where α is an adjustable gain coefficient between 0.1 and 1.0;

[0020] S7. Dynamically adjust the sampling frequency of the ADC from f1 to f2 and continue to sample the analog signal at f2 to obtain a second digital signal sequence.

[0021] Further, the feature extraction algorithm in step S3 includes:

[0022] Use the fast Fourier transform (FFT) to extract the fundamental frequency for periodic signals;

[0023] Use wavelet transform to extract transient features for non-stationary signals;

[0024] Use a peak detection algorithm to extract periodic parameters for biomedical signals.

[0025] Further, in step S3, the features include at least one of the motion frequency, heart rate period, rotation period, instantaneous amplitude, instantaneous frequency, vibration period, or signal energy distribution.

[0026] Further, the dynamic configuration rule of the PID coefficients in step S is as follows:

[0027] When e > e_max, use the PD control mode with Kp = 0.8, Ki = 0, and Kd = 0.2;

[0028] When e_min < e ≤ e_max, use the standard PID mode with Kp = 0.5, Ki = 0.3, and Kd = 0.2;

[0029] When e ≤ e_min, the integral hold mode with Ki = 1.0 is adopted.

[0030] Furthermore, it also includes: setting up a sampling frequency buffer within the MCU to record the sampling frequency sequence {f2,f3,…,fN} after the most recent N adjustments;

[0031] The sampling frequency sequence in the buffer is subjected to smoothing filtering to eliminate high-frequency jitter caused by instantaneous disturbances;

[0032] Smoothing filters are implemented using moving average, exponentially weighted moving average (EWMA), or Kalman filtering.

[0033] Furthermore, in step S7, the ADC sampling frequency is updated dynamically with f2 to ensure that the system satisfies:

[0034] Power consumption = K × f, where K is the device power consumption coefficient, and the feature extraction error e ≤ preset threshold.

[0035] Furthermore, step S7 also includes a resource optimization mechanism:

[0036] When N consecutive samples satisfy e≤e_min, f2 is reduced by β, where β=0.7-0.9;

[0037] When a signal mutation (|de / dt|>δ) is detected, the sampling is immediately switched to f_max.

[0038] Furthermore, in any of steps S2 to S7, if an abnormal transient event is detected, an event-driven interrupt is immediately triggered, the sampling frequency is instantly increased to the preset transient high frequency f_emergency, and then drops back to f2 after the event ends, so as to ensure complete sampling of the transient event.

[0039] A dynamic frequency-optimized signal sampling system, which is used based on the method described above, includes:

[0040] An analog-to-digital converter (ADC) is used to convert analog signals into digital signals.

[0041] The microcontroller unit (MCU) is used to execute feature extraction algorithms, PID calculations, and frequency adjustment.

[0042] The storage unit is used to store target feature values, PID coefficients, historical sampling frequency sequences, and intermediate calculation results.

[0043] A communication interface is provided for uploading sampled data or system parameters to a host computer or cloud server; the communication interface includes:

[0044] The power management unit (PMU) is used to dynamically adjust the supply voltage and clock frequency according to the current sampling frequency in order to reduce power consumption.

[0045] The ADC, MCU, storage unit, communication interface and PMU are connected via bus or point-to-point to form a closed-loop control circuit.

[0046] Furthermore, the microcontroller unit (MCU) incorporates: a digital filter bank for signal preprocessing; a multimodal feature extraction unit supporting parallel computing; and a hardware PID accelerator for hardware-based differential equation solving, enabling one PID iteration operation to be completed within a single clock cycle to reduce software overhead.

[0047] (III) Beneficial Effects

[0048] Compared with the prior art, the present invention provides a dynamic frequency-optimized signal sampling method and system, which has the following beneficial effects:

[0049] This invention extracts signal features in real time and uses PID closed-loop adjustment of the sampling frequency to ensure complete capture of transient events while reducing power consumption and resource consumption. Power consumption decreases adaptively with signal complexity, and the transient event capture rate is high, avoiding the missed sampling of traditional fixed low-frequency solutions. The PID closed-loop adjustment convergence time is <200ms, meeting real-time requirements. It is applicable to multiple scenarios such as wearable devices, industrial monitoring, and automotive electronics. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the system framework of the present invention;

[0051] Figure 2 This is a schematic diagram of the method flow of the present invention;

[0052] Figure 3 This is a schematic diagram of the frequency changing method of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] Example

[0055] like Figure 1 , Figure 2 and Figure 3 As shown, an embodiment of the present invention proposes a dynamic frequency-optimized signal sampling method, which includes the following steps:

[0056] S1. During the system initialization phase, the basic sampling frequency f1 is preset based on the characteristics of the target signal.

[0057] S2. The analog signal is sampled at frequency f1 by the analog-to-digital converter (ADC) to generate the first digital signal sequence;

[0058] S3. Execute a feature extraction algorithm on the first digital signal sequence in the MCU to obtain the actual signal feature value F_actual; the feature includes at least one of motion frequency, heart rate cycle, rotation cycle, instantaneous amplitude, instantaneous frequency, vibration cycle or signal energy distribution.

[0059] S4. Calculate the difference between the actual feature value F_actual and the preset target feature value F_target: e = |F_actual - F_target|;

[0060] S5. Input the difference value e into the PID controller, and generate the frequency adjustment Δf using the following formula:

[0061] Δf=Kp·e+Ki·∫e·dt+Kd·de / dt;

[0062] Where Kp, Ki, and Kd are preset proportional, integral, and differential coefficients;

[0063] S6. Calculate the second sampling frequency f2 = f1 + α·Δf based on the adjustment amount Δf, where α is an adjustable gain coefficient of 0.1-1.0;

[0064] S7. Dynamically adjust the ADC sampling frequency from f1 to f2, and continue sampling the analog signal at f2 to obtain the second digital signal sequence. Update the ADC sampling frequency with f2 for dynamic sampling, so that the system satisfies:

[0065] Power consumption = K × f, where K is the device power consumption coefficient, and the feature extraction error e ≤ preset threshold.

[0066] This invention extracts signal features in real time and uses PID closed-loop adjustment of the sampling frequency to ensure complete capture of transient events while reducing power consumption and resource usage. Power consumption decreases adaptively with signal complexity, and the transient event capture rate is high, avoiding the missed sampling of traditional fixed low-frequency solutions. The PID closed-loop adjustment convergence time is <200ms, meeting real-time requirements. It is applicable to multiple scenarios such as wearable devices, industrial monitoring, and automotive electronics.

[0067] like Figure 1 , Figure 2 and Figure 3 As shown, in some embodiments, the feature extraction algorithm in step S3 includes:

[0068] For periodic signals, the fundamental frequency is extracted using the Fast Fourier Transform (FFT);

[0069] For non-stationary signals, wavelet transform is used to extract transient features;

[0070] For biomedical signals, the peak detection algorithm is used to extract period parameters.

[0071] As Figure 1 、 Figure 2 及 Figure 3 shown, in some embodiments, the PID coefficient dynamic configuration rule in step S5 is:

[0072] When e > e_max, a PD control mode with Kp = 0.8, Ki = 0, Kd = 0.2 is adopted;

[0073] When e_min < e ≤ e_max, a standard PID mode with Kp = 0.5, Ki = 0.3, Kd = 0.2 is adopted;

[0074] When e ≤ e_min, an integral hold mode with Ki = 1.0 is adopted.

[0075] 如 Figure 1 、 Figure 2 及 Figure 3 shown, in some embodiments, it further includes: setting a sampling frequency buffer in the MCU to record the sequence of sampling frequencies {f2, f3, …, fN} after the most recent N adjustments;

[0076] Performing a smoothing filtering process on the sampling frequency sequence in the buffer to eliminate high-frequency jitter caused by instantaneous disturbances;

[0077] The smoothing filtering is implemented using moving average, exponentially weighted moving average EWMA, or Kalman filtering.

[0078] 如 Figure 1 、 Figure 2 及 Figure 3 shown, in some embodiments, the step S7 further includes a resource optimization mechanism:

[0079] When N consecutive samplings satisfy e ≤ e_min, f2 is reduced by a ratio of β, where β = 0.7 - 0.9;

[0080] When a signal mutation (|de / dt| > δ) is detected, sampling is immediately switched to f_max.

[0081] 如 Figure 1 、 Figure 2 及 Figure 3As shown, in some embodiments, if an abnormal transient event is detected in any of steps S2 to S7, an event-driven interrupt is immediately triggered, the sampling frequency is instantly increased to a preset high transient frequency f_emergency, and then drops back to f2 after the event ends, so as to ensure complete sampling of the transient event.

[0082] A dynamic frequency-optimized signal sampling system, which is used based on the method described above, includes:

[0083] An analog-to-digital converter (ADC) is used to convert analog signals into digital signals; the ADC is any one of successive approximation SARADC, Σ-ΔADC, or time-interleaved TIADC, and has a programmable sampling clock input port.

[0084] The microcontroller unit (MCU) is used to execute feature extraction algorithms, PID calculations, and frequency adjustment.

[0085] The microcontroller unit (MCU) incorporates: a digital filter bank for signal preprocessing; a multimodal feature extraction unit supporting parallel computing; and a hardware PID accelerator that implements differential equation solving in hardware, enabling one PID iteration calculation to be completed within a single clock cycle to reduce software overhead.

[0086] The storage unit is used to store target feature values, PID coefficients, historical sampling frequency sequences, and intermediate calculation results.

[0087] A communication interface is provided for uploading sampled data or system parameters to a host computer or cloud server; the communication interface includes:

[0088] Wired interfaces: UART, SPI, I 2 C, USB, CAN, Ethernet;

[0089] Wireless interfaces: BLE, Zigbee, LoRa, NB-IoT, Wi-Fi, Sub-1GHz RF;

[0090] The communication protocol stack supports OTA remote upgrades to update PID coefficients, feature extraction algorithms, or transient event thresholds online.

[0091] The power management unit (PMU) is used to dynamically adjust the supply voltage and clock frequency according to the current sampling frequency to reduce power consumption. The PMU has a multi-level dynamic voltage and frequency regulation (DVFS) function, and its output voltage and frequency satisfy: Vout∝f2^α, where 0<α≤1, so as to minimize power consumption while ensuring data accuracy.

[0092] The ADC, MCU, storage unit, communication interface and PMU are connected via bus or point-to-point to form a closed-loop control circuit.

[0093] When in use, the dynamic frequency-optimized signal sampling method of this application has the following steps:

[0094] Step S1: After the system is powered on, set the initial sampling frequency f1;

[0095] Step S2: Perform analog-to-digital conversion on the analog signal using f1 to obtain the digital signal sequence D1;

[0096] Step S3: Run the feature extraction algorithm in the MCU to obtain the current signal feature value C;

[0097] Step S4: Calculate the feature difference e = |C – Ctarget|, where Ctarget is the preset target feature value;

[0098] Step S5: Input e into the digital PID controller, and output the new sampling frequency f2;

[0099] Step S6: Update the ADC sampling clock to f2, and repeat steps S2-S5 until e enters the allowable error band;

[0100] Step S7: If a transient event flag (such as an amplitude jump or a slope change) is detected, immediately switch to the emergency frequency fEM, and return to f2 after the event ends.

[0101] In summary, this invention extracts signal features in real time and uses PID closed-loop adjustment of the sampling frequency to ensure complete capture of transient events while reducing power consumption and resource usage. Power consumption decreases adaptively with signal complexity, and the transient event capture rate is high, avoiding the missed sampling of traditional fixed low-frequency solutions. The PID closed-loop adjustment convergence time is <200ms, meeting real-time requirements. It is applicable to multiple scenarios such as wearable devices, industrial monitoring, and automotive electronics.

[0102] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0103] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0104] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0105] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0106] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0107] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0108] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A signal sampling method with dynamic frequency optimization, characterized in that, It includes the following steps: S1. In the system initialization stage, preset the basic sampling frequency f1 based on the target signal characteristics; S2. Sample the analog signal at the frequency f1 through the analog-to-digital converter ADC to generate the first digital signal sequence; S3. Execute the feature extraction algorithm on the first digital signal sequence in the MCU to obtain the actual signal feature value F_actual; S4. Calculate the difference value between the actual feature value F_actual and the preset target feature value F_target: e = |F_actual - F_target|; S5. Input the difference value e into the PID controller and generate the frequency adjustment amount Δf through the following formula: Δf = Kp·e + Ki·∫e·dt + Kd·de / dt; where Kp, Ki, and Kd are the preset proportional, integral, and differential coefficients; S6. Calculate the second sampling frequency f2 = f1 + α·Δf according to the adjustment amount Δf, where α is an adjustable gain coefficient of 0.1 - 1.0; S7. Dynamically adjust the sampling frequency of the ADC from f1 to f2 and continue to sample the analog signal at f2 to obtain the second digital signal sequence.

2. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that: The feature extraction algorithm in step S3 includes: Adopt the fast Fourier transform to extract the fundamental frequency for periodic signals; Adopt wavelet transform to extract transient features for non-stationary signals; Adopt the peak detection algorithm to extract periodic parameters for biomedical signals.

3. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that: In step S3, the features include at least one of the movement frequency, heart rate period, rotation period, instantaneous amplitude, instantaneous frequency, vibration period, or signal energy distribution.

4. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that: The dynamic configuration rule of the PID coefficients in step S5 is: When e > e_max, adopt the PD control mode with Kp = 0.8, Ki = 0, and Kd = 0.2; When e_min < e ≤ e_max, adopt the standard PID mode with Kp = 0.5, Ki = 0.3, and Kd = 0.2; When e ≤ e_min, adopt the integral hold mode with Ki = 1.

0.

5. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that... It further includes: Set a sampling frequency buffer in the MCU to record the sampling frequency sequence {f2, f3,..., fN} after the last N adjustments; Perform smoothing filtering on the sampling frequency sequence in the buffer to eliminate the high-frequency jitter caused by instantaneous disturbances; The smoothing filtering is implemented by moving average, exponentially weighted moving average EWMA, or Kalman filtering.

6. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that: In step S7, update the ADC sampling frequency with f2 for dynamic sampling to make the system satisfy: Power consumption Power = K×f, where K is the device power consumption coefficient, and the feature extraction error e ≤ the preset threshold.

7. The signal sampling method with dynamic frequency optimization according to claim 6, characterized in that: Step S7 further includes a resource optimization mechanism: When N consecutive samplings satisfy e ≤ e_min, reduce f2 by a ratio of β, where β = 0.7 - 0.9; When a signal mutation (|de / dt| > δ) is detected, immediately switch to f_max for sampling.

8. The signal sampling method with dynamic frequency optimization according to claim 1, characterized in that: In any step from S2 to S7, if an abnormal transient event is detected, immediately trigger an event-driven interrupt, instantaneously increase the sampling frequency to the preset transient high frequency f_emergency, and return to f2 after the event ends to ensure the complete sampling of the transient event.

9. A dynamic frequency-optimized signal sampling system, the system being used based on the method described in any one of claims 1-8, characterized in that: It includes: An analog-to-digital converter (ADC) is used to convert analog signals into digital signals. The microcontroller unit (MCU) is used to execute feature extraction algorithms, PID calculations, and frequency adjustment. The storage unit is used to store target feature values, PID coefficients, historical sampling frequency sequences, and intermediate calculation results. A communication interface is provided for uploading sampling data or system parameters to a host computer or cloud server; the communication interface includes: The power management unit (PMU) is used to dynamically adjust the supply voltage and clock frequency according to the current sampling frequency. The ADC, MCU, storage unit, communication interface and PMU are connected via bus or point-to-point to form a closed-loop control circuit.

10. A dynamic frequency-optimized signal sampling system according to claim 9, characterized in that: The microcontroller unit (MCU) incorporates: a digital filter bank for signal preprocessing; a multimodal feature extraction unit supporting parallel computing; and a hardware PID accelerator for hardware-based differential equation solving, enabling one PID iteration operation to be completed within a single clock cycle.

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