Shield gate groove type power device and preparation method thereof

Abstract

The invention discloses a shield gate trench type power device and a preparation method thereof. The preparation method comprises the following steps: depositing thick oxide layers with consistent thickness on the inner sides of a first trench and a second trench and the upper surface of a first conductive type epitaxial layer; filling shield gate polycrystalline silicon and a first hard mask layer in the first groove and the second groove, and removing the thick oxide layer by taking the first hard mask layer as a mask; removing the first hard mask layer, and depositing inter-gate oxide and silicon nitride which are consistent in thickness; filling mask polycrystalline silicon and a second hard mask layer in the first groove and the second groove, and removing the inter-gate oxide in the inner side areas of the adjacent first groove and second groove by taking the second hard mask layer as a mask; sequentially removing the second hard mask layer, the mask polycrystalline silicon and the silicon nitride; and depositing a gate oxidation medium with consistent thickness. The thickness of the inter-gate oxide layer dielectric can be ensured to be uniform and consistent, so that the gate source capacitance of the cell in the active region is improved, and the stability of the device performance is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of preparation of shield gate trench power devices, in particular to a shield gate trench power device and a preparation method thereof. BACKGROUND

[0002] The shield gate trench power device refers to a shield gate trench (SGT) power metal oxide semiconductor field effect transistor (MOSFET) device. Due to the presence of the shield gate, the device has a charge coupling effect capability, so that the on-resistance and breakdown voltage of the device reach a corresponding balance, and the device has excellent switching characteristics and on characteristics, which can improve the use efficiency of the system in which the device is used. The shield gate trench power device is widely used as a switching device in power management, driving, household appliances and other fields.

[0003] At present, the shield gate trench MOSFET device cell structure in the prior art has two structures, an up-down structure and a left-right structure. In the up-down structure, the shield gate polysilicon in the trench is located below and is used to connect the source electrode; the polysilicon gate in the trench is located above and is used to connect the gate electrode. In the left-right structure, the shield gate polysilicon in the trench is located in the middle and is used to connect the source electrode; the polysilicon gate in the trench is located on both sides and is used to connect the gate electrode.

[0004] In the up-down structure of the existing N-type shield gate trench power device, the source polysilicon in the shield gate and the gate polysilicon are isolated by an insulating medium layer, which is generally an inter-gate oxide layer medium IPO. There are generally two schemes for generating the inter-gate oxide medium layer IPO. The first scheme is to generate the source shield gate polysilicon, then thermally oxidize the source shield gate polysilicon to generate a silicon dioxide medium, and then etch to form an inter-gate oxide layer medium IPO with a certain thickness. This scheme has complicated steps and high process requirements. The second scheme is to form the source shield gate polysilicon, then deposit and etch a process to form an inter-gate oxide layer medium IPO with a certain thickness on the top of the source shield gate polysilicon. This method has a simple process, but due to the instability of the etching process, the thickness of the inter-gate oxide layer medium IPO cannot be consistent. If the medium layer is too thin, the source shield gate polysilicon and the gate polysilicon can be broken down, and if the medium layer is too thick, the capacitance distribution can be uneven, which affects the performance of the device. SUMMARY

[0005] The present application aims to at least partially solve one of the problems in the related art. To this end, one of the objects of the present application is to provide a preparation method of a shielded gate trench power device, which ensures the uniform thickness of the gate oxide layer medium, thereby improving the Cgs (gate-source capacitance) of the cell in the active region, and helping to ensure the stability of the device performance.

[0006] To achieve the above object, the present application adopts the following technical solution:

[0007] The preparation method of a shielded gate trench power device comprises the following steps:

[0008] S1: forming a first conductive type epitaxial layer in a first conductive type substrate; forming a first trench and a second trench in the first conductive type epitaxial layer, wherein the center line of the first conductive type epitaxial layer between the first trench and the second trench is the boundary line between the terminal region and the active region;

[0009] S2: depositing a thick oxide layer with uniform thickness on the inner side of the first trench and the second trench and the upper surface of the first conductive type epitaxial layer;

[0010] S3: filling the first trench and the second trench with shielded gate polysilicon and a first hard mask layer, wherein the first hard mask layer covers one side of the second trench away from the first trench;

[0011] S4: removing the thick oxide layer with the first hard mask layer as a mask; then removing the first hard mask layer and depositing gate oxide and silicon nitride with uniform thickness;

[0012] S5: filling the first trench and the second trench with mask polysilicon and a second hard mask layer, wherein the second hard mask layer covers one side of the second trench away from the first trench, and the coverage area of the second hard mask layer is greater than or equal to the coverage area of the first hard mask layer;

[0013] S6: removing the gate oxide in the inner side area of the adjacent first trench and second trench with the second hard mask layer as a mask; then sequentially removing the second hard mask layer, the mask polysilicon and the silicon nitride;

[0014] S7: depositing gate oxide medium with uniform thickness; sequentially forming gate polysilicon, second conductive type body region, first conductive type source region, source contact hole, source metal and drain.

[0015] Further, the thick oxide layer in step S2 is deposited by a thermal oxidation process, or is deposited by a thermal oxidation process and a deposition process together.

[0016] Further, the gate oxide and silicon nitride with uniform thickness in step S4 are deposited by a chemical vapor deposition method.

[0017] Further, the thickness of the gate oxide is 2000A-2500A, and the thickness of the silicon nitride is 500A-1000A.

[0018] Further, the step S3 specifically comprises:

[0019] S31: filling shielding gate polysilicon in the first trench and the second trench, and performing planarization treatment; etching back the shielding gate polysilicon so that the upper surface of the shielding gate polysilicon is flush with or lower than the upper surface of the first conductive type epitaxial layer;

[0020] S32: forming a first hard mask layer on the surface of the shielding gate polysilicon, and the first hard mask layer covers the side of the second trench away from the first trench;

[0021] S33: etching back the shielding gate polysilicon with the first hard mask layer as a mask.

[0022] Further, the etching depth of the shielding gate polysilicon in the step S33 is 1.0um-1.5um.

[0023] Further, the step S5 specifically comprises:

[0024] S51: filling mask polysilicon in the first trench and the second trench, and performing planarization treatment; so that the upper surface of the mask polysilicon is higher than the upper surface of the silicon nitride;

[0025] S52: depositing a second hard mask layer on the upper surface of the mask polysilicon, and the second hard mask layer covers the side of the second trench away from the first trench, and the coverage area of the second hard mask layer is greater than or equal to the coverage area of the first hard mask layer;

[0026] S53: etching back the mask polysilicon with the second hard mask layer as a mask until the silicon nitride is exposed.

[0027] Further, the step S6 specifically comprises:

[0028] S61: etching the silicon nitride and the gate oxide in sequence with the second hard mask layer as a mask by using a wet process, to form an inverted concave groove on the side wall of the column, wherein the column refers to the protrusion between the first trench and the second trench;

[0029] S62: removing the second hard mask layer;

[0030] S63: etching and removing the mask polysilicon by using a wet or dry etching process;

[0031] S64: etching and removing the silicon nitride by using a wet or dry etching process.

[0032] Further, the depth of the first and second trenches is 4.0-6.5um.

[0033] The second purpose of the present application is to provide a shielded gate trench power device prepared by the method for preparing a shielded gate trench power device as described above.

[0034] In order to remove the gate oxide between the gate polysilicon and the second conductive type body region, the present application introduces silicon nitride, mask polysilicon and a second hard mask layer, so as to ensure that the gate oxide 105 between the gate polysilicon 106 and the second conductive type body region 108 is completely etched before the gate oxide medium 107 is generated; meanwhile, the gate oxide medium between the shielded gate polysilicon and the gate polysilicon in the present application is formed by the gate oxide and the gate oxide medium, and the gate oxide is directly deposited, and the gate oxide medium is generated by furnace tube thermal oxidation, since both the deposition and the furnace tube thermal oxidation are isotropic, the thickness of the gate oxide medium is uniform, thereby improving the Cgs (gate-source capacitance) of the cell in the active region, and helping to ensure the stability of the device performance. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows, and obviously, those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0037] In the drawings:

[0038] Figure 1 It is a whole schematic diagram of the shielded gate trench power device of the up-down structure cell in the embodiments of the present application.

[0039] Figure 2 It is a structure schematic diagram of forming the first conductive type epitaxial layer in the embodiments of the present application.

[0040] Figure 3 It is a structure schematic diagram of forming the first and second trenches in the embodiments of the present application.

[0041] Figure 4 It is a structure schematic diagram of forming the thick oxide layer in the embodiments of the present application.

[0042] Figure 5 It is a structure schematic diagram of filling the shielded gate polysilicon in the embodiments of the present application.

[0043] Figure 6 Structure diagram of etching back the shielding gate polysilicon in the embodiment of the present application;

[0044] Figure 7 Structure diagram of forming the first hard mask layer in the embodiment of the present application;

[0045] Figure 8 Structure diagram of removing the thick oxide layer in the embodiment of the present application;

[0046] Figure 9 Structure diagram of depositing the inter-gate oxide in the embodiment of the present application;

[0047] Figure 10 Structure diagram of depositing the silicon nitride and the mask polysilicon in the embodiment of the present application;

[0048] Figure 11 Structure diagram of forming the second hard mask layer in the embodiment of the present application;

[0049] Figure 12 Structure diagram of etching back the silicon nitride in the embodiment of the present application;

[0050] Figure 13 Structure diagram of etching back the inter-gate oxide in the embodiment of the present application;

[0051] Figure 14 Structure diagram of removing the mask polysilicon and the silicon nitride in the embodiment of the present application.

[0052] Fig. 101, first conductive type substrate; 102, first conductive type epitaxial layer; 103, thick oxide layer; 104, shielding gate polysilicon; 105, inter-gate oxide; 106, gate polysilicon; 107, gate oxide medium; 108, second conductive type body region; 109, first conductive type source region; 110, source metal; 111, first trench; 112, first hard mask layer; 113, silicon nitride; 114, mask polysilicon; 115, second trench; 116, second hard mask layer. DETAILED DESCRIPTION

[0053] In order to make the technical features, objectives and effects of the present application clearer, the specific embodiments of the present application will be described in detail with reference to the drawings. In the following description, it should be understood that the directions or positional relationships indicated by "front", "back", "upper", "lower", "left", "right", "vertical", "horizontal", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail" and the like are based on the directions or positional relationships shown in the drawings, constructed and operated in a specific direction, and are only for the convenience of describing the technical solutions, and do not indicate that the indicated mechanisms or elements must have a specific direction, so it cannot be understood as a limitation on the present application.

[0054] It should also be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing", "setting" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. When an element is referred to as "on" or "below" another element, the element can be "directly" or "indirectly" above the other element, or there can be one or more intervening elements. The terms "first", "second", "third" and the like are only for the convenience of describing the technical solutions, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features with "first", "second", "third" and the like can be explicitly or implicitly included one or more of the features. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0055] In the following description, specific details such as specific system structures, techniques, etc. are presented for the purpose of illustration, not for the purpose of limitation, so as to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, mechanisms, circuits and methods are omitted to avoid unnecessary details that hinder the description of the present application.

[0056] Embodiment 1

[0057] The present application provides a preparation method of a shield gate trench power device, comprising:

[0058] S1: forming a first conductive type epitaxial layer 102 in a first conductive type substrate 101; forming a first trench 111 and a second trench 115 in the first conductive type epitaxial layer 102, wherein the center line of the first conductive type epitaxial layer 102 between the first trench 111 and the second trench 115 is the boundary line between the terminal region and the active region;

[0059] S2: depositing a thick oxide layer 103 with uniform thickness on the inner side of the first trench 111 and the second trench 115 and the upper surface of the first conductive type epitaxial layer 102;

[0060] S3: filling the shielding gate polysilicon 104 and the first hard mask layer 112 in the first trench 111 and the second trench 115, the first hard mask layer 112 covering the side of the second trench 115 away from the first trench 111;

[0061] S4: removing the thick oxide layer 103 with the first hard mask layer 112 as a mask; then removing the first hard mask layer 112 and depositing the inter-gate oxide 105 and the silicon nitride 113 with uniform thickness;

[0062] S5: filling the mask polysilicon 114 and the second hard mask layer 116 in the first trench and the second trench, the second hard mask layer 116 covering the side of the second trench away from the first trench, and the covering area of the second hard mask layer 116 being greater than or equal to the covering area of the first hard mask layer 112;

[0063] S6: removing the inter-gate oxide 105 on the inner side of the adjacent first trench and second trench with the second hard mask layer 116 as a mask; then sequentially removing the second hard mask layer 116, the mask polysilicon 114 and the silicon nitride 113;

[0064] S7: depositing the gate oxide medium 107 with uniform thickness; sequentially forming the gate polysilicon 106, the second conductive type body region 108, the first conductive type source region 109, the source contact hole, the source metal and the drain.

[0065] In order to remove the inter-gate oxide 105 between the gate polysilicon 106 and the second conductive type body region 108, the silicon nitride 113, the mask polysilicon 114 and the second hard mask layer 116 are introduced in the present application, which ensures that the inter-gate oxide 105 between the gate polysilicon 106 and the second conductive type body region 108 is completely etched before the gate oxide medium 107 is generated.

[0066] The inter-gate oxide medium between the shielding gate polysilicon 104 and the gate polysilicon 106 is formed by the inter-gate oxide 105 and the gate oxide medium 107 in the present application, and the inter-gate oxide 105 is directly deposited and formed, and the gate oxide medium 107 is generated by furnace tube thermal oxidation. Since both deposition and furnace tube thermal oxidation are isotropic, the thickness of the inter-gate oxide medium is uniform, which improves the Cgs (gate-source capacitance) of the cell in the active region and helps to ensure the stability of the device performance.

[0067] Embodiment 2

[0068] Please refer toFigures 1-14 This application provides a method for fabricating a shielded gate trench power device, comprising:

[0069] S1: As Figure 1 As shown, a first conductivity type epitaxial layer 102 is formed in a first conductivity type substrate 101; the first conductivity type can be N-type or P-type; the first conductivity type epitaxial layer 102 is located on the first conductivity type substrate 101, specifically, the first conductivity type epitaxial layer 102 is located on the upper surface of the first conductivity type substrate 101, and the doping concentration of the epitaxial layer 102 is lighter than that of the substrate 101, and the first conductivity type substrate is silicon.

[0070] A hard mask layer for trench etching is formed on the epitaxial layer 102 of the first conductivity type. The hard mask layer consists of an oxide layer and a nitride layer. The first trench 111 and the second trench 115 are formed through photolithography, etching, and other process steps. Figure 3 As shown in the diagram. The center line of the epitaxial layer of the first conductivity type between the first and second trenches serves as the boundary between the termination region and the active region. The depths of the first and second trenches are 4.0 μm to 6.5 μm.

[0071] S2: The hard mask layer composed of oxide and nitride layers is etched away using a wet etching process, such as... Figure 4 As shown, a thick oxide layer 103 of uniform thickness is deposited on the inner side of the first trench 111 and the second trench 115 and on the upper surface of the first conductivity type epitaxial layer 102.

[0072] The thick oxide layer 103 is formed by deposition through a thermal oxidation process, or by a combination of thermal oxidation and deposition processes. The thickness of the oxide layer grown by thermal oxidation is 3000 Å to 5000 Å, while the oxide layer grown by deposition process is 1000 Å to 1500 Å.

[0073] S3: The first trench 111 and the second trench 115 are filled with a shielding gate polysilicon 104 and a first hard mask layer 112, wherein the first hard mask layer 112 covers the side of the second trench away from the first trench; specifically including:

[0074] S31: As Figure 5 As shown, the first trench 111 and the second trench 115 are filled with shielding gate polysilicon 104. At this time, the shielding gate polysilicon 104 covers the entire device surface to ensure that there are no voids or other abnormalities in the filling shielding gate polysilicon 104.

[0075] The polysilicon shielding gate 104 is planarized, with the planarization stopping at a position 200-500 Å above the thick oxide layer 103; for example... Figure 6As shown, the shielding gate polysilicon 104 is etched back, and the etching stop layer is located on the thick oxide layer 103 dielectric above the first conductivity type epitaxial layer 102. Then, the shielding gate polysilicon 104 is etched again so that the upper surface of the shielding gate polysilicon 104 is slightly lower than the upper surface of the first conductivity type epitaxial layer.

[0076] S32: A first hard mask layer 112 is formed on the surface of the shielding gate polysilicon 104, and the first hard mask layer 112 covers the side of the second trench away from the first trench. Specifically, the area covered by the first hard mask layer 112 is located at the exact center of the second trench or at a position where the second trench is 3 / 1 or 3 / 2 away from the first trench.

[0077] For ease of description, the region of the shielding gate polysilicon 104 covered by the first hard mask layer 112 is referred to as the first region of the shielding gate polysilicon 104, and the region of the shielding gate polysilicon 104 not covered by the first hard mask layer 112 is referred to as the second region of the shielding gate polysilicon 104.

[0078] S33: As Figure 7 As shown, the shielding gate polysilicon 104 is etched back using the first hard mask layer 112 as a mask. The etch-back depth of the shielding gate polysilicon 104 can specifically be 1.0um-1.5um. This etch-back step refers to etching back the area exposed outside the first hard mask layer 112, while the shielding gate polysilicon 104 inside the area covered by the first hard mask layer 112 is retained.

[0079] S4: As Figure 8 As shown, using the first hard mask layer 112 as a mask, the thick oxide layer 103 is removed by wet or dry etching. Then, the first hard mask layer 112 is removed, and gate oxide 105 and silicon nitride 113 of uniform thickness are deposited; as... Figure 9 and Figure 10 As shown.

[0080] In this step, gate oxide 105 and silicon nitride 113 of uniform thickness are deposited using chemical vapor deposition (CVD). Unlike existing fabrication methods, the gate oxide 105 in this embodiment is generated solely through CVD deposition, rather than by deposition followed by etching. The thickness of the gate oxide 105 is 2000 Å to 2500 Å, and the thickness of the silicon nitride 113 is 500 Å to 1000 Å. Furthermore, the deposited gate oxide 105 plus the gate oxide dielectric 107 represents the final thickness of the gate oxide layer dielectric between the shielding gate polysilicon 104 and the gate polysilicon 106 in the final shielded gate device.

[0081] S5: filling mask polysilicon 114 and second hard mask layer 116 in the first trench and the second trench, the second hard mask layer 116 covers the side of the second trench away from the first trench, and the coverage area of the second hard mask layer 116 is greater than or equal to the coverage area of the first hard mask layer 112; specifically including:

[0082] S51: as shown in the first trench and the second trench, fill the mask polysilicon 114; and planarization treatment; so that the upper surface of the mask polysilicon 114 is higher than the upper surface of the silicon nitride 113; At this time, the intergate oxide layer 105, the silicon nitride 113, the mask polysilicon 114 exist in turn on the first conductive type epitaxial layer 102. Figure 10

[0083] S52: depositing a second hard mask layer 116 on the upper surface of the mask polysilicon 114, and the second hard mask layer 116 covers the side of the second trench away from the first trench, and the coverage area of the second hard mask layer 116 is greater than or equal to the coverage area of the first hard mask layer 112; The coverage area of the second hard mask layer 116 is greater than or equal to the coverage area of the first hard mask layer 112, which means that the left edge of the second hard mask layer 116 is not located on the left side of the left edge of the first hard mask layer 112.

[0084] S53: taking the second hard mask layer 116 as a mask, and etching back the mask polysilicon 114 until the silicon nitride 113 is exposed, specifically using dry etching process to etch back the mask polysilicon 114, and stopping etching back to the silicon nitride dielectric layer 113 on the first conductive type epitaxial layer 102; as shown in Figure 11

[0085] S6: taking the second hard mask layer 116 as a mask, removing the intergate oxide 105 in the inner side area of the adjacent first trench and second trench; then sequentially removing the second hard mask layer 116, the mask polysilicon 114 and the silicon nitride 113; specifically including:

[0086] S61: taking the second hard mask layer 116 as a mask, using wet process to etch the silicon nitride 113 and the intergate oxide 105 in turn, forming a reverse concave groove on the side wall of the column, the column refers to the protrusion between the first trench and the second trench; as shown in Figure 12 、 13 ,

[0087] ​​As can be seen, due to the presence of the second hard mask layer 116, the mask polysilicon 114 in the area covered by the second hard mask layer 116 will not be etched. Due to the presence of the mask polysilicon 114, the silicon nitride 113 in the area covered by the mask polysilicon 114 will not be etched; only a portion of the window of the silicon nitride 113 will be etched. Due to the presence of the silicon nitride 113, the gate oxide 105 covered by the silicon nitride 113 will not be etched, resulting in the silicon nitride 113 and gate oxide 105 on the side and surface of the pillar being etched, forming a concave blank area. The silicon nitride 113 and gate oxide 105 in the area covered by the mask polysilicon 114 will not be etched.

[0088] S62: Remove the second hard mask layer 116;

[0089] S63: Use wet or dry etching processes to etch and remove the mask polysilicon 114;

[0090] S64: Remove silicon nitride 113 by etching using wet or dry etching processes.

[0091] S7: As Figure 1 As shown, a gate oxide dielectric 107 is formed by furnace tube process; gate polysilicon 106 is deposited, followed by the formation of a second conductivity type body region 108, a first conductivity type source region 109, a source contact hole, and a source metal 110. Finally, the first conductivity type substrate is thinned to form the drain electrode.

[0092] like Figure 1 As shown, a second conductivity type body region 108 is formed in the pillar in this application. A first conductivity type source region 109 is formed on the upper surface of the pillar, and a gate polysilicon 106 is formed at the edge of the pillar. The thickness between the gate polysilicon 106 and the pillar is the thickness of the gate oxide dielectric 107. The gate polysilicon 106 is located in the second region of the shielding gate polysilicon 104. The inter-gate oxide dielectric between the shielding gate polysilicon 104 and the gate polysilicon 106 is formed by the inter-gate oxide 105 and the gate oxide dielectric 107. The inter-gate oxide 105 is formed by direct deposition, and the gate oxide dielectric 107 is generated by furnace tube thermal oxidation. Since both deposition and furnace tube thermal oxidation are isotropic, the thickness of the inter-gate oxide dielectric is ensured to be uniform.

[0093] In this application, the thickness between the gate polysilicon 106 and the pillar is the thickness of the gate oxide dielectric 107. The second region of the shield gate polysilicon 104 simultaneously includes the inter-gate oxide 105 and the gate oxide dielectric 107, while the side of the second trench away from the first trench simultaneously includes a thick oxide layer, the inter-gate oxide 105 and the gate oxide dielectric 107.

[0094] It can be understood that the above embodiments only express the preferred embodiments of the present application, the description is more specific and detailed, but it cannot be understood as the limitation of the patent scope of the present application; it should be pointed out that for ordinary skilled in the art, the above technical features can be freely combined without departing from the concept of the present application, and several modifications and improvements can be made, which belong to the protection scope of the present application; therefore, any equivalent transformation and modification made with the patent claim scope of the present application shall belong to the coverage of the patent claim of the present application.

Claims

1. A method for fabricating a shielded gate trench type power device, characterized in that, include: S1: A first conductivity type epitaxial layer (102) is formed in a first conductivity type substrate (101); A first trench (111) and a second trench (115) are formed in a first conductivity type epitaxial layer (102), wherein the center line of the first conductivity type epitaxial layer (102) between the first trench (111) and the second trench (115) is the boundary line between the terminal region and the active region; S2: A thick oxide layer (103) of uniform thickness is deposited on the inner side of the first trench (111) and the second trench (115) and on the upper surface of the first conductivity type epitaxial layer (102); S3: Fill the first trench (111) and the second trench (115) with shielding gate polysilicon (104) and a first hard mask layer (112), wherein the first hard mask layer (112) covers the side of the second trench (115) away from the first trench (111); S4: Using the first hard mask layer (112) as a mask, remove the thick oxide layer (103); then remove the first hard mask layer (112) and deposit inter-gate oxide (105) and silicon nitride (113) of uniform thickness; S5: Fill the first trench (111) and the second trench (115) with mask polysilicon (114) and the second hard mask layer (116), the second hard mask layer (116) covers the side of the second trench (115) away from the first trench (111), and the coverage area of ​​the second hard mask layer (116) is greater than or equal to the coverage area of ​​the first hard mask layer (112); S6: Using the second hard mask layer (116) as a mask, remove the gate oxide (105) in the inner region of the adjacent first trench and second trench; then remove the second hard mask layer (116), mask polysilicon (114) and silicon nitride (113) in sequence. S7: Deposit gate oxide dielectric (107) with uniform thickness; sequentially form gate polysilicon (106), second conductivity type body region (108), first conductivity type source region (109), source contact hole, source metal (110), and drain.

2. The method for fabricating a shielded gate trench type power device according to claim 1, characterized in that, In step S2, the thick oxide layer (103) is formed by deposition through a thermal oxidation process, or by deposition through a combination of thermal oxidation and deposition processes.

3. The method for fabricating a shielded gate trench type power device according to claim 1, characterized in that, In step S4, inter-gate oxide (105) and silicon nitride (113) of uniform thickness are deposited by chemical vapor deposition.

4. The method for fabricating a shielded gate trench type power device according to claim 1, characterized in that, The thickness of the inter-gate oxide (105) is 2000 Å to 2500 Å, and the thickness of the silicon nitride (113) is 500 Å to 1000 Å.

5. The method for fabricating a shielded gate trench type power device according to claim 1, characterized in that, Step S3 specifically includes: S31: Fill the first trench (111) and the second trench (115) with shielding gate polysilicon (104) and perform planarization; etch back the shielding gate polysilicon (104) so ​​that the upper surface of the shielding gate polysilicon (104) is flush with or lower than the upper surface of the first conductivity type epitaxial layer (102); S32: A first hard mask layer (112) is formed on the surface of the shielding gate polysilicon (104), the first hard mask layer (112) covering the side of the second trench (115) away from the first trench (111); S33: Using the first hard mask layer (112) as a mask, the shielding gate polysilicon (104) is etched back.

6. The method for fabricating a shielded gate trench type power device according to claim 5, characterized in that, In step S33, the etching depth of the shielding gate polysilicon (104) is 1.0um-1.5um.

7. The method for fabricating a shielded trench power device according to claim 1, characterized in that, Step S5 specifically includes: S51: Fill the first trench (111) and the second trench (115) with mask polysilicon (114); and perform planarization treatment; so that the upper surface of the mask polysilicon (114) is higher than the upper surface of the silicon nitride (113); S52: A second hard mask layer (116) is deposited on the upper surface of the mask polysilicon (114), and the second hard mask layer (116) covers the side of the second trench (115) away from the first trench (111), and the coverage area of ​​the second hard mask layer (116) is greater than or equal to the coverage area of ​​the first hard mask layer (112). S53: Using the second hard mask layer (116) as a mask, the mask polysilicon (114) is etched back until the silicon nitride (113) is exposed.

8. The method for fabricating a shielded gate trench type power device according to claim 7, characterized in that, Step S6 specifically includes: S61: Using the second hard mask layer (116) as a mask, silicon nitride (113) and inter-gate oxide (105) are sequentially etched using a wet process to form an inverted concave groove on the side wall of the pillar. The pillar refers to the protrusion between the first groove (111) and the second groove (115). S62: Remove the second hard mask layer; S63: Use wet or dry etching processes to etch and remove the mask polysilicon (114); S64: Remove silicon nitride (113) by etching using a wet or dry etching process.

9. The method for fabricating a shielded gate trench type power device according to claim 1, characterized in that, The depths of the first trench (111) and the second trench (115) are 4.0um-6.5um.

10. A shielded grid trench type power device, characterized in that, It is prepared by the method of any one of claims 1-9 for preparing a shielded trench power device.

Images